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V4L/DVB (6715): ivtv: Remove unnecessary register update
[linux-2.6/verdex.git] / drivers / video / asiliantfb.c
blob1fd22f460b0fa23e990cced9abe9c26f66b04791
1 /*
2 * drivers/video/asiliantfb.c
3 * frame buffer driver for Asiliant 69000 chip
4 * Copyright (C) 2001-2003 Saito.K & Jeanne
5 *
6 * from driver/video/chipsfb.c and,
7 *
8 * drivers/video/asiliantfb.c -- frame buffer device for
9 * Asiliant 69030 chip (formerly Intel, formerly Chips & Technologies)
10 * Author: apc@agelectronics.co.uk
11 * Copyright (C) 2000 AG Electronics
12 * Note: the data sheets don't seem to be available from Asiliant.
13 * They are available by searching developer.intel.com, but are not otherwise
14 * linked to.
15 *
16 * This driver should be portable with minimal effort to the 69000 display
17 * chip, and to the twin-display mode of the 69030.
18 * Contains code from Thomas Hhenleitner <th@visuelle-maschinen.de> (thanks)
19 *
20 * Derived from the CT65550 driver chipsfb.c:
21 * Copyright (C) 1998 Paul Mackerras
22 * ...which was derived from the Powermac "chips" driver:
23 * Copyright (C) 1997 Fabio Riccardi.
24 * And from the frame buffer device for Open Firmware-initialized devices:
25 * Copyright (C) 1997 Geert Uytterhoeven.
26 *
27 * This file is subject to the terms and conditions of the GNU General Public
28 * License. See the file COPYING in the main directory of this archive for
29 * more details.
30 */
31
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/errno.h>
35 #include <linux/string.h>
36 #include <linux/mm.h>
37 #include <linux/slab.h>
38 #include <linux/vmalloc.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/fb.h>
42 #include <linux/init.h>
43 #include <linux/pci.h>
44 #include <asm/io.h>
45
46 /* Built in clock of the 69030 */
47 static const unsigned Fref = 14318180;
48
49 #define mmio_base (p->screen_base + 0x400000)
50
51 #define mm_write_ind(num, val, ap, dp) do { \
52 writeb((num), mmio_base + (ap)); writeb((val), mmio_base + (dp)); \
53 } while (0)
54
55 static void mm_write_xr(struct fb_info *p, u8 reg, u8 data)
56 {
57 mm_write_ind(reg, data, 0x7ac, 0x7ad);
58 }
59 #define write_xr(num, val) mm_write_xr(p, num, val)
60
61 static void mm_write_fr(struct fb_info *p, u8 reg, u8 data)
62 {
63 mm_write_ind(reg, data, 0x7a0, 0x7a1);
64 }
65 #define write_fr(num, val) mm_write_fr(p, num, val)
66
67 static void mm_write_cr(struct fb_info *p, u8 reg, u8 data)
68 {
69 mm_write_ind(reg, data, 0x7a8, 0x7a9);
70 }
71 #define write_cr(num, val) mm_write_cr(p, num, val)
72
73 static void mm_write_gr(struct fb_info *p, u8 reg, u8 data)
74 {
75 mm_write_ind(reg, data, 0x79c, 0x79d);
76 }
77 #define write_gr(num, val) mm_write_gr(p, num, val)
78
79 static void mm_write_sr(struct fb_info *p, u8 reg, u8 data)
80 {
81 mm_write_ind(reg, data, 0x788, 0x789);
82 }
83 #define write_sr(num, val) mm_write_sr(p, num, val)
84
85 static void mm_write_ar(struct fb_info *p, u8 reg, u8 data)
86 {
87 readb(mmio_base + 0x7b4);
88 mm_write_ind(reg, data, 0x780, 0x780);
89 }
90 #define write_ar(num, val) mm_write_ar(p, num, val)
91
92 static int asiliantfb_pci_init(struct pci_dev *dp, const struct pci_device_id *);
93 static int asiliantfb_check_var(struct fb_var_screeninfo *var,
94 struct fb_info *info);
95 static int asiliantfb_set_par(struct fb_info *info);
96 static int asiliantfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
97 u_int transp, struct fb_info *info);
98
99 static struct fb_ops asiliantfb_ops = {
100 .owner = THIS_MODULE,
101 .fb_check_var = asiliantfb_check_var,
102 .fb_set_par = asiliantfb_set_par,
103 .fb_setcolreg = asiliantfb_setcolreg,
104 .fb_fillrect = cfb_fillrect,
105 .fb_copyarea = cfb_copyarea,
106 .fb_imageblit = cfb_imageblit,
107 };
108
109 /* Calculate the ratios for the dot clocks without using a single long long
110 * value */
111 static void asiliant_calc_dclk2(u32 *ppixclock, u8 *dclk2_m, u8 *dclk2_n, u8 *dclk2_div)
112 {
113 unsigned pixclock = *ppixclock;
114 unsigned Ftarget = 1000000 * (1000000 / pixclock);
115 unsigned n;
116 unsigned best_error = 0xffffffff;
117 unsigned best_m = 0xffffffff,
118 best_n = 0xffffffff;
119 unsigned ratio;
120 unsigned remainder;
121 unsigned char divisor = 0;
122
123 /* Calculate the frequency required. This is hard enough. */
124 ratio = 1000000 / pixclock;
125 remainder = 1000000 % pixclock;
126 Ftarget = 1000000 * ratio + (1000000 * remainder) / pixclock;
127
128 while (Ftarget < 100000000) {
129 divisor += 0x10;
130 Ftarget <<= 1;
131 }
132
133 ratio = Ftarget / Fref;
134 remainder = Ftarget % Fref;
135
136 /* This expresses the constraint that 150kHz <= Fref/n <= 5Mhz,
137 * together with 3 <= n <= 257. */
138 for (n = 3; n <= 257; n++) {
139 unsigned m = n * ratio + (n * remainder) / Fref;
140
141 /* 3 <= m <= 257 */
142 if (m >= 3 && m <= 257) {
143 unsigned new_error = ((Ftarget * n) - (Fref * m)) >= 0 ?
144 ((Ftarget * n) - (Fref * m)) : ((Fref * m) - (Ftarget * n));
145 if (new_error < best_error) {
146 best_n = n;
147 best_m = m;
148 best_error = new_error;
149 }
150 }
151 /* But if VLD = 4, then 4m <= 1028 */
152 else if (m <= 1028) {
153 /* remember there are still only 8-bits of precision in m, so
154 * avoid over-optimistic error calculations */
155 unsigned new_error = ((Ftarget * n) - (Fref * (m & ~3))) >= 0 ?
156 ((Ftarget * n) - (Fref * (m & ~3))) : ((Fref * (m & ~3)) - (Ftarget * n));
157 if (new_error < best_error) {
158 best_n = n;
159 best_m = m;
160 best_error = new_error;
161 }
162 }
163 }
164 if (best_m > 257)
165 best_m >>= 2; /* divide m by 4, and leave VCO loop divide at 4 */
166 else
167 divisor |= 4; /* or set VCO loop divide to 1 */
168 *dclk2_m = best_m - 2;
169 *dclk2_n = best_n - 2;
170 *dclk2_div = divisor;
171 *ppixclock = pixclock;
172 return;
173 }
174
175 static void asiliant_set_timing(struct fb_info *p)
176 {
177 unsigned hd = p->var.xres / 8;
178 unsigned hs = (p->var.xres + p->var.right_margin) / 8;
179 unsigned he = (p->var.xres + p->var.right_margin + p->var.hsync_len) / 8;
180 unsigned ht = (p->var.left_margin + p->var.xres + p->var.right_margin + p->var.hsync_len) / 8;
181 unsigned vd = p->var.yres;
182 unsigned vs = p->var.yres + p->var.lower_margin;
183 unsigned ve = p->var.yres + p->var.lower_margin + p->var.vsync_len;
184 unsigned vt = p->var.upper_margin + p->var.yres + p->var.lower_margin + p->var.vsync_len;
185 unsigned wd = (p->var.xres_virtual * ((p->var.bits_per_pixel+7)/8)) / 8;
186
187 if ((p->var.xres == 640) && (p->var.yres == 480) && (p->var.pixclock == 39722)) {
188 write_fr(0x01, 0x02); /* LCD */
189 } else {
190 write_fr(0x01, 0x01); /* CRT */
191 }
192
193 write_cr(0x11, (ve - 1) & 0x0f);
194 write_cr(0x00, (ht - 5) & 0xff);
195 write_cr(0x01, hd - 1);
196 write_cr(0x02, hd);
197 write_cr(0x03, ((ht - 1) & 0x1f) | 0x80);
198 write_cr(0x04, hs);
199 write_cr(0x05, (((ht - 1) & 0x20) <<2) | (he & 0x1f));
200 write_cr(0x3c, (ht - 1) & 0xc0);
201 write_cr(0x06, (vt - 2) & 0xff);
202 write_cr(0x30, (vt - 2) >> 8);
203 write_cr(0x07, 0x00);
204 write_cr(0x08, 0x00);
205 write_cr(0x09, 0x00);
206 write_cr(0x10, (vs - 1) & 0xff);
207 write_cr(0x32, ((vs - 1) >> 8) & 0xf);
208 write_cr(0x11, ((ve - 1) & 0x0f) | 0x80);
209 write_cr(0x12, (vd - 1) & 0xff);
210 write_cr(0x31, ((vd - 1) & 0xf00) >> 8);
211 write_cr(0x13, wd & 0xff);
212 write_cr(0x41, (wd & 0xf00) >> 8);
213 write_cr(0x15, (vs - 1) & 0xff);
214 write_cr(0x33, ((vs - 1) >> 8) & 0xf);
215 write_cr(0x38, ((ht - 5) & 0x100) >> 8);
216 write_cr(0x16, (vt - 1) & 0xff);
217 write_cr(0x18, 0x00);
218
219 if (p->var.xres == 640) {
220 writeb(0xc7, mmio_base + 0x784); /* set misc output reg */
221 } else {
222 writeb(0x07, mmio_base + 0x784); /* set misc output reg */
223 }
224 }
225
226 static int asiliantfb_check_var(struct fb_var_screeninfo *var,
227 struct fb_info *p)
228 {
229 unsigned long Ftarget, ratio, remainder;
230
231 ratio = 1000000 / var->pixclock;
232 remainder = 1000000 % var->pixclock;
233 Ftarget = 1000000 * ratio + (1000000 * remainder) / var->pixclock;
234
235 /* First check the constraint that the maximum post-VCO divisor is 32,
236 * and the maximum Fvco is 220MHz */
237 if (Ftarget > 220000000 || Ftarget < 3125000) {
238 printk(KERN_ERR "asiliantfb dotclock must be between 3.125 and 220MHz\n");
239 return -ENXIO;
240 }
241 var->xres_virtual = var->xres;
242 var->yres_virtual = var->yres;
243
244 if (var->bits_per_pixel == 24) {
245 var->red.offset = 16;
246 var->green.offset = 8;
247 var->blue.offset = 0;
248 var->red.length = var->blue.length = var->green.length = 8;
249 } else if (var->bits_per_pixel == 16) {
250 switch (var->red.offset) {
251 case 11:
252 var->green.length = 6;
253 break;
254 case 10:
255 var->green.length = 5;
256 break;
257 default:
258 return -EINVAL;
259 }
260 var->green.offset = 5;
261 var->blue.offset = 0;
262 var->red.length = var->blue.length = 5;
263 } else if (var->bits_per_pixel == 8) {
264 var->red.offset = var->green.offset = var->blue.offset = 0;
265 var->red.length = var->green.length = var->blue.length = 8;
266 }
267 return 0;
268 }
269
270 static int asiliantfb_set_par(struct fb_info *p)
271 {
272 u8 dclk2_m; /* Holds m-2 value for register */
273 u8 dclk2_n; /* Holds n-2 value for register */
274 u8 dclk2_div; /* Holds divisor bitmask */
275
276 /* Set pixclock */
277 asiliant_calc_dclk2(&p->var.pixclock, &dclk2_m, &dclk2_n, &dclk2_div);
278
279 /* Set color depth */
280 if (p->var.bits_per_pixel == 24) {
281 write_xr(0x81, 0x16); /* 24 bit packed color mode */
282 write_xr(0x82, 0x00); /* Disable palettes */
283 write_xr(0x20, 0x20); /* 24 bit blitter mode */
284 } else if (p->var.bits_per_pixel == 16) {
285 if (p->var.red.offset == 11)
286 write_xr(0x81, 0x15); /* 16 bit color mode */
287 else
288 write_xr(0x81, 0x14); /* 15 bit color mode */
289 write_xr(0x82, 0x00); /* Disable palettes */
290 write_xr(0x20, 0x10); /* 16 bit blitter mode */
291 } else if (p->var.bits_per_pixel == 8) {
292 write_xr(0x0a, 0x02); /* Linear */
293 write_xr(0x81, 0x12); /* 8 bit color mode */
294 write_xr(0x82, 0x00); /* Graphics gamma enable */
295 write_xr(0x20, 0x00); /* 8 bit blitter mode */
296 }
297 p->fix.line_length = p->var.xres * (p->var.bits_per_pixel >> 3);
298 p->fix.visual = (p->var.bits_per_pixel == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
299 write_xr(0xc4, dclk2_m);
300 write_xr(0xc5, dclk2_n);
301 write_xr(0xc7, dclk2_div);
302 /* Set up the CR registers */
303 asiliant_set_timing(p);
304 return 0;
305 }
306
307 static int asiliantfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
308 u_int transp, struct fb_info *p)
309 {
310 if (regno > 255)
311 return 1;
312 red >>= 8;
313 green >>= 8;
314 blue >>= 8;
315
316 /* Set hardware palete */
317 writeb(regno, mmio_base + 0x790);
318 udelay(1);
319 writeb(red, mmio_base + 0x791);
320 writeb(green, mmio_base + 0x791);
321 writeb(blue, mmio_base + 0x791);
322
323 if (regno < 16) {
324 switch(p->var.red.offset) {
325 case 10: /* RGB 555 */
326 ((u32 *)(p->pseudo_palette))[regno] =
327 ((red & 0xf8) << 7) |
328 ((green & 0xf8) << 2) |
329 ((blue & 0xf8) >> 3);
330 break;
331 case 11: /* RGB 565 */
332 ((u32 *)(p->pseudo_palette))[regno] =
333 ((red & 0xf8) << 8) |
334 ((green & 0xfc) << 3) |
335 ((blue & 0xf8) >> 3);
336 break;
337 case 16: /* RGB 888 */
338 ((u32 *)(p->pseudo_palette))[regno] =
339 (red << 16) |
340 (green << 8) |
341 (blue);
342 break;
343 }
344 }
345
346 return 0;
347 }
348
349 struct chips_init_reg {
350 unsigned char addr;
351 unsigned char data;
352 };
353
354 static struct chips_init_reg chips_init_sr[] =
355 {
356 {0x00, 0x03}, /* Reset register */
357 {0x01, 0x01}, /* Clocking mode */
358 {0x02, 0x0f}, /* Plane mask */
359 {0x04, 0x0e} /* Memory mode */
360 };
361
362 static struct chips_init_reg chips_init_gr[] =
363 {
364 {0x03, 0x00}, /* Data rotate */
365 {0x05, 0x00}, /* Graphics mode */
366 {0x06, 0x01}, /* Miscellaneous */
367 {0x08, 0x00} /* Bit mask */
368 };
369
370 static struct chips_init_reg chips_init_ar[] =
371 {
372 {0x10, 0x01}, /* Mode control */
373 {0x11, 0x00}, /* Overscan */
374 {0x12, 0x0f}, /* Memory plane enable */
375 {0x13, 0x00} /* Horizontal pixel panning */
376 };
377
378 static struct chips_init_reg chips_init_cr[] =
379 {
380 {0x0c, 0x00}, /* Start address high */
381 {0x0d, 0x00}, /* Start address low */
382 {0x40, 0x00}, /* Extended Start Address */
383 {0x41, 0x00}, /* Extended Start Address */
384 {0x14, 0x00}, /* Underline location */
385 {0x17, 0xe3}, /* CRT mode control */
386 {0x70, 0x00} /* Interlace control */
387 };
388
389
390 static struct chips_init_reg chips_init_fr[] =
391 {
392 {0x01, 0x02},
393 {0x03, 0x08},
394 {0x08, 0xcc},
395 {0x0a, 0x08},
396 {0x18, 0x00},
397 {0x1e, 0x80},
398 {0x40, 0x83},
399 {0x41, 0x00},
400 {0x48, 0x13},
401 {0x4d, 0x60},
402 {0x4e, 0x0f},
403
404 {0x0b, 0x01},
405
406 {0x21, 0x51},
407 {0x22, 0x1d},
408 {0x23, 0x5f},
409 {0x20, 0x4f},
410 {0x34, 0x00},
411 {0x24, 0x51},
412 {0x25, 0x00},
413 {0x27, 0x0b},
414 {0x26, 0x00},
415 {0x37, 0x80},
416 {0x33, 0x0b},
417 {0x35, 0x11},
418 {0x36, 0x02},
419 {0x31, 0xea},
420 {0x32, 0x0c},
421 {0x30, 0xdf},
422 {0x10, 0x0c},
423 {0x11, 0xe0},
424 {0x12, 0x50},
425 {0x13, 0x00},
426 {0x16, 0x03},
427 {0x17, 0xbd},
428 {0x1a, 0x00},
429 };
430
431
432 static struct chips_init_reg chips_init_xr[] =
433 {
434 {0xce, 0x00}, /* set default memory clock */
435 {0xcc, 200 }, /* MCLK ratio M */
436 {0xcd, 18 }, /* MCLK ratio N */
437 {0xce, 0x90}, /* MCLK divisor = 2 */
438
439 {0xc4, 209 },
440 {0xc5, 118 },
441 {0xc7, 32 },
442 {0xcf, 0x06},
443 {0x09, 0x01}, /* IO Control - CRT controller extensions */
444 {0x0a, 0x02}, /* Frame buffer mapping */
445 {0x0b, 0x01}, /* PCI burst write */
446 {0x40, 0x03}, /* Memory access control */
447 {0x80, 0x82}, /* Pixel pipeline configuration 0 */
448 {0x81, 0x12}, /* Pixel pipeline configuration 1 */
449 {0x82, 0x08}, /* Pixel pipeline configuration 2 */
450
451 {0xd0, 0x0f},
452 {0xd1, 0x01},
453 };
454
455 static void __devinit chips_hw_init(struct fb_info *p)
456 {
457 int i;
458
459 for (i = 0; i < ARRAY_SIZE(chips_init_xr); ++i)
460 write_xr(chips_init_xr[i].addr, chips_init_xr[i].data);
461 write_xr(0x81, 0x12);
462 write_xr(0x82, 0x08);
463 write_xr(0x20, 0x00);
464 for (i = 0; i < ARRAY_SIZE(chips_init_sr); ++i)
465 write_sr(chips_init_sr[i].addr, chips_init_sr[i].data);
466 for (i = 0; i < ARRAY_SIZE(chips_init_gr); ++i)
467 write_gr(chips_init_gr[i].addr, chips_init_gr[i].data);
468 for (i = 0; i < ARRAY_SIZE(chips_init_ar); ++i)
469 write_ar(chips_init_ar[i].addr, chips_init_ar[i].data);
470 /* Enable video output in attribute index register */
471 writeb(0x20, mmio_base + 0x780);
472 for (i = 0; i < ARRAY_SIZE(chips_init_cr); ++i)
473 write_cr(chips_init_cr[i].addr, chips_init_cr[i].data);
474 for (i = 0; i < ARRAY_SIZE(chips_init_fr); ++i)
475 write_fr(chips_init_fr[i].addr, chips_init_fr[i].data);
476 }
477
478 static struct fb_fix_screeninfo asiliantfb_fix __devinitdata = {
479 .id = "Asiliant 69000",
480 .type = FB_TYPE_PACKED_PIXELS,
481 .visual = FB_VISUAL_PSEUDOCOLOR,
482 .accel = FB_ACCEL_NONE,
483 .line_length = 640,
484 .smem_len = 0x200000, /* 2MB */
485 };
486
487 static struct fb_var_screeninfo asiliantfb_var __devinitdata = {
488 .xres = 640,
489 .yres = 480,
490 .xres_virtual = 640,
491 .yres_virtual = 480,
492 .bits_per_pixel = 8,
493 .red = { .length = 8 },
494 .green = { .length = 8 },
495 .blue = { .length = 8 },
496 .height = -1,
497 .width = -1,
498 .vmode = FB_VMODE_NONINTERLACED,
499 .pixclock = 39722,
500 .left_margin = 48,
501 .right_margin = 16,
502 .upper_margin = 33,
503 .lower_margin = 10,
504 .hsync_len = 96,
505 .vsync_len = 2,
506 };
507
508 static void __devinit init_asiliant(struct fb_info *p, unsigned long addr)
509 {
510 p->fix = asiliantfb_fix;
511 p->fix.smem_start = addr;
512 p->var = asiliantfb_var;
513 p->fbops = &asiliantfb_ops;
514 p->flags = FBINFO_DEFAULT;
515
516 fb_alloc_cmap(&p->cmap, 256, 0);
517
518 if (register_framebuffer(p) < 0) {
519 printk(KERN_ERR "C&T 69000 framebuffer failed to register\n");
520 return;
521 }
522
523 printk(KERN_INFO "fb%d: Asiliant 69000 frame buffer (%dK RAM detected)\n",
524 p->node, p->fix.smem_len / 1024);
525
526 writeb(0xff, mmio_base + 0x78c);
527 chips_hw_init(p);
528 }
529
530 static int __devinit
531 asiliantfb_pci_init(struct pci_dev *dp, const struct pci_device_id *ent)
532 {
533 unsigned long addr, size;
534 struct fb_info *p;
535
536 if ((dp->resource[0].flags & IORESOURCE_MEM) == 0)
537 return -ENODEV;
538 addr = pci_resource_start(dp, 0);
539 size = pci_resource_len(dp, 0);
540 if (addr == 0)
541 return -ENODEV;
542 if (!request_mem_region(addr, size, "asiliantfb"))
543 return -EBUSY;
544
545 p = framebuffer_alloc(sizeof(u32) * 16, &dp->dev);
546 if (!p) {
547 release_mem_region(addr, size);
548 return -ENOMEM;
549 }
550 p->pseudo_palette = p->par;
551 p->par = NULL;
552
553 p->screen_base = ioremap(addr, 0x800000);
554 if (p->screen_base == NULL) {
555 release_mem_region(addr, size);
556 framebuffer_release(p);
557 return -ENOMEM;
558 }
559
560 pci_write_config_dword(dp, 4, 0x02800083);
561 writeb(3, p->screen_base + 0x400784);
562
563 init_asiliant(p, addr);
564
565 pci_set_drvdata(dp, p);
566 return 0;
567 }
568
569 static void __devexit asiliantfb_remove(struct pci_dev *dp)
570 {
571 struct fb_info *p = pci_get_drvdata(dp);
572
573 unregister_framebuffer(p);
574 iounmap(p->screen_base);
575 release_mem_region(pci_resource_start(dp, 0), pci_resource_len(dp, 0));
576 pci_set_drvdata(dp, NULL);
577 framebuffer_release(p);
578 }
579
580 static struct pci_device_id asiliantfb_pci_tbl[] __devinitdata = {
581 { PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69000, PCI_ANY_ID, PCI_ANY_ID },
582 { 0 }
583 };
584
585 MODULE_DEVICE_TABLE(pci, asiliantfb_pci_tbl);
586
587 static struct pci_driver asiliantfb_driver = {
588 .name = "asiliantfb",
589 .id_table = asiliantfb_pci_tbl,
590 .probe = asiliantfb_pci_init,
591 .remove = __devexit_p(asiliantfb_remove),
592 };
593
594 static int __init asiliantfb_init(void)
595 {
596 if (fb_get_options("asiliantfb", NULL))
597 return -ENODEV;
598
599 return pci_register_driver(&asiliantfb_driver);
600 }
601
602 module_init(asiliantfb_init);
603
604 static void __exit asiliantfb_exit(void)
605 {
606 pci_unregister_driver(&asiliantfb_driver);
607 }
608
609 MODULE_LICENSE("GPL");
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