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V4L/DVB (6715): ivtv: Remove unnecessary register update
[linux-2.6/verdex.git] / drivers / video / aty / radeon_base.c
blob62867cb63fefb2894dfc98096affff66c4fd5d22
1 /*
2 * drivers/video/aty/radeon_base.c
3 *
4 * framebuffer driver for ATI Radeon chipset video boards
5 *
6 * Copyright 2003 Ben. Herrenschmidt <benh@kernel.crashing.org>
7 * Copyright 2000 Ani Joshi <ajoshi@kernel.crashing.org>
8 *
9 * i2c bits from Luca Tettamanti <kronos@kronoz.cjb.net>
10 *
11 * Special thanks to ATI DevRel team for their hardware donations.
12 *
13 * ...Insert GPL boilerplate here...
14 *
15 * Significant portions of this driver apdated from XFree86 Radeon
16 * driver which has the following copyright notice:
17 *
18 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
19 * VA Linux Systems Inc., Fremont, California.
20 *
21 * All Rights Reserved.
22 *
23 * Permission is hereby granted, free of charge, to any person obtaining
24 * a copy of this software and associated documentation files (the
25 * "Software"), to deal in the Software without restriction, including
26 * without limitation on the rights to use, copy, modify, merge,
27 * publish, distribute, sublicense, and/or sell copies of the Software,
28 * and to permit persons to whom the Software is furnished to do so,
29 * subject to the following conditions:
30 *
31 * The above copyright notice and this permission notice (including the
32 * next paragraph) shall be included in all copies or substantial
33 * portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
37 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
39 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
41 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
42 * DEALINGS IN THE SOFTWARE.
43 *
44 * XFree86 driver authors:
45 *
46 * Kevin E. Martin <martin@xfree86.org>
47 * Rickard E. Faith <faith@valinux.com>
48 * Alan Hourihane <alanh@fairlite.demon.co.uk>
49 *
50 */
51
52
53 #define RADEON_VERSION "0.2.0"
54
55 #include <linux/module.h>
56 #include <linux/moduleparam.h>
57 #include <linux/kernel.h>
58 #include <linux/errno.h>
59 #include <linux/string.h>
60 #include <linux/mm.h>
61 #include <linux/slab.h>
62 #include <linux/delay.h>
63 #include <linux/time.h>
64 #include <linux/fb.h>
65 #include <linux/ioport.h>
66 #include <linux/init.h>
67 #include <linux/pci.h>
68 #include <linux/vmalloc.h>
69 #include <linux/device.h>
70
71 #include <asm/io.h>
72 #include <linux/uaccess.h>
73
74 #ifdef CONFIG_PPC_OF
75
76 #include <asm/pci-bridge.h>
77 #include "../macmodes.h"
78
79 #ifdef CONFIG_BOOTX_TEXT
80 #include <asm/btext.h>
81 #endif
82
83 #endif /* CONFIG_PPC_OF */
84
85 #ifdef CONFIG_MTRR
86 #include <asm/mtrr.h>
87 #endif
88
89 #include <video/radeon.h>
90 #include <linux/radeonfb.h>
91
92 #include "../edid.h" // MOVE THAT TO include/video
93 #include "ati_ids.h"
94 #include "radeonfb.h"
95
96 #define MAX_MAPPED_VRAM (2048*2048*4)
97 #define MIN_MAPPED_VRAM (1024*768*1)
98
99 #define CHIP_DEF(id, family, flags) \
100 { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) }
101
102 static struct pci_device_id radeonfb_pci_table[] = {
103 /* Radeon Xpress 200m */
104 CHIP_DEF(PCI_CHIP_RS480_5955, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
105 CHIP_DEF(PCI_CHIP_RS482_5975, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
106 /* Mobility M6 */
107 CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
108 CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
109 /* Radeon VE/7000 */
110 CHIP_DEF(PCI_CHIP_RV100_QY, RV100, CHIP_HAS_CRTC2),
111 CHIP_DEF(PCI_CHIP_RV100_QZ, RV100, CHIP_HAS_CRTC2),
112 CHIP_DEF(PCI_CHIP_RN50, RV100, CHIP_HAS_CRTC2),
113 /* Radeon IGP320M (U1) */
114 CHIP_DEF(PCI_CHIP_RS100_4336, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
115 /* Radeon IGP320 (A3) */
116 CHIP_DEF(PCI_CHIP_RS100_4136, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
117 /* IGP330M/340M/350M (U2) */
118 CHIP_DEF(PCI_CHIP_RS200_4337, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
119 /* IGP330/340/350 (A4) */
120 CHIP_DEF(PCI_CHIP_RS200_4137, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
121 /* Mobility 7000 IGP */
122 CHIP_DEF(PCI_CHIP_RS250_4437, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
123 /* 7000 IGP (A4+) */
124 CHIP_DEF(PCI_CHIP_RS250_4237, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
125 /* 8500 AIW */
126 CHIP_DEF(PCI_CHIP_R200_BB, R200, CHIP_HAS_CRTC2),
127 CHIP_DEF(PCI_CHIP_R200_BC, R200, CHIP_HAS_CRTC2),
128 /* 8700/8800 */
129 CHIP_DEF(PCI_CHIP_R200_QH, R200, CHIP_HAS_CRTC2),
130 /* 8500 */
131 CHIP_DEF(PCI_CHIP_R200_QL, R200, CHIP_HAS_CRTC2),
132 /* 9100 */
133 CHIP_DEF(PCI_CHIP_R200_QM, R200, CHIP_HAS_CRTC2),
134 /* Mobility M7 */
135 CHIP_DEF(PCI_CHIP_RADEON_LW, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
136 CHIP_DEF(PCI_CHIP_RADEON_LX, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
137 /* 7500 */
138 CHIP_DEF(PCI_CHIP_RV200_QW, RV200, CHIP_HAS_CRTC2),
139 CHIP_DEF(PCI_CHIP_RV200_QX, RV200, CHIP_HAS_CRTC2),
140 /* Mobility M9 */
141 CHIP_DEF(PCI_CHIP_RV250_Ld, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
142 CHIP_DEF(PCI_CHIP_RV250_Le, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
143 CHIP_DEF(PCI_CHIP_RV250_Lf, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
144 CHIP_DEF(PCI_CHIP_RV250_Lg, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
145 /* 9000/Pro */
146 CHIP_DEF(PCI_CHIP_RV250_If, RV250, CHIP_HAS_CRTC2),
147 CHIP_DEF(PCI_CHIP_RV250_Ig, RV250, CHIP_HAS_CRTC2),
148
149 CHIP_DEF(PCI_CHIP_RC410_5A62, RC410, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
150 /* Mobility 9100 IGP (U3) */
151 CHIP_DEF(PCI_CHIP_RS300_5835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
152 CHIP_DEF(PCI_CHIP_RS350_7835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
153 /* 9100 IGP (A5) */
154 CHIP_DEF(PCI_CHIP_RS300_5834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
155 CHIP_DEF(PCI_CHIP_RS350_7834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
156 /* Mobility 9200 (M9+) */
157 CHIP_DEF(PCI_CHIP_RV280_5C61, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
158 CHIP_DEF(PCI_CHIP_RV280_5C63, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
159 /* 9200 */
160 CHIP_DEF(PCI_CHIP_RV280_5960, RV280, CHIP_HAS_CRTC2),
161 CHIP_DEF(PCI_CHIP_RV280_5961, RV280, CHIP_HAS_CRTC2),
162 CHIP_DEF(PCI_CHIP_RV280_5962, RV280, CHIP_HAS_CRTC2),
163 CHIP_DEF(PCI_CHIP_RV280_5964, RV280, CHIP_HAS_CRTC2),
164 /* 9500 */
165 CHIP_DEF(PCI_CHIP_R300_AD, R300, CHIP_HAS_CRTC2),
166 CHIP_DEF(PCI_CHIP_R300_AE, R300, CHIP_HAS_CRTC2),
167 /* 9600TX / FireGL Z1 */
168 CHIP_DEF(PCI_CHIP_R300_AF, R300, CHIP_HAS_CRTC2),
169 CHIP_DEF(PCI_CHIP_R300_AG, R300, CHIP_HAS_CRTC2),
170 /* 9700/9500/Pro/FireGL X1 */
171 CHIP_DEF(PCI_CHIP_R300_ND, R300, CHIP_HAS_CRTC2),
172 CHIP_DEF(PCI_CHIP_R300_NE, R300, CHIP_HAS_CRTC2),
173 CHIP_DEF(PCI_CHIP_R300_NF, R300, CHIP_HAS_CRTC2),
174 CHIP_DEF(PCI_CHIP_R300_NG, R300, CHIP_HAS_CRTC2),
175 /* Mobility M10/M11 */
176 CHIP_DEF(PCI_CHIP_RV350_NP, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
177 CHIP_DEF(PCI_CHIP_RV350_NQ, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
178 CHIP_DEF(PCI_CHIP_RV350_NR, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
179 CHIP_DEF(PCI_CHIP_RV350_NS, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
180 CHIP_DEF(PCI_CHIP_RV350_NT, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
181 CHIP_DEF(PCI_CHIP_RV350_NV, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
182 /* 9600/FireGL T2 */
183 CHIP_DEF(PCI_CHIP_RV350_AP, RV350, CHIP_HAS_CRTC2),
184 CHIP_DEF(PCI_CHIP_RV350_AQ, RV350, CHIP_HAS_CRTC2),
185 CHIP_DEF(PCI_CHIP_RV360_AR, RV350, CHIP_HAS_CRTC2),
186 CHIP_DEF(PCI_CHIP_RV350_AS, RV350, CHIP_HAS_CRTC2),
187 CHIP_DEF(PCI_CHIP_RV350_AT, RV350, CHIP_HAS_CRTC2),
188 CHIP_DEF(PCI_CHIP_RV350_AV, RV350, CHIP_HAS_CRTC2),
189 /* 9800/Pro/FileGL X2 */
190 CHIP_DEF(PCI_CHIP_R350_AH, R350, CHIP_HAS_CRTC2),
191 CHIP_DEF(PCI_CHIP_R350_AI, R350, CHIP_HAS_CRTC2),
192 CHIP_DEF(PCI_CHIP_R350_AJ, R350, CHIP_HAS_CRTC2),
193 CHIP_DEF(PCI_CHIP_R350_AK, R350, CHIP_HAS_CRTC2),
194 CHIP_DEF(PCI_CHIP_R350_NH, R350, CHIP_HAS_CRTC2),
195 CHIP_DEF(PCI_CHIP_R350_NI, R350, CHIP_HAS_CRTC2),
196 CHIP_DEF(PCI_CHIP_R360_NJ, R350, CHIP_HAS_CRTC2),
197 CHIP_DEF(PCI_CHIP_R350_NK, R350, CHIP_HAS_CRTC2),
198 /* Newer stuff */
199 CHIP_DEF(PCI_CHIP_RV380_3E50, RV380, CHIP_HAS_CRTC2),
200 CHIP_DEF(PCI_CHIP_RV380_3E54, RV380, CHIP_HAS_CRTC2),
201 CHIP_DEF(PCI_CHIP_RV380_3150, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
202 CHIP_DEF(PCI_CHIP_RV380_3154, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
203 CHIP_DEF(PCI_CHIP_RV370_5B60, RV380, CHIP_HAS_CRTC2),
204 CHIP_DEF(PCI_CHIP_RV370_5B62, RV380, CHIP_HAS_CRTC2),
205 CHIP_DEF(PCI_CHIP_RV370_5B63, RV380, CHIP_HAS_CRTC2),
206 CHIP_DEF(PCI_CHIP_RV370_5B64, RV380, CHIP_HAS_CRTC2),
207 CHIP_DEF(PCI_CHIP_RV370_5B65, RV380, CHIP_HAS_CRTC2),
208 CHIP_DEF(PCI_CHIP_RV370_5460, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
209 CHIP_DEF(PCI_CHIP_RV370_5464, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
210 CHIP_DEF(PCI_CHIP_R420_JH, R420, CHIP_HAS_CRTC2),
211 CHIP_DEF(PCI_CHIP_R420_JI, R420, CHIP_HAS_CRTC2),
212 CHIP_DEF(PCI_CHIP_R420_JJ, R420, CHIP_HAS_CRTC2),
213 CHIP_DEF(PCI_CHIP_R420_JK, R420, CHIP_HAS_CRTC2),
214 CHIP_DEF(PCI_CHIP_R420_JL, R420, CHIP_HAS_CRTC2),
215 CHIP_DEF(PCI_CHIP_R420_JM, R420, CHIP_HAS_CRTC2),
216 CHIP_DEF(PCI_CHIP_R420_JN, R420, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
217 CHIP_DEF(PCI_CHIP_R420_JP, R420, CHIP_HAS_CRTC2),
218 CHIP_DEF(PCI_CHIP_R423_UH, R420, CHIP_HAS_CRTC2),
219 CHIP_DEF(PCI_CHIP_R423_UI, R420, CHIP_HAS_CRTC2),
220 CHIP_DEF(PCI_CHIP_R423_UJ, R420, CHIP_HAS_CRTC2),
221 CHIP_DEF(PCI_CHIP_R423_UK, R420, CHIP_HAS_CRTC2),
222 CHIP_DEF(PCI_CHIP_R423_UQ, R420, CHIP_HAS_CRTC2),
223 CHIP_DEF(PCI_CHIP_R423_UR, R420, CHIP_HAS_CRTC2),
224 CHIP_DEF(PCI_CHIP_R423_UT, R420, CHIP_HAS_CRTC2),
225 CHIP_DEF(PCI_CHIP_R423_5D57, R420, CHIP_HAS_CRTC2),
226 /* Original Radeon/7200 */
227 CHIP_DEF(PCI_CHIP_RADEON_QD, RADEON, 0),
228 CHIP_DEF(PCI_CHIP_RADEON_QE, RADEON, 0),
229 CHIP_DEF(PCI_CHIP_RADEON_QF, RADEON, 0),
230 CHIP_DEF(PCI_CHIP_RADEON_QG, RADEON, 0),
231 { 0, }
232 };
233 MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
234
235
236 typedef struct {
237 u16 reg;
238 u32 val;
239 } reg_val;
240
241
242 /* these common regs are cleared before mode setting so they do not
243 * interfere with anything
244 */
245 static reg_val common_regs[] = {
246 { OVR_CLR, 0 },
247 { OVR_WID_LEFT_RIGHT, 0 },
248 { OVR_WID_TOP_BOTTOM, 0 },
249 { OV0_SCALE_CNTL, 0 },
250 { SUBPIC_CNTL, 0 },
251 { VIPH_CONTROL, 0 },
252 { I2C_CNTL_1, 0 },
253 { GEN_INT_CNTL, 0 },
254 { CAP0_TRIG_CNTL, 0 },
255 { CAP1_TRIG_CNTL, 0 },
256 };
257
258 /*
259 * globals
260 */
261
262 static char *mode_option;
263 static char *monitor_layout;
264 static int noaccel = 0;
265 static int default_dynclk = -2;
266 static int nomodeset = 0;
267 static int ignore_edid = 0;
268 static int mirror = 0;
269 static int panel_yres = 0;
270 static int force_dfp = 0;
271 static int force_measure_pll = 0;
272 #ifdef CONFIG_MTRR
273 static int nomtrr = 0;
274 #endif
275 static int force_sleep;
276 static int ignore_devlist;
277 #ifdef CONFIG_PMAC_BACKLIGHT
278 static int backlight = 1;
279 #else
280 static int backlight = 0;
281 #endif
282
283 /*
284 * prototypes
285 */
286
287 static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
288 {
289 if (!rinfo->bios_seg)
290 return;
291 pci_unmap_rom(dev, rinfo->bios_seg);
292 }
293
294 static int __devinit radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
295 {
296 void __iomem *rom;
297 u16 dptr;
298 u8 rom_type;
299 size_t rom_size;
300
301 /* If this is a primary card, there is a shadow copy of the
302 * ROM somewhere in the first meg. We will just ignore the copy
303 * and use the ROM directly.
304 */
305
306 /* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */
307 unsigned int temp;
308 temp = INREG(MPP_TB_CONFIG);
309 temp &= 0x00ffffffu;
310 temp |= 0x04 << 24;
311 OUTREG(MPP_TB_CONFIG, temp);
312 temp = INREG(MPP_TB_CONFIG);
313
314 rom = pci_map_rom(dev, &rom_size);
315 if (!rom) {
316 printk(KERN_ERR "radeonfb (%s): ROM failed to map\n",
317 pci_name(rinfo->pdev));
318 return -ENOMEM;
319 }
320
321 rinfo->bios_seg = rom;
322
323 /* Very simple test to make sure it appeared */
324 if (BIOS_IN16(0) != 0xaa55) {
325 printk(KERN_DEBUG "radeonfb (%s): Invalid ROM signature %x "
326 "should be 0xaa55\n",
327 pci_name(rinfo->pdev), BIOS_IN16(0));
328 goto failed;
329 }
330 /* Look for the PCI data to check the ROM type */
331 dptr = BIOS_IN16(0x18);
332
333 /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
334 * for now, until I've verified this works everywhere. The goal here is more
335 * to phase out Open Firmware images.
336 *
337 * Currently, we only look at the first PCI data, we could iteratre and deal with
338 * them all, and we should use fb_bios_start relative to start of image and not
339 * relative start of ROM, but so far, I never found a dual-image ATI card
340 *
341 * typedef struct {
342 * u32 signature; + 0x00
343 * u16 vendor; + 0x04
344 * u16 device; + 0x06
345 * u16 reserved_1; + 0x08
346 * u16 dlen; + 0x0a
347 * u8 drevision; + 0x0c
348 * u8 class_hi; + 0x0d
349 * u16 class_lo; + 0x0e
350 * u16 ilen; + 0x10
351 * u16 irevision; + 0x12
352 * u8 type; + 0x14
353 * u8 indicator; + 0x15
354 * u16 reserved_2; + 0x16
355 * } pci_data_t;
356 */
357 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
358 printk(KERN_WARNING "radeonfb (%s): PCI DATA signature in ROM"
359 "incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr));
360 goto anyway;
361 }
362 rom_type = BIOS_IN8(dptr + 0x14);
363 switch(rom_type) {
364 case 0:
365 printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n");
366 break;
367 case 1:
368 printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n");
369 goto failed;
370 case 2:
371 printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n");
372 goto failed;
373 default:
374 printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type);
375 goto failed;
376 }
377 anyway:
378 /* Locate the flat panel infos, do some sanity checking !!! */
379 rinfo->fp_bios_start = BIOS_IN16(0x48);
380 return 0;
381
382 failed:
383 rinfo->bios_seg = NULL;
384 radeon_unmap_ROM(rinfo, dev);
385 return -ENXIO;
386 }
387
388 #ifdef CONFIG_X86
389 static int __devinit radeon_find_mem_vbios(struct radeonfb_info *rinfo)
390 {
391 /* I simplified this code as we used to miss the signatures in
392 * a lot of case. It's now closer to XFree, we just don't check
393 * for signatures at all... Something better will have to be done
394 * if we end up having conflicts
395 */
396 u32 segstart;
397 void __iomem *rom_base = NULL;
398
399 for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
400 rom_base = ioremap(segstart, 0x10000);
401 if (rom_base == NULL)
402 return -ENOMEM;
403 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
404 break;
405 iounmap(rom_base);
406 rom_base = NULL;
407 }
408 if (rom_base == NULL)
409 return -ENXIO;
410
411 /* Locate the flat panel infos, do some sanity checking !!! */
412 rinfo->bios_seg = rom_base;
413 rinfo->fp_bios_start = BIOS_IN16(0x48);
414
415 return 0;
416 }
417 #endif
418
419 #if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
420 /*
421 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
422 * tree. Hopefully, ATI OF driver is kind enough to fill these
423 */
424 static int __devinit radeon_read_xtal_OF (struct radeonfb_info *rinfo)
425 {
426 struct device_node *dp = rinfo->of_node;
427 const u32 *val;
428
429 if (dp == NULL)
430 return -ENODEV;
431 val = of_get_property(dp, "ATY,RefCLK", NULL);
432 if (!val || !*val) {
433 printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
434 return -EINVAL;
435 }
436
437 rinfo->pll.ref_clk = (*val) / 10;
438
439 val = of_get_property(dp, "ATY,SCLK", NULL);
440 if (val && *val)
441 rinfo->pll.sclk = (*val) / 10;
442
443 val = of_get_property(dp, "ATY,MCLK", NULL);
444 if (val && *val)
445 rinfo->pll.mclk = (*val) / 10;
446
447 return 0;
448 }
449 #endif /* CONFIG_PPC_OF || CONFIG_SPARC */
450
451 /*
452 * Read PLL infos from chip registers
453 */
454 static int __devinit radeon_probe_pll_params(struct radeonfb_info *rinfo)
455 {
456 unsigned char ppll_div_sel;
457 unsigned Ns, Nm, M;
458 unsigned sclk, mclk, tmp, ref_div;
459 int hTotal, vTotal, num, denom, m, n;
460 unsigned long long hz, vclk;
461 long xtal;
462 struct timeval start_tv, stop_tv;
463 long total_secs, total_usecs;
464 int i;
465
466 /* Ugh, we cut interrupts, bad bad bad, but we want some precision
467 * here, so... --BenH
468 */
469
470 /* Flush PCI buffers ? */
471 tmp = INREG16(DEVICE_ID);
472
473 local_irq_disable();
474
475 for(i=0; i<1000000; i++)
476 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
477 break;
478
479 do_gettimeofday(&start_tv);
480
481 for(i=0; i<1000000; i++)
482 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0)
483 break;
484
485 for(i=0; i<1000000; i++)
486 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
487 break;
488
489 do_gettimeofday(&stop_tv);
490
491 local_irq_enable();
492
493 total_secs = stop_tv.tv_sec - start_tv.tv_sec;
494 if (total_secs > 10)
495 return -1;
496 total_usecs = stop_tv.tv_usec - start_tv.tv_usec;
497 total_usecs += total_secs * 1000000;
498 if (total_usecs < 0)
499 total_usecs = -total_usecs;
500 hz = 1000000/total_usecs;
501
502 hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;
503 vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1);
504 vclk = (long long)hTotal * (long long)vTotal * hz;
505
506 switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) {
507 case 0:
508 default:
509 num = 1;
510 denom = 1;
511 break;
512 case 1:
513 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff);
514 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
515 num = 2*n;
516 denom = 2*m;
517 break;
518 case 2:
519 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff);
520 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
521 num = 2*n;
522 denom = 2*m;
523 break;
524 }
525
526 ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3;
527 radeon_pll_errata_after_index(rinfo);
528
529 n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff);
530 m = (INPLL(PPLL_REF_DIV) & 0x3ff);
531
532 num *= n;
533 denom *= m;
534
535 switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {
536 case 1:
537 denom *= 2;
538 break;
539 case 2:
540 denom *= 4;
541 break;
542 case 3:
543 denom *= 8;
544 break;
545 case 4:
546 denom *= 3;
547 break;
548 case 6:
549 denom *= 6;
550 break;
551 case 7:
552 denom *= 12;
553 break;
554 }
555
556 vclk *= denom;
557 do_div(vclk, 1000 * num);
558 xtal = vclk;
559
560 if ((xtal > 26900) && (xtal < 27100))
561 xtal = 2700;
562 else if ((xtal > 14200) && (xtal < 14400))
563 xtal = 1432;
564 else if ((xtal > 29400) && (xtal < 29600))
565 xtal = 2950;
566 else {
567 printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal);
568 return -1;
569 }
570
571 tmp = INPLL(M_SPLL_REF_FB_DIV);
572 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
573
574 Ns = (tmp & 0xff0000) >> 16;
575 Nm = (tmp & 0xff00) >> 8;
576 M = (tmp & 0xff);
577 sclk = round_div((2 * Ns * xtal), (2 * M));
578 mclk = round_div((2 * Nm * xtal), (2 * M));
579
580 /* we're done, hopefully these are sane values */
581 rinfo->pll.ref_clk = xtal;
582 rinfo->pll.ref_div = ref_div;
583 rinfo->pll.sclk = sclk;
584 rinfo->pll.mclk = mclk;
585
586 return 0;
587 }
588
589 /*
590 * Retrieve PLL infos by different means (BIOS, Open Firmware, register probing...)
591 */
592 static void __devinit radeon_get_pllinfo(struct radeonfb_info *rinfo)
593 {
594 /*
595 * In the case nothing works, these are defaults; they are mostly
596 * incomplete, however. It does provide ppll_max and _min values
597 * even for most other methods, however.
598 */
599 switch (rinfo->chipset) {
600 case PCI_DEVICE_ID_ATI_RADEON_QW:
601 case PCI_DEVICE_ID_ATI_RADEON_QX:
602 rinfo->pll.ppll_max = 35000;
603 rinfo->pll.ppll_min = 12000;
604 rinfo->pll.mclk = 23000;
605 rinfo->pll.sclk = 23000;
606 rinfo->pll.ref_clk = 2700;
607 break;
608 case PCI_DEVICE_ID_ATI_RADEON_QL:
609 case PCI_DEVICE_ID_ATI_RADEON_QN:
610 case PCI_DEVICE_ID_ATI_RADEON_QO:
611 case PCI_DEVICE_ID_ATI_RADEON_Ql:
612 case PCI_DEVICE_ID_ATI_RADEON_BB:
613 rinfo->pll.ppll_max = 35000;
614 rinfo->pll.ppll_min = 12000;
615 rinfo->pll.mclk = 27500;
616 rinfo->pll.sclk = 27500;
617 rinfo->pll.ref_clk = 2700;
618 break;
619 case PCI_DEVICE_ID_ATI_RADEON_Id:
620 case PCI_DEVICE_ID_ATI_RADEON_Ie:
621 case PCI_DEVICE_ID_ATI_RADEON_If:
622 case PCI_DEVICE_ID_ATI_RADEON_Ig:
623 rinfo->pll.ppll_max = 35000;
624 rinfo->pll.ppll_min = 12000;
625 rinfo->pll.mclk = 25000;
626 rinfo->pll.sclk = 25000;
627 rinfo->pll.ref_clk = 2700;
628 break;
629 case PCI_DEVICE_ID_ATI_RADEON_ND:
630 case PCI_DEVICE_ID_ATI_RADEON_NE:
631 case PCI_DEVICE_ID_ATI_RADEON_NF:
632 case PCI_DEVICE_ID_ATI_RADEON_NG:
633 rinfo->pll.ppll_max = 40000;
634 rinfo->pll.ppll_min = 20000;
635 rinfo->pll.mclk = 27000;
636 rinfo->pll.sclk = 27000;
637 rinfo->pll.ref_clk = 2700;
638 break;
639 case PCI_DEVICE_ID_ATI_RADEON_QD:
640 case PCI_DEVICE_ID_ATI_RADEON_QE:
641 case PCI_DEVICE_ID_ATI_RADEON_QF:
642 case PCI_DEVICE_ID_ATI_RADEON_QG:
643 default:
644 rinfo->pll.ppll_max = 35000;
645 rinfo->pll.ppll_min = 12000;
646 rinfo->pll.mclk = 16600;
647 rinfo->pll.sclk = 16600;
648 rinfo->pll.ref_clk = 2700;
649 break;
650 }
651 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
652
653
654 #if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
655 /*
656 * Retrieve PLL infos from Open Firmware first
657 */
658 if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) {
659 printk(KERN_INFO "radeonfb: Retrieved PLL infos from Open Firmware\n");
660 goto found;
661 }
662 #endif /* CONFIG_PPC_OF || CONFIG_SPARC */
663
664 /*
665 * Check out if we have an X86 which gave us some PLL informations
666 * and if yes, retrieve them
667 */
668 if (!force_measure_pll && rinfo->bios_seg) {
669 u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);
670
671 rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08);
672 rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a);
673 rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e);
674 rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10);
675 rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12);
676 rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16);
677
678 printk(KERN_INFO "radeonfb: Retrieved PLL infos from BIOS\n");
679 goto found;
680 }
681
682 /*
683 * We didn't get PLL parameters from either OF or BIOS, we try to
684 * probe them
685 */
686 if (radeon_probe_pll_params(rinfo) == 0) {
687 printk(KERN_INFO "radeonfb: Retrieved PLL infos from registers\n");
688 goto found;
689 }
690
691 /*
692 * Fall back to already-set defaults...
693 */
694 printk(KERN_INFO "radeonfb: Used default PLL infos\n");
695
696 found:
697 /*
698 * Some methods fail to retrieve SCLK and MCLK values, we apply default
699 * settings in this case (200Mhz). If that really happne often, we could
700 * fetch from registers instead...
701 */
702 if (rinfo->pll.mclk == 0)
703 rinfo->pll.mclk = 20000;
704 if (rinfo->pll.sclk == 0)
705 rinfo->pll.sclk = 20000;
706
707 printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n",
708 rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,
709 rinfo->pll.ref_div,
710 rinfo->pll.mclk / 100, rinfo->pll.mclk % 100,
711 rinfo->pll.sclk / 100, rinfo->pll.sclk % 100);
712 printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max);
713 }
714
715 static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
716 {
717 struct radeonfb_info *rinfo = info->par;
718 struct fb_var_screeninfo v;
719 int nom, den;
720 unsigned int pitch;
721
722 if (radeon_match_mode(rinfo, &v, var))
723 return -EINVAL;
724
725 switch (v.bits_per_pixel) {
726 case 0 ... 8:
727 v.bits_per_pixel = 8;
728 break;
729 case 9 ... 16:
730 v.bits_per_pixel = 16;
731 break;
732 case 17 ... 24:
733 #if 0 /* Doesn't seem to work */
734 v.bits_per_pixel = 24;
735 break;
736 #endif
737 return -EINVAL;
738 case 25 ... 32:
739 v.bits_per_pixel = 32;
740 break;
741 default:
742 return -EINVAL;
743 }
744
745 switch (var_to_depth(&v)) {
746 case 8:
747 nom = den = 1;
748 v.red.offset = v.green.offset = v.blue.offset = 0;
749 v.red.length = v.green.length = v.blue.length = 8;
750 v.transp.offset = v.transp.length = 0;
751 break;
752 case 15:
753 nom = 2;
754 den = 1;
755 v.red.offset = 10;
756 v.green.offset = 5;
757 v.blue.offset = 0;
758 v.red.length = v.green.length = v.blue.length = 5;
759 v.transp.offset = v.transp.length = 0;
760 break;
761 case 16:
762 nom = 2;
763 den = 1;
764 v.red.offset = 11;
765 v.green.offset = 5;
766 v.blue.offset = 0;
767 v.red.length = 5;
768 v.green.length = 6;
769 v.blue.length = 5;
770 v.transp.offset = v.transp.length = 0;
771 break;
772 case 24:
773 nom = 4;
774 den = 1;
775 v.red.offset = 16;
776 v.green.offset = 8;
777 v.blue.offset = 0;
778 v.red.length = v.blue.length = v.green.length = 8;
779 v.transp.offset = v.transp.length = 0;
780 break;
781 case 32:
782 nom = 4;
783 den = 1;
784 v.red.offset = 16;
785 v.green.offset = 8;
786 v.blue.offset = 0;
787 v.red.length = v.blue.length = v.green.length = 8;
788 v.transp.offset = 24;
789 v.transp.length = 8;
790 break;
791 default:
792 printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
793 var->xres, var->yres, var->bits_per_pixel);
794 return -EINVAL;
795 }
796
797 if (v.yres_virtual < v.yres)
798 v.yres_virtual = v.yres;
799 if (v.xres_virtual < v.xres)
800 v.xres_virtual = v.xres;
801
802
803 /* XXX I'm adjusting xres_virtual to the pitch, that may help XFree
804 * with some panels, though I don't quite like this solution
805 */
806 if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) {
807 v.xres_virtual = v.xres_virtual & ~7ul;
808 } else {
809 pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f)
810 & ~(0x3f)) >> 6;
811 v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8);
812 }
813
814 if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram)
815 return -EINVAL;
816
817 if (v.xres_virtual < v.xres)
818 v.xres = v.xres_virtual;
819
820 if (v.xoffset < 0)
821 v.xoffset = 0;
822 if (v.yoffset < 0)
823 v.yoffset = 0;
824
825 if (v.xoffset > v.xres_virtual - v.xres)
826 v.xoffset = v.xres_virtual - v.xres - 1;
827
828 if (v.yoffset > v.yres_virtual - v.yres)
829 v.yoffset = v.yres_virtual - v.yres - 1;
830
831 v.red.msb_right = v.green.msb_right = v.blue.msb_right =
832 v.transp.offset = v.transp.length =
833 v.transp.msb_right = 0;
834
835 memcpy(var, &v, sizeof(v));
836
837 return 0;
838 }
839
840
841 static int radeonfb_pan_display (struct fb_var_screeninfo *var,
842 struct fb_info *info)
843 {
844 struct radeonfb_info *rinfo = info->par;
845
846 if ((var->xoffset + var->xres > var->xres_virtual)
847 || (var->yoffset + var->yres > var->yres_virtual))
848 return -EINVAL;
849
850 if (rinfo->asleep)
851 return 0;
852
853 radeon_fifo_wait(2);
854 OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
855 * var->bits_per_pixel / 8) & ~7);
856 return 0;
857 }
858
859
860 static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd,
861 unsigned long arg)
862 {
863 struct radeonfb_info *rinfo = info->par;
864 unsigned int tmp;
865 u32 value = 0;
866 int rc;
867
868 switch (cmd) {
869 /*
870 * TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's
871 * and do something better using 2nd CRTC instead of just hackish
872 * routing to second output
873 */
874 case FBIO_RADEON_SET_MIRROR:
875 if (!rinfo->is_mobility)
876 return -EINVAL;
877
878 rc = get_user(value, (__u32 __user *)arg);
879
880 if (rc)
881 return rc;
882
883 radeon_fifo_wait(2);
884 if (value & 0x01) {
885 tmp = INREG(LVDS_GEN_CNTL);
886
887 tmp |= (LVDS_ON | LVDS_BLON);
888 } else {
889 tmp = INREG(LVDS_GEN_CNTL);
890
891 tmp &= ~(LVDS_ON | LVDS_BLON);
892 }
893
894 OUTREG(LVDS_GEN_CNTL, tmp);
895
896 if (value & 0x02) {
897 tmp = INREG(CRTC_EXT_CNTL);
898 tmp |= CRTC_CRT_ON;
899
900 mirror = 1;
901 } else {
902 tmp = INREG(CRTC_EXT_CNTL);
903 tmp &= ~CRTC_CRT_ON;
904
905 mirror = 0;
906 }
907
908 OUTREG(CRTC_EXT_CNTL, tmp);
909
910 return 0;
911 case FBIO_RADEON_GET_MIRROR:
912 if (!rinfo->is_mobility)
913 return -EINVAL;
914
915 tmp = INREG(LVDS_GEN_CNTL);
916 if ((LVDS_ON | LVDS_BLON) & tmp)
917 value |= 0x01;
918
919 tmp = INREG(CRTC_EXT_CNTL);
920 if (CRTC_CRT_ON & tmp)
921 value |= 0x02;
922
923 return put_user(value, (__u32 __user *)arg);
924 default:
925 return -EINVAL;
926 }
927
928 return -EINVAL;
929 }
930
931
932 int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
933 {
934 u32 val;
935 u32 tmp_pix_clks;
936 int unblank = 0;
937
938 if (rinfo->lock_blank)
939 return 0;
940
941 radeon_engine_idle();
942
943 val = INREG(CRTC_EXT_CNTL);
944 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
945 CRTC_VSYNC_DIS);
946 switch (blank) {
947 case FB_BLANK_VSYNC_SUSPEND:
948 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
949 break;
950 case FB_BLANK_HSYNC_SUSPEND:
951 val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
952 break;
953 case FB_BLANK_POWERDOWN:
954 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
955 CRTC_HSYNC_DIS);
956 break;
957 case FB_BLANK_NORMAL:
958 val |= CRTC_DISPLAY_DIS;
959 break;
960 case FB_BLANK_UNBLANK:
961 default:
962 unblank = 1;
963 }
964 OUTREG(CRTC_EXT_CNTL, val);
965
966
967 switch (rinfo->mon1_type) {
968 case MT_DFP:
969 if (unblank)
970 OUTREGP(FP_GEN_CNTL, (FP_FPON | FP_TMDS_EN),
971 ~(FP_FPON | FP_TMDS_EN));
972 else {
973 if (mode_switch || blank == FB_BLANK_NORMAL)
974 break;
975 OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN));
976 }
977 break;
978 case MT_LCD:
979 del_timer_sync(&rinfo->lvds_timer);
980 val = INREG(LVDS_GEN_CNTL);
981 if (unblank) {
982 u32 target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON
983 | LVDS_EN | (rinfo->init_state.lvds_gen_cntl
984 & (LVDS_DIGON | LVDS_BL_MOD_EN));
985 if ((val ^ target_val) == LVDS_DISPLAY_DIS)
986 OUTREG(LVDS_GEN_CNTL, target_val);
987 else if ((val ^ target_val) != 0) {
988 OUTREG(LVDS_GEN_CNTL, target_val
989 & ~(LVDS_ON | LVDS_BL_MOD_EN));
990 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
991 rinfo->init_state.lvds_gen_cntl |=
992 target_val & LVDS_STATE_MASK;
993 if (mode_switch) {
994 radeon_msleep(rinfo->panel_info.pwr_delay);
995 OUTREG(LVDS_GEN_CNTL, target_val);
996 }
997 else {
998 rinfo->pending_lvds_gen_cntl = target_val;
999 mod_timer(&rinfo->lvds_timer,
1000 jiffies +
1001 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1002 }
1003 }
1004 } else {
1005 val |= LVDS_DISPLAY_DIS;
1006 OUTREG(LVDS_GEN_CNTL, val);
1007
1008 /* We don't do a full switch-off on a simple mode switch */
1009 if (mode_switch || blank == FB_BLANK_NORMAL)
1010 break;
1011
1012 /* Asic bug, when turning off LVDS_ON, we have to make sure
1013 * RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
1014 */
1015 tmp_pix_clks = INPLL(PIXCLKS_CNTL);
1016 if (rinfo->is_mobility || rinfo->is_IGP)
1017 OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1018 val &= ~(LVDS_BL_MOD_EN);
1019 OUTREG(LVDS_GEN_CNTL, val);
1020 udelay(100);
1021 val &= ~(LVDS_ON | LVDS_EN);
1022 OUTREG(LVDS_GEN_CNTL, val);
1023 val &= ~LVDS_DIGON;
1024 rinfo->pending_lvds_gen_cntl = val;
1025 mod_timer(&rinfo->lvds_timer,
1026 jiffies +
1027 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1028 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1029 rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK;
1030 if (rinfo->is_mobility || rinfo->is_IGP)
1031 OUTPLL(PIXCLKS_CNTL, tmp_pix_clks);
1032 }
1033 break;
1034 case MT_CRT:
1035 // todo: powerdown DAC
1036 default:
1037 break;
1038 }
1039
1040 return 0;
1041 }
1042
1043 static int radeonfb_blank (int blank, struct fb_info *info)
1044 {
1045 struct radeonfb_info *rinfo = info->par;
1046
1047 if (rinfo->asleep)
1048 return 0;
1049
1050 return radeon_screen_blank(rinfo, blank, 0);
1051 }
1052
1053 static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
1054 unsigned blue, unsigned transp,
1055 struct radeonfb_info *rinfo)
1056 {
1057 u32 pindex;
1058 unsigned int i;
1059
1060
1061 if (regno > 255)
1062 return -EINVAL;
1063
1064 red >>= 8;
1065 green >>= 8;
1066 blue >>= 8;
1067 rinfo->palette[regno].red = red;
1068 rinfo->palette[regno].green = green;
1069 rinfo->palette[regno].blue = blue;
1070
1071 /* default */
1072 pindex = regno;
1073
1074 if (!rinfo->asleep) {
1075 radeon_fifo_wait(9);
1076
1077 if (rinfo->bpp == 16) {
1078 pindex = regno * 8;
1079
1080 if (rinfo->depth == 16 && regno > 63)
1081 return -EINVAL;
1082 if (rinfo->depth == 15 && regno > 31)
1083 return -EINVAL;
1084
1085 /* For 565, the green component is mixed one order
1086 * below
1087 */
1088 if (rinfo->depth == 16) {
1089 OUTREG(PALETTE_INDEX, pindex>>1);
1090 OUTREG(PALETTE_DATA,
1091 (rinfo->palette[regno>>1].red << 16) |
1092 (green << 8) |
1093 (rinfo->palette[regno>>1].blue));
1094 green = rinfo->palette[regno<<1].green;
1095 }
1096 }
1097
1098 if (rinfo->depth != 16 || regno < 32) {
1099 OUTREG(PALETTE_INDEX, pindex);
1100 OUTREG(PALETTE_DATA, (red << 16) |
1101 (green << 8) | blue);
1102 }
1103 }
1104 if (regno < 16) {
1105 u32 *pal = rinfo->info->pseudo_palette;
1106 switch (rinfo->depth) {
1107 case 15:
1108 pal[regno] = (regno << 10) | (regno << 5) | regno;
1109 break;
1110 case 16:
1111 pal[regno] = (regno << 11) | (regno << 5) | regno;
1112 break;
1113 case 24:
1114 pal[regno] = (regno << 16) | (regno << 8) | regno;
1115 break;
1116 case 32:
1117 i = (regno << 8) | regno;
1118 pal[regno] = (i << 16) | i;
1119 break;
1120 }
1121 }
1122 return 0;
1123 }
1124
1125 static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1126 unsigned blue, unsigned transp,
1127 struct fb_info *info)
1128 {
1129 struct radeonfb_info *rinfo = info->par;
1130 u32 dac_cntl2, vclk_cntl = 0;
1131 int rc;
1132
1133 if (!rinfo->asleep) {
1134 if (rinfo->is_mobility) {
1135 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1136 OUTPLL(VCLK_ECP_CNTL,
1137 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1138 }
1139
1140 /* Make sure we are on first palette */
1141 if (rinfo->has_CRTC2) {
1142 dac_cntl2 = INREG(DAC_CNTL2);
1143 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1144 OUTREG(DAC_CNTL2, dac_cntl2);
1145 }
1146 }
1147
1148 rc = radeon_setcolreg (regno, red, green, blue, transp, rinfo);
1149
1150 if (!rinfo->asleep && rinfo->is_mobility)
1151 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1152
1153 return rc;
1154 }
1155
1156 static int radeonfb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
1157 {
1158 struct radeonfb_info *rinfo = info->par;
1159 u16 *red, *green, *blue, *transp;
1160 u32 dac_cntl2, vclk_cntl = 0;
1161 int i, start, rc = 0;
1162
1163 if (!rinfo->asleep) {
1164 if (rinfo->is_mobility) {
1165 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1166 OUTPLL(VCLK_ECP_CNTL,
1167 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1168 }
1169
1170 /* Make sure we are on first palette */
1171 if (rinfo->has_CRTC2) {
1172 dac_cntl2 = INREG(DAC_CNTL2);
1173 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1174 OUTREG(DAC_CNTL2, dac_cntl2);
1175 }
1176 }
1177
1178 red = cmap->red;
1179 green = cmap->green;
1180 blue = cmap->blue;
1181 transp = cmap->transp;
1182 start = cmap->start;
1183
1184 for (i = 0; i < cmap->len; i++) {
1185 u_int hred, hgreen, hblue, htransp = 0xffff;
1186
1187 hred = *red++;
1188 hgreen = *green++;
1189 hblue = *blue++;
1190 if (transp)
1191 htransp = *transp++;
1192 rc = radeon_setcolreg (start++, hred, hgreen, hblue, htransp,
1193 rinfo);
1194 if (rc)
1195 break;
1196 }
1197
1198 if (!rinfo->asleep && rinfo->is_mobility)
1199 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1200
1201 return rc;
1202 }
1203
1204 static void radeon_save_state (struct radeonfb_info *rinfo,
1205 struct radeon_regs *save)
1206 {
1207 /* CRTC regs */
1208 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1209 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1210 save->crtc_more_cntl = INREG(CRTC_MORE_CNTL);
1211 save->dac_cntl = INREG(DAC_CNTL);
1212 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
1213 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
1214 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
1215 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
1216 save->crtc_pitch = INREG(CRTC_PITCH);
1217 save->surface_cntl = INREG(SURFACE_CNTL);
1218
1219 /* FP regs */
1220 save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
1221 save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
1222 save->fp_gen_cntl = INREG(FP_GEN_CNTL);
1223 save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
1224 save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
1225 save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
1226 save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
1227 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1228 save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
1229 save->tmds_crc = INREG(TMDS_CRC);
1230 save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
1231 save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
1232
1233 /* PLL regs */
1234 save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f;
1235 radeon_pll_errata_after_index(rinfo);
1236 save->ppll_div_3 = INPLL(PPLL_DIV_3);
1237 save->ppll_ref_div = INPLL(PPLL_REF_DIV);
1238 }
1239
1240
1241 static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
1242 {
1243 int i;
1244
1245 radeon_fifo_wait(20);
1246
1247 /* Workaround from XFree */
1248 if (rinfo->is_mobility) {
1249 /* A temporal workaround for the occational blanking on certain laptop
1250 * panels. This appears to related to the PLL divider registers
1251 * (fail to lock?). It occurs even when all dividers are the same
1252 * with their old settings. In this case we really don't need to
1253 * fiddle with PLL registers. By doing this we can avoid the blanking
1254 * problem with some panels.
1255 */
1256 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
1257 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
1258 (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
1259 /* We still have to force a switch to selected PPLL div thanks to
1260 * an XFree86 driver bug which will switch it away in some cases
1261 * even when using UseFDev */
1262 OUTREGP(CLOCK_CNTL_INDEX,
1263 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1264 ~PPLL_DIV_SEL_MASK);
1265 radeon_pll_errata_after_index(rinfo);
1266 radeon_pll_errata_after_data(rinfo);
1267 return;
1268 }
1269 }
1270
1271 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
1272 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
1273
1274 /* Reset PPLL & enable atomic update */
1275 OUTPLLP(PPLL_CNTL,
1276 PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
1277 ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1278
1279 /* Switch to selected PPLL divider */
1280 OUTREGP(CLOCK_CNTL_INDEX,
1281 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1282 ~PPLL_DIV_SEL_MASK);
1283 radeon_pll_errata_after_index(rinfo);
1284 radeon_pll_errata_after_data(rinfo);
1285
1286 /* Set PPLL ref. div */
1287 if (rinfo->family == CHIP_FAMILY_R300 ||
1288 rinfo->family == CHIP_FAMILY_RS300 ||
1289 rinfo->family == CHIP_FAMILY_R350 ||
1290 rinfo->family == CHIP_FAMILY_RV350 ||
1291 rinfo->family == CHIP_FAMILY_RV380 ) {
1292 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
1293 /* When restoring console mode, use saved PPLL_REF_DIV
1294 * setting.
1295 */
1296 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
1297 } else {
1298 /* R300 uses ref_div_acc field as real ref divider */
1299 OUTPLLP(PPLL_REF_DIV,
1300 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
1301 ~R300_PPLL_REF_DIV_ACC_MASK);
1302 }
1303 } else
1304 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
1305
1306 /* Set PPLL divider 3 & post divider*/
1307 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
1308 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
1309
1310 /* Write update */
1311 while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)
1312 ;
1313 OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
1314
1315 /* Wait read update complete */
1316 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
1317 the cause yet, but this workaround will mask the problem for now.
1318 Other chips usually will pass at the very first test, so the
1319 workaround shouldn't have any effect on them. */
1320 for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)
1321 ;
1322
1323 OUTPLL(HTOTAL_CNTL, 0);
1324
1325 /* Clear reset & atomic update */
1326 OUTPLLP(PPLL_CNTL, 0,
1327 ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1328
1329 /* We may want some locking ... oh well */
1330 radeon_msleep(5);
1331
1332 /* Switch back VCLK source to PPLL */
1333 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
1334 }
1335
1336 /*
1337 * Timer function for delayed LVDS panel power up/down
1338 */
1339 static void radeon_lvds_timer_func(unsigned long data)
1340 {
1341 struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1342
1343 radeon_engine_idle();
1344
1345 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
1346 }
1347
1348 /*
1349 * Apply a video mode. This will apply the whole register set, including
1350 * the PLL registers, to the card
1351 */
1352 void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1353 int regs_only)
1354 {
1355 int i;
1356 int primary_mon = PRIMARY_MONITOR(rinfo);
1357
1358 if (nomodeset)
1359 return;
1360
1361 if (!regs_only)
1362 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);
1363
1364 radeon_fifo_wait(31);
1365 for (i=0; i<10; i++)
1366 OUTREG(common_regs[i].reg, common_regs[i].val);
1367
1368 /* Apply surface registers */
1369 for (i=0; i<8; i++) {
1370 OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);
1371 OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);
1372 OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]);
1373 }
1374
1375 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
1376 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
1377 ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
1378 OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl);
1379 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
1380 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
1381 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
1382 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
1383 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
1384 OUTREG(CRTC_OFFSET, 0);
1385 OUTREG(CRTC_OFFSET_CNTL, 0);
1386 OUTREG(CRTC_PITCH, mode->crtc_pitch);
1387 OUTREG(SURFACE_CNTL, mode->surface_cntl);
1388
1389 radeon_write_pll_regs(rinfo, mode);
1390
1391 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1392 radeon_fifo_wait(10);
1393 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
1394 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
1395 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
1396 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
1397 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
1398 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
1399 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
1400 OUTREG(TMDS_CRC, mode->tmds_crc);
1401 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
1402 }
1403
1404 if (!regs_only)
1405 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);
1406
1407 radeon_fifo_wait(2);
1408 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
1409
1410 return;
1411 }
1412
1413 /*
1414 * Calculate the PLL values for a given mode
1415 */
1416 static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs,
1417 unsigned long freq)
1418 {
1419 const struct {
1420 int divider;
1421 int bitvalue;
1422 } *post_div,
1423 post_divs[] = {
1424 { 1, 0 },
1425 { 2, 1 },
1426 { 4, 2 },
1427 { 8, 3 },
1428 { 3, 4 },
1429 { 16, 5 },
1430 { 6, 6 },
1431 { 12, 7 },
1432 { 0, 0 },
1433 };
1434 int fb_div, pll_output_freq = 0;
1435 int uses_dvo = 0;
1436
1437 /* Check if the DVO port is enabled and sourced from the primary CRTC. I'm
1438 * not sure which model starts having FP2_GEN_CNTL, I assume anything more
1439 * recent than an r(v)100...
1440 */
1441 #if 1
1442 /* XXX I had reports of flicker happening with the cinema display
1443 * on TMDS1 that seem to be fixed if I also forbit odd dividers in
1444 * this case. This could just be a bandwidth calculation issue, I
1445 * haven't implemented the bandwidth code yet, but in the meantime,
1446 * forcing uses_dvo to 1 fixes it and shouln't have bad side effects,
1447 * I haven't seen a case were were absolutely needed an odd PLL
1448 * divider. I'll find a better fix once I have more infos on the
1449 * real cause of the problem.
1450 */
1451 while (rinfo->has_CRTC2) {
1452 u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL);
1453 u32 disp_output_cntl;
1454 int source;
1455
1456 /* FP2 path not enabled */
1457 if ((fp2_gen_cntl & FP2_ON) == 0)
1458 break;
1459 /* Not all chip revs have the same format for this register,
1460 * extract the source selection
1461 */
1462 if (rinfo->family == CHIP_FAMILY_R200 ||
1463 rinfo->family == CHIP_FAMILY_R300 ||
1464 rinfo->family == CHIP_FAMILY_R350 ||
1465 rinfo->family == CHIP_FAMILY_RV350) {
1466 source = (fp2_gen_cntl >> 10) & 0x3;
1467 /* sourced from transform unit, check for transform unit
1468 * own source
1469 */
1470 if (source == 3) {
1471 disp_output_cntl = INREG(DISP_OUTPUT_CNTL);
1472 source = (disp_output_cntl >> 12) & 0x3;
1473 }
1474 } else
1475 source = (fp2_gen_cntl >> 13) & 0x1;
1476 /* sourced from CRTC2 -> exit */
1477 if (source == 1)
1478 break;
1479
1480 /* so we end up on CRTC1, let's set uses_dvo to 1 now */
1481 uses_dvo = 1;
1482 break;
1483 }
1484 #else
1485 uses_dvo = 1;
1486 #endif
1487 if (freq > rinfo->pll.ppll_max)
1488 freq = rinfo->pll.ppll_max;
1489 if (freq*12 < rinfo->pll.ppll_min)
1490 freq = rinfo->pll.ppll_min / 12;
1491 RTRACE("freq = %lu, PLL min = %u, PLL max = %u\n",
1492 freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max);
1493
1494 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1495 pll_output_freq = post_div->divider * freq;
1496 /* If we output to the DVO port (external TMDS), we don't allow an
1497 * odd PLL divider as those aren't supported on this path
1498 */
1499 if (uses_dvo && (post_div->divider & 1))
1500 continue;
1501 if (pll_output_freq >= rinfo->pll.ppll_min &&
1502 pll_output_freq <= rinfo->pll.ppll_max)
1503 break;
1504 }
1505
1506 /* If we fall through the bottom, try the "default value"
1507 given by the terminal post_div->bitvalue */
1508 if ( !post_div->divider ) {
1509 post_div = &post_divs[post_div->bitvalue];
1510 pll_output_freq = post_div->divider * freq;
1511 }
1512 RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1513 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1514 pll_output_freq);
1515
1516 /* If we fall through the bottom, try the "default value"
1517 given by the terminal post_div->bitvalue */
1518 if ( !post_div->divider ) {
1519 post_div = &post_divs[post_div->bitvalue];
1520 pll_output_freq = post_div->divider * freq;
1521 }
1522 RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1523 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1524 pll_output_freq);
1525
1526 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,
1527 rinfo->pll.ref_clk);
1528 regs->ppll_ref_div = rinfo->pll.ref_div;
1529 regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16);
1530
1531 RTRACE("post div = 0x%x\n", post_div->bitvalue);
1532 RTRACE("fb_div = 0x%x\n", fb_div);
1533 RTRACE("ppll_div_3 = 0x%x\n", regs->ppll_div_3);
1534 }
1535
1536 static int radeonfb_set_par(struct fb_info *info)
1537 {
1538 struct radeonfb_info *rinfo = info->par;
1539 struct fb_var_screeninfo *mode = &info->var;
1540 struct radeon_regs *newmode;
1541 int hTotal, vTotal, hSyncStart, hSyncEnd,
1542 hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
1543 u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
1544 u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
1545 u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock;
1546 int i, freq;
1547 int format = 0;
1548 int nopllcalc = 0;
1549 int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
1550 int primary_mon = PRIMARY_MONITOR(rinfo);
1551 int depth = var_to_depth(mode);
1552 int use_rmx = 0;
1553
1554 newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL);
1555 if (!newmode)
1556 return -ENOMEM;
1557
1558 /* We always want engine to be idle on a mode switch, even
1559 * if we won't actually change the mode
1560 */
1561 radeon_engine_idle();
1562
1563 hSyncStart = mode->xres + mode->right_margin;
1564 hSyncEnd = hSyncStart + mode->hsync_len;
1565 hTotal = hSyncEnd + mode->left_margin;
1566
1567 vSyncStart = mode->yres + mode->lower_margin;
1568 vSyncEnd = vSyncStart + mode->vsync_len;
1569 vTotal = vSyncEnd + mode->upper_margin;
1570 pixClock = mode->pixclock;
1571
1572 sync = mode->sync;
1573 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1574 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1575
1576 if (primary_mon == MT_DFP || primary_mon == MT_LCD) {
1577 if (rinfo->panel_info.xres < mode->xres)
1578 mode->xres = rinfo->panel_info.xres;
1579 if (rinfo->panel_info.yres < mode->yres)
1580 mode->yres = rinfo->panel_info.yres;
1581
1582 hTotal = mode->xres + rinfo->panel_info.hblank;
1583 hSyncStart = mode->xres + rinfo->panel_info.hOver_plus;
1584 hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width;
1585
1586 vTotal = mode->yres + rinfo->panel_info.vblank;
1587 vSyncStart = mode->yres + rinfo->panel_info.vOver_plus;
1588 vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width;
1589
1590 h_sync_pol = !rinfo->panel_info.hAct_high;
1591 v_sync_pol = !rinfo->panel_info.vAct_high;
1592
1593 pixClock = 100000000 / rinfo->panel_info.clock;
1594
1595 if (rinfo->panel_info.use_bios_dividers) {
1596 nopllcalc = 1;
1597 newmode->ppll_div_3 = rinfo->panel_info.fbk_divider |
1598 (rinfo->panel_info.post_divider << 16);
1599 newmode->ppll_ref_div = rinfo->panel_info.ref_divider;
1600 }
1601 }
1602 dotClock = 1000000000 / pixClock;
1603 freq = dotClock / 10; /* x100 */
1604
1605 RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",
1606 hSyncStart, hSyncEnd, hTotal);
1607 RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",
1608 vSyncStart, vSyncEnd, vTotal);
1609
1610 hsync_wid = (hSyncEnd - hSyncStart) / 8;
1611 vsync_wid = vSyncEnd - vSyncStart;
1612 if (hsync_wid == 0)
1613 hsync_wid = 1;
1614 else if (hsync_wid > 0x3f) /* max */
1615 hsync_wid = 0x3f;
1616
1617 if (vsync_wid == 0)
1618 vsync_wid = 1;
1619 else if (vsync_wid > 0x1f) /* max */
1620 vsync_wid = 0x1f;
1621
1622 hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1623 vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1624
1625 cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1626
1627 format = radeon_get_dstbpp(depth);
1628 bytpp = mode->bits_per_pixel >> 3;
1629
1630 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
1631 hsync_fudge = hsync_fudge_fp[format-1];
1632 else
1633 hsync_fudge = hsync_adj_tab[format-1];
1634
1635 hsync_start = hSyncStart - 8 + hsync_fudge;
1636
1637 newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
1638 (format << 8);
1639
1640 /* Clear auto-center etc... */
1641 newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;
1642 newmode->crtc_more_cntl &= 0xfffffff0;
1643
1644 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1645 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
1646 if (mirror)
1647 newmode->crtc_ext_cntl |= CRTC_CRT_ON;
1648
1649 newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
1650 CRTC_INTERLACE_EN);
1651 } else {
1652 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
1653 CRTC_CRT_ON;
1654 }
1655
1656 newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
1657 DAC_8BIT_EN;
1658
1659 newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
1660 (((mode->xres / 8) - 1) << 16));
1661
1662 newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
1663 (hsync_wid << 16) | (h_sync_pol << 23));
1664
1665 newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
1666 ((mode->yres - 1) << 16);
1667
1668 newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
1669 (vsync_wid << 16) | (v_sync_pol << 23));
1670
1671 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
1672 /* We first calculate the engine pitch */
1673 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1674 & ~(0x3f)) >> 6;
1675
1676 /* Then, re-multiply it to get the CRTC pitch */
1677 newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
1678 } else
1679 newmode->crtc_pitch = (mode->xres_virtual >> 3);
1680
1681 newmode->crtc_pitch |= (newmode->crtc_pitch << 16);
1682
1683 /*
1684 * It looks like recent chips have a problem with SURFACE_CNTL,
1685 * setting SURF_TRANSLATION_DIS completely disables the
1686 * swapper as well, so we leave it unset now.
1687 */
1688 newmode->surface_cntl = 0;
1689
1690 #if defined(__BIG_ENDIAN)
1691
1692 /* Setup swapping on both apertures, though we currently
1693 * only use aperture 0, enabling swapper on aperture 1
1694 * won't harm
1695 */
1696 switch (mode->bits_per_pixel) {
1697 case 16:
1698 newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP;
1699 newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP;
1700 break;
1701 case 24:
1702 case 32:
1703 newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP;
1704 newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP;
1705 break;
1706 }
1707 #endif
1708
1709 /* Clear surface registers */
1710 for (i=0; i<8; i++) {
1711 newmode->surf_lower_bound[i] = 0;
1712 newmode->surf_upper_bound[i] = 0x1f;
1713 newmode->surf_info[i] = 0;
1714 }
1715
1716 RTRACE("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
1717 newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid);
1718 RTRACE("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
1719 newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid);
1720
1721 rinfo->bpp = mode->bits_per_pixel;
1722 rinfo->depth = depth;
1723
1724 RTRACE("pixclock = %lu\n", (unsigned long)pixClock);
1725 RTRACE("freq = %lu\n", (unsigned long)freq);
1726
1727 /* We use PPLL_DIV_3 */
1728 newmode->clk_cntl_index = 0x300;
1729
1730 /* Calculate PPLL value if necessary */
1731 if (!nopllcalc)
1732 radeon_calc_pll_regs(rinfo, newmode, freq);
1733
1734 newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1735
1736 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1737 unsigned int hRatio, vRatio;
1738
1739 if (mode->xres > rinfo->panel_info.xres)
1740 mode->xres = rinfo->panel_info.xres;
1741 if (mode->yres > rinfo->panel_info.yres)
1742 mode->yres = rinfo->panel_info.yres;
1743
1744 newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1)
1745 << HORZ_PANEL_SHIFT);
1746 newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1)
1747 << VERT_PANEL_SHIFT);
1748
1749 if (mode->xres != rinfo->panel_info.xres) {
1750 hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
1751 rinfo->panel_info.xres);
1752 newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
1753 (newmode->fp_horz_stretch &
1754 (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
1755 HORZ_AUTO_RATIO_INC)));
1756 newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND |
1757 HORZ_STRETCH_ENABLE);
1758 use_rmx = 1;
1759 }
1760 newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO;
1761
1762 if (mode->yres != rinfo->panel_info.yres) {
1763 vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
1764 rinfo->panel_info.yres);
1765 newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
1766 (newmode->fp_vert_stretch &
1767 (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
1768 newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND |
1769 VERT_STRETCH_ENABLE);
1770 use_rmx = 1;
1771 }
1772 newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
1773
1774 newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
1775 ~(FP_SEL_CRTC2 |
1776 FP_RMX_HVSYNC_CONTROL_EN |
1777 FP_DFP_SYNC_SEL |
1778 FP_CRT_SYNC_SEL |
1779 FP_CRTC_LOCK_8DOT |
1780 FP_USE_SHADOW_EN |
1781 FP_CRTC_USE_SHADOW_VEND |
1782 FP_CRT_SYNC_ALT));
1783
1784 newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
1785 FP_CRTC_DONT_SHADOW_HEND |
1786 FP_PANEL_FORMAT);
1787
1788 if (IS_R300_VARIANT(rinfo) ||
1789 (rinfo->family == CHIP_FAMILY_R200)) {
1790 newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
1791 if (use_rmx)
1792 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
1793 else
1794 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
1795 } else
1796 newmode->fp_gen_cntl |= FP_SEL_CRTC1;
1797
1798 newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
1799 newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
1800 newmode->tmds_crc = rinfo->init_state.tmds_crc;
1801 newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
1802
1803 if (primary_mon == MT_LCD) {
1804 newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
1805 newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
1806 } else {
1807 /* DFP */
1808 newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
1809 newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST);
1810 /* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */
1811 if (IS_R300_VARIANT(rinfo) ||
1812 (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2)
1813 newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN;
1814 else
1815 newmode->tmds_transmitter_cntl |= TMDS_PLL_EN;
1816 newmode->crtc_ext_cntl &= ~CRTC_CRT_ON;
1817 }
1818
1819 newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) |
1820 (((mode->xres / 8) - 1) << 16));
1821 newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) |
1822 ((mode->yres - 1) << 16);
1823 newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) |
1824 (hsync_wid << 16) | (h_sync_pol << 23));
1825 newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) |
1826 (vsync_wid << 16) | (v_sync_pol << 23));
1827 }
1828
1829 /* do it! */
1830 if (!rinfo->asleep) {
1831 memcpy(&rinfo->state, newmode, sizeof(*newmode));
1832 radeon_write_mode (rinfo, newmode, 0);
1833 /* (re)initialize the engine */
1834 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1835 radeonfb_engine_init (rinfo);
1836 }
1837 /* Update fix */
1838 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1839 info->fix.line_length = rinfo->pitch*64;
1840 else
1841 info->fix.line_length = mode->xres_virtual
1842 * ((mode->bits_per_pixel + 1) / 8);
1843 info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR
1844 : FB_VISUAL_DIRECTCOLOR;
1845
1846 #ifdef CONFIG_BOOTX_TEXT
1847 /* Update debug text engine */
1848 btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
1849 rinfo->depth, info->fix.line_length);
1850 #endif
1851
1852 kfree(newmode);
1853 return 0;
1854 }
1855
1856
1857 static struct fb_ops radeonfb_ops = {
1858 .owner = THIS_MODULE,
1859 .fb_check_var = radeonfb_check_var,
1860 .fb_set_par = radeonfb_set_par,
1861 .fb_setcolreg = radeonfb_setcolreg,
1862 .fb_setcmap = radeonfb_setcmap,
1863 .fb_pan_display = radeonfb_pan_display,
1864 .fb_blank = radeonfb_blank,
1865 .fb_ioctl = radeonfb_ioctl,
1866 .fb_sync = radeonfb_sync,
1867 .fb_fillrect = radeonfb_fillrect,
1868 .fb_copyarea = radeonfb_copyarea,
1869 .fb_imageblit = radeonfb_imageblit,
1870 };
1871
1872
1873 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
1874 {
1875 struct fb_info *info = rinfo->info;
1876
1877 info->par = rinfo;
1878 info->pseudo_palette = rinfo->pseudo_palette;
1879 info->flags = FBINFO_DEFAULT
1880 | FBINFO_HWACCEL_COPYAREA
1881 | FBINFO_HWACCEL_FILLRECT
1882 | FBINFO_HWACCEL_XPAN
1883 | FBINFO_HWACCEL_YPAN;
1884 info->fbops = &radeonfb_ops;
1885 info->screen_base = rinfo->fb_base;
1886 info->screen_size = rinfo->mapped_vram;
1887 /* Fill fix common fields */
1888 strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
1889 info->fix.smem_start = rinfo->fb_base_phys;
1890 info->fix.smem_len = rinfo->video_ram;
1891 info->fix.type = FB_TYPE_PACKED_PIXELS;
1892 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1893 info->fix.xpanstep = 8;
1894 info->fix.ypanstep = 1;
1895 info->fix.ywrapstep = 0;
1896 info->fix.type_aux = 0;
1897 info->fix.mmio_start = rinfo->mmio_base_phys;
1898 info->fix.mmio_len = RADEON_REGSIZE;
1899 info->fix.accel = FB_ACCEL_ATI_RADEON;
1900
1901 fb_alloc_cmap(&info->cmap, 256, 0);
1902
1903 if (noaccel)
1904 info->flags |= FBINFO_HWACCEL_DISABLED;
1905
1906 return 0;
1907 }
1908
1909 /*
1910 * This reconfigure the card's internal memory map. In theory, we'd like
1911 * to setup the card's memory at the same address as it's PCI bus address,
1912 * and the AGP aperture right after that so that system RAM on 32 bits
1913 * machines at least, is directly accessible. However, doing so would
1914 * conflict with the current XFree drivers...
1915 * Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree
1916 * on the proper way to set this up and duplicate this here. In the meantime,
1917 * I put the card's memory at 0 in card space and AGP at some random high
1918 * local (0xe0000000 for now) that will be changed by XFree/DRI anyway
1919 */
1920 #ifdef CONFIG_PPC_OF
1921 #undef SET_MC_FB_FROM_APERTURE
1922 static void fixup_memory_mappings(struct radeonfb_info *rinfo)
1923 {
1924 u32 save_crtc_gen_cntl, save_crtc2_gen_cntl = 0;
1925 u32 save_crtc_ext_cntl;
1926 u32 aper_base, aper_size;
1927 u32 agp_base;
1928
1929 /* First, we disable display to avoid interfering */
1930 if (rinfo->has_CRTC2) {
1931 save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL);
1932 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B);
1933 }
1934 save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1935 save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1936
1937 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS);
1938 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
1939 mdelay(100);
1940
1941 aper_base = INREG(CONFIG_APER_0_BASE);
1942 aper_size = INREG(CONFIG_APER_SIZE);
1943
1944 #ifdef SET_MC_FB_FROM_APERTURE
1945 /* Set framebuffer to be at the same address as set in PCI BAR */
1946 OUTREG(MC_FB_LOCATION,
1947 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16));
1948 rinfo->fb_local_base = aper_base;
1949 #else
1950 OUTREG(MC_FB_LOCATION, 0x7fff0000);
1951 rinfo->fb_local_base = 0;
1952 #endif
1953 agp_base = aper_base + aper_size;
1954 if (agp_base & 0xf0000000)
1955 agp_base = (aper_base | 0x0fffffff) + 1;
1956
1957 /* Set AGP to be just after the framebuffer on a 256Mb boundary. This
1958 * assumes the FB isn't mapped to 0xf0000000 or above, but this is
1959 * always the case on PPCs afaik.
1960 */
1961 #ifdef SET_MC_FB_FROM_APERTURE
1962 OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16));
1963 #else
1964 OUTREG(MC_AGP_LOCATION, 0xffffe000);
1965 #endif
1966
1967 /* Fixup the display base addresses & engine offsets while we
1968 * are at it as well
1969 */
1970 #ifdef SET_MC_FB_FROM_APERTURE
1971 OUTREG(DISPLAY_BASE_ADDR, aper_base);
1972 if (rinfo->has_CRTC2)
1973 OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base);
1974 OUTREG(OV0_BASE_ADDR, aper_base);
1975 #else
1976 OUTREG(DISPLAY_BASE_ADDR, 0);
1977 if (rinfo->has_CRTC2)
1978 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0);
1979 OUTREG(OV0_BASE_ADDR, 0);
1980 #endif
1981 mdelay(100);
1982
1983 /* Restore display settings */
1984 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl);
1985 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl);
1986 if (rinfo->has_CRTC2)
1987 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl);
1988
1989 RTRACE("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n",
1990 aper_base,
1991 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16),
1992 0xffff0000 | (agp_base >> 16));
1993 }
1994 #endif /* CONFIG_PPC_OF */
1995
1996
1997 static void radeon_identify_vram(struct radeonfb_info *rinfo)
1998 {
1999 u32 tmp;
2000
2001 /* framebuffer size */
2002 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2003 (rinfo->family == CHIP_FAMILY_RS200) ||
2004 (rinfo->family == CHIP_FAMILY_RS300) ||
2005 (rinfo->family == CHIP_FAMILY_RC410) ||
2006 (rinfo->family == CHIP_FAMILY_RS480) ) {
2007 u32 tom = INREG(NB_TOM);
2008 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
2009
2010 radeon_fifo_wait(6);
2011 OUTREG(MC_FB_LOCATION, tom);
2012 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2013 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2014 OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
2015
2016 /* This is supposed to fix the crtc2 noise problem. */
2017 OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
2018
2019 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2020 (rinfo->family == CHIP_FAMILY_RS200)) {
2021 /* This is to workaround the asic bug for RMX, some versions
2022 of BIOS dosen't have this register initialized correctly.
2023 */
2024 OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
2025 ~CRTC_H_CUTOFF_ACTIVE_EN);
2026 }
2027 } else {
2028 tmp = INREG(CONFIG_MEMSIZE);
2029 }
2030
2031 /* mem size is bits [28:0], mask off the rest */
2032 rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
2033
2034 /*
2035 * Hack to get around some busted production M6's
2036 * reporting no ram
2037 */
2038 if (rinfo->video_ram == 0) {
2039 switch (rinfo->pdev->device) {
2040 case PCI_CHIP_RADEON_LY:
2041 case PCI_CHIP_RADEON_LZ:
2042 rinfo->video_ram = 8192 * 1024;
2043 break;
2044 default:
2045 break;
2046 }
2047 }
2048
2049
2050 /*
2051 * Now try to identify VRAM type
2052 */
2053 if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) ||
2054 (INREG(MEM_SDRAM_MODE_REG) & (1<<30)))
2055 rinfo->vram_ddr = 1;
2056 else
2057 rinfo->vram_ddr = 0;
2058
2059 tmp = INREG(MEM_CNTL);
2060 if (IS_R300_VARIANT(rinfo)) {
2061 tmp &= R300_MEM_NUM_CHANNELS_MASK;
2062 switch (tmp) {
2063 case 0: rinfo->vram_width = 64; break;
2064 case 1: rinfo->vram_width = 128; break;
2065 case 2: rinfo->vram_width = 256; break;
2066 default: rinfo->vram_width = 128; break;
2067 }
2068 } else if ((rinfo->family == CHIP_FAMILY_RV100) ||
2069 (rinfo->family == CHIP_FAMILY_RS100) ||
2070 (rinfo->family == CHIP_FAMILY_RS200)){
2071 if (tmp & RV100_MEM_HALF_MODE)
2072 rinfo->vram_width = 32;
2073 else
2074 rinfo->vram_width = 64;
2075 } else {
2076 if (tmp & MEM_NUM_CHANNELS_MASK)
2077 rinfo->vram_width = 128;
2078 else
2079 rinfo->vram_width = 64;
2080 }
2081
2082 /* This may not be correct, as some cards can have half of channel disabled
2083 * ToDo: identify these cases
2084 */
2085
2086 RTRACE("radeonfb (%s): Found %ldk of %s %d bits wide videoram\n",
2087 pci_name(rinfo->pdev),
2088 rinfo->video_ram / 1024,
2089 rinfo->vram_ddr ? "DDR" : "SDRAM",
2090 rinfo->vram_width);
2091 }
2092
2093 /*
2094 * Sysfs
2095 */
2096
2097 static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid)
2098 {
2099 if (off > EDID_LENGTH)
2100 return 0;
2101
2102 if (off + count > EDID_LENGTH)
2103 count = EDID_LENGTH - off;
2104
2105 memcpy(buf, edid + off, count);
2106
2107 return count;
2108 }
2109
2110
2111 static ssize_t radeon_show_edid1(struct kobject *kobj,
2112 struct bin_attribute *bin_attr,
2113 char *buf, loff_t off, size_t count)
2114 {
2115 struct device *dev = container_of(kobj, struct device, kobj);
2116 struct pci_dev *pdev = to_pci_dev(dev);
2117 struct fb_info *info = pci_get_drvdata(pdev);
2118 struct radeonfb_info *rinfo = info->par;
2119
2120 return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID);
2121 }
2122
2123
2124 static ssize_t radeon_show_edid2(struct kobject *kobj,
2125 struct bin_attribute *bin_attr,
2126 char *buf, loff_t off, size_t count)
2127 {
2128 struct device *dev = container_of(kobj, struct device, kobj);
2129 struct pci_dev *pdev = to_pci_dev(dev);
2130 struct fb_info *info = pci_get_drvdata(pdev);
2131 struct radeonfb_info *rinfo = info->par;
2132
2133 return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID);
2134 }
2135
2136 static struct bin_attribute edid1_attr = {
2137 .attr = {
2138 .name = "edid1",
2139 .mode = 0444,
2140 },
2141 .size = EDID_LENGTH,
2142 .read = radeon_show_edid1,
2143 };
2144
2145 static struct bin_attribute edid2_attr = {
2146 .attr = {
2147 .name = "edid2",
2148 .mode = 0444,
2149 },
2150 .size = EDID_LENGTH,
2151 .read = radeon_show_edid2,
2152 };
2153
2154
2155 static int __devinit radeonfb_pci_register (struct pci_dev *pdev,
2156 const struct pci_device_id *ent)
2157 {
2158 struct fb_info *info;
2159 struct radeonfb_info *rinfo;
2160 int ret;
2161
2162 RTRACE("radeonfb_pci_register BEGIN\n");
2163
2164 /* Enable device in PCI config */
2165 ret = pci_enable_device(pdev);
2166 if (ret < 0) {
2167 printk(KERN_ERR "radeonfb (%s): Cannot enable PCI device\n",
2168 pci_name(pdev));
2169 goto err_out;
2170 }
2171
2172 info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev);
2173 if (!info) {
2174 printk (KERN_ERR "radeonfb (%s): could not allocate memory\n",
2175 pci_name(pdev));
2176 ret = -ENOMEM;
2177 goto err_disable;
2178 }
2179 rinfo = info->par;
2180 rinfo->info = info;
2181 rinfo->pdev = pdev;
2182
2183 spin_lock_init(&rinfo->reg_lock);
2184 init_timer(&rinfo->lvds_timer);
2185 rinfo->lvds_timer.function = radeon_lvds_timer_func;
2186 rinfo->lvds_timer.data = (unsigned long)rinfo;
2187
2188 strcpy(rinfo->name, "ATI Radeon XX ");
2189 rinfo->name[11] = ent->device >> 8;
2190 rinfo->name[12] = ent->device & 0xFF;
2191 rinfo->family = ent->driver_data & CHIP_FAMILY_MASK;
2192 rinfo->chipset = pdev->device;
2193 rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0;
2194 rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0;
2195 rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0;
2196
2197 /* Set base addrs */
2198 rinfo->fb_base_phys = pci_resource_start (pdev, 0);
2199 rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
2200
2201 /* request the mem regions */
2202 ret = pci_request_region(pdev, 0, "radeonfb framebuffer");
2203 if (ret < 0) {
2204 printk( KERN_ERR "radeonfb (%s): cannot request region 0.\n",
2205 pci_name(rinfo->pdev));
2206 goto err_release_fb;
2207 }
2208
2209 ret = pci_request_region(pdev, 2, "radeonfb mmio");
2210 if (ret < 0) {
2211 printk( KERN_ERR "radeonfb (%s): cannot request region 2.\n",
2212 pci_name(rinfo->pdev));
2213 goto err_release_pci0;
2214 }
2215
2216 /* map the regions */
2217 rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE);
2218 if (!rinfo->mmio_base) {
2219 printk(KERN_ERR "radeonfb (%s): cannot map MMIO\n",
2220 pci_name(rinfo->pdev));
2221 ret = -EIO;
2222 goto err_release_pci2;
2223 }
2224
2225 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
2226
2227 /*
2228 * Check for errata
2229 */
2230 rinfo->errata = 0;
2231 if (rinfo->family == CHIP_FAMILY_R300 &&
2232 (INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK)
2233 == CFG_ATI_REV_A11)
2234 rinfo->errata |= CHIP_ERRATA_R300_CG;
2235
2236 if (rinfo->family == CHIP_FAMILY_RV200 ||
2237 rinfo->family == CHIP_FAMILY_RS200)
2238 rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2239
2240 if (rinfo->family == CHIP_FAMILY_RV100 ||
2241 rinfo->family == CHIP_FAMILY_RS100 ||
2242 rinfo->family == CHIP_FAMILY_RS200)
2243 rinfo->errata |= CHIP_ERRATA_PLL_DELAY;
2244
2245 #if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
2246 /* On PPC, we obtain the OF device-node pointer to the firmware
2247 * data for this chip
2248 */
2249 rinfo->of_node = pci_device_to_OF_node(pdev);
2250 if (rinfo->of_node == NULL)
2251 printk(KERN_WARNING "radeonfb (%s): Cannot match card to OF node !\n",
2252 pci_name(rinfo->pdev));
2253
2254 #endif /* CONFIG_PPC_OF || CONFIG_SPARC */
2255 #ifdef CONFIG_PPC_OF
2256 /* On PPC, the firmware sets up a memory mapping that tends
2257 * to cause lockups when enabling the engine. We reconfigure
2258 * the card internal memory mappings properly
2259 */
2260 fixup_memory_mappings(rinfo);
2261 #endif /* CONFIG_PPC_OF */
2262
2263 /* Get VRAM size and type */
2264 radeon_identify_vram(rinfo);
2265
2266 rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram);
2267
2268 do {
2269 rinfo->fb_base = ioremap (rinfo->fb_base_phys,
2270 rinfo->mapped_vram);
2271 } while ( rinfo->fb_base == 0 &&
2272 ((rinfo->mapped_vram /=2) >= MIN_MAPPED_VRAM) );
2273
2274 if (rinfo->fb_base == NULL) {
2275 printk (KERN_ERR "radeonfb (%s): cannot map FB\n",
2276 pci_name(rinfo->pdev));
2277 ret = -EIO;
2278 goto err_unmap_rom;
2279 }
2280
2281 RTRACE("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev),
2282 rinfo->mapped_vram/1024);
2283
2284 /*
2285 * Map the BIOS ROM if any and retrieve PLL parameters from
2286 * the BIOS. We skip that on mobility chips as the real panel
2287 * values we need aren't in the ROM but in the BIOS image in
2288 * memory. This is definitely not the best meacnism though,
2289 * we really need the arch code to tell us which is the "primary"
2290 * video adapter to use the memory image (or better, the arch
2291 * should provide us a copy of the BIOS image to shield us from
2292 * archs who would store that elsewhere and/or could initialize
2293 * more than one adapter during boot).
2294 */
2295 if (!rinfo->is_mobility)
2296 radeon_map_ROM(rinfo, pdev);
2297
2298 /*
2299 * On x86, the primary display on laptop may have it's BIOS
2300 * ROM elsewhere, try to locate it at the legacy memory hole.
2301 * We probably need to make sure this is the primary display,
2302 * but that is difficult without some arch support.
2303 */
2304 #ifdef CONFIG_X86
2305 if (rinfo->bios_seg == NULL)
2306 radeon_find_mem_vbios(rinfo);
2307 #endif
2308
2309 /* If both above failed, try the BIOS ROM again for mobility
2310 * chips
2311 */
2312 if (rinfo->bios_seg == NULL && rinfo->is_mobility)
2313 radeon_map_ROM(rinfo, pdev);
2314
2315 /* Get informations about the board's PLL */
2316 radeon_get_pllinfo(rinfo);
2317
2318 #ifdef CONFIG_FB_RADEON_I2C
2319 /* Register I2C bus */
2320 radeon_create_i2c_busses(rinfo);
2321 #endif
2322
2323 /* set all the vital stuff */
2324 radeon_set_fbinfo (rinfo);
2325
2326 /* Probe screen types */
2327 radeon_probe_screens(rinfo, monitor_layout, ignore_edid);
2328
2329 /* Build mode list, check out panel native model */
2330 radeon_check_modes(rinfo, mode_option);
2331
2332 /* Register some sysfs stuff (should be done better) */
2333 if (rinfo->mon1_EDID)
2334 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2335 if (rinfo->mon2_EDID)
2336 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2337
2338 /* save current mode regs before we switch into the new one
2339 * so we can restore this upon __exit
2340 */
2341 radeon_save_state (rinfo, &rinfo->init_state);
2342 memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs));
2343
2344 /* Setup Power Management capabilities */
2345 if (default_dynclk < -1) {
2346 /* -2 is special: means ON on mobility chips and do not
2347 * change on others
2348 */
2349 radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1, ignore_devlist, force_sleep);
2350 } else
2351 radeonfb_pm_init(rinfo, default_dynclk, ignore_devlist, force_sleep);
2352
2353 pci_set_drvdata(pdev, info);
2354
2355 /* Register with fbdev layer */
2356 ret = register_framebuffer(info);
2357 if (ret < 0) {
2358 printk (KERN_ERR "radeonfb (%s): could not register framebuffer\n",
2359 pci_name(rinfo->pdev));
2360 goto err_unmap_fb;
2361 }
2362
2363 #ifdef CONFIG_MTRR
2364 rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys,
2365 rinfo->video_ram,
2366 MTRR_TYPE_WRCOMB, 1);
2367 #endif
2368
2369 if (backlight)
2370 radeonfb_bl_init(rinfo);
2371
2372 printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name);
2373
2374 if (rinfo->bios_seg)
2375 radeon_unmap_ROM(rinfo, pdev);
2376 RTRACE("radeonfb_pci_register END\n");
2377
2378 return 0;
2379 err_unmap_fb:
2380 iounmap(rinfo->fb_base);
2381 err_unmap_rom:
2382 kfree(rinfo->mon1_EDID);
2383 kfree(rinfo->mon2_EDID);
2384 if (rinfo->mon1_modedb)
2385 fb_destroy_modedb(rinfo->mon1_modedb);
2386 fb_dealloc_cmap(&info->cmap);
2387 #ifdef CONFIG_FB_RADEON_I2C
2388 radeon_delete_i2c_busses(rinfo);
2389 #endif
2390 if (rinfo->bios_seg)
2391 radeon_unmap_ROM(rinfo, pdev);
2392 iounmap(rinfo->mmio_base);
2393 err_release_pci2:
2394 pci_release_region(pdev, 2);
2395 err_release_pci0:
2396 pci_release_region(pdev, 0);
2397 err_release_fb:
2398 framebuffer_release(info);
2399 err_disable:
2400 err_out:
2401 return ret;
2402 }
2403
2404
2405
2406 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
2407 {
2408 struct fb_info *info = pci_get_drvdata(pdev);
2409 struct radeonfb_info *rinfo = info->par;
2410
2411 if (!rinfo)
2412 return;
2413
2414 radeonfb_pm_exit(rinfo);
2415
2416 if (rinfo->mon1_EDID)
2417 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2418 if (rinfo->mon2_EDID)
2419 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2420
2421 #if 0
2422 /* restore original state
2423 *
2424 * Doesn't quite work yet, I suspect if we come from a legacy
2425 * VGA mode (or worse, text mode), we need to do some VGA black
2426 * magic here that I know nothing about. --BenH
2427 */
2428 radeon_write_mode (rinfo, &rinfo->init_state, 1);
2429 #endif
2430
2431 del_timer_sync(&rinfo->lvds_timer);
2432
2433 #ifdef CONFIG_MTRR
2434 if (rinfo->mtrr_hdl >= 0)
2435 mtrr_del(rinfo->mtrr_hdl, 0, 0);
2436 #endif
2437
2438 unregister_framebuffer(info);
2439
2440 radeonfb_bl_exit(rinfo);
2441
2442 iounmap(rinfo->mmio_base);
2443 iounmap(rinfo->fb_base);
2444
2445 pci_release_region(pdev, 2);
2446 pci_release_region(pdev, 0);
2447
2448 kfree(rinfo->mon1_EDID);
2449 kfree(rinfo->mon2_EDID);
2450 if (rinfo->mon1_modedb)
2451 fb_destroy_modedb(rinfo->mon1_modedb);
2452 #ifdef CONFIG_FB_RADEON_I2C
2453 radeon_delete_i2c_busses(rinfo);
2454 #endif
2455 fb_dealloc_cmap(&info->cmap);
2456 framebuffer_release(info);
2457 }
2458
2459
2460 static struct pci_driver radeonfb_driver = {
2461 .name = "radeonfb",
2462 .id_table = radeonfb_pci_table,
2463 .probe = radeonfb_pci_register,
2464 .remove = __devexit_p(radeonfb_pci_unregister),
2465 #ifdef CONFIG_PM
2466 .suspend = radeonfb_pci_suspend,
2467 .resume = radeonfb_pci_resume,
2468 #endif /* CONFIG_PM */
2469 };
2470
2471 #ifndef MODULE
2472 static int __init radeonfb_setup (char *options)
2473 {
2474 char *this_opt;
2475
2476 if (!options || !*options)
2477 return 0;
2478
2479 while ((this_opt = strsep (&options, ",")) != NULL) {
2480 if (!*this_opt)
2481 continue;
2482
2483 if (!strncmp(this_opt, "noaccel", 7)) {
2484 noaccel = 1;
2485 } else if (!strncmp(this_opt, "mirror", 6)) {
2486 mirror = 1;
2487 } else if (!strncmp(this_opt, "force_dfp", 9)) {
2488 force_dfp = 1;
2489 } else if (!strncmp(this_opt, "panel_yres:", 11)) {
2490 panel_yres = simple_strtoul((this_opt+11), NULL, 0);
2491 } else if (!strncmp(this_opt, "backlight:", 10)) {
2492 backlight = simple_strtoul(this_opt+10, NULL, 0);
2493 #ifdef CONFIG_MTRR
2494 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2495 nomtrr = 1;
2496 #endif
2497 } else if (!strncmp(this_opt, "nomodeset", 9)) {
2498 nomodeset = 1;
2499 } else if (!strncmp(this_opt, "force_measure_pll", 17)) {
2500 force_measure_pll = 1;
2501 } else if (!strncmp(this_opt, "ignore_edid", 11)) {
2502 ignore_edid = 1;
2503 #if defined(CONFIG_PM) && defined(CONFIG_X86)
2504 } else if (!strncmp(this_opt, "force_sleep", 11)) {
2505 force_sleep = 1;
2506 } else if (!strncmp(this_opt, "ignore_devlist", 14)) {
2507 ignore_devlist = 1;
2508 #endif
2509 } else
2510 mode_option = this_opt;
2511 }
2512 return 0;
2513 }
2514 #endif /* MODULE */
2515
2516 static int __init radeonfb_init (void)
2517 {
2518 #ifndef MODULE
2519 char *option = NULL;
2520
2521 if (fb_get_options("radeonfb", &option))
2522 return -ENODEV;
2523 radeonfb_setup(option);
2524 #endif
2525 return pci_register_driver (&radeonfb_driver);
2526 }
2527
2528
2529 static void __exit radeonfb_exit (void)
2530 {
2531 pci_unregister_driver (&radeonfb_driver);
2532 }
2533
2534 module_init(radeonfb_init);
2535 module_exit(radeonfb_exit);
2536
2537 MODULE_AUTHOR("Ani Joshi");
2538 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
2539 MODULE_LICENSE("GPL");
2540 module_param(noaccel, bool, 0);
2541 module_param(default_dynclk, int, 0);
2542 MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on");
2543 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2544 module_param(nomodeset, bool, 0);
2545 MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode");
2546 module_param(mirror, bool, 0);
2547 MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors");
2548 module_param(force_dfp, bool, 0);
2549 MODULE_PARM_DESC(force_dfp, "bool: force display to dfp");
2550 module_param(ignore_edid, bool, 0);
2551 MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe");
2552 module_param(monitor_layout, charp, 0);
2553 MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)");
2554 module_param(force_measure_pll, bool, 0);
2555 MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)");
2556 #ifdef CONFIG_MTRR
2557 module_param(nomtrr, bool, 0);
2558 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
2559 #endif
2560 module_param(panel_yres, int, 0);
2561 MODULE_PARM_DESC(panel_yres, "int: set panel yres");
2562 module_param(mode_option, charp, 0);
2563 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2564 #if defined(CONFIG_PM) && defined(CONFIG_X86)
2565 module_param(force_sleep, bool, 0);
2566 MODULE_PARM_DESC(force_sleep, "bool: force D2 sleep mode on all hardware");
2567 module_param(ignore_devlist, bool, 0);
2568 MODULE_PARM_DESC(ignore_devlist, "bool: ignore workarounds for bugs in specific laptops");
2569 #endif
Verdex Pro support