drivers/video/aty/radeonfb.h

   1 #ifndef __RADEONFB_H__
   2 #define __RADEONFB_H__
   3
   4 #include <linux/module.h>
   5 #include <linux/kernel.h>
   6 #include <linux/sched.h>
   7 #include <linux/delay.h>
   8 #include <linux/pci.h>
   9 #include <linux/fb.h>
  10
  11
  12 #ifdef CONFIG_FB_RADEON_I2C
  13 #include <linux/i2c.h>
  14 #include <linux/i2c-algo-bit.h>
  15 #endif
  16
  17 #include <asm/io.h>
  18
  19 #if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
  20 #include <asm/prom.h>
  21 #endif
  22
  23 #include <video/radeon.h>
  24
  25 /***************************************************************
  26  * Most of the definitions here are adapted right from XFree86 *
  27  ***************************************************************/
  28
  29
  30 /*
  31  * Chip families. Must fit in the low 16 bits of a long word
  32  */
  33 enum radeon_family {
  34         CHIP_FAMILY_UNKNOW,
  35         CHIP_FAMILY_LEGACY,
  36         CHIP_FAMILY_RADEON,
  37         CHIP_FAMILY_RV100,
  38         CHIP_FAMILY_RS100,    /* U1 (IGP320M) or A3 (IGP320)*/
  39         CHIP_FAMILY_RV200,
  40         CHIP_FAMILY_RS200,    /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350),
  41                                  RS250 (IGP 7000) */
  42         CHIP_FAMILY_R200,
  43         CHIP_FAMILY_RV250,
  44         CHIP_FAMILY_RS300,    /* Radeon 9000 IGP */
  45         CHIP_FAMILY_RV280,
  46         CHIP_FAMILY_R300,
  47         CHIP_FAMILY_R350,
  48         CHIP_FAMILY_RV350,
  49         CHIP_FAMILY_RV380,    /* RV370/RV380/M22/M24 */
  50         CHIP_FAMILY_R420,     /* R420/R423/M18 */
  51         CHIP_FAMILY_RC410,
  52         CHIP_FAMILY_RS480,
  53         CHIP_FAMILY_LAST,
  54 };
  55
  56 #define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100)  || \
  57                                  ((rinfo)->family == CHIP_FAMILY_RV200)  || \
  58                                  ((rinfo)->family == CHIP_FAMILY_RS100)  || \
  59                                  ((rinfo)->family == CHIP_FAMILY_RS200)  || \
  60                                  ((rinfo)->family == CHIP_FAMILY_RV250)  || \
  61                                  ((rinfo)->family == CHIP_FAMILY_RV280)  || \
  62                                  ((rinfo)->family == CHIP_FAMILY_RS300))
  63
  64
  65 #define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300)  || \
  66                                 ((rinfo)->family == CHIP_FAMILY_RV350) || \
  67                                 ((rinfo)->family == CHIP_FAMILY_R350)  || \
  68                                 ((rinfo)->family == CHIP_FAMILY_RV380) || \
  69                                 ((rinfo)->family == CHIP_FAMILY_R420)  || \
  70                                ((rinfo)->family == CHIP_FAMILY_RC410) || \
  71                                ((rinfo)->family == CHIP_FAMILY_RS480))
  72
  73 /*
  74  * Chip flags
  75  */
  76 enum radeon_chip_flags {
  77         CHIP_FAMILY_MASK        = 0x0000ffffUL,
  78         CHIP_FLAGS_MASK         = 0xffff0000UL,
  79         CHIP_IS_MOBILITY        = 0x00010000UL,
  80         CHIP_IS_IGP             = 0x00020000UL,
  81         CHIP_HAS_CRTC2          = 0x00040000UL,
  82 };
  83
  84 /*
  85  * Errata workarounds
  86  */
  87 enum radeon_errata {
  88         CHIP_ERRATA_R300_CG             = 0x00000001,
  89         CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
  90         CHIP_ERRATA_PLL_DELAY           = 0x00000004,
  91 };
  92
  93
  94 /*
  95  * Monitor types
  96  */
  97 enum radeon_montype {
  98         MT_NONE = 0,
  99         MT_CRT,         /* CRT */
 100         MT_LCD,         /* LCD */
 101         MT_DFP,         /* DVI */
 102         MT_CTV,         /* composite TV */
 103         MT_STV          /* S-Video out */
 104 };
 105
 106 /*
 107  * DDC i2c ports
 108  */
 109 enum ddc_type {
 110         ddc_none,
 111         ddc_monid,
 112         ddc_dvi,
 113         ddc_vga,
 114         ddc_crt2,
 115 };
 116
 117 /*
 118  * Connector types
 119  */
 120 enum conn_type {
 121         conn_none,
 122         conn_proprietary,
 123         conn_crt,
 124         conn_DVI_I,
 125         conn_DVI_D,
 126 };
 127
 128
 129 /*
 130  * PLL infos
 131  */
 132 struct pll_info {
 133         int ppll_max;
 134         int ppll_min;
 135         int sclk, mclk;
 136         int ref_div;
 137         int ref_clk;
 138 };
 139
 140
 141 /*
 142  * This structure contains the various registers manipulated by this
 143  * driver for setting or restoring a mode. It's mostly copied from
 144  * XFree's RADEONSaveRec structure. A few chip settings might still be
 145  * tweaked without beeing reflected or saved in these registers though
 146  */
 147 struct radeon_regs {
 148         /* Common registers */
 149         u32             ovr_clr;
 150         u32             ovr_wid_left_right;
 151         u32             ovr_wid_top_bottom;
 152         u32             ov0_scale_cntl;
 153         u32             mpp_tb_config;
 154         u32             mpp_gp_config;
 155         u32             subpic_cntl;
 156         u32             viph_control;
 157         u32             i2c_cntl_1;
 158         u32             gen_int_cntl;
 159         u32             cap0_trig_cntl;
 160         u32             cap1_trig_cntl;
 161         u32             bus_cntl;
 162         u32             surface_cntl;
 163         u32             bios_5_scratch;
 164
 165         /* Other registers to save for VT switches or driver load/unload */
 166         u32             dp_datatype;
 167         u32             rbbm_soft_reset;
 168         u32             clock_cntl_index;
 169         u32             amcgpio_en_reg;
 170         u32             amcgpio_mask;
 171
 172         /* Surface/tiling registers */
 173         u32             surf_lower_bound[8];
 174         u32             surf_upper_bound[8];
 175         u32             surf_info[8];
 176
 177         /* CRTC registers */
 178         u32             crtc_gen_cntl;
 179         u32             crtc_ext_cntl;
 180         u32             dac_cntl;
 181         u32             crtc_h_total_disp;
 182         u32             crtc_h_sync_strt_wid;
 183         u32             crtc_v_total_disp;
 184         u32             crtc_v_sync_strt_wid;
 185         u32             crtc_offset;
 186         u32             crtc_offset_cntl;
 187         u32             crtc_pitch;
 188         u32             disp_merge_cntl;
 189         u32             grph_buffer_cntl;
 190         u32             crtc_more_cntl;
 191
 192         /* CRTC2 registers */
 193         u32             crtc2_gen_cntl;
 194         u32             dac2_cntl;
 195         u32             disp_output_cntl;
 196         u32             disp_hw_debug;
 197         u32             disp2_merge_cntl;
 198         u32             grph2_buffer_cntl;
 199         u32             crtc2_h_total_disp;
 200         u32             crtc2_h_sync_strt_wid;
 201         u32             crtc2_v_total_disp;
 202         u32             crtc2_v_sync_strt_wid;
 203         u32             crtc2_offset;
 204         u32             crtc2_offset_cntl;
 205         u32             crtc2_pitch;
 206
 207         /* Flat panel regs */
 208         u32             fp_crtc_h_total_disp;
 209         u32             fp_crtc_v_total_disp;
 210         u32             fp_gen_cntl;
 211         u32             fp2_gen_cntl;
 212         u32             fp_h_sync_strt_wid;
 213         u32             fp2_h_sync_strt_wid;
 214         u32             fp_horz_stretch;
 215         u32             fp_panel_cntl;
 216         u32             fp_v_sync_strt_wid;
 217         u32             fp2_v_sync_strt_wid;
 218         u32             fp_vert_stretch;
 219         u32             lvds_gen_cntl;
 220         u32             lvds_pll_cntl;
 221         u32             tmds_crc;
 222         u32             tmds_transmitter_cntl;
 223
 224         /* Computed values for PLL */
 225         u32             dot_clock_freq;
 226         int             feedback_div;
 227         int             post_div;
 228
 229         /* PLL registers */
 230         u32             ppll_div_3;
 231         u32             ppll_ref_div;
 232         u32             vclk_ecp_cntl;
 233         u32             clk_cntl_index;
 234
 235         /* Computed values for PLL2 */
 236         u32             dot_clock_freq_2;
 237         int             feedback_div_2;
 238         int             post_div_2;
 239
 240         /* PLL2 registers */
 241         u32             p2pll_ref_div;
 242         u32             p2pll_div_0;
 243         u32             htotal_cntl2;
 244
 245         /* Palette */
 246         int             palette_valid;
 247 };
 248
 249 struct panel_info {
 250         int xres, yres;
 251         int valid;
 252         int clock;
 253         int hOver_plus, hSync_width, hblank;
 254         int vOver_plus, vSync_width, vblank;
 255         int hAct_high, vAct_high, interlaced;
 256         int pwr_delay;
 257         int use_bios_dividers;
 258         int ref_divider;
 259         int post_divider;
 260         int fbk_divider;
 261 };
 262
 263 struct radeonfb_info;
 264
 265 #ifdef CONFIG_FB_RADEON_I2C
 266 struct radeon_i2c_chan {
 267         struct radeonfb_info            *rinfo;
 268         u32                             ddc_reg;
 269         struct i2c_adapter              adapter;
 270         struct i2c_algo_bit_data        algo;
 271 };
 272 #endif
 273
 274 enum radeon_pm_mode {
 275         radeon_pm_none  = 0,            /* Nothing supported */
 276         radeon_pm_d2    = 0x00000001,   /* Can do D2 state */
 277         radeon_pm_off   = 0x00000002,   /* Can resume from D3 cold */
 278 };
 279
 280 typedef void (*reinit_function_ptr)(struct radeonfb_info *rinfo);
 281
 282 struct radeonfb_info {
 283         struct fb_info          *info;
 284
 285         struct radeon_regs      state;
 286         struct radeon_regs      init_state;
 287
 288         char                    name[DEVICE_NAME_SIZE];
 289
 290         unsigned long           mmio_base_phys;
 291         unsigned long           fb_base_phys;
 292
 293         void __iomem            *mmio_base;
 294         void __iomem            *fb_base;
 295
 296         unsigned long           fb_local_base;
 297
 298         struct pci_dev          *pdev;
 299 #if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
 300         struct device_node      *of_node;
 301 #endif
 302
 303         void __iomem            *bios_seg;
 304         int                     fp_bios_start;
 305
 306         u32                     pseudo_palette[16];
 307         struct { u8 red, green, blue, pad; }
 308                                 palette[256];
 309
 310         int                     chipset;
 311         u8                      family;
 312         u8                      rev;
 313         unsigned int            errata;
 314         unsigned long           video_ram;
 315         unsigned long           mapped_vram;
 316         int                     vram_width;
 317         int                     vram_ddr;
 318
 319         int                     pitch, bpp, depth;
 320
 321         int                     has_CRTC2;
 322         int                     is_mobility;
 323         int                     is_IGP;
 324         int                     reversed_DAC;
 325         int                     reversed_TMDS;
 326         struct panel_info       panel_info;
 327         int                     mon1_type;
 328         u8                      *mon1_EDID;
 329         struct fb_videomode     *mon1_modedb;
 330         int                     mon1_dbsize;
 331         int                     mon2_type;
 332         u8                      *mon2_EDID;
 333
 334         u32                     dp_gui_master_cntl;
 335
 336         struct pll_info         pll;
 337
 338         int                     mtrr_hdl;
 339
 340         int                     pm_reg;
 341         u32                     save_regs[100];
 342         int                     asleep;
 343         int                     lock_blank;
 344         int                     dynclk;
 345         int                     no_schedule;
 346         enum radeon_pm_mode     pm_mode;
 347         reinit_function_ptr     reinit_func;
 348
 349         /* Lock on register access */
 350         spinlock_t              reg_lock;
 351
 352         /* Timer used for delayed LVDS operations */
 353         struct timer_list       lvds_timer;
 354         u32                     pending_lvds_gen_cntl;
 355
 356 #ifdef CONFIG_FB_RADEON_I2C
 357         struct radeon_i2c_chan  i2c[4];
 358 #endif
 359
 360         u32                     cfg_save[64];
 361 };
 362
 363
 364 #define PRIMARY_MONITOR(rinfo)  (rinfo->mon1_type)
 365
 366
 367 /*
 368  * Debugging stuffs
 369  */
 370 #ifdef CONFIG_FB_RADEON_DEBUG
 371 #define DEBUG           1
 372 #else
 373 #define DEBUG           0
 374 #endif
 375
 376 #if DEBUG
 377 #define RTRACE          printk
 378 #else
 379 #define RTRACE          if(0) printk
 380 #endif
 381
 382
 383 /*
 384  * IO macros
 385  */
 386
 387 /* Note about this function: we have some rare cases where we must not schedule,
 388  * this typically happen with our special "wake up early" hook which allows us to
 389  * wake up the graphic chip (and thus get the console back) before everything else
 390  * on some machines that support that mechanism. At this point, interrupts are off
 391  * and scheduling is not permitted
 392  */
 393 static inline void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms)
 394 {
 395         if (rinfo->no_schedule || oops_in_progress)
 396                 mdelay(ms);
 397         else
 398                 msleep(ms);
 399 }
 400
 401
 402 #define INREG8(addr)            readb((rinfo->mmio_base)+addr)
 403 #define OUTREG8(addr,val)       writeb(val, (rinfo->mmio_base)+addr)
 404 #define INREG16(addr)           readw((rinfo->mmio_base)+addr)
 405 #define OUTREG16(addr,val)      writew(val, (rinfo->mmio_base)+addr)
 406 #define INREG(addr)             readl((rinfo->mmio_base)+addr)
 407 #define OUTREG(addr,val)        writel(val, (rinfo->mmio_base)+addr)
 408
 409 static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr,
 410                        u32 val, u32 mask)
 411 {
 412         unsigned long flags;
 413         unsigned int tmp;
 414
 415         spin_lock_irqsave(&rinfo->reg_lock, flags);
 416         tmp = INREG(addr);
 417         tmp &= (mask);
 418         tmp |= (val);
 419         OUTREG(addr, tmp);
 420         spin_unlock_irqrestore(&rinfo->reg_lock, flags);
 421 }
 422
 423 #define OUTREGP(addr,val,mask)  _OUTREGP(rinfo, addr, val,mask)
 424
 425 /*
 426  * Note about PLL register accesses:
 427  *
 428  * I have removed the spinlock on them on purpose. The driver now
 429  * expects that it will only manipulate the PLL registers in normal
 430  * task environment, where radeon_msleep() will be called, protected
 431  * by a semaphore (currently the console semaphore) so that no conflict
 432  * will happen on the PLL register index.
 433  *
 434  * With the latest changes to the VT layer, this is guaranteed for all
 435  * calls except the actual drawing/blits which aren't supposed to use
 436  * the PLL registers anyway
 437  *
 438  * This is very important for the workarounds to work properly. The only
 439  * possible exception to this rule is the call to unblank(), which may
 440  * be done at irq time if an oops is in progress.
 441  */
 442 static inline void radeon_pll_errata_after_index(struct radeonfb_info *rinfo)
 443 {
 444         if (!(rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS))
 445                 return;
 446
 447         (void)INREG(CLOCK_CNTL_DATA);
 448         (void)INREG(CRTC_GEN_CNTL);
 449 }
 450
 451 static inline void radeon_pll_errata_after_data(struct radeonfb_info *rinfo)
 452 {
 453         if (rinfo->errata & CHIP_ERRATA_PLL_DELAY) {
 454                 /* we can't deal with posted writes here ... */
 455                 _radeon_msleep(rinfo, 5);
 456         }
 457         if (rinfo->errata & CHIP_ERRATA_R300_CG) {
 458                 u32 save, tmp;
 459                 save = INREG(CLOCK_CNTL_INDEX);
 460                 tmp = save & ~(0x3f | PLL_WR_EN);
 461                 OUTREG(CLOCK_CNTL_INDEX, tmp);
 462                 tmp = INREG(CLOCK_CNTL_DATA);
 463                 OUTREG(CLOCK_CNTL_INDEX, save);
 464         }
 465 }
 466
 467 static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr)
 468 {
 469         u32 data;
 470
 471         OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
 472         radeon_pll_errata_after_index(rinfo);
 473         data = INREG(CLOCK_CNTL_DATA);
 474         radeon_pll_errata_after_data(rinfo);
 475         return data;
 476 }
 477
 478 static inline void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index,
 479                             u32 val)
 480 {
 481
 482         OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080);
 483         radeon_pll_errata_after_index(rinfo);
 484         OUTREG(CLOCK_CNTL_DATA, val);
 485         radeon_pll_errata_after_data(rinfo);
 486 }
 487
 488
 489 static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
 490                              u32 val, u32 mask)
 491 {
 492         unsigned int tmp;
 493
 494         tmp  = __INPLL(rinfo, index);
 495         tmp &= (mask);
 496         tmp |= (val);
 497         __OUTPLL(rinfo, index, tmp);
 498 }
 499
 500
 501 #define INPLL(addr)                     __INPLL(rinfo, addr)
 502 #define OUTPLL(index, val)              __OUTPLL(rinfo, index, val)
 503 #define OUTPLLP(index, val, mask)       __OUTPLLP(rinfo, index, val, mask)
 504
 505
 506 #define BIOS_IN8(v)     (readb(rinfo->bios_seg + (v)))
 507 #define BIOS_IN16(v)    (readb(rinfo->bios_seg + (v)) | \
 508                           (readb(rinfo->bios_seg + (v) + 1) << 8))
 509 #define BIOS_IN32(v)    (readb(rinfo->bios_seg + (v)) | \
 510                           (readb(rinfo->bios_seg + (v) + 1) << 8) | \
 511                           (readb(rinfo->bios_seg + (v) + 2) << 16) | \
 512                           (readb(rinfo->bios_seg + (v) + 3) << 24))
 513
 514 /*
 515  * Inline utilities
 516  */
 517 static inline int round_div(int num, int den)
 518 {
 519         return (num + (den / 2)) / den;
 520 }
 521
 522 static inline int var_to_depth(const struct fb_var_screeninfo *var)
 523 {
 524         if (var->bits_per_pixel != 16)
 525                 return var->bits_per_pixel;
 526         return (var->green.length == 5) ? 15 : 16;
 527 }
 528
 529 static inline u32 radeon_get_dstbpp(u16 depth)
 530 {
 531         switch (depth) {
 532         case 8:
 533                 return DST_8BPP;
 534         case 15:
 535                 return DST_15BPP;
 536         case 16:
 537                 return DST_16BPP;
 538         case 32:
 539                 return DST_32BPP;
 540         default:
 541                 return 0;
 542         }
 543 }
 544
 545 /*
 546  * 2D Engine helper routines
 547  */
 548 static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
 549 {
 550         int i;
 551
 552         /* initiate flush */
 553         OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
 554                 ~RB2D_DC_FLUSH_ALL);
 555
 556         for (i=0; i < 2000000; i++) {
 557                 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
 558                         return;
 559                 udelay(1);
 560         }
 561         printk(KERN_ERR "radeonfb: Flush Timeout !\n");
 562 }
 563
 564
 565 static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
 566 {
 567         int i;
 568
 569         for (i=0; i<2000000; i++) {
 570                 if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
 571                         return;
 572                 udelay(1);
 573         }
 574         printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
 575 }
 576
 577
 578 static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
 579 {
 580         int i;
 581
 582         /* ensure FIFO is empty before waiting for idle */
 583         _radeon_fifo_wait (rinfo, 64);
 584
 585         for (i=0; i<2000000; i++) {
 586                 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
 587                         radeon_engine_flush (rinfo);
 588                         return;
 589                 }
 590                 udelay(1);
 591         }
 592         printk(KERN_ERR "radeonfb: Idle Timeout !\n");
 593 }
 594
 595
 596 #define radeon_engine_idle()            _radeon_engine_idle(rinfo)
 597 #define radeon_fifo_wait(entries)       _radeon_fifo_wait(rinfo,entries)
 598 #define radeon_msleep(ms)               _radeon_msleep(rinfo,ms)
 599
 600
 601 /* I2C Functions */
 602 extern void radeon_create_i2c_busses(struct radeonfb_info *rinfo);
 603 extern void radeon_delete_i2c_busses(struct radeonfb_info *rinfo);
 604 extern int radeon_probe_i2c_connector(struct radeonfb_info *rinfo, int conn, u8 **out_edid);
 605
 606 /* PM Functions */
 607 extern int radeonfb_pci_suspend(struct pci_dev *pdev, pm_message_t state);
 608 extern int radeonfb_pci_resume(struct pci_dev *pdev);
 609 extern void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk, int ignore_devlist, int force_sleep);
 610 extern void radeonfb_pm_exit(struct radeonfb_info *rinfo);
 611
 612 /* Monitor probe functions */
 613 extern void radeon_probe_screens(struct radeonfb_info *rinfo,
 614                                  const char *monitor_layout, int ignore_edid);
 615 extern void radeon_check_modes(struct radeonfb_info *rinfo, const char *mode_option);
 616 extern int radeon_match_mode(struct radeonfb_info *rinfo,
 617                              struct fb_var_screeninfo *dest,
 618                              const struct fb_var_screeninfo *src);
 619
 620 /* Accel functions */
 621 extern void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region);
 622 extern void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
 623 extern void radeonfb_imageblit(struct fb_info *p, const struct fb_image *image);
 624 extern int radeonfb_sync(struct fb_info *info);
 625 extern void radeonfb_engine_init (struct radeonfb_info *rinfo);
 626 extern void radeonfb_engine_reset(struct radeonfb_info *rinfo);
 627
 628 /* Other functions */
 629 extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch);
 630 extern void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
 631                                int reg_only);
 632
 633 /* Backlight functions */
 634 #ifdef CONFIG_FB_RADEON_BACKLIGHT
 635 extern void radeonfb_bl_init(struct radeonfb_info *rinfo);
 636 extern void radeonfb_bl_exit(struct radeonfb_info *rinfo);
 637 #else
 638 static inline void radeonfb_bl_init(struct radeonfb_info *rinfo) {}
 639 static inline void radeonfb_bl_exit(struct radeonfb_info *rinfo) {}
 640 #endif
 641
 642 #endif /* __RADEONFB_H__ */