arch/powerpc/sysdev/dart_iommu.c

   1 /*
   2  * arch/powerpc/sysdev/dart_iommu.c
   3  *
   4  * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
   5  * Copyright (C) 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>,
   6  *                    IBM Corporation
   7  *
   8  * Based on pSeries_iommu.c:
   9  * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
  10  * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
  11  *
  12  * Dynamic DMA mapping support, Apple U3, U4 & IBM CPC925 "DART" iommu.
  13  *
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2 of the License, or
  18  * (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  28  */
  29
  30 #include <linux/init.h>
  31 #include <linux/types.h>
  32 #include <linux/slab.h>
  33 #include <linux/mm.h>
  34 #include <linux/spinlock.h>
  35 #include <linux/string.h>
  36 #include <linux/pci.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/vmalloc.h>
  39 #include <asm/io.h>
  40 #include <asm/prom.h>
  41 #include <asm/iommu.h>
  42 #include <asm/pci-bridge.h>
  43 #include <asm/machdep.h>
  44 #include <asm/abs_addr.h>
  45 #include <asm/cacheflush.h>
  46 #include <asm/lmb.h>
  47 #include <asm/ppc-pci.h>
  48
  49 #include "dart.h"
  50
  51 extern int iommu_is_off;
  52 extern int iommu_force_on;
  53
  54 /* Physical base address and size of the DART table */
  55 unsigned long dart_tablebase; /* exported to htab_initialize */
  56 static unsigned long dart_tablesize;
  57
  58 /* Virtual base address of the DART table */
  59 static u32 *dart_vbase;
  60
  61 /* Mapped base address for the dart */
  62 static unsigned int __iomem *dart;
  63
  64 /* Dummy val that entries are set to when unused */
  65 static unsigned int dart_emptyval;
  66
  67 static struct iommu_table iommu_table_dart;
  68 static int iommu_table_dart_inited;
  69 static int dart_dirty;
  70 static int dart_is_u4;
  71
  72 #define DBG(...)
  73
  74 static inline void dart_tlb_invalidate_all(void)
  75 {
  76         unsigned long l = 0;
  77         unsigned int reg, inv_bit;
  78         unsigned long limit;
  79
  80         DBG("dart: flush\n");
  81
  82         /* To invalidate the DART, set the DARTCNTL_FLUSHTLB bit in the
  83          * control register and wait for it to clear.
  84          *
  85          * Gotcha: Sometimes, the DART won't detect that the bit gets
  86          * set. If so, clear it and set it again.
  87          */
  88
  89         limit = 0;
  90
  91         inv_bit = dart_is_u4 ? DART_CNTL_U4_FLUSHTLB : DART_CNTL_U3_FLUSHTLB;
  92 retry:
  93         l = 0;
  94         reg = DART_IN(DART_CNTL);
  95         reg |= inv_bit;
  96         DART_OUT(DART_CNTL, reg);
  97
  98         while ((DART_IN(DART_CNTL) & inv_bit) && l < (1L << limit))
  99                 l++;
 100         if (l == (1L << limit)) {
 101                 if (limit < 4) {
 102                         limit++;
 103                         reg = DART_IN(DART_CNTL);
 104                         reg &= ~inv_bit;
 105                         DART_OUT(DART_CNTL, reg);
 106                         goto retry;
 107                 } else
 108                         panic("DART: TLB did not flush after waiting a long "
 109                               "time. Buggy U3 ?");
 110         }
 111 }
 112
 113 static inline void dart_tlb_invalidate_one(unsigned long bus_rpn)
 114 {
 115         unsigned int reg;
 116         unsigned int l, limit;
 117
 118         reg = DART_CNTL_U4_ENABLE | DART_CNTL_U4_IONE |
 119                 (bus_rpn & DART_CNTL_U4_IONE_MASK);
 120         DART_OUT(DART_CNTL, reg);
 121
 122         limit = 0;
 123 wait_more:
 124         l = 0;
 125         while ((DART_IN(DART_CNTL) & DART_CNTL_U4_IONE) && l < (1L << limit)) {
 126                 rmb();
 127                 l++;
 128         }
 129
 130         if (l == (1L << limit)) {
 131                 if (limit < 4) {
 132                         limit++;
 133                         goto wait_more;
 134                 } else
 135                         panic("DART: TLB did not flush after waiting a long "
 136                               "time. Buggy U4 ?");
 137         }
 138 }
 139
 140 static void dart_flush(struct iommu_table *tbl)
 141 {
 142         mb();
 143         if (dart_dirty) {
 144                 dart_tlb_invalidate_all();
 145                 dart_dirty = 0;
 146         }
 147 }
 148
 149 static void dart_build(struct iommu_table *tbl, long index,
 150                        long npages, unsigned long uaddr,
 151                        enum dma_data_direction direction)
 152 {
 153         unsigned int *dp;
 154         unsigned int rpn;
 155         long l;
 156
 157         DBG("dart: build at: %lx, %lx, addr: %x\n", index, npages, uaddr);
 158
 159         index <<= DART_PAGE_FACTOR;
 160         npages <<= DART_PAGE_FACTOR;
 161
 162         dp = ((unsigned int*)tbl->it_base) + index;
 163
 164         /* On U3, all memory is contigous, so we can move this
 165          * out of the loop.
 166          */
 167         l = npages;
 168         while (l--) {
 169                 rpn = virt_to_abs(uaddr) >> DART_PAGE_SHIFT;
 170
 171                 *(dp++) = DARTMAP_VALID | (rpn & DARTMAP_RPNMASK);
 172
 173                 uaddr += DART_PAGE_SIZE;
 174         }
 175
 176         /* make sure all updates have reached memory */
 177         mb();
 178         in_be32((unsigned __iomem *)dp);
 179         mb();
 180
 181         if (dart_is_u4) {
 182                 rpn = index;
 183                 while (npages--)
 184                         dart_tlb_invalidate_one(rpn++);
 185         } else {
 186                 dart_dirty = 1;
 187         }
 188 }
 189
 190
 191 static void dart_free(struct iommu_table *tbl, long index, long npages)
 192 {
 193         unsigned int *dp;
 194
 195         /* We don't worry about flushing the TLB cache. The only drawback of
 196          * not doing it is that we won't catch buggy device drivers doing
 197          * bad DMAs, but then no 32-bit architecture ever does either.
 198          */
 199
 200         DBG("dart: free at: %lx, %lx\n", index, npages);
 201
 202         index <<= DART_PAGE_FACTOR;
 203         npages <<= DART_PAGE_FACTOR;
 204
 205         dp  = ((unsigned int *)tbl->it_base) + index;
 206
 207         while (npages--)
 208                 *(dp++) = dart_emptyval;
 209 }
 210
 211
 212 static int dart_init(struct device_node *dart_node)
 213 {
 214         unsigned int i;
 215         unsigned long tmp, base, size;
 216         struct resource r;
 217
 218         if (dart_tablebase == 0 || dart_tablesize == 0) {
 219                 printk(KERN_INFO "DART: table not allocated, using "
 220                        "direct DMA\n");
 221                 return -ENODEV;
 222         }
 223
 224         if (of_address_to_resource(dart_node, 0, &r))
 225                 panic("DART: can't get register base ! ");
 226
 227         /* Make sure nothing from the DART range remains in the CPU cache
 228          * from a previous mapping that existed before the kernel took
 229          * over
 230          */
 231         flush_dcache_phys_range(dart_tablebase,
 232                                 dart_tablebase + dart_tablesize);
 233
 234         /* Allocate a spare page to map all invalid DART pages. We need to do
 235          * that to work around what looks like a problem with the HT bridge
 236          * prefetching into invalid pages and corrupting data
 237          */
 238         tmp = lmb_alloc(DART_PAGE_SIZE, DART_PAGE_SIZE);
 239         dart_emptyval = DARTMAP_VALID | ((tmp >> DART_PAGE_SHIFT) &
 240                                          DARTMAP_RPNMASK);
 241
 242         /* Map in DART registers */
 243         dart = ioremap(r.start, r.end - r.start + 1);
 244         if (dart == NULL)
 245                 panic("DART: Cannot map registers!");
 246
 247         /* Map in DART table */
 248         dart_vbase = ioremap(virt_to_abs(dart_tablebase), dart_tablesize);
 249
 250         /* Fill initial table */
 251         for (i = 0; i < dart_tablesize/4; i++)
 252                 dart_vbase[i] = dart_emptyval;
 253
 254         /* Initialize DART with table base and enable it. */
 255         base = dart_tablebase >> DART_PAGE_SHIFT;
 256         size = dart_tablesize >> DART_PAGE_SHIFT;
 257         if (dart_is_u4) {
 258                 size &= DART_SIZE_U4_SIZE_MASK;
 259                 DART_OUT(DART_BASE_U4, base);
 260                 DART_OUT(DART_SIZE_U4, size);
 261                 DART_OUT(DART_CNTL, DART_CNTL_U4_ENABLE);
 262         } else {
 263                 size &= DART_CNTL_U3_SIZE_MASK;
 264                 DART_OUT(DART_CNTL,
 265                          DART_CNTL_U3_ENABLE |
 266                          (base << DART_CNTL_U3_BASE_SHIFT) |
 267                          (size << DART_CNTL_U3_SIZE_SHIFT));
 268         }
 269
 270         /* Invalidate DART to get rid of possible stale TLBs */
 271         dart_tlb_invalidate_all();
 272
 273         printk(KERN_INFO "DART IOMMU initialized for %s type chipset\n",
 274                dart_is_u4 ? "U4" : "U3");
 275
 276         return 0;
 277 }
 278
 279 static void iommu_table_dart_setup(void)
 280 {
 281         iommu_table_dart.it_busno = 0;
 282         iommu_table_dart.it_offset = 0;
 283         /* it_size is in number of entries */
 284         iommu_table_dart.it_size = (dart_tablesize / sizeof(u32)) >> DART_PAGE_FACTOR;
 285
 286         /* Initialize the common IOMMU code */
 287         iommu_table_dart.it_base = (unsigned long)dart_vbase;
 288         iommu_table_dart.it_index = 0;
 289         iommu_table_dart.it_blocksize = 1;
 290         iommu_init_table(&iommu_table_dart, -1);
 291
 292         /* Reserve the last page of the DART to avoid possible prefetch
 293          * past the DART mapped area
 294          */
 295         set_bit(iommu_table_dart.it_size - 1, iommu_table_dart.it_map);
 296 }
 297
 298 static void iommu_dev_setup_dart(struct pci_dev *dev)
 299 {
 300         struct device_node *dn;
 301
 302         /* We only have one iommu table on the mac for now, which makes
 303          * things simple. Setup all PCI devices to point to this table
 304          *
 305          * We must use pci_device_to_OF_node() to make sure that
 306          * we get the real "final" pointer to the device in the
 307          * pci_dev sysdata and not the temporary PHB one
 308          */
 309         dn = pci_device_to_OF_node(dev);
 310
 311         if (dn)
 312                 PCI_DN(dn)->iommu_table = &iommu_table_dart;
 313 }
 314
 315 static void iommu_bus_setup_dart(struct pci_bus *bus)
 316 {
 317         struct device_node *dn;
 318
 319         if (!iommu_table_dart_inited) {
 320                 iommu_table_dart_inited = 1;
 321                 iommu_table_dart_setup();
 322         }
 323
 324         dn = pci_bus_to_OF_node(bus);
 325
 326         if (dn)
 327                 PCI_DN(dn)->iommu_table = &iommu_table_dart;
 328 }
 329
 330 static void iommu_dev_setup_null(struct pci_dev *dev) { }
 331 static void iommu_bus_setup_null(struct pci_bus *bus) { }
 332
 333 void iommu_init_early_dart(void)
 334 {
 335         struct device_node *dn;
 336
 337         /* Find the DART in the device-tree */
 338         dn = of_find_compatible_node(NULL, "dart", "u3-dart");
 339         if (dn == NULL) {
 340                 dn = of_find_compatible_node(NULL, "dart", "u4-dart");
 341                 if (dn == NULL)
 342                         goto bail;
 343                 dart_is_u4 = 1;
 344         }
 345
 346         /* Setup low level TCE operations for the core IOMMU code */
 347         ppc_md.tce_build = dart_build;
 348         ppc_md.tce_free  = dart_free;
 349         ppc_md.tce_flush = dart_flush;
 350
 351         /* Initialize the DART HW */
 352         if (dart_init(dn) == 0) {
 353                 ppc_md.iommu_dev_setup = iommu_dev_setup_dart;
 354                 ppc_md.iommu_bus_setup = iommu_bus_setup_dart;
 355
 356                 /* Setup pci_dma ops */
 357                 pci_iommu_init();
 358
 359                 return;
 360         }
 361
 362  bail:
 363         /* If init failed, use direct iommu and null setup functions */
 364         ppc_md.iommu_dev_setup = iommu_dev_setup_null;
 365         ppc_md.iommu_bus_setup = iommu_bus_setup_null;
 366
 367         /* Setup pci_dma ops */
 368         pci_direct_iommu_init();
 369 }
 370
 371
 372 void __init alloc_dart_table(void)
 373 {
 374         /* Only reserve DART space if machine has more than 1GB of RAM
 375          * or if requested with iommu=on on cmdline.
 376          *
 377          * 1GB of RAM is picked as limit because some default devices
 378          * (i.e. Airport Extreme) have 30 bit address range limits.
 379          */
 380
 381         if (iommu_is_off)
 382                 return;
 383
 384         if (!iommu_force_on && lmb_end_of_DRAM() <= 0x40000000ull)
 385                 return;
 386
 387         /* 512 pages (2MB) is max DART tablesize. */
 388         dart_tablesize = 1UL << 21;
 389         /* 16MB (1 << 24) alignment. We allocate a full 16Mb chuck since we
 390          * will blow up an entire large page anyway in the kernel mapping
 391          */
 392         dart_tablebase = (unsigned long)
 393                 abs_to_virt(lmb_alloc_base(1UL<<24, 1UL<<24, 0x80000000L));
 394
 395         printk(KERN_INFO "DART table allocated at: %lx\n", dart_tablebase);
 396 }