2 * arch/ppc/syslib/mv64x60.c
4 * Common routines for the Marvell/Galileo Discovery line of host bridges
5 * (gt64260, mv64360, mv64460, ...).
7 * Author: Mark A. Greer <mgreer@mvista.com>
9 * 2004 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/pci.h>
17 #include <linux/slab.h>
18 #include <linux/module.h>
19 #include <linux/string.h>
20 #include <linux/spinlock.h>
21 #include <linux/mv643xx.h>
22 #include <linux/platform_device.h>
24 #include <asm/byteorder.h>
27 #include <asm/uaccess.h>
28 #include <asm/machdep.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/delay.h>
31 #include <asm/mv64x60.h>
34 u8 mv64x60_pci_exclude_bridge
= 1;
35 DEFINE_SPINLOCK(mv64x60_lock
);
37 static phys_addr_t mv64x60_bridge_pbase
;
38 static void __iomem
*mv64x60_bridge_vbase
;
39 static u32 mv64x60_bridge_type
= MV64x60_TYPE_INVALID
;
40 static u32 mv64x60_bridge_rev
;
41 #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
42 static struct pci_controller sysfs_hose_a
;
45 static u32
gt64260_translate_size(u32 base
, u32 size
, u32 num_bits
);
46 static u32
gt64260_untranslate_size(u32 base
, u32 size
, u32 num_bits
);
47 static void gt64260_set_pci2mem_window(struct pci_controller
*hose
, u32 bus
,
48 u32 window
, u32 base
);
49 static void gt64260_set_pci2regs_window(struct mv64x60_handle
*bh
,
50 struct pci_controller
*hose
, u32 bus
, u32 base
);
51 static u32
gt64260_is_enabled_32bit(struct mv64x60_handle
*bh
, u32 window
);
52 static void gt64260_enable_window_32bit(struct mv64x60_handle
*bh
, u32 window
);
53 static void gt64260_disable_window_32bit(struct mv64x60_handle
*bh
, u32 window
);
54 static void gt64260_enable_window_64bit(struct mv64x60_handle
*bh
, u32 window
);
55 static void gt64260_disable_window_64bit(struct mv64x60_handle
*bh
, u32 window
);
56 static void gt64260_disable_all_windows(struct mv64x60_handle
*bh
,
57 struct mv64x60_setup_info
*si
);
58 static void gt64260a_chip_specific_init(struct mv64x60_handle
*bh
,
59 struct mv64x60_setup_info
*si
);
60 static void gt64260b_chip_specific_init(struct mv64x60_handle
*bh
,
61 struct mv64x60_setup_info
*si
);
63 static u32
mv64360_translate_size(u32 base
, u32 size
, u32 num_bits
);
64 static u32
mv64360_untranslate_size(u32 base
, u32 size
, u32 num_bits
);
65 static void mv64360_set_pci2mem_window(struct pci_controller
*hose
, u32 bus
,
66 u32 window
, u32 base
);
67 static void mv64360_set_pci2regs_window(struct mv64x60_handle
*bh
,
68 struct pci_controller
*hose
, u32 bus
, u32 base
);
69 static u32
mv64360_is_enabled_32bit(struct mv64x60_handle
*bh
, u32 window
);
70 static void mv64360_enable_window_32bit(struct mv64x60_handle
*bh
, u32 window
);
71 static void mv64360_disable_window_32bit(struct mv64x60_handle
*bh
, u32 window
);
72 static void mv64360_enable_window_64bit(struct mv64x60_handle
*bh
, u32 window
);
73 static void mv64360_disable_window_64bit(struct mv64x60_handle
*bh
, u32 window
);
74 static void mv64360_disable_all_windows(struct mv64x60_handle
*bh
,
75 struct mv64x60_setup_info
*si
);
76 static void mv64360_config_io2mem_windows(struct mv64x60_handle
*bh
,
77 struct mv64x60_setup_info
*si
,
78 u32 mem_windows
[MV64x60_CPU2MEM_WINDOWS
][2]);
79 static void mv64360_set_mpsc2regs_window(struct mv64x60_handle
*bh
, u32 base
);
80 static void mv64360_chip_specific_init(struct mv64x60_handle
*bh
,
81 struct mv64x60_setup_info
*si
);
82 static void mv64460_chip_specific_init(struct mv64x60_handle
*bh
,
83 struct mv64x60_setup_info
*si
);
87 * Define tables that have the chip-specific info for each type of
88 * Marvell bridge chip.
90 static struct mv64x60_chip_info gt64260a_ci __initdata
= { /* GT64260A */
91 .translate_size
= gt64260_translate_size
,
92 .untranslate_size
= gt64260_untranslate_size
,
93 .set_pci2mem_window
= gt64260_set_pci2mem_window
,
94 .set_pci2regs_window
= gt64260_set_pci2regs_window
,
95 .is_enabled_32bit
= gt64260_is_enabled_32bit
,
96 .enable_window_32bit
= gt64260_enable_window_32bit
,
97 .disable_window_32bit
= gt64260_disable_window_32bit
,
98 .enable_window_64bit
= gt64260_enable_window_64bit
,
99 .disable_window_64bit
= gt64260_disable_window_64bit
,
100 .disable_all_windows
= gt64260_disable_all_windows
,
101 .chip_specific_init
= gt64260a_chip_specific_init
,
102 .window_tab_32bit
= gt64260_32bit_windows
,
103 .window_tab_64bit
= gt64260_64bit_windows
,
106 static struct mv64x60_chip_info gt64260b_ci __initdata
= { /* GT64260B */
107 .translate_size
= gt64260_translate_size
,
108 .untranslate_size
= gt64260_untranslate_size
,
109 .set_pci2mem_window
= gt64260_set_pci2mem_window
,
110 .set_pci2regs_window
= gt64260_set_pci2regs_window
,
111 .is_enabled_32bit
= gt64260_is_enabled_32bit
,
112 .enable_window_32bit
= gt64260_enable_window_32bit
,
113 .disable_window_32bit
= gt64260_disable_window_32bit
,
114 .enable_window_64bit
= gt64260_enable_window_64bit
,
115 .disable_window_64bit
= gt64260_disable_window_64bit
,
116 .disable_all_windows
= gt64260_disable_all_windows
,
117 .chip_specific_init
= gt64260b_chip_specific_init
,
118 .window_tab_32bit
= gt64260_32bit_windows
,
119 .window_tab_64bit
= gt64260_64bit_windows
,
122 static struct mv64x60_chip_info mv64360_ci __initdata
= { /* MV64360 */
123 .translate_size
= mv64360_translate_size
,
124 .untranslate_size
= mv64360_untranslate_size
,
125 .set_pci2mem_window
= mv64360_set_pci2mem_window
,
126 .set_pci2regs_window
= mv64360_set_pci2regs_window
,
127 .is_enabled_32bit
= mv64360_is_enabled_32bit
,
128 .enable_window_32bit
= mv64360_enable_window_32bit
,
129 .disable_window_32bit
= mv64360_disable_window_32bit
,
130 .enable_window_64bit
= mv64360_enable_window_64bit
,
131 .disable_window_64bit
= mv64360_disable_window_64bit
,
132 .disable_all_windows
= mv64360_disable_all_windows
,
133 .config_io2mem_windows
= mv64360_config_io2mem_windows
,
134 .set_mpsc2regs_window
= mv64360_set_mpsc2regs_window
,
135 .chip_specific_init
= mv64360_chip_specific_init
,
136 .window_tab_32bit
= mv64360_32bit_windows
,
137 .window_tab_64bit
= mv64360_64bit_windows
,
140 static struct mv64x60_chip_info mv64460_ci __initdata
= { /* MV64460 */
141 .translate_size
= mv64360_translate_size
,
142 .untranslate_size
= mv64360_untranslate_size
,
143 .set_pci2mem_window
= mv64360_set_pci2mem_window
,
144 .set_pci2regs_window
= mv64360_set_pci2regs_window
,
145 .is_enabled_32bit
= mv64360_is_enabled_32bit
,
146 .enable_window_32bit
= mv64360_enable_window_32bit
,
147 .disable_window_32bit
= mv64360_disable_window_32bit
,
148 .enable_window_64bit
= mv64360_enable_window_64bit
,
149 .disable_window_64bit
= mv64360_disable_window_64bit
,
150 .disable_all_windows
= mv64360_disable_all_windows
,
151 .config_io2mem_windows
= mv64360_config_io2mem_windows
,
152 .set_mpsc2regs_window
= mv64360_set_mpsc2regs_window
,
153 .chip_specific_init
= mv64460_chip_specific_init
,
154 .window_tab_32bit
= mv64360_32bit_windows
,
155 .window_tab_64bit
= mv64360_64bit_windows
,
159 *****************************************************************************
161 * Platform Device Definitions
163 *****************************************************************************
165 #ifdef CONFIG_SERIAL_MPSC
166 static struct mpsc_shared_pdata mv64x60_mpsc_shared_pdata
= {
167 .mrr_val
= 0x3ffffe38,
174 static struct resource mv64x60_mpsc_shared_resources
[] = {
175 /* Do not change the order of the IORESOURCE_MEM resources */
177 .name
= "mpsc routing base",
178 .start
= MV64x60_MPSC_ROUTING_OFFSET
,
179 .end
= MV64x60_MPSC_ROUTING_OFFSET
+
180 MPSC_ROUTING_REG_BLOCK_SIZE
- 1,
181 .flags
= IORESOURCE_MEM
,
184 .name
= "sdma intr base",
185 .start
= MV64x60_SDMA_INTR_OFFSET
,
186 .end
= MV64x60_SDMA_INTR_OFFSET
+
187 MPSC_SDMA_INTR_REG_BLOCK_SIZE
- 1,
188 .flags
= IORESOURCE_MEM
,
192 static struct platform_device mpsc_shared_device
= { /* Shared device */
193 .name
= MPSC_SHARED_NAME
,
195 .num_resources
= ARRAY_SIZE(mv64x60_mpsc_shared_resources
),
196 .resource
= mv64x60_mpsc_shared_resources
,
198 .platform_data
= &mv64x60_mpsc_shared_pdata
,
202 static struct mpsc_pdata mv64x60_mpsc0_pdata
= {
206 .default_baud
= 9600,
208 .default_parity
= 'n',
210 .chr_1_val
= 0x00000000,
211 .chr_2_val
= 0x00000000,
212 .chr_10_val
= 0x00000003,
216 .brg_clk_src
= 8, /* Default to TCLK */
217 .brg_clk_freq
= 100000000, /* Default to 100 MHz */
220 static struct resource mv64x60_mpsc0_resources
[] = {
221 /* Do not change the order of the IORESOURCE_MEM resources */
223 .name
= "mpsc 0 base",
224 .start
= MV64x60_MPSC_0_OFFSET
,
225 .end
= MV64x60_MPSC_0_OFFSET
+ MPSC_REG_BLOCK_SIZE
- 1,
226 .flags
= IORESOURCE_MEM
,
229 .name
= "sdma 0 base",
230 .start
= MV64x60_SDMA_0_OFFSET
,
231 .end
= MV64x60_SDMA_0_OFFSET
+ MPSC_SDMA_REG_BLOCK_SIZE
- 1,
232 .flags
= IORESOURCE_MEM
,
235 .name
= "brg 0 base",
236 .start
= MV64x60_BRG_0_OFFSET
,
237 .end
= MV64x60_BRG_0_OFFSET
+ MPSC_BRG_REG_BLOCK_SIZE
- 1,
238 .flags
= IORESOURCE_MEM
,
241 .name
= "sdma 0 irq",
242 .start
= MV64x60_IRQ_SDMA_0
,
243 .end
= MV64x60_IRQ_SDMA_0
,
244 .flags
= IORESOURCE_IRQ
,
248 static struct platform_device mpsc0_device
= {
249 .name
= MPSC_CTLR_NAME
,
251 .num_resources
= ARRAY_SIZE(mv64x60_mpsc0_resources
),
252 .resource
= mv64x60_mpsc0_resources
,
254 .platform_data
= &mv64x60_mpsc0_pdata
,
258 static struct mpsc_pdata mv64x60_mpsc1_pdata
= {
262 .default_baud
= 9600,
264 .default_parity
= 'n',
266 .chr_1_val
= 0x00000000,
267 .chr_1_val
= 0x00000000,
268 .chr_2_val
= 0x00000000,
269 .chr_10_val
= 0x00000003,
273 .brg_clk_src
= 8, /* Default to TCLK */
274 .brg_clk_freq
= 100000000, /* Default to 100 MHz */
277 static struct resource mv64x60_mpsc1_resources
[] = {
278 /* Do not change the order of the IORESOURCE_MEM resources */
280 .name
= "mpsc 1 base",
281 .start
= MV64x60_MPSC_1_OFFSET
,
282 .end
= MV64x60_MPSC_1_OFFSET
+ MPSC_REG_BLOCK_SIZE
- 1,
283 .flags
= IORESOURCE_MEM
,
286 .name
= "sdma 1 base",
287 .start
= MV64x60_SDMA_1_OFFSET
,
288 .end
= MV64x60_SDMA_1_OFFSET
+ MPSC_SDMA_REG_BLOCK_SIZE
- 1,
289 .flags
= IORESOURCE_MEM
,
292 .name
= "brg 1 base",
293 .start
= MV64x60_BRG_1_OFFSET
,
294 .end
= MV64x60_BRG_1_OFFSET
+ MPSC_BRG_REG_BLOCK_SIZE
- 1,
295 .flags
= IORESOURCE_MEM
,
298 .name
= "sdma 1 irq",
299 .start
= MV64360_IRQ_SDMA_1
,
300 .end
= MV64360_IRQ_SDMA_1
,
301 .flags
= IORESOURCE_IRQ
,
305 static struct platform_device mpsc1_device
= {
306 .name
= MPSC_CTLR_NAME
,
308 .num_resources
= ARRAY_SIZE(mv64x60_mpsc1_resources
),
309 .resource
= mv64x60_mpsc1_resources
,
311 .platform_data
= &mv64x60_mpsc1_pdata
,
316 #ifdef CONFIG_MV643XX_ETH
317 static struct resource mv64x60_eth_shared_resources
[] = {
319 .name
= "ethernet shared base",
320 .start
= MV643XX_ETH_SHARED_REGS
,
321 .end
= MV643XX_ETH_SHARED_REGS
+
322 MV643XX_ETH_SHARED_REGS_SIZE
- 1,
323 .flags
= IORESOURCE_MEM
,
327 static struct platform_device mv64x60_eth_shared_device
= {
328 .name
= MV643XX_ETH_SHARED_NAME
,
330 .num_resources
= ARRAY_SIZE(mv64x60_eth_shared_resources
),
331 .resource
= mv64x60_eth_shared_resources
,
334 #ifdef CONFIG_MV643XX_ETH_0
335 static struct resource mv64x60_eth0_resources
[] = {
338 .start
= MV64x60_IRQ_ETH_0
,
339 .end
= MV64x60_IRQ_ETH_0
,
340 .flags
= IORESOURCE_IRQ
,
344 static struct mv643xx_eth_platform_data eth0_pd
;
346 static struct platform_device eth0_device
= {
347 .name
= MV643XX_ETH_NAME
,
349 .num_resources
= ARRAY_SIZE(mv64x60_eth0_resources
),
350 .resource
= mv64x60_eth0_resources
,
352 .platform_data
= ð0_pd
,
357 #ifdef CONFIG_MV643XX_ETH_1
358 static struct resource mv64x60_eth1_resources
[] = {
361 .start
= MV64x60_IRQ_ETH_1
,
362 .end
= MV64x60_IRQ_ETH_1
,
363 .flags
= IORESOURCE_IRQ
,
367 static struct mv643xx_eth_platform_data eth1_pd
;
369 static struct platform_device eth1_device
= {
370 .name
= MV643XX_ETH_NAME
,
372 .num_resources
= ARRAY_SIZE(mv64x60_eth1_resources
),
373 .resource
= mv64x60_eth1_resources
,
375 .platform_data
= ð1_pd
,
380 #ifdef CONFIG_MV643XX_ETH_2
381 static struct resource mv64x60_eth2_resources
[] = {
384 .start
= MV64x60_IRQ_ETH_2
,
385 .end
= MV64x60_IRQ_ETH_2
,
386 .flags
= IORESOURCE_IRQ
,
390 static struct mv643xx_eth_platform_data eth2_pd
;
392 static struct platform_device eth2_device
= {
393 .name
= MV643XX_ETH_NAME
,
395 .num_resources
= ARRAY_SIZE(mv64x60_eth2_resources
),
396 .resource
= mv64x60_eth2_resources
,
398 .platform_data
= ð2_pd
,
404 #ifdef CONFIG_I2C_MV64XXX
405 static struct mv64xxx_i2c_pdata mv64xxx_i2c_pdata
= {
408 .timeout
= 1000, /* Default timeout of 1 second */
412 static struct resource mv64xxx_i2c_resources
[] = {
413 /* Do not change the order of the IORESOURCE_MEM resources */
415 .name
= "mv64xxx i2c base",
416 .start
= MV64XXX_I2C_OFFSET
,
417 .end
= MV64XXX_I2C_OFFSET
+ MV64XXX_I2C_REG_BLOCK_SIZE
- 1,
418 .flags
= IORESOURCE_MEM
,
421 .name
= "mv64xxx i2c irq",
422 .start
= MV64x60_IRQ_I2C
,
423 .end
= MV64x60_IRQ_I2C
,
424 .flags
= IORESOURCE_IRQ
,
428 static struct platform_device i2c_device
= {
429 .name
= MV64XXX_I2C_CTLR_NAME
,
431 .num_resources
= ARRAY_SIZE(mv64xxx_i2c_resources
),
432 .resource
= mv64xxx_i2c_resources
,
434 .platform_data
= &mv64xxx_i2c_pdata
,
439 #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
440 static struct mv64xxx_pdata mv64xxx_pdata
= {
444 static struct platform_device mv64xxx_device
= { /* general mv64x60 stuff */
445 .name
= MV64XXX_DEV_NAME
,
448 .platform_data
= &mv64xxx_pdata
,
453 static struct platform_device
*mv64x60_pd_devs
[] __initdata
= {
454 #ifdef CONFIG_SERIAL_MPSC
459 #ifdef CONFIG_MV643XX_ETH
460 &mv64x60_eth_shared_device
,
462 #ifdef CONFIG_MV643XX_ETH_0
465 #ifdef CONFIG_MV643XX_ETH_1
468 #ifdef CONFIG_MV643XX_ETH_2
471 #ifdef CONFIG_I2C_MV64XXX
474 #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
480 *****************************************************************************
482 * Bridge Initialization Routines
484 *****************************************************************************
489 * Initialze the bridge based on setting passed in via 'si'. The bridge
490 * handle, 'bh', will be set so that it can be used to make subsequent
491 * calls to routines in this file.
494 mv64x60_init(struct mv64x60_handle
*bh
, struct mv64x60_setup_info
*si
)
496 u32 mem_windows
[MV64x60_CPU2MEM_WINDOWS
][2];
499 ppc_md
.progress("mv64x60 initialization", 0x0);
501 spin_lock_init(&mv64x60_lock
);
502 mv64x60_early_init(bh
, si
);
504 if (mv64x60_get_type(bh
) || mv64x60_setup_for_chip(bh
)) {
508 ppc_md
.progress("mv64x60_init: Can't determine chip",0);
512 bh
->ci
->disable_all_windows(bh
, si
);
513 mv64x60_get_mem_windows(bh
, mem_windows
);
514 mv64x60_config_cpu2mem_windows(bh
, si
, mem_windows
);
516 if (bh
->ci
->config_io2mem_windows
)
517 bh
->ci
->config_io2mem_windows(bh
, si
, mem_windows
);
518 if (bh
->ci
->set_mpsc2regs_window
)
519 bh
->ci
->set_mpsc2regs_window(bh
, si
->phys_reg_base
);
521 if (si
->pci_1
.enable_bus
) {
522 bh
->io_base_b
= (u32
)ioremap(si
->pci_1
.pci_io
.cpu_base
,
523 si
->pci_1
.pci_io
.size
);
524 isa_io_base
= bh
->io_base_b
;
527 if (si
->pci_0
.enable_bus
) {
528 bh
->io_base_a
= (u32
)ioremap(si
->pci_0
.pci_io
.cpu_base
,
529 si
->pci_0
.pci_io
.size
);
530 isa_io_base
= bh
->io_base_a
;
532 mv64x60_alloc_hose(bh
, MV64x60_PCI0_CONFIG_ADDR
,
533 MV64x60_PCI0_CONFIG_DATA
, &bh
->hose_a
);
534 mv64x60_config_resources(bh
->hose_a
, &si
->pci_0
, bh
->io_base_a
);
535 mv64x60_config_pci_params(bh
->hose_a
, &si
->pci_0
);
537 mv64x60_config_cpu2pci_windows(bh
, &si
->pci_0
, 0);
538 mv64x60_config_pci2mem_windows(bh
, bh
->hose_a
, &si
->pci_0
, 0,
540 bh
->ci
->set_pci2regs_window(bh
, bh
->hose_a
, 0,
544 if (si
->pci_1
.enable_bus
) {
545 mv64x60_alloc_hose(bh
, MV64x60_PCI1_CONFIG_ADDR
,
546 MV64x60_PCI1_CONFIG_DATA
, &bh
->hose_b
);
547 mv64x60_config_resources(bh
->hose_b
, &si
->pci_1
, bh
->io_base_b
);
548 mv64x60_config_pci_params(bh
->hose_b
, &si
->pci_1
);
550 mv64x60_config_cpu2pci_windows(bh
, &si
->pci_1
, 1);
551 mv64x60_config_pci2mem_windows(bh
, bh
->hose_b
, &si
->pci_1
, 1,
553 bh
->ci
->set_pci2regs_window(bh
, bh
->hose_b
, 1,
557 bh
->ci
->chip_specific_init(bh
, si
);
558 mv64x60_pd_fixup(bh
, mv64x60_pd_devs
, ARRAY_SIZE(mv64x60_pd_devs
));
564 * mv64x60_early_init()
566 * Do some bridge work that must take place before we start messing with
567 * the bridge for real.
570 mv64x60_early_init(struct mv64x60_handle
*bh
, struct mv64x60_setup_info
*si
)
572 struct pci_controller hose_a
, hose_b
;
574 memset(bh
, 0, sizeof(*bh
));
576 bh
->p_base
= si
->phys_reg_base
;
577 bh
->v_base
= ioremap(bh
->p_base
, MV64x60_INTERNAL_SPACE_SIZE
);
579 mv64x60_bridge_pbase
= bh
->p_base
;
580 mv64x60_bridge_vbase
= bh
->v_base
;
582 /* Assuming pci mode [reserved] bits 4:5 on 64260 are 0 */
583 bh
->pci_mode_a
= mv64x60_read(bh
, MV64x60_PCI0_MODE
) &
584 MV64x60_PCIMODE_MASK
;
585 bh
->pci_mode_b
= mv64x60_read(bh
, MV64x60_PCI1_MODE
) &
586 MV64x60_PCIMODE_MASK
;
588 /* Need temporary hose structs to call mv64x60_set_bus() */
589 memset(&hose_a
, 0, sizeof(hose_a
));
590 memset(&hose_b
, 0, sizeof(hose_b
));
591 setup_indirect_pci_nomap(&hose_a
, bh
->v_base
+ MV64x60_PCI0_CONFIG_ADDR
,
592 bh
->v_base
+ MV64x60_PCI0_CONFIG_DATA
);
593 setup_indirect_pci_nomap(&hose_b
, bh
->v_base
+ MV64x60_PCI1_CONFIG_ADDR
,
594 bh
->v_base
+ MV64x60_PCI1_CONFIG_DATA
);
595 bh
->hose_a
= &hose_a
;
596 bh
->hose_b
= &hose_b
;
598 #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
599 /* Save a copy of hose_a for sysfs functions -- hack */
600 memcpy(&sysfs_hose_a
, &hose_a
, sizeof(hose_a
));
603 mv64x60_set_bus(bh
, 0, 0);
604 mv64x60_set_bus(bh
, 1, 0);
609 /* Clear bit 0 of PCI addr decode control so PCI->CPU remap 1:1 */
610 mv64x60_clr_bits(bh
, MV64x60_PCI0_PCI_DECODE_CNTL
, 0x00000001);
611 mv64x60_clr_bits(bh
, MV64x60_PCI1_PCI_DECODE_CNTL
, 0x00000001);
613 /* Bit 12 MUST be 0; set bit 27--don't auto-update cpu remap regs */
614 mv64x60_clr_bits(bh
, MV64x60_CPU_CONFIG
, (1<<12));
615 mv64x60_set_bits(bh
, MV64x60_CPU_CONFIG
, (1<<27));
617 mv64x60_set_bits(bh
, MV64x60_PCI0_TO_RETRY
, 0xffff);
618 mv64x60_set_bits(bh
, MV64x60_PCI1_TO_RETRY
, 0xffff);
622 *****************************************************************************
624 * Window Config Routines
626 *****************************************************************************
629 * mv64x60_get_32bit_window()
631 * Determine the base address and size of a 32-bit window on the bridge.
634 mv64x60_get_32bit_window(struct mv64x60_handle
*bh
, u32 window
,
635 u32
*base
, u32
*size
)
637 u32 val
, base_reg
, size_reg
, base_bits
, size_bits
;
638 u32 (*get_from_field
)(u32 val
, u32 num_bits
);
640 base_reg
= bh
->ci
->window_tab_32bit
[window
].base_reg
;
643 size_reg
= bh
->ci
->window_tab_32bit
[window
].size_reg
;
644 base_bits
= bh
->ci
->window_tab_32bit
[window
].base_bits
;
645 size_bits
= bh
->ci
->window_tab_32bit
[window
].size_bits
;
646 get_from_field
= bh
->ci
->window_tab_32bit
[window
].get_from_field
;
648 val
= mv64x60_read(bh
, base_reg
);
649 *base
= get_from_field(val
, base_bits
);
652 val
= mv64x60_read(bh
, size_reg
);
653 val
= get_from_field(val
, size_bits
);
654 *size
= bh
->ci
->untranslate_size(*base
, val
, size_bits
);
662 pr_debug("get 32bit window: %d, base: 0x%x, size: 0x%x\n",
663 window
, *base
, *size
);
667 * mv64x60_set_32bit_window()
669 * Set the base address and size of a 32-bit window on the bridge.
672 mv64x60_set_32bit_window(struct mv64x60_handle
*bh
, u32 window
,
673 u32 base
, u32 size
, u32 other_bits
)
675 u32 val
, base_reg
, size_reg
, base_bits
, size_bits
;
676 u32 (*map_to_field
)(u32 val
, u32 num_bits
);
678 pr_debug("set 32bit window: %d, base: 0x%x, size: 0x%x, other: 0x%x\n",
679 window
, base
, size
, other_bits
);
681 base_reg
= bh
->ci
->window_tab_32bit
[window
].base_reg
;
684 size_reg
= bh
->ci
->window_tab_32bit
[window
].size_reg
;
685 base_bits
= bh
->ci
->window_tab_32bit
[window
].base_bits
;
686 size_bits
= bh
->ci
->window_tab_32bit
[window
].size_bits
;
687 map_to_field
= bh
->ci
->window_tab_32bit
[window
].map_to_field
;
689 val
= map_to_field(base
, base_bits
) | other_bits
;
690 mv64x60_write(bh
, base_reg
, val
);
693 val
= bh
->ci
->translate_size(base
, size
, size_bits
);
694 val
= map_to_field(val
, size_bits
);
695 mv64x60_write(bh
, size_reg
, val
);
698 (void)mv64x60_read(bh
, base_reg
); /* Flush FIFO */
703 * mv64x60_get_64bit_window()
705 * Determine the base address and size of a 64-bit window on the bridge.
708 mv64x60_get_64bit_window(struct mv64x60_handle
*bh
, u32 window
,
709 u32
*base_hi
, u32
*base_lo
, u32
*size
)
711 u32 val
, base_lo_reg
, size_reg
, base_lo_bits
, size_bits
;
712 u32 (*get_from_field
)(u32 val
, u32 num_bits
);
714 base_lo_reg
= bh
->ci
->window_tab_64bit
[window
].base_lo_reg
;
716 if (base_lo_reg
!= 0) {
717 size_reg
= bh
->ci
->window_tab_64bit
[window
].size_reg
;
718 base_lo_bits
= bh
->ci
->window_tab_64bit
[window
].base_lo_bits
;
719 size_bits
= bh
->ci
->window_tab_64bit
[window
].size_bits
;
720 get_from_field
= bh
->ci
->window_tab_64bit
[window
].get_from_field
;
722 *base_hi
= mv64x60_read(bh
,
723 bh
->ci
->window_tab_64bit
[window
].base_hi_reg
);
725 val
= mv64x60_read(bh
, base_lo_reg
);
726 *base_lo
= get_from_field(val
, base_lo_bits
);
729 val
= mv64x60_read(bh
, size_reg
);
730 val
= get_from_field(val
, size_bits
);
731 *size
= bh
->ci
->untranslate_size(*base_lo
, val
,
741 pr_debug("get 64bit window: %d, base hi: 0x%x, base lo: 0x%x, "
742 "size: 0x%x\n", window
, *base_hi
, *base_lo
, *size
);
746 * mv64x60_set_64bit_window()
748 * Set the base address and size of a 64-bit window on the bridge.
751 mv64x60_set_64bit_window(struct mv64x60_handle
*bh
, u32 window
,
752 u32 base_hi
, u32 base_lo
, u32 size
, u32 other_bits
)
754 u32 val
, base_lo_reg
, size_reg
, base_lo_bits
, size_bits
;
755 u32 (*map_to_field
)(u32 val
, u32 num_bits
);
757 pr_debug("set 64bit window: %d, base hi: 0x%x, base lo: 0x%x, "
758 "size: 0x%x, other: 0x%x\n",
759 window
, base_hi
, base_lo
, size
, other_bits
);
761 base_lo_reg
= bh
->ci
->window_tab_64bit
[window
].base_lo_reg
;
763 if (base_lo_reg
!= 0) {
764 size_reg
= bh
->ci
->window_tab_64bit
[window
].size_reg
;
765 base_lo_bits
= bh
->ci
->window_tab_64bit
[window
].base_lo_bits
;
766 size_bits
= bh
->ci
->window_tab_64bit
[window
].size_bits
;
767 map_to_field
= bh
->ci
->window_tab_64bit
[window
].map_to_field
;
769 mv64x60_write(bh
, bh
->ci
->window_tab_64bit
[window
].base_hi_reg
,
772 val
= map_to_field(base_lo
, base_lo_bits
) | other_bits
;
773 mv64x60_write(bh
, base_lo_reg
, val
);
776 val
= bh
->ci
->translate_size(base_lo
, size
, size_bits
);
777 val
= map_to_field(val
, size_bits
);
778 mv64x60_write(bh
, size_reg
, val
);
781 (void)mv64x60_read(bh
, base_lo_reg
); /* Flush FIFO */
788 * Take the high-order 'num_bits' of 'val' & mask off low bits.
791 mv64x60_mask(u32 val
, u32 num_bits
)
793 return val
& (0xffffffff << (32 - num_bits
));
797 * mv64x60_shift_left()
799 * Take the low-order 'num_bits' of 'val', shift left to align at bit 31 (MSB).
802 mv64x60_shift_left(u32 val
, u32 num_bits
)
804 return val
<< (32 - num_bits
);
808 * mv64x60_shift_right()
810 * Take the high-order 'num_bits' of 'val', shift right to align at bit 0 (LSB).
813 mv64x60_shift_right(u32 val
, u32 num_bits
)
815 return val
>> (32 - num_bits
);
819 *****************************************************************************
821 * Chip Identification Routines
823 *****************************************************************************
828 * Determine the type of bridge chip we have.
831 mv64x60_get_type(struct mv64x60_handle
*bh
)
833 struct pci_controller hose
;
837 memset(&hose
, 0, sizeof(hose
));
838 setup_indirect_pci_nomap(&hose
, bh
->v_base
+ MV64x60_PCI0_CONFIG_ADDR
,
839 bh
->v_base
+ MV64x60_PCI0_CONFIG_DATA
);
841 save_exclude
= mv64x60_pci_exclude_bridge
;
842 mv64x60_pci_exclude_bridge
= 0;
843 /* Sanity check of bridge's Vendor ID */
844 early_read_config_word(&hose
, 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID
, &val
);
846 if (val
!= PCI_VENDOR_ID_MARVELL
) {
847 mv64x60_pci_exclude_bridge
= save_exclude
;
851 /* Get the revision of the chip */
852 early_read_config_word(&hose
, 0, PCI_DEVFN(0, 0), PCI_CLASS_REVISION
,
854 bh
->rev
= (u32
)(val
& 0xff);
856 /* Figure out the type of Marvell bridge it is */
857 early_read_config_word(&hose
, 0, PCI_DEVFN(0, 0), PCI_DEVICE_ID
, &val
);
858 mv64x60_pci_exclude_bridge
= save_exclude
;
861 case PCI_DEVICE_ID_MARVELL_GT64260
:
864 bh
->type
= MV64x60_TYPE_GT64260A
;
868 printk(KERN_WARNING
"Unsupported GT64260 rev %04x\n",
870 /* Assume its similar to a 'B' rev and fallthru */
872 bh
->type
= MV64x60_TYPE_GT64260B
;
877 case PCI_DEVICE_ID_MARVELL_MV64360
:
878 /* Marvell won't tell me how to distinguish a 64361 & 64362 */
879 bh
->type
= MV64x60_TYPE_MV64360
;
882 case PCI_DEVICE_ID_MARVELL_MV64460
:
883 bh
->type
= MV64x60_TYPE_MV64460
;
887 printk(KERN_ERR
"Unknown Marvell bridge type %04x\n", val
);
891 /* Hang onto bridge type & rev for PIC code */
892 mv64x60_bridge_type
= bh
->type
;
893 mv64x60_bridge_rev
= bh
->rev
;
899 * mv64x60_setup_for_chip()
901 * Set 'bh' to use the proper set of routine for the bridge chip that we have.
904 mv64x60_setup_for_chip(struct mv64x60_handle
*bh
)
908 /* Set up chip-specific info based on the chip/bridge type */
910 case MV64x60_TYPE_GT64260A
:
911 bh
->ci
= >64260a_ci
;
914 case MV64x60_TYPE_GT64260B
:
915 bh
->ci
= >64260b_ci
;
918 case MV64x60_TYPE_MV64360
:
919 bh
->ci
= &mv64360_ci
;
922 case MV64x60_TYPE_MV64460
:
923 bh
->ci
= &mv64460_ci
;
926 case MV64x60_TYPE_INVALID
:
929 ppc_md
.progress("mv64x60: Unsupported bridge", 0x0);
930 printk(KERN_ERR
"mv64x60: Unsupported bridge\n");
938 * mv64x60_get_bridge_vbase()
940 * Return the virtual address of the bridge's registers.
943 mv64x60_get_bridge_vbase(void)
945 return mv64x60_bridge_vbase
;
949 * mv64x60_get_bridge_type()
951 * Return the type of bridge on the platform.
954 mv64x60_get_bridge_type(void)
956 return mv64x60_bridge_type
;
960 * mv64x60_get_bridge_rev()
962 * Return the revision of the bridge on the platform.
965 mv64x60_get_bridge_rev(void)
967 return mv64x60_bridge_rev
;
971 *****************************************************************************
973 * System Memory Window Related Routines
975 *****************************************************************************
978 * mv64x60_get_mem_size()
980 * Calculate the amount of memory that the memory controller is set up for.
981 * This should only be used by board-specific code if there is no other
982 * way to determine the amount of memory in the system.
985 mv64x60_get_mem_size(u32 bridge_base
, u32 chip_type
)
987 struct mv64x60_handle bh
;
988 u32 mem_windows
[MV64x60_CPU2MEM_WINDOWS
][2];
991 memset(&bh
, 0, sizeof(bh
));
994 bh
.v_base
= (void *)bridge_base
;
996 if (!mv64x60_setup_for_chip(&bh
)) {
997 mv64x60_get_mem_windows(&bh
, mem_windows
);
998 rc
= mv64x60_calc_mem_size(&bh
, mem_windows
);
1005 * mv64x60_get_mem_windows()
1007 * Get the values in the memory controller & return in the 'mem_windows' array.
1010 mv64x60_get_mem_windows(struct mv64x60_handle
*bh
,
1011 u32 mem_windows
[MV64x60_CPU2MEM_WINDOWS
][2])
1015 for (win
=MV64x60_CPU2MEM_0_WIN
,i
=0;win
<=MV64x60_CPU2MEM_3_WIN
;win
++,i
++)
1016 if (bh
->ci
->is_enabled_32bit(bh
, win
))
1017 mv64x60_get_32bit_window(bh
, win
,
1018 &mem_windows
[i
][0], &mem_windows
[i
][1]);
1020 mem_windows
[i
][0] = 0;
1021 mem_windows
[i
][1] = 0;
1026 * mv64x60_calc_mem_size()
1028 * Using the memory controller register values in 'mem_windows', determine
1029 * how much memory it is set up for.
1032 mv64x60_calc_mem_size(struct mv64x60_handle
*bh
,
1033 u32 mem_windows
[MV64x60_CPU2MEM_WINDOWS
][2])
1037 for (i
=0; i
<MV64x60_CPU2MEM_WINDOWS
; i
++)
1038 total
+= mem_windows
[i
][1];
1044 *****************************************************************************
1046 * CPU->System MEM, PCI Config Routines
1048 *****************************************************************************
1051 * mv64x60_config_cpu2mem_windows()
1053 * Configure CPU->Memory windows on the bridge.
1055 static u32 prot_tab
[] __initdata
= {
1056 MV64x60_CPU_PROT_0_WIN
, MV64x60_CPU_PROT_1_WIN
,
1057 MV64x60_CPU_PROT_2_WIN
, MV64x60_CPU_PROT_3_WIN
1060 static u32 cpu_snoop_tab
[] __initdata
= {
1061 MV64x60_CPU_SNOOP_0_WIN
, MV64x60_CPU_SNOOP_1_WIN
,
1062 MV64x60_CPU_SNOOP_2_WIN
, MV64x60_CPU_SNOOP_3_WIN
1066 mv64x60_config_cpu2mem_windows(struct mv64x60_handle
*bh
,
1067 struct mv64x60_setup_info
*si
,
1068 u32 mem_windows
[MV64x60_CPU2MEM_WINDOWS
][2])
1072 /* Set CPU protection & snoop windows */
1073 for (win
=MV64x60_CPU2MEM_0_WIN
,i
=0;win
<=MV64x60_CPU2MEM_3_WIN
;win
++,i
++)
1074 if (bh
->ci
->is_enabled_32bit(bh
, win
)) {
1075 mv64x60_set_32bit_window(bh
, prot_tab
[i
],
1076 mem_windows
[i
][0], mem_windows
[i
][1],
1077 si
->cpu_prot_options
[i
]);
1078 bh
->ci
->enable_window_32bit(bh
, prot_tab
[i
]);
1080 if (bh
->ci
->window_tab_32bit
[cpu_snoop_tab
[i
]].
1082 mv64x60_set_32bit_window(bh
, cpu_snoop_tab
[i
],
1083 mem_windows
[i
][0], mem_windows
[i
][1],
1084 si
->cpu_snoop_options
[i
]);
1085 bh
->ci
->enable_window_32bit(bh
,
1093 * mv64x60_config_cpu2pci_windows()
1095 * Configure the CPU->PCI windows for one of the PCI buses.
1097 static u32 win_tab
[2][4] __initdata
= {
1098 { MV64x60_CPU2PCI0_IO_WIN
, MV64x60_CPU2PCI0_MEM_0_WIN
,
1099 MV64x60_CPU2PCI0_MEM_1_WIN
, MV64x60_CPU2PCI0_MEM_2_WIN
},
1100 { MV64x60_CPU2PCI1_IO_WIN
, MV64x60_CPU2PCI1_MEM_0_WIN
,
1101 MV64x60_CPU2PCI1_MEM_1_WIN
, MV64x60_CPU2PCI1_MEM_2_WIN
},
1104 static u32 remap_tab
[2][4] __initdata
= {
1105 { MV64x60_CPU2PCI0_IO_REMAP_WIN
, MV64x60_CPU2PCI0_MEM_0_REMAP_WIN
,
1106 MV64x60_CPU2PCI0_MEM_1_REMAP_WIN
, MV64x60_CPU2PCI0_MEM_2_REMAP_WIN
},
1107 { MV64x60_CPU2PCI1_IO_REMAP_WIN
, MV64x60_CPU2PCI1_MEM_0_REMAP_WIN
,
1108 MV64x60_CPU2PCI1_MEM_1_REMAP_WIN
, MV64x60_CPU2PCI1_MEM_2_REMAP_WIN
}
1112 mv64x60_config_cpu2pci_windows(struct mv64x60_handle
*bh
,
1113 struct mv64x60_pci_info
*pi
, u32 bus
)
1117 if (pi
->pci_io
.size
> 0) {
1118 mv64x60_set_32bit_window(bh
, win_tab
[bus
][0],
1119 pi
->pci_io
.cpu_base
, pi
->pci_io
.size
, pi
->pci_io
.swap
);
1120 mv64x60_set_32bit_window(bh
, remap_tab
[bus
][0],
1121 pi
->pci_io
.pci_base_lo
, 0, 0);
1122 bh
->ci
->enable_window_32bit(bh
, win_tab
[bus
][0]);
1123 } else /* Actually, the window should already be disabled */
1124 bh
->ci
->disable_window_32bit(bh
, win_tab
[bus
][0]);
1127 if (pi
->pci_mem
[i
].size
> 0) {
1128 mv64x60_set_32bit_window(bh
, win_tab
[bus
][i
+1],
1129 pi
->pci_mem
[i
].cpu_base
, pi
->pci_mem
[i
].size
,
1130 pi
->pci_mem
[i
].swap
);
1131 mv64x60_set_64bit_window(bh
, remap_tab
[bus
][i
+1],
1132 pi
->pci_mem
[i
].pci_base_hi
,
1133 pi
->pci_mem
[i
].pci_base_lo
, 0, 0);
1134 bh
->ci
->enable_window_32bit(bh
, win_tab
[bus
][i
+1]);
1135 } else /* Actually, the window should already be disabled */
1136 bh
->ci
->disable_window_32bit(bh
, win_tab
[bus
][i
+1]);
1140 *****************************************************************************
1142 * PCI->System MEM Config Routines
1144 *****************************************************************************
1147 * mv64x60_config_pci2mem_windows()
1149 * Configure the PCI->Memory windows on the bridge.
1151 static u32 pci_acc_tab
[2][4] __initdata
= {
1152 { MV64x60_PCI02MEM_ACC_CNTL_0_WIN
, MV64x60_PCI02MEM_ACC_CNTL_1_WIN
,
1153 MV64x60_PCI02MEM_ACC_CNTL_2_WIN
, MV64x60_PCI02MEM_ACC_CNTL_3_WIN
},
1154 { MV64x60_PCI12MEM_ACC_CNTL_0_WIN
, MV64x60_PCI12MEM_ACC_CNTL_1_WIN
,
1155 MV64x60_PCI12MEM_ACC_CNTL_2_WIN
, MV64x60_PCI12MEM_ACC_CNTL_3_WIN
}
1158 static u32 pci_snoop_tab
[2][4] __initdata
= {
1159 { MV64x60_PCI02MEM_SNOOP_0_WIN
, MV64x60_PCI02MEM_SNOOP_1_WIN
,
1160 MV64x60_PCI02MEM_SNOOP_2_WIN
, MV64x60_PCI02MEM_SNOOP_3_WIN
},
1161 { MV64x60_PCI12MEM_SNOOP_0_WIN
, MV64x60_PCI12MEM_SNOOP_1_WIN
,
1162 MV64x60_PCI12MEM_SNOOP_2_WIN
, MV64x60_PCI12MEM_SNOOP_3_WIN
}
1165 static u32 pci_size_tab
[2][4] __initdata
= {
1166 { MV64x60_PCI0_MEM_0_SIZE
, MV64x60_PCI0_MEM_1_SIZE
,
1167 MV64x60_PCI0_MEM_2_SIZE
, MV64x60_PCI0_MEM_3_SIZE
},
1168 { MV64x60_PCI1_MEM_0_SIZE
, MV64x60_PCI1_MEM_1_SIZE
,
1169 MV64x60_PCI1_MEM_2_SIZE
, MV64x60_PCI1_MEM_3_SIZE
}
1173 mv64x60_config_pci2mem_windows(struct mv64x60_handle
*bh
,
1174 struct pci_controller
*hose
, struct mv64x60_pci_info
*pi
,
1175 u32 bus
, u32 mem_windows
[MV64x60_CPU2MEM_WINDOWS
][2])
1180 * Set the access control, snoop, BAR size, and window base addresses.
1181 * PCI->MEM windows base addresses will match exactly what the
1182 * CPU->MEM windows are.
1184 for (win
=MV64x60_CPU2MEM_0_WIN
,i
=0;win
<=MV64x60_CPU2MEM_3_WIN
;win
++,i
++)
1185 if (bh
->ci
->is_enabled_32bit(bh
, win
)) {
1186 mv64x60_set_64bit_window(bh
,
1187 pci_acc_tab
[bus
][i
], 0,
1188 mem_windows
[i
][0], mem_windows
[i
][1],
1189 pi
->acc_cntl_options
[i
]);
1190 bh
->ci
->enable_window_64bit(bh
, pci_acc_tab
[bus
][i
]);
1192 if (bh
->ci
->window_tab_64bit
[
1193 pci_snoop_tab
[bus
][i
]].base_lo_reg
!= 0) {
1195 mv64x60_set_64bit_window(bh
,
1196 pci_snoop_tab
[bus
][i
], 0,
1197 mem_windows
[i
][0], mem_windows
[i
][1],
1198 pi
->snoop_options
[i
]);
1199 bh
->ci
->enable_window_64bit(bh
,
1200 pci_snoop_tab
[bus
][i
]);
1203 bh
->ci
->set_pci2mem_window(hose
, bus
, i
,
1205 mv64x60_write(bh
, pci_size_tab
[bus
][i
],
1206 mv64x60_mask(mem_windows
[i
][1] - 1, 20));
1208 /* Enable the window */
1209 mv64x60_clr_bits(bh
, ((bus
== 0) ?
1210 MV64x60_PCI0_BAR_ENABLE
:
1211 MV64x60_PCI1_BAR_ENABLE
), (1 << i
));
1216 *****************************************************************************
1218 * Hose & Resource Alloc/Init Routines
1220 *****************************************************************************
1223 * mv64x60_alloc_hoses()
1225 * Allocate the PCI hose structures for the bridge's PCI buses.
1228 mv64x60_alloc_hose(struct mv64x60_handle
*bh
, u32 cfg_addr
, u32 cfg_data
,
1229 struct pci_controller
**hose
)
1231 *hose
= pcibios_alloc_controller();
1232 setup_indirect_pci_nomap(*hose
, bh
->v_base
+ cfg_addr
,
1233 bh
->v_base
+ cfg_data
);
1237 * mv64x60_config_resources()
1239 * Calculate the offsets, etc. for the hose structures to reflect all of
1240 * the address remapping that happens as you go from CPU->PCI and PCI->MEM.
1243 mv64x60_config_resources(struct pci_controller
*hose
,
1244 struct mv64x60_pci_info
*pi
, u32 io_base
)
1247 /* 2 hoses; 4 resources/hose; string <= 64 bytes */
1248 static char s
[2][4][64];
1250 if (pi
->pci_io
.size
!= 0) {
1251 sprintf(s
[hose
->index
][0], "PCI hose %d I/O Space",
1253 pci_init_resource(&hose
->io_resource
, io_base
- isa_io_base
,
1254 io_base
- isa_io_base
+ pi
->pci_io
.size
- 1,
1255 IORESOURCE_IO
, s
[hose
->index
][0]);
1256 hose
->io_space
.start
= pi
->pci_io
.pci_base_lo
;
1257 hose
->io_space
.end
= pi
->pci_io
.pci_base_lo
+ pi
->pci_io
.size
-1;
1258 hose
->io_base_phys
= pi
->pci_io
.cpu_base
;
1259 hose
->io_base_virt
= (void *)isa_io_base
;
1263 if (pi
->pci_mem
[i
].size
!= 0) {
1264 sprintf(s
[hose
->index
][i
+1], "PCI hose %d MEM Space %d",
1266 pci_init_resource(&hose
->mem_resources
[i
],
1267 pi
->pci_mem
[i
].cpu_base
,
1268 pi
->pci_mem
[i
].cpu_base
+ pi
->pci_mem
[i
].size
-1,
1269 IORESOURCE_MEM
, s
[hose
->index
][i
+1]);
1272 hose
->mem_space
.end
= pi
->pci_mem
[0].pci_base_lo
+
1273 pi
->pci_mem
[0].size
- 1;
1274 hose
->pci_mem_offset
= pi
->pci_mem
[0].cpu_base
-
1275 pi
->pci_mem
[0].pci_base_lo
;
1279 * mv64x60_config_pci_params()
1281 * Configure a hose's PCI config space parameters.
1284 mv64x60_config_pci_params(struct pci_controller
*hose
,
1285 struct mv64x60_pci_info
*pi
)
1291 devfn
= PCI_DEVFN(0,0);
1293 save_exclude
= mv64x60_pci_exclude_bridge
;
1294 mv64x60_pci_exclude_bridge
= 0;
1296 /* Set class code to indicate host bridge */
1297 u16_val
= PCI_CLASS_BRIDGE_HOST
; /* 0x0600 (host bridge) */
1298 early_write_config_word(hose
, 0, devfn
, PCI_CLASS_DEVICE
, u16_val
);
1300 /* Enable bridge to be PCI master & respond to PCI MEM cycles */
1301 early_read_config_word(hose
, 0, devfn
, PCI_COMMAND
, &u16_val
);
1302 u16_val
&= ~(PCI_COMMAND_IO
| PCI_COMMAND_INVALIDATE
|
1303 PCI_COMMAND_PARITY
| PCI_COMMAND_SERR
| PCI_COMMAND_FAST_BACK
);
1304 u16_val
|= pi
->pci_cmd_bits
| PCI_COMMAND_MASTER
| PCI_COMMAND_MEMORY
;
1305 early_write_config_word(hose
, 0, devfn
, PCI_COMMAND
, u16_val
);
1307 /* Set latency timer, cache line size, clear BIST */
1308 u16_val
= (pi
->latency_timer
<< 8) | (L1_CACHE_BYTES
>> 2);
1309 early_write_config_word(hose
, 0, devfn
, PCI_CACHE_LINE_SIZE
, u16_val
);
1311 mv64x60_pci_exclude_bridge
= save_exclude
;
1315 *****************************************************************************
1317 * PCI Related Routine
1319 *****************************************************************************
1324 * Set the bus number for the hose directly under the bridge.
1327 mv64x60_set_bus(struct mv64x60_handle
*bh
, u32 bus
, u32 child_bus
)
1329 struct pci_controller
*hose
;
1330 u32 pci_mode
, p2p_cfg
, pci_cfg_offset
, val
;
1334 pci_mode
= bh
->pci_mode_a
;
1335 p2p_cfg
= MV64x60_PCI0_P2P_CONFIG
;
1336 pci_cfg_offset
= 0x64;
1339 pci_mode
= bh
->pci_mode_b
;
1340 p2p_cfg
= MV64x60_PCI1_P2P_CONFIG
;
1341 pci_cfg_offset
= 0xe4;
1346 val
= mv64x60_read(bh
, p2p_cfg
);
1348 if (pci_mode
== MV64x60_PCIMODE_CONVENTIONAL
) {
1349 val
&= 0xe0000000; /* Force dev num to 0, turn off P2P bridge */
1350 val
|= (child_bus
<< 16) | 0xff;
1351 mv64x60_write(bh
, p2p_cfg
, val
);
1352 (void)mv64x60_read(bh
, p2p_cfg
); /* Flush FIFO */
1353 } else { /* PCI-X */
1355 * Need to use the current bus/dev number (that's in the
1356 * P2P CONFIG reg) to access the bridge's pci config space.
1358 save_exclude
= mv64x60_pci_exclude_bridge
;
1359 mv64x60_pci_exclude_bridge
= 0;
1360 early_write_config_dword(hose
, (val
& 0x00ff0000) >> 16,
1361 PCI_DEVFN(((val
& 0x1f000000) >> 24), 0),
1362 pci_cfg_offset
, child_bus
<< 8);
1363 mv64x60_pci_exclude_bridge
= save_exclude
;
1368 * mv64x60_pci_exclude_device()
1370 * This routine is used to make the bridge not appear when the
1371 * PCI subsystem is accessing PCI devices (in PCI config space).
1374 mv64x60_pci_exclude_device(u8 bus
, u8 devfn
)
1376 struct pci_controller
*hose
;
1378 hose
= pci_bus_to_hose(bus
);
1380 /* Skip slot 0 on both hoses */
1381 if ((mv64x60_pci_exclude_bridge
== 1) && (PCI_SLOT(devfn
) == 0) &&
1382 (hose
->first_busno
== bus
))
1384 return PCIBIOS_DEVICE_NOT_FOUND
;
1386 return PCIBIOS_SUCCESSFUL
;
1387 } /* mv64x60_pci_exclude_device() */
1390 *****************************************************************************
1392 * Platform Device Routines
1394 *****************************************************************************
1398 * mv64x60_pd_fixup()
1400 * Need to add the base addr of where the bridge's regs are mapped in the
1401 * physical addr space so drivers can ioremap() them.
1404 mv64x60_pd_fixup(struct mv64x60_handle
*bh
, struct platform_device
*pd_devs
[],
1410 for (i
=0; i
<entries
; i
++) {
1413 while ((r
= platform_get_resource(pd_devs
[i
],IORESOURCE_MEM
,j
))
1416 r
->start
+= bh
->p_base
;
1417 r
->end
+= bh
->p_base
;
1426 * Add the mv64x60 platform devices to the list of platform devices.
1429 mv64x60_add_pds(void)
1431 return platform_add_devices(mv64x60_pd_devs
,
1432 ARRAY_SIZE(mv64x60_pd_devs
));
1434 arch_initcall(mv64x60_add_pds
);
1437 *****************************************************************************
1439 * GT64260-Specific Routines
1441 *****************************************************************************
1444 * gt64260_translate_size()
1446 * On the GT64260, the size register is really the "top" address of the window.
1449 gt64260_translate_size(u32 base
, u32 size
, u32 num_bits
)
1451 return base
+ mv64x60_mask(size
- 1, num_bits
);
1455 * gt64260_untranslate_size()
1457 * Translate the top address of a window into a window size.
1460 gt64260_untranslate_size(u32 base
, u32 size
, u32 num_bits
)
1463 size
= size
- base
+ (1 << (32 - num_bits
));
1471 * gt64260_set_pci2mem_window()
1473 * The PCI->MEM window registers are actually in PCI config space so need
1474 * to set them by setting the correct config space BARs.
1476 static u32 gt64260_reg_addrs
[2][4] __initdata
= {
1477 { 0x10, 0x14, 0x18, 0x1c }, { 0x90, 0x94, 0x98, 0x9c }
1481 gt64260_set_pci2mem_window(struct pci_controller
*hose
, u32 bus
, u32 window
,
1486 pr_debug("set pci->mem window: %d, hose: %d, base: 0x%x\n", window
,
1489 save_exclude
= mv64x60_pci_exclude_bridge
;
1490 mv64x60_pci_exclude_bridge
= 0;
1491 early_write_config_dword(hose
, 0, PCI_DEVFN(0, 0),
1492 gt64260_reg_addrs
[bus
][window
], mv64x60_mask(base
, 20) | 0x8);
1493 mv64x60_pci_exclude_bridge
= save_exclude
;
1497 * gt64260_set_pci2regs_window()
1499 * Set where the bridge's registers appear in PCI MEM space.
1501 static u32 gt64260_offset
[2] __initdata
= {0x20, 0xa0};
1504 gt64260_set_pci2regs_window(struct mv64x60_handle
*bh
,
1505 struct pci_controller
*hose
, u32 bus
, u32 base
)
1509 pr_debug("set pci->internal regs hose: %d, base: 0x%x\n", hose
->index
,
1512 save_exclude
= mv64x60_pci_exclude_bridge
;
1513 mv64x60_pci_exclude_bridge
= 0;
1514 early_write_config_dword(hose
, 0, PCI_DEVFN(0,0), gt64260_offset
[bus
],
1516 mv64x60_pci_exclude_bridge
= save_exclude
;
1520 * gt64260_is_enabled_32bit()
1522 * On a GT64260, a window is enabled iff its top address is >= to its base
1526 gt64260_is_enabled_32bit(struct mv64x60_handle
*bh
, u32 window
)
1530 if ((gt64260_32bit_windows
[window
].base_reg
!= 0) &&
1531 (gt64260_32bit_windows
[window
].size_reg
!= 0) &&
1532 ((mv64x60_read(bh
, gt64260_32bit_windows
[window
].size_reg
) &
1533 ((1 << gt64260_32bit_windows
[window
].size_bits
) - 1)) >=
1534 (mv64x60_read(bh
, gt64260_32bit_windows
[window
].base_reg
) &
1535 ((1 << gt64260_32bit_windows
[window
].base_bits
) - 1))))
1543 * gt64260_enable_window_32bit()
1545 * On the GT64260, a window is enabled iff the top address is >= to the base
1546 * address of the window. Since the window has already been configured by
1547 * the time this routine is called, we have nothing to do here.
1550 gt64260_enable_window_32bit(struct mv64x60_handle
*bh
, u32 window
)
1552 pr_debug("enable 32bit window: %d\n", window
);
1556 * gt64260_disable_window_32bit()
1558 * On a GT64260, you disable a window by setting its top address to be less
1559 * than its base address.
1562 gt64260_disable_window_32bit(struct mv64x60_handle
*bh
, u32 window
)
1564 pr_debug("disable 32bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
1565 window
, gt64260_32bit_windows
[window
].base_reg
,
1566 gt64260_32bit_windows
[window
].size_reg
);
1568 if ((gt64260_32bit_windows
[window
].base_reg
!= 0) &&
1569 (gt64260_32bit_windows
[window
].size_reg
!= 0)) {
1571 /* To disable, make bottom reg higher than top reg */
1572 mv64x60_write(bh
, gt64260_32bit_windows
[window
].base_reg
,0xfff);
1573 mv64x60_write(bh
, gt64260_32bit_windows
[window
].size_reg
, 0);
1578 * gt64260_enable_window_64bit()
1580 * On the GT64260, a window is enabled iff the top address is >= to the base
1581 * address of the window. Since the window has already been configured by
1582 * the time this routine is called, we have nothing to do here.
1585 gt64260_enable_window_64bit(struct mv64x60_handle
*bh
, u32 window
)
1587 pr_debug("enable 64bit window: %d\n", window
);
1591 * gt64260_disable_window_64bit()
1593 * On a GT64260, you disable a window by setting its top address to be less
1594 * than its base address.
1597 gt64260_disable_window_64bit(struct mv64x60_handle
*bh
, u32 window
)
1599 pr_debug("disable 64bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
1600 window
, gt64260_64bit_windows
[window
].base_lo_reg
,
1601 gt64260_64bit_windows
[window
].size_reg
);
1603 if ((gt64260_64bit_windows
[window
].base_lo_reg
!= 0) &&
1604 (gt64260_64bit_windows
[window
].size_reg
!= 0)) {
1606 /* To disable, make bottom reg higher than top reg */
1607 mv64x60_write(bh
, gt64260_64bit_windows
[window
].base_lo_reg
,
1609 mv64x60_write(bh
, gt64260_64bit_windows
[window
].base_hi_reg
, 0);
1610 mv64x60_write(bh
, gt64260_64bit_windows
[window
].size_reg
, 0);
1615 * gt64260_disable_all_windows()
1617 * The GT64260 has several windows that aren't represented in the table of
1618 * windows at the top of this file. This routine turns all of them off
1619 * except for the memory controller windows, of course.
1622 gt64260_disable_all_windows(struct mv64x60_handle
*bh
,
1623 struct mv64x60_setup_info
*si
)
1627 /* Disable 32bit windows (don't disable cpu->mem windows) */
1628 for (i
=MV64x60_CPU2DEV_0_WIN
; i
<MV64x60_32BIT_WIN_COUNT
; i
++) {
1630 preserve
= si
->window_preserve_mask_32_lo
& (1 << i
);
1632 preserve
= si
->window_preserve_mask_32_hi
& (1<<(i
-32));
1635 gt64260_disable_window_32bit(bh
, i
);
1638 /* Disable 64bit windows */
1639 for (i
=0; i
<MV64x60_64BIT_WIN_COUNT
; i
++)
1640 if (!(si
->window_preserve_mask_64
& (1<<i
)))
1641 gt64260_disable_window_64bit(bh
, i
);
1643 /* Turn off cpu protection windows not in gt64260_32bit_windows[] */
1644 mv64x60_write(bh
, GT64260_CPU_PROT_BASE_4
, 0xfff);
1645 mv64x60_write(bh
, GT64260_CPU_PROT_SIZE_4
, 0);
1646 mv64x60_write(bh
, GT64260_CPU_PROT_BASE_5
, 0xfff);
1647 mv64x60_write(bh
, GT64260_CPU_PROT_SIZE_5
, 0);
1648 mv64x60_write(bh
, GT64260_CPU_PROT_BASE_6
, 0xfff);
1649 mv64x60_write(bh
, GT64260_CPU_PROT_SIZE_6
, 0);
1650 mv64x60_write(bh
, GT64260_CPU_PROT_BASE_7
, 0xfff);
1651 mv64x60_write(bh
, GT64260_CPU_PROT_SIZE_7
, 0);
1653 /* Turn off PCI->MEM access cntl wins not in gt64260_64bit_windows[] */
1654 mv64x60_write(bh
, MV64x60_PCI0_ACC_CNTL_4_BASE_LO
, 0xfff);
1655 mv64x60_write(bh
, MV64x60_PCI0_ACC_CNTL_4_BASE_HI
, 0);
1656 mv64x60_write(bh
, MV64x60_PCI0_ACC_CNTL_4_SIZE
, 0);
1657 mv64x60_write(bh
, MV64x60_PCI0_ACC_CNTL_5_BASE_LO
, 0xfff);
1658 mv64x60_write(bh
, MV64x60_PCI0_ACC_CNTL_5_BASE_HI
, 0);
1659 mv64x60_write(bh
, MV64x60_PCI0_ACC_CNTL_5_SIZE
, 0);
1660 mv64x60_write(bh
, GT64260_PCI0_ACC_CNTL_6_BASE_LO
, 0xfff);
1661 mv64x60_write(bh
, GT64260_PCI0_ACC_CNTL_6_BASE_HI
, 0);
1662 mv64x60_write(bh
, GT64260_PCI0_ACC_CNTL_6_SIZE
, 0);
1663 mv64x60_write(bh
, GT64260_PCI0_ACC_CNTL_7_BASE_LO
, 0xfff);
1664 mv64x60_write(bh
, GT64260_PCI0_ACC_CNTL_7_BASE_HI
, 0);
1665 mv64x60_write(bh
, GT64260_PCI0_ACC_CNTL_7_SIZE
, 0);
1667 mv64x60_write(bh
, MV64x60_PCI1_ACC_CNTL_4_BASE_LO
, 0xfff);
1668 mv64x60_write(bh
, MV64x60_PCI1_ACC_CNTL_4_BASE_HI
, 0);
1669 mv64x60_write(bh
, MV64x60_PCI1_ACC_CNTL_4_SIZE
, 0);
1670 mv64x60_write(bh
, MV64x60_PCI1_ACC_CNTL_5_BASE_LO
, 0xfff);
1671 mv64x60_write(bh
, MV64x60_PCI1_ACC_CNTL_5_BASE_HI
, 0);
1672 mv64x60_write(bh
, MV64x60_PCI1_ACC_CNTL_5_SIZE
, 0);
1673 mv64x60_write(bh
, GT64260_PCI1_ACC_CNTL_6_BASE_LO
, 0xfff);
1674 mv64x60_write(bh
, GT64260_PCI1_ACC_CNTL_6_BASE_HI
, 0);
1675 mv64x60_write(bh
, GT64260_PCI1_ACC_CNTL_6_SIZE
, 0);
1676 mv64x60_write(bh
, GT64260_PCI1_ACC_CNTL_7_BASE_LO
, 0xfff);
1677 mv64x60_write(bh
, GT64260_PCI1_ACC_CNTL_7_BASE_HI
, 0);
1678 mv64x60_write(bh
, GT64260_PCI1_ACC_CNTL_7_SIZE
, 0);
1680 /* Disable all PCI-><whatever> windows */
1681 mv64x60_set_bits(bh
, MV64x60_PCI0_BAR_ENABLE
, 0x07fffdff);
1682 mv64x60_set_bits(bh
, MV64x60_PCI1_BAR_ENABLE
, 0x07fffdff);
1685 * Some firmwares enable a bunch of intr sources
1686 * for the PCI INT output pins.
1688 mv64x60_write(bh
, GT64260_IC_CPU_INTR_MASK_LO
, 0);
1689 mv64x60_write(bh
, GT64260_IC_CPU_INTR_MASK_HI
, 0);
1690 mv64x60_write(bh
, GT64260_IC_PCI0_INTR_MASK_LO
, 0);
1691 mv64x60_write(bh
, GT64260_IC_PCI0_INTR_MASK_HI
, 0);
1692 mv64x60_write(bh
, GT64260_IC_PCI1_INTR_MASK_LO
, 0);
1693 mv64x60_write(bh
, GT64260_IC_PCI1_INTR_MASK_HI
, 0);
1694 mv64x60_write(bh
, GT64260_IC_CPU_INT_0_MASK
, 0);
1695 mv64x60_write(bh
, GT64260_IC_CPU_INT_1_MASK
, 0);
1696 mv64x60_write(bh
, GT64260_IC_CPU_INT_2_MASK
, 0);
1697 mv64x60_write(bh
, GT64260_IC_CPU_INT_3_MASK
, 0);
1701 * gt64260a_chip_specific_init()
1703 * Implement errata work arounds for the GT64260A.
1706 gt64260a_chip_specific_init(struct mv64x60_handle
*bh
,
1707 struct mv64x60_setup_info
*si
)
1709 #ifdef CONFIG_SERIAL_MPSC
1712 #if !defined(CONFIG_NOT_COHERENT_CACHE)
1717 if (si
->pci_0
.enable_bus
)
1718 mv64x60_set_bits(bh
, MV64x60_PCI0_CMD
,
1719 ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
1721 if (si
->pci_1
.enable_bus
)
1722 mv64x60_set_bits(bh
, MV64x60_PCI1_CMD
,
1723 ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
1726 * Dave Wilhardt found that bit 4 in the PCI Command registers must
1727 * be set if you are using cache coherency.
1729 #if !defined(CONFIG_NOT_COHERENT_CACHE)
1730 /* Res #MEM-4 -- cpu read buffer to buffer 1 */
1731 if ((mv64x60_read(bh
, MV64x60_CPU_MODE
) & 0xf0) == 0x40)
1732 mv64x60_set_bits(bh
, GT64260_SDRAM_CONFIG
, (1<<26));
1734 save_exclude
= mv64x60_pci_exclude_bridge
;
1735 mv64x60_pci_exclude_bridge
= 0;
1736 if (si
->pci_0
.enable_bus
) {
1737 early_read_config_dword(bh
->hose_a
, 0, PCI_DEVFN(0,0),
1739 val
|= PCI_COMMAND_INVALIDATE
;
1740 early_write_config_dword(bh
->hose_a
, 0, PCI_DEVFN(0,0),
1744 if (si
->pci_1
.enable_bus
) {
1745 early_read_config_dword(bh
->hose_b
, 0, PCI_DEVFN(0,0),
1747 val
|= PCI_COMMAND_INVALIDATE
;
1748 early_write_config_dword(bh
->hose_b
, 0, PCI_DEVFN(0,0),
1751 mv64x60_pci_exclude_bridge
= save_exclude
;
1754 /* Disable buffer/descriptor snooping */
1755 mv64x60_clr_bits(bh
, 0xf280, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
1756 mv64x60_clr_bits(bh
, 0xf2c0, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
1758 #ifdef CONFIG_SERIAL_MPSC
1759 mv64x60_mpsc0_pdata
.mirror_regs
= 1;
1760 mv64x60_mpsc0_pdata
.cache_mgmt
= 1;
1761 mv64x60_mpsc1_pdata
.mirror_regs
= 1;
1762 mv64x60_mpsc1_pdata
.cache_mgmt
= 1;
1764 if ((r
= platform_get_resource(&mpsc1_device
, IORESOURCE_IRQ
, 0))
1766 r
->start
= MV64x60_IRQ_SDMA_0
;
1767 r
->end
= MV64x60_IRQ_SDMA_0
;
1773 * gt64260b_chip_specific_init()
1775 * Implement errata work arounds for the GT64260B.
1778 gt64260b_chip_specific_init(struct mv64x60_handle
*bh
,
1779 struct mv64x60_setup_info
*si
)
1781 #ifdef CONFIG_SERIAL_MPSC
1784 #if !defined(CONFIG_NOT_COHERENT_CACHE)
1789 if (si
->pci_0
.enable_bus
)
1790 mv64x60_set_bits(bh
, MV64x60_PCI0_CMD
,
1791 ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
1793 if (si
->pci_1
.enable_bus
)
1794 mv64x60_set_bits(bh
, MV64x60_PCI1_CMD
,
1795 ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
1798 * Dave Wilhardt found that bit 4 in the PCI Command registers must
1799 * be set if you are using cache coherency.
1801 #if !defined(CONFIG_NOT_COHERENT_CACHE)
1802 mv64x60_set_bits(bh
, GT64260_CPU_WB_PRIORITY_BUFFER_DEPTH
, 0xf);
1804 /* Res #MEM-4 -- cpu read buffer to buffer 1 */
1805 if ((mv64x60_read(bh
, MV64x60_CPU_MODE
) & 0xf0) == 0x40)
1806 mv64x60_set_bits(bh
, GT64260_SDRAM_CONFIG
, (1<<26));
1808 save_exclude
= mv64x60_pci_exclude_bridge
;
1809 mv64x60_pci_exclude_bridge
= 0;
1810 if (si
->pci_0
.enable_bus
) {
1811 early_read_config_dword(bh
->hose_a
, 0, PCI_DEVFN(0,0),
1813 val
|= PCI_COMMAND_INVALIDATE
;
1814 early_write_config_dword(bh
->hose_a
, 0, PCI_DEVFN(0,0),
1818 if (si
->pci_1
.enable_bus
) {
1819 early_read_config_dword(bh
->hose_b
, 0, PCI_DEVFN(0,0),
1821 val
|= PCI_COMMAND_INVALIDATE
;
1822 early_write_config_dword(bh
->hose_b
, 0, PCI_DEVFN(0,0),
1825 mv64x60_pci_exclude_bridge
= save_exclude
;
1828 /* Disable buffer/descriptor snooping */
1829 mv64x60_clr_bits(bh
, 0xf280, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
1830 mv64x60_clr_bits(bh
, 0xf2c0, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
1832 #ifdef CONFIG_SERIAL_MPSC
1834 * The 64260B is not supposed to have the bug where the MPSC & ENET
1835 * can't access cache coherent regions. However, testing has shown
1836 * that the MPSC, at least, still has this bug.
1838 mv64x60_mpsc0_pdata
.cache_mgmt
= 1;
1839 mv64x60_mpsc1_pdata
.cache_mgmt
= 1;
1841 if ((r
= platform_get_resource(&mpsc1_device
, IORESOURCE_IRQ
, 0))
1843 r
->start
= MV64x60_IRQ_SDMA_0
;
1844 r
->end
= MV64x60_IRQ_SDMA_0
;
1850 *****************************************************************************
1852 * MV64360-Specific Routines
1854 *****************************************************************************
1857 * mv64360_translate_size()
1859 * On the MV64360, the size register is set similar to the size you get
1860 * from a pci config space BAR register. That is, programmed from LSB to MSB
1861 * as a sequence of 1's followed by a sequence of 0's. IOW, "size -1" with the
1862 * assumption that the size is a power of 2.
1865 mv64360_translate_size(u32 base_addr
, u32 size
, u32 num_bits
)
1867 return mv64x60_mask(size
- 1, num_bits
);
1871 * mv64360_untranslate_size()
1873 * Translate the size register value of a window into a window size.
1876 mv64360_untranslate_size(u32 base_addr
, u32 size
, u32 num_bits
)
1879 size
>>= (32 - num_bits
);
1881 size
<<= (32 - num_bits
);
1888 * mv64360_set_pci2mem_window()
1890 * The PCI->MEM window registers are actually in PCI config space so need
1891 * to set them by setting the correct config space BARs.
1897 } static mv64360_reg_addrs
[2][4] __initdata
= {
1898 {{ 0, 0x14, 0x10 }, { 0, 0x1c, 0x18 },
1899 { 1, 0x14, 0x10 }, { 1, 0x1c, 0x18 }},
1900 {{ 0, 0x94, 0x90 }, { 0, 0x9c, 0x98 },
1901 { 1, 0x94, 0x90 }, { 1, 0x9c, 0x98 }}
1905 mv64360_set_pci2mem_window(struct pci_controller
*hose
, u32 bus
, u32 window
,
1910 pr_debug("set pci->mem window: %d, hose: %d, base: 0x%x\n", window
,
1913 save_exclude
= mv64x60_pci_exclude_bridge
;
1914 mv64x60_pci_exclude_bridge
= 0;
1915 early_write_config_dword(hose
, 0,
1916 PCI_DEVFN(0, mv64360_reg_addrs
[bus
][window
].fcn
),
1917 mv64360_reg_addrs
[bus
][window
].base_hi_bar
, 0);
1918 early_write_config_dword(hose
, 0,
1919 PCI_DEVFN(0, mv64360_reg_addrs
[bus
][window
].fcn
),
1920 mv64360_reg_addrs
[bus
][window
].base_lo_bar
,
1921 mv64x60_mask(base
,20) | 0xc);
1922 mv64x60_pci_exclude_bridge
= save_exclude
;
1926 * mv64360_set_pci2regs_window()
1928 * Set where the bridge's registers appear in PCI MEM space.
1930 static u32 mv64360_offset
[2][2] __initdata
= {{0x20, 0x24}, {0xa0, 0xa4}};
1933 mv64360_set_pci2regs_window(struct mv64x60_handle
*bh
,
1934 struct pci_controller
*hose
, u32 bus
, u32 base
)
1938 pr_debug("set pci->internal regs hose: %d, base: 0x%x\n", hose
->index
,
1941 save_exclude
= mv64x60_pci_exclude_bridge
;
1942 mv64x60_pci_exclude_bridge
= 0;
1943 early_write_config_dword(hose
, 0, PCI_DEVFN(0,0),
1944 mv64360_offset
[bus
][0], (base
<< 16));
1945 early_write_config_dword(hose
, 0, PCI_DEVFN(0,0),
1946 mv64360_offset
[bus
][1], 0);
1947 mv64x60_pci_exclude_bridge
= save_exclude
;
1951 * mv64360_is_enabled_32bit()
1953 * On a MV64360, a window is enabled by either clearing a bit in the
1954 * CPU BAR Enable reg or setting a bit in the window's base reg.
1955 * Note that this doesn't work for windows on the PCI slave side but we don't
1956 * check those so its okay.
1959 mv64360_is_enabled_32bit(struct mv64x60_handle
*bh
, u32 window
)
1963 if (((mv64360_32bit_windows
[window
].base_reg
!= 0) &&
1964 (mv64360_32bit_windows
[window
].size_reg
!= 0)) ||
1965 (window
== MV64x60_CPU2SRAM_WIN
)) {
1967 extra
= mv64360_32bit_windows
[window
].extra
;
1969 switch (extra
& MV64x60_EXTRA_MASK
) {
1970 case MV64x60_EXTRA_CPUWIN_ENAB
:
1971 rc
= (mv64x60_read(bh
, MV64360_CPU_BAR_ENABLE
) &
1972 (1 << (extra
& 0x1f))) == 0;
1975 case MV64x60_EXTRA_CPUPROT_ENAB
:
1976 rc
= (mv64x60_read(bh
,
1977 mv64360_32bit_windows
[window
].base_reg
) &
1978 (1 << (extra
& 0x1f))) != 0;
1981 case MV64x60_EXTRA_ENET_ENAB
:
1982 rc
= (mv64x60_read(bh
, MV64360_ENET2MEM_BAR_ENABLE
) &
1983 (1 << (extra
& 0x7))) == 0;
1986 case MV64x60_EXTRA_MPSC_ENAB
:
1987 rc
= (mv64x60_read(bh
, MV64360_MPSC2MEM_BAR_ENABLE
) &
1988 (1 << (extra
& 0x3))) == 0;
1991 case MV64x60_EXTRA_IDMA_ENAB
:
1992 rc
= (mv64x60_read(bh
, MV64360_IDMA2MEM_BAR_ENABLE
) &
1993 (1 << (extra
& 0x7))) == 0;
1997 printk(KERN_ERR
"mv64360_is_enabled: %s\n",
1998 "32bit table corrupted");
2006 * mv64360_enable_window_32bit()
2008 * On a MV64360, a window is enabled by either clearing a bit in the
2009 * CPU BAR Enable reg or setting a bit in the window's base reg.
2012 mv64360_enable_window_32bit(struct mv64x60_handle
*bh
, u32 window
)
2016 pr_debug("enable 32bit window: %d\n", window
);
2018 if (((mv64360_32bit_windows
[window
].base_reg
!= 0) &&
2019 (mv64360_32bit_windows
[window
].size_reg
!= 0)) ||
2020 (window
== MV64x60_CPU2SRAM_WIN
)) {
2022 extra
= mv64360_32bit_windows
[window
].extra
;
2024 switch (extra
& MV64x60_EXTRA_MASK
) {
2025 case MV64x60_EXTRA_CPUWIN_ENAB
:
2026 mv64x60_clr_bits(bh
, MV64360_CPU_BAR_ENABLE
,
2027 (1 << (extra
& 0x1f)));
2030 case MV64x60_EXTRA_CPUPROT_ENAB
:
2031 mv64x60_set_bits(bh
,
2032 mv64360_32bit_windows
[window
].base_reg
,
2033 (1 << (extra
& 0x1f)));
2036 case MV64x60_EXTRA_ENET_ENAB
:
2037 mv64x60_clr_bits(bh
, MV64360_ENET2MEM_BAR_ENABLE
,
2038 (1 << (extra
& 0x7)));
2041 case MV64x60_EXTRA_MPSC_ENAB
:
2042 mv64x60_clr_bits(bh
, MV64360_MPSC2MEM_BAR_ENABLE
,
2043 (1 << (extra
& 0x3)));
2046 case MV64x60_EXTRA_IDMA_ENAB
:
2047 mv64x60_clr_bits(bh
, MV64360_IDMA2MEM_BAR_ENABLE
,
2048 (1 << (extra
& 0x7)));
2052 printk(KERN_ERR
"mv64360_enable: %s\n",
2053 "32bit table corrupted");
2059 * mv64360_disable_window_32bit()
2061 * On a MV64360, a window is disabled by either setting a bit in the
2062 * CPU BAR Enable reg or clearing a bit in the window's base reg.
2065 mv64360_disable_window_32bit(struct mv64x60_handle
*bh
, u32 window
)
2069 pr_debug("disable 32bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
2070 window
, mv64360_32bit_windows
[window
].base_reg
,
2071 mv64360_32bit_windows
[window
].size_reg
);
2073 if (((mv64360_32bit_windows
[window
].base_reg
!= 0) &&
2074 (mv64360_32bit_windows
[window
].size_reg
!= 0)) ||
2075 (window
== MV64x60_CPU2SRAM_WIN
)) {
2077 extra
= mv64360_32bit_windows
[window
].extra
;
2079 switch (extra
& MV64x60_EXTRA_MASK
) {
2080 case MV64x60_EXTRA_CPUWIN_ENAB
:
2081 mv64x60_set_bits(bh
, MV64360_CPU_BAR_ENABLE
,
2082 (1 << (extra
& 0x1f)));
2085 case MV64x60_EXTRA_CPUPROT_ENAB
:
2086 mv64x60_clr_bits(bh
,
2087 mv64360_32bit_windows
[window
].base_reg
,
2088 (1 << (extra
& 0x1f)));
2091 case MV64x60_EXTRA_ENET_ENAB
:
2092 mv64x60_set_bits(bh
, MV64360_ENET2MEM_BAR_ENABLE
,
2093 (1 << (extra
& 0x7)));
2096 case MV64x60_EXTRA_MPSC_ENAB
:
2097 mv64x60_set_bits(bh
, MV64360_MPSC2MEM_BAR_ENABLE
,
2098 (1 << (extra
& 0x3)));
2101 case MV64x60_EXTRA_IDMA_ENAB
:
2102 mv64x60_set_bits(bh
, MV64360_IDMA2MEM_BAR_ENABLE
,
2103 (1 << (extra
& 0x7)));
2107 printk(KERN_ERR
"mv64360_disable: %s\n",
2108 "32bit table corrupted");
2114 * mv64360_enable_window_64bit()
2116 * On the MV64360, a 64-bit window is enabled by setting a bit in the window's
2120 mv64360_enable_window_64bit(struct mv64x60_handle
*bh
, u32 window
)
2122 pr_debug("enable 64bit window: %d\n", window
);
2124 if ((mv64360_64bit_windows
[window
].base_lo_reg
!= 0) &&
2125 (mv64360_64bit_windows
[window
].size_reg
!= 0)) {
2127 if ((mv64360_64bit_windows
[window
].extra
& MV64x60_EXTRA_MASK
)
2128 == MV64x60_EXTRA_PCIACC_ENAB
)
2129 mv64x60_set_bits(bh
,
2130 mv64360_64bit_windows
[window
].base_lo_reg
,
2131 (1 << (mv64360_64bit_windows
[window
].extra
&
2134 printk(KERN_ERR
"mv64360_enable: %s\n",
2135 "64bit table corrupted");
2140 * mv64360_disable_window_64bit()
2142 * On a MV64360, a 64-bit window is disabled by clearing a bit in the window's
2146 mv64360_disable_window_64bit(struct mv64x60_handle
*bh
, u32 window
)
2148 pr_debug("disable 64bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
2149 window
, mv64360_64bit_windows
[window
].base_lo_reg
,
2150 mv64360_64bit_windows
[window
].size_reg
);
2152 if ((mv64360_64bit_windows
[window
].base_lo_reg
!= 0) &&
2153 (mv64360_64bit_windows
[window
].size_reg
!= 0)) {
2154 if ((mv64360_64bit_windows
[window
].extra
& MV64x60_EXTRA_MASK
)
2155 == MV64x60_EXTRA_PCIACC_ENAB
)
2156 mv64x60_clr_bits(bh
,
2157 mv64360_64bit_windows
[window
].base_lo_reg
,
2158 (1 << (mv64360_64bit_windows
[window
].extra
&
2161 printk(KERN_ERR
"mv64360_disable: %s\n",
2162 "64bit table corrupted");
2167 * mv64360_disable_all_windows()
2169 * The MV64360 has a few windows that aren't represented in the table of
2170 * windows at the top of this file. This routine turns all of them off
2171 * except for the memory controller windows, of course.
2174 mv64360_disable_all_windows(struct mv64x60_handle
*bh
,
2175 struct mv64x60_setup_info
*si
)
2179 /* Disable 32bit windows (don't disable cpu->mem windows) */
2180 for (i
=MV64x60_CPU2DEV_0_WIN
; i
<MV64x60_32BIT_WIN_COUNT
; i
++) {
2182 preserve
= si
->window_preserve_mask_32_lo
& (1 << i
);
2184 preserve
= si
->window_preserve_mask_32_hi
& (1<<(i
-32));
2187 mv64360_disable_window_32bit(bh
, i
);
2190 /* Disable 64bit windows */
2191 for (i
=0; i
<MV64x60_64BIT_WIN_COUNT
; i
++)
2192 if (!(si
->window_preserve_mask_64
& (1<<i
)))
2193 mv64360_disable_window_64bit(bh
, i
);
2195 /* Turn off PCI->MEM access cntl wins not in mv64360_64bit_windows[] */
2196 mv64x60_clr_bits(bh
, MV64x60_PCI0_ACC_CNTL_4_BASE_LO
, 0);
2197 mv64x60_clr_bits(bh
, MV64x60_PCI0_ACC_CNTL_5_BASE_LO
, 0);
2198 mv64x60_clr_bits(bh
, MV64x60_PCI1_ACC_CNTL_4_BASE_LO
, 0);
2199 mv64x60_clr_bits(bh
, MV64x60_PCI1_ACC_CNTL_5_BASE_LO
, 0);
2201 /* Disable all PCI-><whatever> windows */
2202 mv64x60_set_bits(bh
, MV64x60_PCI0_BAR_ENABLE
, 0x0000f9ff);
2203 mv64x60_set_bits(bh
, MV64x60_PCI1_BAR_ENABLE
, 0x0000f9ff);
2207 * mv64360_config_io2mem_windows()
2209 * ENET, MPSC, and IDMA ctlrs on the MV64[34]60 have separate windows that
2210 * must be set up so that the respective ctlr can access system memory.
2212 static u32 enet_tab
[MV64x60_CPU2MEM_WINDOWS
] __initdata
= {
2213 MV64x60_ENET2MEM_0_WIN
, MV64x60_ENET2MEM_1_WIN
,
2214 MV64x60_ENET2MEM_2_WIN
, MV64x60_ENET2MEM_3_WIN
,
2217 static u32 mpsc_tab
[MV64x60_CPU2MEM_WINDOWS
] __initdata
= {
2218 MV64x60_MPSC2MEM_0_WIN
, MV64x60_MPSC2MEM_1_WIN
,
2219 MV64x60_MPSC2MEM_2_WIN
, MV64x60_MPSC2MEM_3_WIN
,
2222 static u32 idma_tab
[MV64x60_CPU2MEM_WINDOWS
] __initdata
= {
2223 MV64x60_IDMA2MEM_0_WIN
, MV64x60_IDMA2MEM_1_WIN
,
2224 MV64x60_IDMA2MEM_2_WIN
, MV64x60_IDMA2MEM_3_WIN
,
2227 static u32 dram_selects
[MV64x60_CPU2MEM_WINDOWS
] __initdata
=
2228 { 0xe, 0xd, 0xb, 0x7 };
2231 mv64360_config_io2mem_windows(struct mv64x60_handle
*bh
,
2232 struct mv64x60_setup_info
*si
,
2233 u32 mem_windows
[MV64x60_CPU2MEM_WINDOWS
][2])
2237 pr_debug("config_io2regs_windows: enet, mpsc, idma -> bridge regs\n");
2239 mv64x60_write(bh
, MV64360_ENET2MEM_ACC_PROT_0
, 0);
2240 mv64x60_write(bh
, MV64360_ENET2MEM_ACC_PROT_1
, 0);
2241 mv64x60_write(bh
, MV64360_ENET2MEM_ACC_PROT_2
, 0);
2243 mv64x60_write(bh
, MV64360_MPSC2MEM_ACC_PROT_0
, 0);
2244 mv64x60_write(bh
, MV64360_MPSC2MEM_ACC_PROT_1
, 0);
2246 mv64x60_write(bh
, MV64360_IDMA2MEM_ACC_PROT_0
, 0);
2247 mv64x60_write(bh
, MV64360_IDMA2MEM_ACC_PROT_1
, 0);
2248 mv64x60_write(bh
, MV64360_IDMA2MEM_ACC_PROT_2
, 0);
2249 mv64x60_write(bh
, MV64360_IDMA2MEM_ACC_PROT_3
, 0);
2251 /* Assume that mem ctlr has no more windows than embedded I/O ctlr */
2252 for (win
=MV64x60_CPU2MEM_0_WIN
,i
=0;win
<=MV64x60_CPU2MEM_3_WIN
;win
++,i
++)
2253 if (bh
->ci
->is_enabled_32bit(bh
, win
)) {
2254 mv64x60_set_32bit_window(bh
, enet_tab
[i
],
2255 mem_windows
[i
][0], mem_windows
[i
][1],
2256 (dram_selects
[i
] << 8) |
2257 (si
->enet_options
[i
] & 0x3000));
2258 bh
->ci
->enable_window_32bit(bh
, enet_tab
[i
]);
2260 /* Give enet r/w access to memory region */
2261 mv64x60_set_bits(bh
, MV64360_ENET2MEM_ACC_PROT_0
,
2263 mv64x60_set_bits(bh
, MV64360_ENET2MEM_ACC_PROT_1
,
2265 mv64x60_set_bits(bh
, MV64360_ENET2MEM_ACC_PROT_2
,
2268 mv64x60_set_32bit_window(bh
, mpsc_tab
[i
],
2269 mem_windows
[i
][0], mem_windows
[i
][1],
2270 (dram_selects
[i
] << 8) |
2271 (si
->mpsc_options
[i
] & 0x3000));
2272 bh
->ci
->enable_window_32bit(bh
, mpsc_tab
[i
]);
2274 /* Give mpsc r/w access to memory region */
2275 mv64x60_set_bits(bh
, MV64360_MPSC2MEM_ACC_PROT_0
,
2277 mv64x60_set_bits(bh
, MV64360_MPSC2MEM_ACC_PROT_1
,
2280 mv64x60_set_32bit_window(bh
, idma_tab
[i
],
2281 mem_windows
[i
][0], mem_windows
[i
][1],
2282 (dram_selects
[i
] << 8) |
2283 (si
->idma_options
[i
] & 0x3000));
2284 bh
->ci
->enable_window_32bit(bh
, idma_tab
[i
]);
2286 /* Give idma r/w access to memory region */
2287 mv64x60_set_bits(bh
, MV64360_IDMA2MEM_ACC_PROT_0
,
2289 mv64x60_set_bits(bh
, MV64360_IDMA2MEM_ACC_PROT_1
,
2291 mv64x60_set_bits(bh
, MV64360_IDMA2MEM_ACC_PROT_2
,
2293 mv64x60_set_bits(bh
, MV64360_IDMA2MEM_ACC_PROT_3
,
2299 * mv64360_set_mpsc2regs_window()
2301 * MPSC has a window to the bridge's internal registers. Call this routine
2302 * to change that window so it doesn't conflict with the windows mapping the
2303 * mpsc to system memory.
2306 mv64360_set_mpsc2regs_window(struct mv64x60_handle
*bh
, u32 base
)
2308 pr_debug("set mpsc->internal regs, base: 0x%x\n", base
);
2309 mv64x60_write(bh
, MV64360_MPSC2REGS_BASE
, base
& 0xffff0000);
2313 * mv64360_chip_specific_init()
2315 * Implement errata work arounds for the MV64360.
2318 mv64360_chip_specific_init(struct mv64x60_handle
*bh
,
2319 struct mv64x60_setup_info
*si
)
2321 #if !defined(CONFIG_NOT_COHERENT_CACHE)
2322 mv64x60_set_bits(bh
, MV64360_D_UNIT_CONTROL_HIGH
, (1<<24));
2324 #ifdef CONFIG_SERIAL_MPSC
2325 mv64x60_mpsc0_pdata
.brg_can_tune
= 1;
2326 mv64x60_mpsc0_pdata
.cache_mgmt
= 1;
2327 mv64x60_mpsc1_pdata
.brg_can_tune
= 1;
2328 mv64x60_mpsc1_pdata
.cache_mgmt
= 1;
2333 * mv64460_chip_specific_init()
2335 * Implement errata work arounds for the MV64460.
2338 mv64460_chip_specific_init(struct mv64x60_handle
*bh
,
2339 struct mv64x60_setup_info
*si
)
2341 #if !defined(CONFIG_NOT_COHERENT_CACHE)
2342 mv64x60_set_bits(bh
, MV64360_D_UNIT_CONTROL_HIGH
, (1<<24) | (1<<25));
2343 mv64x60_set_bits(bh
, MV64460_D_UNIT_MMASK
, (1<<1) | (1<<4));
2345 #ifdef CONFIG_SERIAL_MPSC
2346 mv64x60_mpsc0_pdata
.brg_can_tune
= 1;
2347 mv64x60_mpsc0_pdata
.cache_mgmt
= 1;
2348 mv64x60_mpsc1_pdata
.brg_can_tune
= 1;
2349 mv64x60_mpsc1_pdata
.cache_mgmt
= 1;
2354 #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
2355 /* Export the hotswap register via sysfs for enum event monitoring */
2356 #define VAL_LEN_MAX 11 /* 32-bit hex or dec stringified number + '\n' */
2358 DECLARE_MUTEX(mv64xxx_hs_lock
);
2361 mv64xxx_hs_reg_read(struct kobject
*kobj
, char *buf
, loff_t off
, size_t count
)
2368 if (count
< VAL_LEN_MAX
)
2371 if (down_interruptible(&mv64xxx_hs_lock
))
2372 return -ERESTARTSYS
;
2373 save_exclude
= mv64x60_pci_exclude_bridge
;
2374 mv64x60_pci_exclude_bridge
= 0;
2375 early_read_config_dword(&sysfs_hose_a
, 0, PCI_DEVFN(0, 0),
2376 MV64360_PCICFG_CPCI_HOTSWAP
, &v
);
2377 mv64x60_pci_exclude_bridge
= save_exclude
;
2378 up(&mv64xxx_hs_lock
);
2380 return sprintf(buf
, "0x%08x\n", v
);
2384 mv64xxx_hs_reg_write(struct kobject
*kobj
, char *buf
, loff_t off
, size_t count
)
2394 if (sscanf(buf
, "%i", &v
) == 1) {
2395 if (down_interruptible(&mv64xxx_hs_lock
))
2396 return -ERESTARTSYS
;
2397 save_exclude
= mv64x60_pci_exclude_bridge
;
2398 mv64x60_pci_exclude_bridge
= 0;
2399 early_write_config_dword(&sysfs_hose_a
, 0, PCI_DEVFN(0, 0),
2400 MV64360_PCICFG_CPCI_HOTSWAP
, v
);
2401 mv64x60_pci_exclude_bridge
= save_exclude
;
2402 up(&mv64xxx_hs_lock
);
2410 static struct bin_attribute mv64xxx_hs_reg_attr
= { /* Hotswap register */
2413 .mode
= S_IRUGO
| S_IWUSR
,
2414 .owner
= THIS_MODULE
,
2416 .size
= VAL_LEN_MAX
,
2417 .read
= mv64xxx_hs_reg_read
,
2418 .write
= mv64xxx_hs_reg_write
,
2421 /* Provide sysfs file indicating if this platform supports the hs_reg */
2423 mv64xxx_hs_reg_valid_show(struct device
*dev
, struct device_attribute
*attr
,
2426 struct platform_device
*pdev
;
2427 struct mv64xxx_pdata
*pdp
;
2430 pdev
= container_of(dev
, struct platform_device
, dev
);
2431 pdp
= (struct mv64xxx_pdata
*)pdev
->dev
.platform_data
;
2433 if (down_interruptible(&mv64xxx_hs_lock
))
2434 return -ERESTARTSYS
;
2435 v
= pdp
->hs_reg_valid
;
2436 up(&mv64xxx_hs_lock
);
2438 return sprintf(buf
, "%i\n", v
);
2440 static DEVICE_ATTR(hs_reg_valid
, S_IRUGO
, mv64xxx_hs_reg_valid_show
, NULL
);
2443 mv64xxx_sysfs_init(void)
2445 sysfs_create_bin_file(&mv64xxx_device
.dev
.kobj
, &mv64xxx_hs_reg_attr
);
2446 sysfs_create_file(&mv64xxx_device
.dev
.kobj
,&dev_attr_hs_reg_valid
.attr
);
2449 subsys_initcall(mv64xxx_sysfs_init
);