include/asm-m68knommu/mcfsim.h

   1 /****************************************************************************/
   2
   3 /*
   4  *      mcfsim.h -- ColdFire System Integration Module support.
   5  *
   6  *      (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com)
   7  *      (C) Copyright 2000, Lineo Inc. (www.lineo.com)
   8  */
   9
  10 /****************************************************************************/
  11 #ifndef mcfsim_h
  12 #define mcfsim_h
  13 /****************************************************************************/
  14
  15 #include <linux/config.h>
  16
  17 /*
  18  *      Include 5204, 5206/e, 5249, 5270/5271, 5272, 5280/5282, 5307 or
  19  *      5407 specific addresses.
  20  */
  21 #if defined(CONFIG_M5204)
  22 #include <asm/m5204sim.h>
  23 #elif defined(CONFIG_M5206) || defined(CONFIG_M5206e)
  24 #include <asm/m5206sim.h>
  25 #elif defined(CONFIG_M5249)
  26 #include <asm/m5249sim.h>
  27 #elif defined(CONFIG_M527x)
  28 #include <asm/m527xsim.h>
  29 #elif defined(CONFIG_M5272)
  30 #include <asm/m5272sim.h>
  31 #elif defined(CONFIG_M528x)
  32 #include <asm/m528xsim.h>
  33 #elif defined(CONFIG_M5307)
  34 #include <asm/m5307sim.h>
  35 #elif defined(CONFIG_M5407)
  36 #include <asm/m5407sim.h>
  37 #endif
  38
  39
  40 /*
  41  *      Define the base address of the SIM within the MBAR address space.
  42  */
  43 #define MCFSIM_BASE             0x0             /* Base address of SIM */
  44
  45
  46 /*
  47  *      Bit definitions for the ICR family of registers.
  48  */
  49 #define MCFSIM_ICR_AUTOVEC      0x80            /* Auto-vectored intr */
  50 #define MCFSIM_ICR_LEVEL0       0x00            /* Level 0 intr */
  51 #define MCFSIM_ICR_LEVEL1       0x04            /* Level 1 intr */
  52 #define MCFSIM_ICR_LEVEL2       0x08            /* Level 2 intr */
  53 #define MCFSIM_ICR_LEVEL3       0x0c            /* Level 3 intr */
  54 #define MCFSIM_ICR_LEVEL4       0x10            /* Level 4 intr */
  55 #define MCFSIM_ICR_LEVEL5       0x14            /* Level 5 intr */
  56 #define MCFSIM_ICR_LEVEL6       0x18            /* Level 6 intr */
  57 #define MCFSIM_ICR_LEVEL7       0x1c            /* Level 7 intr */
  58
  59 #define MCFSIM_ICR_PRI0         0x00            /* Priority 0 intr */
  60 #define MCFSIM_ICR_PRI1         0x01            /* Priority 1 intr */
  61 #define MCFSIM_ICR_PRI2         0x02            /* Priority 2 intr */
  62 #define MCFSIM_ICR_PRI3         0x03            /* Priority 3 intr */
  63
  64 /*
  65  *      Bit definitions for the Interrupt Mask register (IMR).
  66  */
  67 #define MCFSIM_IMR_EINT1        0x0002          /* External intr # 1 */
  68 #define MCFSIM_IMR_EINT2        0x0004          /* External intr # 2 */
  69 #define MCFSIM_IMR_EINT3        0x0008          /* External intr # 3 */
  70 #define MCFSIM_IMR_EINT4        0x0010          /* External intr # 4 */
  71 #define MCFSIM_IMR_EINT5        0x0020          /* External intr # 5 */
  72 #define MCFSIM_IMR_EINT6        0x0040          /* External intr # 6 */
  73 #define MCFSIM_IMR_EINT7        0x0080          /* External intr # 7 */
  74
  75 #define MCFSIM_IMR_SWD          0x0100          /* Software Watchdog intr */
  76 #define MCFSIM_IMR_TIMER1       0x0200          /* TIMER 1 intr */
  77 #define MCFSIM_IMR_TIMER2       0x0400          /* TIMER 2 intr */
  78 #define MCFSIM_IMR_MBUS         0x0800          /* MBUS intr    */
  79 #define MCFSIM_IMR_UART1        0x1000          /* UART 1 intr */
  80 #define MCFSIM_IMR_UART2        0x2000          /* UART 2 intr */
  81
  82 #if defined(CONFIG_M5206e)
  83 #define MCFSIM_IMR_DMA1         0x4000          /* DMA 1 intr */
  84 #define MCFSIM_IMR_DMA2         0x8000          /* DMA 2 intr */
  85 #elif defined(CONFIG_M5249) || defined(CONFIG_M5307)
  86 #define MCFSIM_IMR_DMA0         0x4000          /* DMA 0 intr */
  87 #define MCFSIM_IMR_DMA1         0x8000          /* DMA 1 intr */
  88 #define MCFSIM_IMR_DMA2         0x10000         /* DMA 2 intr */
  89 #define MCFSIM_IMR_DMA3         0x20000         /* DMA 3 intr */
  90 #endif
  91
  92 /*
  93  *      Mask for all of the SIM devices. Some parts have more or less
  94  *      SIM devices. This is a catchall for the sandard set.
  95  */
  96 #ifndef MCFSIM_IMR_MASKALL
  97 #define MCFSIM_IMR_MASKALL      0x3ffe          /* All intr sources */
  98 #endif
  99
 100
 101 #ifndef __ASSEMBLY__
 102 /*
 103  *      Definition for the interrupt auto-vectoring support.
 104  */
 105 extern void     mcf_autovector(unsigned int vec);
 106 #endif /* __ASSEMBLY__ */
 107
 108 /****************************************************************************/
 109 #endif  /* mcfsim_h */