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[PATCH] ARM: Fix VFP to use do_div()
[linux-2.6/verdex.git] / include / linux / pci.h
blob66798b46f3081e33d2a2aa7bc03fb3fb6aef2ba1
1 /*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17 #ifndef LINUX_PCI_H
18 #define LINUX_PCI_H
19
20 #include <linux/mod_devicetable.h>
21
22 /*
23 * Under PCI, each device has 256 bytes of configuration address space,
24 * of which the first 64 bytes are standardized as follows:
25 */
26 #define PCI_VENDOR_ID 0x00 /* 16 bits */
27 #define PCI_DEVICE_ID 0x02 /* 16 bits */
28 #define PCI_COMMAND 0x04 /* 16 bits */
29 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
30 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
31 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
32 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
33 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
34 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
35 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
36 #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
37 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */
38 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
39 #define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
40
41 #define PCI_STATUS 0x06 /* 16 bits */
42 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
43 #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
44 #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
45 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
46 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */
47 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
48 #define PCI_STATUS_DEVSEL_FAST 0x000
49 #define PCI_STATUS_DEVSEL_MEDIUM 0x200
50 #define PCI_STATUS_DEVSEL_SLOW 0x400
51 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
52 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
53 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
54 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
55 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
56
57 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
58 revision */
59 #define PCI_REVISION_ID 0x08 /* Revision ID */
60 #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
61 #define PCI_CLASS_DEVICE 0x0a /* Device class */
62
63 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
64 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */
65 #define PCI_HEADER_TYPE 0x0e /* 8 bits */
66 #define PCI_HEADER_TYPE_NORMAL 0
67 #define PCI_HEADER_TYPE_BRIDGE 1
68 #define PCI_HEADER_TYPE_CARDBUS 2
69
70 #define PCI_BIST 0x0f /* 8 bits */
71 #define PCI_BIST_CODE_MASK 0x0f /* Return result */
72 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
73 #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
74
75 /*
76 * Base addresses specify locations in memory or I/O space.
77 * Decoded size can be determined by writing a value of
78 * 0xffffffff to the register, and reading it back. Only
79 * 1 bits are decoded.
80 */
81 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
82 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
83 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
84 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
85 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
86 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
87 #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
88 #define PCI_BASE_ADDRESS_SPACE_IO 0x01
89 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
90 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
91 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
92 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
93 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
94 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
95 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
96 #define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
97 /* bit 1 is reserved if address_space = 1 */
98
99 /* Header type 0 (normal devices) */
100 #define PCI_CARDBUS_CIS 0x28
101 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
102 #define PCI_SUBSYSTEM_ID 0x2e
103 #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
104 #define PCI_ROM_ADDRESS_ENABLE 0x01
105 #define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
106
107 #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
108
109 /* 0x35-0x3b are reserved */
110 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
111 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
112 #define PCI_MIN_GNT 0x3e /* 8 bits */
113 #define PCI_MAX_LAT 0x3f /* 8 bits */
114
115 /* Header type 1 (PCI-to-PCI bridges) */
116 #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
117 #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
118 #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
119 #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
120 #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
121 #define PCI_IO_LIMIT 0x1d
122 #define PCI_IO_RANGE_TYPE_MASK 0x0fUL /* I/O bridging type */
123 #define PCI_IO_RANGE_TYPE_16 0x00
124 #define PCI_IO_RANGE_TYPE_32 0x01
125 #define PCI_IO_RANGE_MASK (~0x0fUL)
126 #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
127 #define PCI_MEMORY_BASE 0x20 /* Memory range behind */
128 #define PCI_MEMORY_LIMIT 0x22
129 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL
130 #define PCI_MEMORY_RANGE_MASK (~0x0fUL)
131 #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
132 #define PCI_PREF_MEMORY_LIMIT 0x26
133 #define PCI_PREF_RANGE_TYPE_MASK 0x0fUL
134 #define PCI_PREF_RANGE_TYPE_32 0x00
135 #define PCI_PREF_RANGE_TYPE_64 0x01
136 #define PCI_PREF_RANGE_MASK (~0x0fUL)
137 #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
138 #define PCI_PREF_LIMIT_UPPER32 0x2c
139 #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
140 #define PCI_IO_LIMIT_UPPER16 0x32
141 /* 0x34 same as for htype 0 */
142 /* 0x35-0x3b is reserved */
143 #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
144 /* 0x3c-0x3d are same as for htype 0 */
145 #define PCI_BRIDGE_CONTROL 0x3e
146 #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
147 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
148 #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
149 #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
150 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
151 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
152 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
153
154 /* Header type 2 (CardBus bridges) */
155 #define PCI_CB_CAPABILITY_LIST 0x14
156 /* 0x15 reserved */
157 #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
158 #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
159 #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
160 #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
161 #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
162 #define PCI_CB_MEMORY_BASE_0 0x1c
163 #define PCI_CB_MEMORY_LIMIT_0 0x20
164 #define PCI_CB_MEMORY_BASE_1 0x24
165 #define PCI_CB_MEMORY_LIMIT_1 0x28
166 #define PCI_CB_IO_BASE_0 0x2c
167 #define PCI_CB_IO_BASE_0_HI 0x2e
168 #define PCI_CB_IO_LIMIT_0 0x30
169 #define PCI_CB_IO_LIMIT_0_HI 0x32
170 #define PCI_CB_IO_BASE_1 0x34
171 #define PCI_CB_IO_BASE_1_HI 0x36
172 #define PCI_CB_IO_LIMIT_1 0x38
173 #define PCI_CB_IO_LIMIT_1_HI 0x3a
174 #define PCI_CB_IO_RANGE_MASK (~0x03UL)
175 /* 0x3c-0x3d are same as for htype 0 */
176 #define PCI_CB_BRIDGE_CONTROL 0x3e
177 #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
178 #define PCI_CB_BRIDGE_CTL_SERR 0x02
179 #define PCI_CB_BRIDGE_CTL_ISA 0x04
180 #define PCI_CB_BRIDGE_CTL_VGA 0x08
181 #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
182 #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
183 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
184 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
185 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
186 #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
187 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
188 #define PCI_CB_SUBSYSTEM_ID 0x42
189 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
190 /* 0x48-0x7f reserved */
191
192 /* Capability lists */
193
194 #define PCI_CAP_LIST_ID 0 /* Capability ID */
195 #define PCI_CAP_ID_PM 0x01 /* Power Management */
196 #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
197 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
198 #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
199 #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
200 #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
201 #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
202 #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
203 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */
204 #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
205 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
206 #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
207 #define PCI_CAP_SIZEOF 4
208
209 /* Power Management Registers */
210
211 #define PCI_PM_PMC 2 /* PM Capabilities Register */
212 #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
213 #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
214 #define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */
215 #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
216 #define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */
217 #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
218 #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
219 #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
220 #define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */
221 #define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */
222 #define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */
223 #define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
224 #define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */
225 #define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
226 #define PCI_PM_CTRL 4 /* PM control and status register */
227 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
228 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
229 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
230 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
231 #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
232 #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
233 #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
234 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
235 #define PCI_PM_DATA_REGISTER 7 /* (??) */
236 #define PCI_PM_SIZEOF 8
237
238 /* AGP registers */
239
240 #define PCI_AGP_VERSION 2 /* BCD version number */
241 #define PCI_AGP_RFU 3 /* Rest of capability flags */
242 #define PCI_AGP_STATUS 4 /* Status register */
243 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
244 #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
245 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
246 #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
247 #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
248 #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
249 #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
250 #define PCI_AGP_COMMAND 8 /* Control register */
251 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
252 #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
253 #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
254 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
255 #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
256 #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
257 #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */
258 #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */
259 #define PCI_AGP_SIZEOF 12
260
261 /* Vital Product Data */
262
263 #define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */
264 #define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */
265 #define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */
266 #define PCI_VPD_DATA 4 /* 32-bits of data returned here */
267
268 /* Slot Identification */
269
270 #define PCI_SID_ESR 2 /* Expansion Slot Register */
271 #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
272 #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
273 #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
274
275 /* Message Signalled Interrupts registers */
276
277 #define PCI_MSI_FLAGS 2 /* Various flags */
278 #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
279 #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
280 #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
281 #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
282 #define PCI_MSI_FLAGS_MASKBIT 0x100 /* 64-bit mask bits allowed */
283 #define PCI_MSI_RFU 3 /* Rest of capability flags */
284 #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
285 #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
286 #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
287 #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
288 #define PCI_MSI_MASK_BIT 16 /* Mask bits register */
289
290 /* CompactPCI Hotswap Register */
291
292 #define PCI_CHSWP_CSR 2 /* Control and Status Register */
293 #define PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */
294 #define PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */
295 #define PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */
296 #define PCI_CHSWP_LOO 0x08 /* LED On / Off */
297 #define PCI_CHSWP_PI 0x30 /* Programming Interface */
298 #define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */
299 #define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */
300
301 /* PCI-X registers */
302
303 #define PCI_X_CMD 2 /* Modes & Features */
304 #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
305 #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
306 #define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */
307 #define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */
308 #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
309 #define PCI_X_STATUS 4 /* PCI-X capabilities */
310 #define PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */
311 #define PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */
312 #define PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */
313 #define PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */
314 #define PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */
315 #define PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */
316 #define PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity */
317 #define PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count */
318 #define PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */
319 #define PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */
320 #define PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */
321 #define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
322 #define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
323
324 /* PCI Express capability registers */
325
326 #define PCI_EXP_FLAGS 2 /* Capabilities register */
327 #define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
328 #define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
329 #define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
330 #define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
331 #define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
332 #define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
333 #define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
334 #define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
335 #define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
336 #define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
337 #define PCI_EXP_DEVCAP 4 /* Device capabilities */
338 #define PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
339 #define PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
340 #define PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
341 #define PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
342 #define PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
343 #define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
344 #define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
345 #define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
346 #define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
347 #define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
348 #define PCI_EXP_DEVCTL 8 /* Device Control */
349 #define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */
350 #define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
351 #define PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */
352 #define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */
353 #define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
354 #define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
355 #define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
356 #define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
357 #define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
358 #define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
359 #define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
360 #define PCI_EXP_DEVSTA 10 /* Device Status */
361 #define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
362 #define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
363 #define PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
364 #define PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */
365 #define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
366 #define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
367 #define PCI_EXP_LNKCAP 12 /* Link Capabilities */
368 #define PCI_EXP_LNKCTL 16 /* Link Control */
369 #define PCI_EXP_LNKSTA 18 /* Link Status */
370 #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
371 #define PCI_EXP_SLTCTL 24 /* Slot Control */
372 #define PCI_EXP_SLTSTA 26 /* Slot Status */
373 #define PCI_EXP_RTCTL 28 /* Root Control */
374 #define PCI_EXP_RTCTL_SECEE 0x01 /* System Error on Correctable Error */
375 #define PCI_EXP_RTCTL_SENFEE 0x02 /* System Error on Non-Fatal Error */
376 #define PCI_EXP_RTCTL_SEFEE 0x04 /* System Error on Fatal Error */
377 #define PCI_EXP_RTCTL_PMEIE 0x08 /* PME Interrupt Enable */
378 #define PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */
379 #define PCI_EXP_RTCAP 30 /* Root Capabilities */
380 #define PCI_EXP_RTSTA 32 /* Root Status */
381
382 /* Extended Capabilities (PCI-X 2.0 and Express) */
383 #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
384 #define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
385 #define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
386
387 #define PCI_EXT_CAP_ID_ERR 1
388 #define PCI_EXT_CAP_ID_VC 2
389 #define PCI_EXT_CAP_ID_DSN 3
390 #define PCI_EXT_CAP_ID_PWR 4
391
392 /* Advanced Error Reporting */
393 #define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */
394 #define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */
395 #define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */
396 #define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */
397 #define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */
398 #define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */
399 #define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */
400 #define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */
401 #define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */
402 #define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */
403 #define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */
404 #define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */
405 #define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */
406 /* Same bits as above */
407 #define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */
408 /* Same bits as above */
409 #define PCI_ERR_COR_STATUS 16 /* Correctable Error Status */
410 #define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */
411 #define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */
412 #define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */
413 #define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */
414 #define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */
415 #define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */
416 /* Same bits as above */
417 #define PCI_ERR_CAP 24 /* Advanced Error Capabilities */
418 #define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */
419 #define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */
420 #define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */
421 #define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */
422 #define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
423 #define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */
424 #define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */
425 #define PCI_ERR_ROOT_STATUS 48
426 #define PCI_ERR_ROOT_COR_SRC 52
427 #define PCI_ERR_ROOT_SRC 54
428
429 /* Virtual Channel */
430 #define PCI_VC_PORT_REG1 4
431 #define PCI_VC_PORT_REG2 8
432 #define PCI_VC_PORT_CTRL 12
433 #define PCI_VC_PORT_STATUS 14
434 #define PCI_VC_RES_CAP 16
435 #define PCI_VC_RES_CTRL 20
436 #define PCI_VC_RES_STATUS 26
437
438 /* Power Budgeting */
439 #define PCI_PWR_DSR 4 /* Data Select Register */
440 #define PCI_PWR_DATA 8 /* Data Register */
441 #define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */
442 #define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */
443 #define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */
444 #define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
445 #define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */
446 #define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */
447 #define PCI_PWR_CAP 12 /* Capability */
448 #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */
449
450 /* Include the ID list */
451
452 #include <linux/pci_ids.h>
453
454 /*
455 * The PCI interface treats multi-function devices as independent
456 * devices. The slot/function address of each device is encoded
457 * in a single byte as follows:
458 *
459 * 7:3 = slot
460 * 2:0 = function
461 */
462 #define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
463 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
464 #define PCI_FUNC(devfn) ((devfn) & 0x07)
465
466 /* Ioctls for /proc/bus/pci/X/Y nodes. */
467 #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
468 #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
469 #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
470 #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
471 #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
472
473 #ifdef __KERNEL__
474
475 #include <linux/types.h>
476 #include <linux/config.h>
477 #include <linux/ioport.h>
478 #include <linux/list.h>
479 #include <linux/errno.h>
480 #include <linux/device.h>
481
482 /* File state for mmap()s on /proc/bus/pci/X/Y */
483 enum pci_mmap_state {
484 pci_mmap_io,
485 pci_mmap_mem
486 };
487
488 /* This defines the direction arg to the DMA mapping routines. */
489 #define PCI_DMA_BIDIRECTIONAL 0
490 #define PCI_DMA_TODEVICE 1
491 #define PCI_DMA_FROMDEVICE 2
492 #define PCI_DMA_NONE 3
493
494 #define DEVICE_COUNT_COMPATIBLE 4
495 #define DEVICE_COUNT_RESOURCE 12
496
497 typedef int __bitwise pci_power_t;
498
499 #define PCI_D0 ((pci_power_t __force) 0)
500 #define PCI_D1 ((pci_power_t __force) 1)
501 #define PCI_D2 ((pci_power_t __force) 2)
502 #define PCI_D3hot ((pci_power_t __force) 3)
503 #define PCI_D3cold ((pci_power_t __force) 4)
504 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
505
506 /*
507 * The pci_dev structure is used to describe PCI devices.
508 */
509 struct pci_dev {
510 struct list_head global_list; /* node in list of all PCI devices */
511 struct list_head bus_list; /* node in per-bus list */
512 struct pci_bus *bus; /* bus this device is on */
513 struct pci_bus *subordinate; /* bus this device bridges to */
514
515 void *sysdata; /* hook for sys-specific extension */
516 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
517
518 unsigned int devfn; /* encoded device & function index */
519 unsigned short vendor;
520 unsigned short device;
521 unsigned short subsystem_vendor;
522 unsigned short subsystem_device;
523 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
524 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
525 u8 rom_base_reg; /* which config register controls the ROM */
526
527 struct pci_driver *driver; /* which driver has allocated this device */
528 u64 dma_mask; /* Mask of the bits of bus address this
529 device implements. Normally this is
530 0xffffffff. You only need to change
531 this if your device has broken DMA
532 or supports 64-bit transfers. */
533
534 pci_power_t current_state; /* Current operating state. In ACPI-speak,
535 this is D0-D3, D0 being fully functional,
536 and D3 being off. */
537
538 struct device dev; /* Generic device interface */
539
540 /* device is compatible with these IDs */
541 unsigned short vendor_compatible[DEVICE_COUNT_COMPATIBLE];
542 unsigned short device_compatible[DEVICE_COUNT_COMPATIBLE];
543
544 int cfg_size; /* Size of configuration space */
545
546 /*
547 * Instead of touching interrupt line and base address registers
548 * directly, use the values stored here. They might be different!
549 */
550 unsigned int irq;
551 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
552
553 /* These fields are used by common fixups */
554 unsigned int transparent:1; /* Transparent PCI bridge */
555 unsigned int multifunction:1;/* Part of multi-function device */
556 /* keep track of device state */
557 unsigned int is_enabled:1; /* pci_enable_device has been called */
558 unsigned int is_busmaster:1; /* device is busmaster */
559
560 u32 saved_config_space[16]; /* config space saved at suspend time */
561 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
562 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
563 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
564 #ifdef CONFIG_PCI_NAMES
565 #define PCI_NAME_SIZE 255
566 #define PCI_NAME_HALF __stringify(43) /* less than half to handle slop */
567 char pretty_name[PCI_NAME_SIZE]; /* pretty name for users to see */
568 #endif
569 };
570
571 #define pci_dev_g(n) list_entry(n, struct pci_dev, global_list)
572 #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
573 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
574 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
575
576 /*
577 * For PCI devices, the region numbers are assigned this way:
578 *
579 * 0-5 standard PCI regions
580 * 6 expansion ROM
581 * 7-10 bridges: address space assigned to buses behind the bridge
582 */
583
584 #define PCI_ROM_RESOURCE 6
585 #define PCI_BRIDGE_RESOURCES 7
586 #define PCI_NUM_RESOURCES 11
587
588 #ifndef PCI_BUS_NUM_RESOURCES
589 #define PCI_BUS_NUM_RESOURCES 4
590 #endif
591
592 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
593
594 struct pci_bus {
595 struct list_head node; /* node in list of buses */
596 struct pci_bus *parent; /* parent bus this bridge is on */
597 struct list_head children; /* list of child buses */
598 struct list_head devices; /* list of devices on this bus */
599 struct pci_dev *self; /* bridge device as seen by parent */
600 struct resource *resource[PCI_BUS_NUM_RESOURCES];
601 /* address space routed to this bus */
602
603 struct pci_ops *ops; /* configuration access functions */
604 void *sysdata; /* hook for sys-specific extension */
605 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
606
607 unsigned char number; /* bus number */
608 unsigned char primary; /* number of primary bridge */
609 unsigned char secondary; /* number of secondary bridge */
610 unsigned char subordinate; /* max number of subordinate buses */
611
612 char name[48];
613
614 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
615 unsigned short pad2;
616 struct device *bridge;
617 struct class_device class_dev;
618 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
619 struct bin_attribute *legacy_mem; /* legacy mem */
620 };
621
622 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
623 #define to_pci_bus(n) container_of(n, struct pci_bus, class_dev)
624
625 /*
626 * Error values that may be returned by PCI functions.
627 */
628 #define PCIBIOS_SUCCESSFUL 0x00
629 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
630 #define PCIBIOS_BAD_VENDOR_ID 0x83
631 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
632 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
633 #define PCIBIOS_SET_FAILED 0x88
634 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
635
636 /* Low-level architecture-dependent routines */
637
638 struct pci_ops {
639 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
640 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
641 };
642
643 struct pci_raw_ops {
644 int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
645 int reg, int len, u32 *val);
646 int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
647 int reg, int len, u32 val);
648 };
649
650 extern struct pci_raw_ops *raw_pci_ops;
651
652 struct pci_bus_region {
653 unsigned long start;
654 unsigned long end;
655 };
656
657 struct pci_dynids {
658 spinlock_t lock; /* protects list, index */
659 struct list_head list; /* for IDs added at runtime */
660 unsigned int use_driver_data:1; /* pci_driver->driver_data is used */
661 };
662
663 struct module;
664 struct pci_driver {
665 struct list_head node;
666 char *name;
667 struct module *owner;
668 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
669 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
670 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
671 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
672 int (*resume) (struct pci_dev *dev); /* Device woken up */
673 int (*enable_wake) (struct pci_dev *dev, pci_power_t state, int enable); /* Enable wake event */
674 void (*shutdown) (struct pci_dev *dev);
675
676 struct device_driver driver;
677 struct pci_dynids dynids;
678 };
679
680 #define to_pci_driver(drv) container_of(drv,struct pci_driver, driver)
681
682 /**
683 * PCI_DEVICE - macro used to describe a specific pci device
684 * @vend: the 16 bit PCI Vendor ID
685 * @dev: the 16 bit PCI Device ID
686 *
687 * This macro is used to create a struct pci_device_id that matches a
688 * specific device. The subvendor and subdevice fields will be set to
689 * PCI_ANY_ID.
690 */
691 #define PCI_DEVICE(vend,dev) \
692 .vendor = (vend), .device = (dev), \
693 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
694
695 /**
696 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
697 * @dev_class: the class, subclass, prog-if triple for this device
698 * @dev_class_mask: the class mask for this device
699 *
700 * This macro is used to create a struct pci_device_id that matches a
701 * specific PCI class. The vendor, device, subvendor, and subdevice
702 * fields will be set to PCI_ANY_ID.
703 */
704 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
705 .class = (dev_class), .class_mask = (dev_class_mask), \
706 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
707 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
708
709 /*
710 * pci_module_init is obsolete, this stays here till we fix up all usages of it
711 * in the tree.
712 */
713 #define pci_module_init pci_register_driver
714
715 /* these external functions are only available when PCI support is enabled */
716 #ifdef CONFIG_PCI
717
718 extern struct bus_type pci_bus_type;
719
720 /* Do NOT directly access these two variables, unless you are arch specific pci
721 * code, or pci core code. */
722 extern struct list_head pci_root_buses; /* list of all known PCI buses */
723 extern struct list_head pci_devices; /* list of all devices */
724
725 void pcibios_fixup_bus(struct pci_bus *);
726 int pcibios_enable_device(struct pci_dev *, int mask);
727 char *pcibios_setup (char *str);
728
729 /* Used only when drivers/pci/setup.c is used */
730 void pcibios_align_resource(void *, struct resource *,
731 unsigned long, unsigned long);
732 void pcibios_update_irq(struct pci_dev *, int irq);
733
734 /* Generic PCI functions used internally */
735
736 extern struct pci_bus *pci_find_bus(int domain, int busnr);
737 void pci_bus_add_devices(struct pci_bus *bus);
738 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, struct pci_ops *ops, void *sysdata);
739 static inline struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata)
740 {
741 struct pci_bus *root_bus;
742 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
743 if (root_bus)
744 pci_bus_add_devices(root_bus);
745 return root_bus;
746 }
747 int pci_scan_slot(struct pci_bus *bus, int devfn);
748 struct pci_dev * pci_scan_single_device(struct pci_bus *bus, int devfn);
749 unsigned int pci_scan_child_bus(struct pci_bus *bus);
750 void pci_bus_add_device(struct pci_dev *dev);
751 void pci_name_device(struct pci_dev *dev);
752 char *pci_class_name(u32 class);
753 void pci_read_bridge_bases(struct pci_bus *child);
754 struct resource *pci_find_parent_resource(const struct pci_dev *dev, struct resource *res);
755 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
756 extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
757 extern void pci_dev_put(struct pci_dev *dev);
758 extern void pci_remove_bus(struct pci_bus *b);
759 extern void pci_remove_bus_device(struct pci_dev *dev);
760
761 /* Generic PCI functions exported to card drivers */
762
763 struct pci_dev *pci_find_device (unsigned int vendor, unsigned int device, const struct pci_dev *from);
764 struct pci_dev *pci_find_device_reverse (unsigned int vendor, unsigned int device, const struct pci_dev *from);
765 struct pci_dev *pci_find_slot (unsigned int bus, unsigned int devfn);
766 int pci_find_capability (struct pci_dev *dev, int cap);
767 int pci_find_ext_capability (struct pci_dev *dev, int cap);
768 struct pci_bus * pci_find_next_bus(const struct pci_bus *from);
769
770 struct pci_dev *pci_get_device (unsigned int vendor, unsigned int device, struct pci_dev *from);
771 struct pci_dev *pci_get_subsys (unsigned int vendor, unsigned int device,
772 unsigned int ss_vendor, unsigned int ss_device,
773 struct pci_dev *from);
774 struct pci_dev *pci_get_slot (struct pci_bus *bus, unsigned int devfn);
775 struct pci_dev *pci_get_class (unsigned int class, struct pci_dev *from);
776 int pci_dev_present(const struct pci_device_id *ids);
777
778 int pci_bus_read_config_byte (struct pci_bus *bus, unsigned int devfn, int where, u8 *val);
779 int pci_bus_read_config_word (struct pci_bus *bus, unsigned int devfn, int where, u16 *val);
780 int pci_bus_read_config_dword (struct pci_bus *bus, unsigned int devfn, int where, u32 *val);
781 int pci_bus_write_config_byte (struct pci_bus *bus, unsigned int devfn, int where, u8 val);
782 int pci_bus_write_config_word (struct pci_bus *bus, unsigned int devfn, int where, u16 val);
783 int pci_bus_write_config_dword (struct pci_bus *bus, unsigned int devfn, int where, u32 val);
784
785 static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
786 {
787 return pci_bus_read_config_byte (dev->bus, dev->devfn, where, val);
788 }
789 static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
790 {
791 return pci_bus_read_config_word (dev->bus, dev->devfn, where, val);
792 }
793 static inline int pci_read_config_dword(struct pci_dev *dev, int where, u32 *val)
794 {
795 return pci_bus_read_config_dword (dev->bus, dev->devfn, where, val);
796 }
797 static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
798 {
799 return pci_bus_write_config_byte (dev->bus, dev->devfn, where, val);
800 }
801 static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
802 {
803 return pci_bus_write_config_word (dev->bus, dev->devfn, where, val);
804 }
805 static inline int pci_write_config_dword(struct pci_dev *dev, int where, u32 val)
806 {
807 return pci_bus_write_config_dword (dev->bus, dev->devfn, where, val);
808 }
809
810 int pci_enable_device(struct pci_dev *dev);
811 int pci_enable_device_bars(struct pci_dev *dev, int mask);
812 void pci_disable_device(struct pci_dev *dev);
813 void pci_set_master(struct pci_dev *dev);
814 #define HAVE_PCI_SET_MWI
815 int pci_set_mwi(struct pci_dev *dev);
816 void pci_clear_mwi(struct pci_dev *dev);
817 int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
818 int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask);
819 int pci_assign_resource(struct pci_dev *dev, int i);
820
821 /* ROM control related routines */
822 void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size);
823 void __iomem *pci_map_rom_copy(struct pci_dev *pdev, size_t *size);
824 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
825 void pci_remove_rom(struct pci_dev *pdev);
826
827 /* Power management related routines */
828 int pci_save_state(struct pci_dev *dev);
829 int pci_restore_state(struct pci_dev *dev);
830 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
831 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
832 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable);
833
834 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
835 void pci_bus_assign_resources(struct pci_bus *bus);
836 void pci_bus_size_bridges(struct pci_bus *bus);
837 int pci_claim_resource(struct pci_dev *, int);
838 void pci_assign_unassigned_resources(void);
839 void pdev_enable_device(struct pci_dev *);
840 void pdev_sort_resources(struct pci_dev *, struct resource_list *);
841 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
842 int (*)(struct pci_dev *, u8, u8));
843 #define HAVE_PCI_REQ_REGIONS 2
844 int pci_request_regions(struct pci_dev *, char *);
845 void pci_release_regions(struct pci_dev *);
846 int pci_request_region(struct pci_dev *, int, char *);
847 void pci_release_region(struct pci_dev *, int);
848
849 /* drivers/pci/bus.c */
850 int pci_bus_alloc_resource(struct pci_bus *bus, struct resource *res,
851 unsigned long size, unsigned long align,
852 unsigned long min, unsigned int type_mask,
853 void (*alignf)(void *, struct resource *,
854 unsigned long, unsigned long),
855 void *alignf_data);
856 void pci_enable_bridges(struct pci_bus *bus);
857
858 /* New-style probing supporting hot-pluggable devices */
859 int pci_register_driver(struct pci_driver *);
860 void pci_unregister_driver(struct pci_driver *);
861 void pci_remove_behind_bridge(struct pci_dev *);
862 struct pci_driver *pci_dev_driver(const struct pci_dev *);
863 const struct pci_device_id *pci_match_device(const struct pci_device_id *ids, const struct pci_dev *dev);
864 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass);
865
866 /* kmem_cache style wrapper around pci_alloc_consistent() */
867
868 #include <linux/dmapool.h>
869
870 #define pci_pool dma_pool
871 #define pci_pool_create(name, pdev, size, align, allocation) \
872 dma_pool_create(name, &pdev->dev, size, align, allocation)
873 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
874 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
875 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
876
877 enum pci_dma_burst_strategy {
878 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
879 strategy_parameter is N/A */
880 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
881 byte boundaries */
882 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
883 strategy_parameter byte boundaries */
884 };
885
886 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
887 extern struct pci_dev *isa_bridge;
888 #endif
889
890 struct msix_entry {
891 u16 vector; /* kernel uses to write allocated vector */
892 u16 entry; /* driver uses to specify entry, OS writes */
893 };
894
895 #ifndef CONFIG_PCI_MSI
896 static inline void pci_scan_msi_device(struct pci_dev *dev) {}
897 static inline int pci_enable_msi(struct pci_dev *dev) {return -1;}
898 static inline void pci_disable_msi(struct pci_dev *dev) {}
899 static inline int pci_enable_msix(struct pci_dev* dev,
900 struct msix_entry *entries, int nvec) {return -1;}
901 static inline void pci_disable_msix(struct pci_dev *dev) {}
902 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) {}
903 #else
904 extern void pci_scan_msi_device(struct pci_dev *dev);
905 extern int pci_enable_msi(struct pci_dev *dev);
906 extern void pci_disable_msi(struct pci_dev *dev);
907 extern int pci_enable_msix(struct pci_dev* dev,
908 struct msix_entry *entries, int nvec);
909 extern void pci_disable_msix(struct pci_dev *dev);
910 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
911 #endif
912
913 #endif /* CONFIG_PCI */
914
915 /* Include architecture-dependent settings and functions */
916
917 #include <asm/pci.h>
918
919 /*
920 * If the system does not have PCI, clearly these return errors. Define
921 * these as simple inline functions to avoid hair in drivers.
922 */
923
924 #ifndef CONFIG_PCI
925 #define _PCI_NOP(o,s,t) \
926 static inline int pci_##o##_config_##s (struct pci_dev *dev, int where, t val) \
927 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
928 #define _PCI_NOP_ALL(o,x) _PCI_NOP(o,byte,u8 x) \
929 _PCI_NOP(o,word,u16 x) \
930 _PCI_NOP(o,dword,u32 x)
931 _PCI_NOP_ALL(read, *)
932 _PCI_NOP_ALL(write,)
933
934 static inline struct pci_dev *pci_find_device(unsigned int vendor, unsigned int device, const struct pci_dev *from)
935 { return NULL; }
936
937 static inline struct pci_dev *pci_find_slot(unsigned int bus, unsigned int devfn)
938 { return NULL; }
939
940 static inline struct pci_dev *pci_get_device (unsigned int vendor, unsigned int device, struct pci_dev *from)
941 { return NULL; }
942
943 static inline struct pci_dev *pci_get_subsys (unsigned int vendor, unsigned int device,
944 unsigned int ss_vendor, unsigned int ss_device, struct pci_dev *from)
945 { return NULL; }
946
947 static inline struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from)
948 { return NULL; }
949
950 #define pci_dev_present(ids) (0)
951 #define pci_dev_put(dev) do { } while (0)
952
953 static inline void pci_set_master(struct pci_dev *dev) { }
954 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
955 static inline void pci_disable_device(struct pci_dev *dev) { }
956 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) { return -EIO; }
957 static inline int pci_assign_resource(struct pci_dev *dev, int i) { return -EBUSY;}
958 static inline int pci_register_driver(struct pci_driver *drv) { return 0;}
959 static inline void pci_unregister_driver(struct pci_driver *drv) { }
960 static inline int pci_find_capability (struct pci_dev *dev, int cap) {return 0; }
961 static inline int pci_find_ext_capability (struct pci_dev *dev, int cap) {return 0; }
962 static inline const struct pci_device_id *pci_match_device(const struct pci_device_id *ids, const struct pci_dev *dev) { return NULL; }
963
964 /* Power management related routines */
965 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
966 static inline int pci_restore_state(struct pci_dev *dev) { return 0; }
967 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) { return 0; }
968 static inline pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) { return PCI_D0; }
969 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) { return 0; }
970
971 #define isa_bridge ((struct pci_dev *)NULL)
972
973 #else
974
975 /*
976 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
977 * a PCI domain is defined to be a set of PCI busses which share
978 * configuration space.
979 */
980 #ifndef CONFIG_PCI_DOMAINS
981 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
982 static inline int pci_proc_domain(struct pci_bus *bus)
983 {
984 return 0;
985 }
986 #endif
987
988 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
989
990 #endif /* !CONFIG_PCI */
991
992 /* these helpers provide future and backwards compatibility
993 * for accessing popular PCI BAR info */
994 #define pci_resource_start(dev,bar) ((dev)->resource[(bar)].start)
995 #define pci_resource_end(dev,bar) ((dev)->resource[(bar)].end)
996 #define pci_resource_flags(dev,bar) ((dev)->resource[(bar)].flags)
997 #define pci_resource_len(dev,bar) \
998 ((pci_resource_start((dev),(bar)) == 0 && \
999 pci_resource_end((dev),(bar)) == \
1000 pci_resource_start((dev),(bar))) ? 0 : \
1001 \
1002 (pci_resource_end((dev),(bar)) - \
1003 pci_resource_start((dev),(bar)) + 1))
1004
1005 /* Similar to the helpers above, these manipulate per-pci_dev
1006 * driver-specific data. They are really just a wrapper around
1007 * the generic device structure functions of these calls.
1008 */
1009 static inline void *pci_get_drvdata (struct pci_dev *pdev)
1010 {
1011 return dev_get_drvdata(&pdev->dev);
1012 }
1013
1014 static inline void pci_set_drvdata (struct pci_dev *pdev, void *data)
1015 {
1016 dev_set_drvdata(&pdev->dev, data);
1017 }
1018
1019 /* If you want to know what to call your pci_dev, ask this function.
1020 * Again, it's a wrapper around the generic device.
1021 */
1022 static inline char *pci_name(struct pci_dev *pdev)
1023 {
1024 return pdev->dev.bus_id;
1025 }
1026
1027 /* Some archs want to see the pretty pci name, so use this macro */
1028 #ifdef CONFIG_PCI_NAMES
1029 #define pci_pretty_name(dev) ((dev)->pretty_name)
1030 #else
1031 #define pci_pretty_name(dev) ""
1032 #endif
1033
1034
1035 /* Some archs don't want to expose struct resource to userland as-is
1036 * in sysfs and /proc
1037 */
1038 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1039 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1040 const struct resource *rsrc, u64 *start, u64 *end)
1041 {
1042 *start = rsrc->start;
1043 *end = rsrc->end;
1044 }
1045 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1046
1047
1048 /*
1049 * The world is not perfect and supplies us with broken PCI devices.
1050 * For at least a part of these bugs we need a work-around, so both
1051 * generic (drivers/pci/quirks.c) and per-architecture code can define
1052 * fixup hooks to be called for particular buggy devices.
1053 */
1054
1055 struct pci_fixup {
1056 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
1057 void (*hook)(struct pci_dev *dev);
1058 };
1059
1060 enum pci_fixup_pass {
1061 pci_fixup_early, /* Before probing BARs */
1062 pci_fixup_header, /* After reading configuration header */
1063 pci_fixup_final, /* Final phase of device fixups */
1064 pci_fixup_enable, /* pci_enable_device() time */
1065 };
1066
1067 /* Anonymous variables would be nice... */
1068 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
1069 static struct pci_fixup __pci_fixup_##name __attribute_used__ \
1070 __attribute__((__section__(#section))) = { vendor, device, hook };
1071 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1072 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1073 vendor##device##hook, vendor, device, hook)
1074 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1075 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1076 vendor##device##hook, vendor, device, hook)
1077 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1078 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1079 vendor##device##hook, vendor, device, hook)
1080 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1081 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1082 vendor##device##hook, vendor, device, hook)
1083
1084
1085 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1086
1087 extern int pci_pci_problems;
1088 #define PCIPCI_FAIL 1
1089 #define PCIPCI_TRITON 2
1090 #define PCIPCI_NATOMA 4
1091 #define PCIPCI_VIAETBF 8
1092 #define PCIPCI_VSFX 16
1093 #define PCIPCI_ALIMAGIK 32
1094
1095 #endif /* __KERNEL__ */
1096 #endif /* LINUX_PCI_H */
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