2 * linux/arch/x86_64/nmi.c
4 * NMI watchdog support on APIC systems
6 * Started by Ingo Molnar <mingo@redhat.com>
9 * Mikael Pettersson : AMD K7 support for local APIC NMI watchdog.
10 * Mikael Pettersson : Power Management for local APIC NMI watchdog.
12 * Mikael Pettersson : PM converted to driver model. Disable/enable API.
15 #include <linux/config.h>
17 #include <linux/delay.h>
18 #include <linux/bootmem.h>
19 #include <linux/smp_lock.h>
20 #include <linux/interrupt.h>
21 #include <linux/mc146818rtc.h>
22 #include <linux/kernel_stat.h>
23 #include <linux/module.h>
24 #include <linux/sysdev.h>
25 #include <linux/nmi.h>
26 #include <linux/sysctl.h>
27 #include <linux/kprobes.h>
31 #include <asm/mpspec.h>
34 #include <asm/proto.h>
35 #include <asm/kdebug.h>
36 #include <asm/local.h>
39 * lapic_nmi_owner tracks the ownership of the lapic NMI hardware:
40 * - it may be reserved by some other driver, or not
41 * - when not reserved by some other driver, it may be used for
42 * the NMI watchdog, or not
44 * This is maintained separately from nmi_active because the NMI
45 * watchdog may also be driven from the I/O APIC timer.
47 static DEFINE_SPINLOCK(lapic_nmi_owner_lock
);
48 static unsigned int lapic_nmi_owner
;
49 #define LAPIC_NMI_WATCHDOG (1<<0)
50 #define LAPIC_NMI_RESERVED (1<<1)
53 * +1: the lapic NMI watchdog is active, but can be disabled
54 * 0: the lapic NMI watchdog has not been set up, and cannot
56 * -1: the lapic NMI watchdog is disabled, but can be enabled
58 int nmi_active
; /* oprofile uses this */
61 unsigned int nmi_watchdog
= NMI_DEFAULT
;
62 static unsigned int nmi_hz
= HZ
;
63 static unsigned int nmi_perfctr_msr
; /* the MSR to reset in NMI handler */
64 static unsigned int nmi_p4_cccr_val
;
66 /* Note that these events don't tick when the CPU idles. This means
67 the frequency varies with CPU load. */
69 #define K7_EVNTSEL_ENABLE (1 << 22)
70 #define K7_EVNTSEL_INT (1 << 20)
71 #define K7_EVNTSEL_OS (1 << 17)
72 #define K7_EVNTSEL_USR (1 << 16)
73 #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING 0x76
74 #define K7_NMI_EVENT K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
76 #define MSR_P4_MISC_ENABLE 0x1A0
77 #define MSR_P4_MISC_ENABLE_PERF_AVAIL (1<<7)
78 #define MSR_P4_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
79 #define MSR_P4_PERFCTR0 0x300
80 #define MSR_P4_CCCR0 0x360
81 #define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
82 #define P4_ESCR_OS (1<<3)
83 #define P4_ESCR_USR (1<<2)
84 #define P4_CCCR_OVF_PMI0 (1<<26)
85 #define P4_CCCR_OVF_PMI1 (1<<27)
86 #define P4_CCCR_THRESHOLD(N) ((N)<<20)
87 #define P4_CCCR_COMPLEMENT (1<<19)
88 #define P4_CCCR_COMPARE (1<<18)
89 #define P4_CCCR_REQUIRED (3<<16)
90 #define P4_CCCR_ESCR_SELECT(N) ((N)<<13)
91 #define P4_CCCR_ENABLE (1<<12)
92 /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
93 CRU_ESCR0 (with any non-null event selector) through a complemented
94 max threshold. [IA32-Vol3, Section 14.9.9] */
95 #define MSR_P4_IQ_COUNTER0 0x30C
96 #define P4_NMI_CRU_ESCR0 (P4_ESCR_EVENT_SELECT(0x3F)|P4_ESCR_OS|P4_ESCR_USR)
97 #define P4_NMI_IQ_CCCR0 \
98 (P4_CCCR_OVF_PMI0|P4_CCCR_THRESHOLD(15)|P4_CCCR_COMPLEMENT| \
99 P4_CCCR_COMPARE|P4_CCCR_REQUIRED|P4_CCCR_ESCR_SELECT(4)|P4_CCCR_ENABLE)
101 static __cpuinit
inline int nmi_known_cpu(void)
103 switch (boot_cpu_data
.x86_vendor
) {
105 return boot_cpu_data
.x86
== 15;
106 case X86_VENDOR_INTEL
:
107 return boot_cpu_data
.x86
== 15;
112 /* Run after command line and cpu_init init, but before all other checks */
113 void __cpuinit
nmi_watchdog_default(void)
115 if (nmi_watchdog
!= NMI_DEFAULT
)
118 nmi_watchdog
= NMI_LOCAL_APIC
;
120 nmi_watchdog
= NMI_IO_APIC
;
124 /* The performance counters used by NMI_LOCAL_APIC don't trigger when
125 * the CPU is idle. To make sure the NMI watchdog really ticks on all
126 * CPUs during the test make them busy.
128 static __init
void nmi_cpu_busy(void *data
)
130 volatile int *endflag
= data
;
132 /* Intentionally don't use cpu_relax here. This is
133 to make sure that the performance counter really ticks,
134 even if there is a simulator or similar that catches the
135 pause instruction. On a real HT machine this is fine because
136 all other CPUs are busy with "useless" delay loops and don't
137 care if they get somewhat less cycles. */
138 while (*endflag
== 0)
143 int __init
check_nmi_watchdog (void)
145 volatile int endflag
= 0;
149 counts
= kmalloc(NR_CPUS
* sizeof(int), GFP_KERNEL
);
153 printk(KERN_INFO
"testing NMI watchdog ... ");
156 if (nmi_watchdog
== NMI_LOCAL_APIC
)
157 smp_call_function(nmi_cpu_busy
, (void *)&endflag
, 0, 0);
160 for (cpu
= 0; cpu
< NR_CPUS
; cpu
++)
161 counts
[cpu
] = cpu_pda(cpu
)->__nmi_count
;
163 mdelay((10*1000)/nmi_hz
); // wait 10 ticks
165 for (cpu
= 0; cpu
< NR_CPUS
; cpu
++) {
166 if (!cpu_online(cpu
))
168 if (cpu_pda(cpu
)->__nmi_count
- counts
[cpu
] <= 5) {
170 printk("CPU#%d: NMI appears to be stuck (%d->%d)!\n",
173 cpu_pda(cpu
)->__nmi_count
);
175 lapic_nmi_owner
&= ~LAPIC_NMI_WATCHDOG
;
184 /* now that we know it works we can reduce NMI frequency to
185 something more reasonable; makes a difference in some configs */
186 if (nmi_watchdog
== NMI_LOCAL_APIC
)
193 int __init
setup_nmi_watchdog(char *str
)
197 if (!strncmp(str
,"panic",5)) {
198 panic_on_timeout
= 1;
199 str
= strchr(str
, ',');
205 get_option(&str
, &nmi
);
207 if (nmi
>= NMI_INVALID
)
213 __setup("nmi_watchdog=", setup_nmi_watchdog
);
215 static void disable_lapic_nmi_watchdog(void)
219 switch (boot_cpu_data
.x86_vendor
) {
221 wrmsr(MSR_K7_EVNTSEL0
, 0, 0);
223 case X86_VENDOR_INTEL
:
224 if (boot_cpu_data
.x86
== 15) {
225 wrmsr(MSR_P4_IQ_CCCR0
, 0, 0);
226 wrmsr(MSR_P4_CRU_ESCR0
, 0, 0);
231 /* tell do_nmi() and others that we're not active any more */
235 static void enable_lapic_nmi_watchdog(void)
237 if (nmi_active
< 0) {
238 nmi_watchdog
= NMI_LOCAL_APIC
;
239 touch_nmi_watchdog();
240 setup_apic_nmi_watchdog();
244 int reserve_lapic_nmi(void)
246 unsigned int old_owner
;
248 spin_lock(&lapic_nmi_owner_lock
);
249 old_owner
= lapic_nmi_owner
;
250 lapic_nmi_owner
|= LAPIC_NMI_RESERVED
;
251 spin_unlock(&lapic_nmi_owner_lock
);
252 if (old_owner
& LAPIC_NMI_RESERVED
)
254 if (old_owner
& LAPIC_NMI_WATCHDOG
)
255 disable_lapic_nmi_watchdog();
259 void release_lapic_nmi(void)
261 unsigned int new_owner
;
263 spin_lock(&lapic_nmi_owner_lock
);
264 new_owner
= lapic_nmi_owner
& ~LAPIC_NMI_RESERVED
;
265 lapic_nmi_owner
= new_owner
;
266 spin_unlock(&lapic_nmi_owner_lock
);
267 if (new_owner
& LAPIC_NMI_WATCHDOG
)
268 enable_lapic_nmi_watchdog();
271 void disable_timer_nmi_watchdog(void)
273 if ((nmi_watchdog
!= NMI_IO_APIC
) || (nmi_active
<= 0))
277 unset_nmi_callback();
279 nmi_watchdog
= NMI_NONE
;
282 void enable_timer_nmi_watchdog(void)
284 if (nmi_active
< 0) {
285 nmi_watchdog
= NMI_IO_APIC
;
286 touch_nmi_watchdog();
294 static int nmi_pm_active
; /* nmi_active before suspend */
296 static int lapic_nmi_suspend(struct sys_device
*dev
, pm_message_t state
)
298 nmi_pm_active
= nmi_active
;
299 disable_lapic_nmi_watchdog();
303 static int lapic_nmi_resume(struct sys_device
*dev
)
305 if (nmi_pm_active
> 0)
306 enable_lapic_nmi_watchdog();
310 static struct sysdev_class nmi_sysclass
= {
311 set_kset_name("lapic_nmi"),
312 .resume
= lapic_nmi_resume
,
313 .suspend
= lapic_nmi_suspend
,
316 static struct sys_device device_lapic_nmi
= {
318 .cls
= &nmi_sysclass
,
321 static int __init
init_lapic_nmi_sysfs(void)
325 if (nmi_active
== 0 || nmi_watchdog
!= NMI_LOCAL_APIC
)
328 error
= sysdev_class_register(&nmi_sysclass
);
330 error
= sysdev_register(&device_lapic_nmi
);
333 /* must come after the local APIC's device_initcall() */
334 late_initcall(init_lapic_nmi_sysfs
);
336 #endif /* CONFIG_PM */
339 * Activate the NMI watchdog via the local APIC.
340 * Original code written by Keith Owens.
343 static void clear_msr_range(unsigned int base
, unsigned int n
)
347 for(i
= 0; i
< n
; ++i
)
351 static void setup_k7_watchdog(void)
354 unsigned int evntsel
;
356 nmi_perfctr_msr
= MSR_K7_PERFCTR0
;
358 for(i
= 0; i
< 4; ++i
) {
359 /* Simulator may not support it */
360 if (checking_wrmsrl(MSR_K7_EVNTSEL0
+i
, 0UL)) {
364 wrmsrl(MSR_K7_PERFCTR0
+i
, 0UL);
367 evntsel
= K7_EVNTSEL_INT
372 wrmsr(MSR_K7_EVNTSEL0
, evntsel
, 0);
373 wrmsrl(MSR_K7_PERFCTR0
, -((u64
)cpu_khz
* 1000 / nmi_hz
));
374 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
375 evntsel
|= K7_EVNTSEL_ENABLE
;
376 wrmsr(MSR_K7_EVNTSEL0
, evntsel
, 0);
380 static int setup_p4_watchdog(void)
382 unsigned int misc_enable
, dummy
;
384 rdmsr(MSR_P4_MISC_ENABLE
, misc_enable
, dummy
);
385 if (!(misc_enable
& MSR_P4_MISC_ENABLE_PERF_AVAIL
))
388 nmi_perfctr_msr
= MSR_P4_IQ_COUNTER0
;
389 nmi_p4_cccr_val
= P4_NMI_IQ_CCCR0
;
391 if (smp_num_siblings
== 2)
392 nmi_p4_cccr_val
|= P4_CCCR_OVF_PMI1
;
395 if (!(misc_enable
& MSR_P4_MISC_ENABLE_PEBS_UNAVAIL
))
396 clear_msr_range(0x3F1, 2);
397 /* MSR 0x3F0 seems to have a default value of 0xFC00, but current
398 docs doesn't fully define it, so leave it alone for now. */
399 if (boot_cpu_data
.x86_model
>= 0x3) {
400 /* MSR_P4_IQ_ESCR0/1 (0x3ba/0x3bb) removed */
401 clear_msr_range(0x3A0, 26);
402 clear_msr_range(0x3BC, 3);
404 clear_msr_range(0x3A0, 31);
406 clear_msr_range(0x3C0, 6);
407 clear_msr_range(0x3C8, 6);
408 clear_msr_range(0x3E0, 2);
409 clear_msr_range(MSR_P4_CCCR0
, 18);
410 clear_msr_range(MSR_P4_PERFCTR0
, 18);
412 wrmsr(MSR_P4_CRU_ESCR0
, P4_NMI_CRU_ESCR0
, 0);
413 wrmsr(MSR_P4_IQ_CCCR0
, P4_NMI_IQ_CCCR0
& ~P4_CCCR_ENABLE
, 0);
414 Dprintk("setting P4_IQ_COUNTER0 to 0x%08lx\n", -(cpu_khz
* 1000UL / nmi_hz
));
415 wrmsrl(MSR_P4_IQ_COUNTER0
, -((u64
)cpu_khz
* 1000 / nmi_hz
));
416 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
417 wrmsr(MSR_P4_IQ_CCCR0
, nmi_p4_cccr_val
, 0);
421 void setup_apic_nmi_watchdog(void)
423 switch (boot_cpu_data
.x86_vendor
) {
425 if (boot_cpu_data
.x86
!= 15)
427 if (strstr(boot_cpu_data
.x86_model_id
, "Screwdriver"))
431 case X86_VENDOR_INTEL
:
432 if (boot_cpu_data
.x86
!= 15)
434 if (!setup_p4_watchdog())
441 lapic_nmi_owner
= LAPIC_NMI_WATCHDOG
;
446 * the best way to detect whether a CPU has a 'hard lockup' problem
447 * is to check it's local APIC timer IRQ counts. If they are not
448 * changing then that CPU has some problem.
450 * as these watchdog NMI IRQs are generated on every CPU, we only
451 * have to check the current processor.
454 static DEFINE_PER_CPU(unsigned, last_irq_sum
);
455 static DEFINE_PER_CPU(local_t
, alert_counter
);
456 static DEFINE_PER_CPU(int, nmi_touch
);
458 void touch_nmi_watchdog (void)
460 if (nmi_watchdog
> 0) {
464 * Tell other CPUs to reset their alert counters. We cannot
465 * do it ourselves because the alert count increase is not
468 for_each_present_cpu (cpu
)
469 per_cpu(nmi_touch
, cpu
) = 1;
472 touch_softlockup_watchdog();
475 void __kprobes
nmi_watchdog_tick(struct pt_regs
* regs
, unsigned reason
)
480 sum
= read_pda(apic_timer_irqs
);
481 if (__get_cpu_var(nmi_touch
)) {
482 __get_cpu_var(nmi_touch
) = 0;
485 if (!touched
&& __get_cpu_var(last_irq_sum
) == sum
) {
487 * Ayiee, looks like this CPU is stuck ...
488 * wait a few IRQs (5 seconds) before doing the oops ...
490 local_inc(&__get_cpu_var(alert_counter
));
491 if (local_read(&__get_cpu_var(alert_counter
)) == 5*nmi_hz
) {
492 if (notify_die(DIE_NMI
, "nmi", regs
, reason
, 2, SIGINT
)
494 local_set(&__get_cpu_var(alert_counter
), 0);
497 die_nmi("NMI Watchdog detected LOCKUP on CPU %d\n", regs
);
500 __get_cpu_var(last_irq_sum
) = sum
;
501 local_set(&__get_cpu_var(alert_counter
), 0);
503 if (nmi_perfctr_msr
) {
504 if (nmi_perfctr_msr
== MSR_P4_IQ_COUNTER0
) {
507 * - An overflown perfctr will assert its interrupt
508 * until the OVF flag in its CCCR is cleared.
509 * - LVTPC is masked on interrupt and must be
510 * unmasked by the LVTPC handler.
512 wrmsr(MSR_P4_IQ_CCCR0
, nmi_p4_cccr_val
, 0);
513 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
515 wrmsrl(nmi_perfctr_msr
, -((u64
)cpu_khz
* 1000 / nmi_hz
));
519 static __kprobes
int dummy_nmi_callback(struct pt_regs
* regs
, int cpu
)
524 static nmi_callback_t nmi_callback
= dummy_nmi_callback
;
526 asmlinkage __kprobes
void do_nmi(struct pt_regs
* regs
, long error_code
)
528 int cpu
= safe_smp_processor_id();
531 add_pda(__nmi_count
,1);
532 if (!rcu_dereference(nmi_callback
)(regs
, cpu
))
533 default_do_nmi(regs
);
537 void set_nmi_callback(nmi_callback_t callback
)
539 rcu_assign_pointer(nmi_callback
, callback
);
542 void unset_nmi_callback(void)
544 nmi_callback
= dummy_nmi_callback
;
549 static int unknown_nmi_panic_callback(struct pt_regs
*regs
, int cpu
)
551 unsigned char reason
= get_nmi_reason();
554 if (!(reason
& 0xc0)) {
555 sprintf(buf
, "NMI received for unknown reason %02x\n", reason
);
562 * proc handler for /proc/sys/kernel/unknown_nmi_panic
564 int proc_unknown_nmi_panic(struct ctl_table
*table
, int write
, struct file
*file
,
565 void __user
*buffer
, size_t *length
, loff_t
*ppos
)
569 old_state
= unknown_nmi_panic
;
570 proc_dointvec(table
, write
, file
, buffer
, length
, ppos
);
571 if (!!old_state
== !!unknown_nmi_panic
)
574 if (unknown_nmi_panic
) {
575 if (reserve_lapic_nmi() < 0) {
576 unknown_nmi_panic
= 0;
579 set_nmi_callback(unknown_nmi_panic_callback
);
583 unset_nmi_callback();
590 EXPORT_SYMBOL(nmi_active
);
591 EXPORT_SYMBOL(nmi_watchdog
);
592 EXPORT_SYMBOL(reserve_lapic_nmi
);
593 EXPORT_SYMBOL(release_lapic_nmi
);
594 EXPORT_SYMBOL(disable_timer_nmi_watchdog
);
595 EXPORT_SYMBOL(enable_timer_nmi_watchdog
);
596 EXPORT_SYMBOL(touch_nmi_watchdog
);