2 * Port for PPC64 David Engebretsen, IBM Corp.
3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6 * Rework, based on alpha PCI code.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/string.h>
19 #include <linux/init.h>
20 #include <linux/bootmem.h>
22 #include <linux/list.h>
23 #include <linux/syscalls.h>
24 #include <linux/irq.h>
25 #include <linux/vmalloc.h>
27 #include <asm/processor.h>
30 #include <asm/pci-bridge.h>
31 #include <asm/byteorder.h>
32 #include <asm/machdep.h>
33 #include <asm/ppc-pci.h>
37 #define DBG(fmt...) printk(fmt)
42 unsigned long pci_probe_only
= 1;
43 int pci_assign_all_buses
= 0;
45 static void fixup_resource(struct resource
*res
, struct pci_dev
*dev
);
46 static void do_bus_setup(struct pci_bus
*bus
);
48 /* pci_io_base -- the base address from which io bars are offsets.
49 * This is the lowest I/O base address (so bar values are always positive),
50 * and it *must* be the start of ISA space if an ISA bus exists because
51 * ISA drivers use hard coded offsets. If no ISA bus exists nothing
52 * is mapped on the first 64K of IO space
54 unsigned long pci_io_base
= ISA_IO_BASE
;
55 EXPORT_SYMBOL(pci_io_base
);
59 static struct dma_mapping_ops
*pci_dma_ops
;
61 void set_pci_dma_ops(struct dma_mapping_ops
*dma_ops
)
63 pci_dma_ops
= dma_ops
;
66 struct dma_mapping_ops
*get_pci_dma_ops(void)
70 EXPORT_SYMBOL(get_pci_dma_ops
);
72 static void fixup_broken_pcnet32(struct pci_dev
* dev
)
74 if ((dev
->class>>8 == PCI_CLASS_NETWORK_ETHERNET
)) {
75 dev
->vendor
= PCI_VENDOR_ID_AMD
;
76 pci_write_config_word(dev
, PCI_VENDOR_ID
, PCI_VENDOR_ID_AMD
);
79 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT
, PCI_ANY_ID
, fixup_broken_pcnet32
);
81 void pcibios_resource_to_bus(struct pci_dev
*dev
, struct pci_bus_region
*region
,
84 unsigned long offset
= 0;
85 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
90 if (res
->flags
& IORESOURCE_IO
)
91 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
93 if (res
->flags
& IORESOURCE_MEM
)
94 offset
= hose
->pci_mem_offset
;
96 region
->start
= res
->start
- offset
;
97 region
->end
= res
->end
- offset
;
100 void pcibios_bus_to_resource(struct pci_dev
*dev
, struct resource
*res
,
101 struct pci_bus_region
*region
)
103 unsigned long offset
= 0;
104 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
109 if (res
->flags
& IORESOURCE_IO
)
110 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
112 if (res
->flags
& IORESOURCE_MEM
)
113 offset
= hose
->pci_mem_offset
;
115 res
->start
= region
->start
+ offset
;
116 res
->end
= region
->end
+ offset
;
119 #ifdef CONFIG_HOTPLUG
120 EXPORT_SYMBOL(pcibios_resource_to_bus
);
121 EXPORT_SYMBOL(pcibios_bus_to_resource
);
125 * We need to avoid collisions with `mirrored' VGA ports
126 * and other strange ISA hardware, so we always want the
127 * addresses to be allocated in the 0x000-0x0ff region
130 * Why? Because some silly external IO cards only decode
131 * the low 10 bits of the IO address. The 0x00-0xff region
132 * is reserved for motherboard devices that decode all 16
133 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
134 * but we want to try to avoid allocating at 0x2900-0x2bff
135 * which might have be mirrored at 0x0100-0x03ff..
137 void pcibios_align_resource(void *data
, struct resource
*res
,
138 resource_size_t size
, resource_size_t align
)
140 struct pci_dev
*dev
= data
;
141 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
142 resource_size_t start
= res
->start
;
143 unsigned long alignto
;
145 if (res
->flags
& IORESOURCE_IO
) {
146 unsigned long offset
= (unsigned long)hose
->io_base_virt
-
148 /* Make sure we start at our min on all hoses */
149 if (start
- offset
< PCIBIOS_MIN_IO
)
150 start
= PCIBIOS_MIN_IO
+ offset
;
153 * Put everything into 0x00-0xff region modulo 0x400
156 start
= (start
+ 0x3ff) & ~0x3ff;
158 } else if (res
->flags
& IORESOURCE_MEM
) {
159 /* Make sure we start at our min on all hoses */
160 if (start
- hose
->pci_mem_offset
< PCIBIOS_MIN_MEM
)
161 start
= PCIBIOS_MIN_MEM
+ hose
->pci_mem_offset
;
163 /* Align to multiple of size of minimum base. */
164 alignto
= max(0x1000UL
, align
);
165 start
= ALIGN(start
, alignto
);
171 void __devinit
pcibios_claim_one_bus(struct pci_bus
*b
)
174 struct pci_bus
*child_bus
;
176 list_for_each_entry(dev
, &b
->devices
, bus_list
) {
179 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
180 struct resource
*r
= &dev
->resource
[i
];
182 if (r
->parent
|| !r
->start
|| !r
->flags
)
184 pci_claim_resource(dev
, i
);
188 list_for_each_entry(child_bus
, &b
->children
, node
)
189 pcibios_claim_one_bus(child_bus
);
191 #ifdef CONFIG_HOTPLUG
192 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus
);
195 static void __init
pcibios_claim_of_setup(void)
199 list_for_each_entry(b
, &pci_root_buses
, node
)
200 pcibios_claim_one_bus(b
);
203 static u32
get_int_prop(struct device_node
*np
, const char *name
, u32 def
)
208 prop
= of_get_property(np
, name
, &len
);
209 if (prop
&& len
>= 4)
214 static unsigned int pci_parse_of_flags(u32 addr0
)
216 unsigned int flags
= 0;
218 if (addr0
& 0x02000000) {
219 flags
= IORESOURCE_MEM
| PCI_BASE_ADDRESS_SPACE_MEMORY
;
220 flags
|= (addr0
>> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64
;
221 flags
|= (addr0
>> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M
;
222 if (addr0
& 0x40000000)
223 flags
|= IORESOURCE_PREFETCH
224 | PCI_BASE_ADDRESS_MEM_PREFETCH
;
225 } else if (addr0
& 0x01000000)
226 flags
= IORESOURCE_IO
| PCI_BASE_ADDRESS_SPACE_IO
;
231 static void pci_parse_of_addrs(struct device_node
*node
, struct pci_dev
*dev
)
235 struct resource
*res
;
240 addrs
= of_get_property(node
, "assigned-addresses", &proplen
);
243 DBG(" parse addresses (%d bytes) @ %p\n", proplen
, addrs
);
244 for (; proplen
>= 20; proplen
-= 20, addrs
+= 5) {
245 flags
= pci_parse_of_flags(addrs
[0]);
248 base
= of_read_number(&addrs
[1], 2);
249 size
= of_read_number(&addrs
[3], 2);
253 DBG(" base: %llx, size: %llx, i: %x\n",
254 (unsigned long long)base
, (unsigned long long)size
, i
);
256 if (PCI_BASE_ADDRESS_0
<= i
&& i
<= PCI_BASE_ADDRESS_5
) {
257 res
= &dev
->resource
[(i
- PCI_BASE_ADDRESS_0
) >> 2];
258 } else if (i
== dev
->rom_base_reg
) {
259 res
= &dev
->resource
[PCI_ROM_RESOURCE
];
260 flags
|= IORESOURCE_READONLY
| IORESOURCE_CACHEABLE
;
262 printk(KERN_ERR
"PCI: bad cfg reg num 0x%x\n", i
);
266 res
->end
= base
+ size
- 1;
268 res
->name
= pci_name(dev
);
269 fixup_resource(res
, dev
);
273 struct pci_dev
*of_create_pci_dev(struct device_node
*node
,
274 struct pci_bus
*bus
, int devfn
)
279 dev
= alloc_pci_dev();
282 type
= of_get_property(node
, "device_type", NULL
);
286 DBG(" create device, devfn: %x, type: %s\n", devfn
, type
);
290 dev
->dev
.parent
= bus
->bridge
;
291 dev
->dev
.bus
= &pci_bus_type
;
293 dev
->multifunction
= 0; /* maybe a lie? */
295 dev
->vendor
= get_int_prop(node
, "vendor-id", 0xffff);
296 dev
->device
= get_int_prop(node
, "device-id", 0xffff);
297 dev
->subsystem_vendor
= get_int_prop(node
, "subsystem-vendor-id", 0);
298 dev
->subsystem_device
= get_int_prop(node
, "subsystem-id", 0);
300 dev
->cfg_size
= pci_cfg_space_size(dev
);
302 sprintf(pci_name(dev
), "%04x:%02x:%02x.%d", pci_domain_nr(bus
),
303 dev
->bus
->number
, PCI_SLOT(devfn
), PCI_FUNC(devfn
));
304 dev
->class = get_int_prop(node
, "class-code", 0);
305 dev
->revision
= get_int_prop(node
, "revision-id", 0);
307 DBG(" class: 0x%x\n", dev
->class);
308 DBG(" revision: 0x%x\n", dev
->revision
);
310 dev
->current_state
= 4; /* unknown power state */
311 dev
->error_state
= pci_channel_io_normal
;
312 dev
->dma_mask
= 0xffffffff;
314 if (!strcmp(type
, "pci") || !strcmp(type
, "pciex")) {
315 /* a PCI-PCI bridge */
316 dev
->hdr_type
= PCI_HEADER_TYPE_BRIDGE
;
317 dev
->rom_base_reg
= PCI_ROM_ADDRESS1
;
318 } else if (!strcmp(type
, "cardbus")) {
319 dev
->hdr_type
= PCI_HEADER_TYPE_CARDBUS
;
321 dev
->hdr_type
= PCI_HEADER_TYPE_NORMAL
;
322 dev
->rom_base_reg
= PCI_ROM_ADDRESS
;
323 /* Maybe do a default OF mapping here */
327 pci_parse_of_addrs(node
, dev
);
329 DBG(" adding to system ...\n");
331 pci_device_add(dev
, bus
);
335 EXPORT_SYMBOL(of_create_pci_dev
);
337 void __devinit
of_scan_bus(struct device_node
*node
,
340 struct device_node
*child
= NULL
;
345 DBG("of_scan_bus(%s) bus no %d... \n", node
->full_name
, bus
->number
);
347 while ((child
= of_get_next_child(node
, child
)) != NULL
) {
348 DBG(" * %s\n", child
->full_name
);
349 reg
= of_get_property(child
, "reg", ®len
);
350 if (reg
== NULL
|| reglen
< 20)
352 devfn
= (reg
[0] >> 8) & 0xff;
354 /* create a new pci_dev for this device */
355 dev
= of_create_pci_dev(child
, bus
, devfn
);
358 DBG("dev header type: %x\n", dev
->hdr_type
);
360 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
||
361 dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
)
362 of_scan_pci_bridge(child
, dev
);
367 EXPORT_SYMBOL(of_scan_bus
);
369 void __devinit
of_scan_pci_bridge(struct device_node
*node
,
373 const u32
*busrange
, *ranges
;
375 struct resource
*res
;
379 DBG("of_scan_pci_bridge(%s)\n", node
->full_name
);
381 /* parse bus-range property */
382 busrange
= of_get_property(node
, "bus-range", &len
);
383 if (busrange
== NULL
|| len
!= 8) {
384 printk(KERN_DEBUG
"Can't get bus-range for PCI-PCI bridge %s\n",
388 ranges
= of_get_property(node
, "ranges", &len
);
389 if (ranges
== NULL
) {
390 printk(KERN_DEBUG
"Can't get ranges for PCI-PCI bridge %s\n",
395 bus
= pci_add_new_bus(dev
->bus
, dev
, busrange
[0]);
397 printk(KERN_ERR
"Failed to create pci bus for %s\n",
402 bus
->primary
= dev
->bus
->number
;
403 bus
->subordinate
= busrange
[1];
407 /* parse ranges property */
408 /* PCI #address-cells == 3 and #size-cells == 2 always */
409 res
= &dev
->resource
[PCI_BRIDGE_RESOURCES
];
410 for (i
= 0; i
< PCI_NUM_RESOURCES
- PCI_BRIDGE_RESOURCES
; ++i
) {
412 bus
->resource
[i
] = res
;
416 for (; len
>= 32; len
-= 32, ranges
+= 8) {
417 flags
= pci_parse_of_flags(ranges
[0]);
418 size
= of_read_number(&ranges
[6], 2);
419 if (flags
== 0 || size
== 0)
421 if (flags
& IORESOURCE_IO
) {
422 res
= bus
->resource
[0];
424 printk(KERN_ERR
"PCI: ignoring extra I/O range"
425 " for bridge %s\n", node
->full_name
);
429 if (i
>= PCI_NUM_RESOURCES
- PCI_BRIDGE_RESOURCES
) {
430 printk(KERN_ERR
"PCI: too many memory ranges"
431 " for bridge %s\n", node
->full_name
);
434 res
= bus
->resource
[i
];
437 res
->start
= of_read_number(&ranges
[1], 2);
438 res
->end
= res
->start
+ size
- 1;
440 fixup_resource(res
, dev
);
442 sprintf(bus
->name
, "PCI Bus %04x:%02x", pci_domain_nr(bus
),
444 DBG(" bus name: %s\n", bus
->name
);
446 mode
= PCI_PROBE_NORMAL
;
447 if (ppc_md
.pci_probe_mode
)
448 mode
= ppc_md
.pci_probe_mode(bus
);
449 DBG(" probe mode: %d\n", mode
);
451 if (mode
== PCI_PROBE_DEVTREE
)
452 of_scan_bus(node
, bus
);
453 else if (mode
== PCI_PROBE_NORMAL
)
454 pci_scan_child_bus(bus
);
456 EXPORT_SYMBOL(of_scan_pci_bridge
);
458 void __devinit
scan_phb(struct pci_controller
*hose
)
461 struct device_node
*node
= hose
->dn
;
463 struct resource
*res
;
465 DBG("Scanning PHB %s\n", node
? node
->full_name
: "<NO NAME>");
467 bus
= pci_create_bus(hose
->parent
, hose
->first_busno
, hose
->ops
, node
);
469 printk(KERN_ERR
"Failed to create bus for PCI domain %04x\n",
470 hose
->global_number
);
473 bus
->secondary
= hose
->first_busno
;
476 pcibios_map_io_space(bus
);
478 bus
->resource
[0] = res
= &hose
->io_resource
;
479 if (res
->flags
&& request_resource(&ioport_resource
, res
)) {
480 printk(KERN_ERR
"Failed to request PCI IO region "
481 "on PCI domain %04x\n", hose
->global_number
);
482 DBG("res->start = 0x%016lx, res->end = 0x%016lx\n",
483 res
->start
, res
->end
);
486 for (i
= 0; i
< 3; ++i
) {
487 res
= &hose
->mem_resources
[i
];
488 bus
->resource
[i
+1] = res
;
489 if (res
->flags
&& request_resource(&iomem_resource
, res
))
490 printk(KERN_ERR
"Failed to request PCI memory region "
491 "on PCI domain %04x\n", hose
->global_number
);
494 mode
= PCI_PROBE_NORMAL
;
496 if (node
&& ppc_md
.pci_probe_mode
)
497 mode
= ppc_md
.pci_probe_mode(bus
);
498 DBG(" probe mode: %d\n", mode
);
499 if (mode
== PCI_PROBE_DEVTREE
) {
500 bus
->subordinate
= hose
->last_busno
;
501 of_scan_bus(node
, bus
);
504 if (mode
== PCI_PROBE_NORMAL
)
505 hose
->last_busno
= bus
->subordinate
= pci_scan_child_bus(bus
);
508 static int __init
pcibios_init(void)
510 struct pci_controller
*hose
, *tmp
;
512 /* For now, override phys_mem_access_prot. If we need it,
513 * later, we may move that initialization to each ppc_md
515 ppc_md
.phys_mem_access_prot
= pci_phys_mem_access_prot
;
517 printk(KERN_DEBUG
"PCI: Probing PCI hardware\n");
519 /* Scan all of the recorded PCI controllers. */
520 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
522 pci_bus_add_devices(hose
->bus
);
526 pcibios_claim_of_setup();
528 /* FIXME: `else' will be removed when
529 pci_assign_unassigned_resources() is able to work
530 correctly with [partially] allocated PCI tree. */
531 pci_assign_unassigned_resources();
533 /* Call machine dependent final fixup */
534 if (ppc_md
.pcibios_fixup
)
535 ppc_md
.pcibios_fixup();
537 printk(KERN_DEBUG
"PCI: Probing PCI hardware done\n");
542 subsys_initcall(pcibios_init
);
544 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
549 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
552 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
553 struct resource
*res
= &dev
->resource
[i
];
555 /* Only set up the requested stuff */
556 if (!(mask
& (1<<i
)))
559 if (res
->flags
& IORESOURCE_IO
)
560 cmd
|= PCI_COMMAND_IO
;
561 if (res
->flags
& IORESOURCE_MEM
)
562 cmd
|= PCI_COMMAND_MEMORY
;
566 printk(KERN_DEBUG
"PCI: Enabling device: (%s), cmd %x\n",
568 /* Enable the appropriate bits in the PCI command register. */
569 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
574 /* Decide whether to display the domain number in /proc */
575 int pci_proc_domain(struct pci_bus
*bus
)
577 struct pci_controller
*hose
= pci_bus_to_host(bus
);
578 return hose
->buid
!= 0;
581 void __devinit
pci_process_bridge_OF_ranges(struct pci_controller
*hose
,
582 struct device_node
*dev
, int prim
)
584 const unsigned int *ranges
;
585 unsigned int pci_space
;
589 struct resource
*res
;
590 int np
, na
= of_n_addr_cells(dev
);
591 unsigned long pci_addr
, cpu_phys_addr
;
595 /* From "PCI Binding to 1275"
596 * The ranges property is laid out as an array of elements,
597 * each of which comprises:
598 * cells 0 - 2: a PCI address
599 * cells 3 or 3+4: a CPU physical address
600 * (size depending on dev->n_addr_cells)
601 * cells 4+5 or 5+6: the size of the range
603 ranges
= of_get_property(dev
, "ranges", &rlen
);
606 hose
->io_base_phys
= 0;
607 while ((rlen
-= np
* sizeof(unsigned int)) >= 0) {
609 pci_space
= ranges
[0];
610 pci_addr
= ((unsigned long)ranges
[1] << 32) | ranges
[2];
611 cpu_phys_addr
= of_translate_address(dev
, &ranges
[3]);
612 size
= ((unsigned long)ranges
[na
+3] << 32) | ranges
[na
+4];
617 /* Now consume following elements while they are contiguous */
618 while (rlen
>= np
* sizeof(unsigned int)) {
619 unsigned long addr
, phys
;
621 if (ranges
[0] != pci_space
)
623 addr
= ((unsigned long)ranges
[1] << 32) | ranges
[2];
626 phys
= (phys
<< 32) | ranges
[4];
627 if (addr
!= pci_addr
+ size
||
628 phys
!= cpu_phys_addr
+ size
)
631 size
+= ((unsigned long)ranges
[na
+3] << 32)
634 rlen
-= np
* sizeof(unsigned int);
637 switch ((pci_space
>> 24) & 0x3) {
638 case 1: /* I/O space */
639 hose
->io_base_phys
= cpu_phys_addr
- pci_addr
;
640 /* handle from 0 to top of I/O window */
641 hose
->pci_io_size
= pci_addr
+ size
;
643 res
= &hose
->io_resource
;
644 res
->flags
= IORESOURCE_IO
;
645 res
->start
= pci_addr
;
646 DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose
->global_number
,
647 res
->start
, res
->start
+ size
- 1);
649 case 2: /* memory space */
651 while (memno
< 3 && hose
->mem_resources
[memno
].flags
)
655 hose
->pci_mem_offset
= cpu_phys_addr
- pci_addr
;
657 res
= &hose
->mem_resources
[memno
];
658 res
->flags
= IORESOURCE_MEM
;
659 res
->start
= cpu_phys_addr
;
660 DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose
->global_number
,
661 res
->start
, res
->start
+ size
- 1);
666 res
->name
= dev
->full_name
;
667 res
->end
= res
->start
+ size
- 1;
675 #ifdef CONFIG_HOTPLUG
677 int pcibios_unmap_io_space(struct pci_bus
*bus
)
679 struct pci_controller
*hose
;
681 WARN_ON(bus
== NULL
);
683 /* If this is not a PHB, we only flush the hash table over
684 * the area mapped by this bridge. We don't play with the PTE
685 * mappings since we might have to deal with sub-page alignemnts
686 * so flushing the hash table is the only sane way to make sure
687 * that no hash entries are covering that removed bridge area
688 * while still allowing other busses overlapping those pages
691 struct resource
*res
= bus
->resource
[0];
693 DBG("IO unmapping for PCI-PCI bridge %s\n",
694 pci_name(bus
->self
));
696 __flush_hash_table_range(&init_mm
, res
->start
+ _IO_BASE
,
697 res
->end
- res
->start
+ 1);
701 /* Get the host bridge */
702 hose
= pci_bus_to_host(bus
);
704 /* Check if we have IOs allocated */
705 if (hose
->io_base_alloc
== 0)
708 DBG("IO unmapping for PHB %s\n", hose
->dn
->full_name
);
709 DBG(" alloc=0x%p\n", hose
->io_base_alloc
);
711 /* This is a PHB, we fully unmap the IO area */
712 vunmap(hose
->io_base_alloc
);
716 EXPORT_SYMBOL_GPL(pcibios_unmap_io_space
);
718 #endif /* CONFIG_HOTPLUG */
720 int __devinit
pcibios_map_io_space(struct pci_bus
*bus
)
722 struct vm_struct
*area
;
723 unsigned long phys_page
;
724 unsigned long size_page
;
725 unsigned long io_virt_offset
;
726 struct pci_controller
*hose
;
728 WARN_ON(bus
== NULL
);
730 /* If this not a PHB, nothing to do, page tables still exist and
731 * thus HPTEs will be faulted in when needed
734 DBG("IO mapping for PCI-PCI bridge %s\n",
735 pci_name(bus
->self
));
736 DBG(" virt=0x%016lx...0x%016lx\n",
737 bus
->resource
[0]->start
+ _IO_BASE
,
738 bus
->resource
[0]->end
+ _IO_BASE
);
742 /* Get the host bridge */
743 hose
= pci_bus_to_host(bus
);
744 phys_page
= _ALIGN_DOWN(hose
->io_base_phys
, PAGE_SIZE
);
745 size_page
= _ALIGN_UP(hose
->pci_io_size
, PAGE_SIZE
);
747 /* Make sure IO area address is clear */
748 hose
->io_base_alloc
= NULL
;
750 /* If there's no IO to map on that bus, get away too */
751 if (hose
->pci_io_size
== 0 || hose
->io_base_phys
== 0)
754 /* Let's allocate some IO space for that guy. We don't pass
755 * VM_IOREMAP because we don't care about alignment tricks that
756 * the core does in that case. Maybe we should due to stupid card
757 * with incomplete address decoding but I'd rather not deal with
758 * those outside of the reserved 64K legacy region.
760 area
= __get_vm_area(size_page
, 0, PHB_IO_BASE
, PHB_IO_END
);
763 hose
->io_base_alloc
= area
->addr
;
764 hose
->io_base_virt
= (void __iomem
*)(area
->addr
+
765 hose
->io_base_phys
- phys_page
);
767 DBG("IO mapping for PHB %s\n", hose
->dn
->full_name
);
768 DBG(" phys=0x%016lx, virt=0x%p (alloc=0x%p)\n",
769 hose
->io_base_phys
, hose
->io_base_virt
, hose
->io_base_alloc
);
770 DBG(" size=0x%016lx (alloc=0x%016lx)\n",
771 hose
->pci_io_size
, size_page
);
773 /* Establish the mapping */
774 if (__ioremap_at(phys_page
, area
->addr
, size_page
,
775 _PAGE_NO_CACHE
| _PAGE_GUARDED
) == NULL
)
778 /* Fixup hose IO resource */
779 io_virt_offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
780 hose
->io_resource
.start
+= io_virt_offset
;
781 hose
->io_resource
.end
+= io_virt_offset
;
783 DBG(" hose->io_resource=0x%016lx...0x%016lx\n",
784 hose
->io_resource
.start
, hose
->io_resource
.end
);
788 EXPORT_SYMBOL_GPL(pcibios_map_io_space
);
790 static void __devinit
fixup_resource(struct resource
*res
, struct pci_dev
*dev
)
792 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
793 unsigned long offset
;
795 if (res
->flags
& IORESOURCE_IO
) {
796 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
797 res
->start
+= offset
;
799 } else if (res
->flags
& IORESOURCE_MEM
) {
800 res
->start
+= hose
->pci_mem_offset
;
801 res
->end
+= hose
->pci_mem_offset
;
805 void __devinit
pcibios_fixup_device_resources(struct pci_dev
*dev
,
808 /* Update device resources. */
811 DBG("%s: Fixup resources:\n", pci_name(dev
));
812 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
813 struct resource
*res
= &dev
->resource
[i
];
817 DBG(" 0x%02x < %08lx:0x%016lx...0x%016lx\n",
818 i
, res
->flags
, res
->start
, res
->end
);
820 fixup_resource(res
, dev
);
822 DBG(" > %08lx:0x%016lx...0x%016lx\n",
823 res
->flags
, res
->start
, res
->end
);
826 EXPORT_SYMBOL(pcibios_fixup_device_resources
);
828 void __devinit
pcibios_setup_new_device(struct pci_dev
*dev
)
830 struct dev_archdata
*sd
= &dev
->dev
.archdata
;
832 sd
->of_node
= pci_device_to_OF_node(dev
);
834 DBG("PCI device %s OF node: %s\n", pci_name(dev
),
835 sd
->of_node
? sd
->of_node
->full_name
: "<none>");
837 sd
->dma_ops
= pci_dma_ops
;
839 sd
->numa_node
= pcibus_to_node(dev
->bus
);
843 if (ppc_md
.pci_dma_dev_setup
)
844 ppc_md
.pci_dma_dev_setup(dev
);
846 EXPORT_SYMBOL(pcibios_setup_new_device
);
848 static void __devinit
do_bus_setup(struct pci_bus
*bus
)
852 if (ppc_md
.pci_dma_bus_setup
)
853 ppc_md
.pci_dma_bus_setup(bus
);
855 list_for_each_entry(dev
, &bus
->devices
, bus_list
)
856 pcibios_setup_new_device(dev
);
858 /* Read default IRQs and fixup if necessary */
859 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
860 pci_read_irq_line(dev
);
861 if (ppc_md
.pci_irq_fixup
)
862 ppc_md
.pci_irq_fixup(dev
);
866 void __devinit
pcibios_fixup_bus(struct pci_bus
*bus
)
868 struct pci_dev
*dev
= bus
->self
;
869 struct device_node
*np
;
871 np
= pci_bus_to_OF_node(bus
);
873 DBG("pcibios_fixup_bus(%s)\n", np
? np
->full_name
: "<???>");
875 if (dev
&& pci_probe_only
&&
876 (dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
) {
877 /* This is a subordinate bridge */
879 pci_read_bridge_bases(bus
);
880 pcibios_fixup_device_resources(dev
, bus
);
888 list_for_each_entry(dev
, &bus
->devices
, bus_list
)
889 if ((dev
->class >> 8) != PCI_CLASS_BRIDGE_PCI
)
890 pcibios_fixup_device_resources(dev
, bus
);
892 EXPORT_SYMBOL(pcibios_fixup_bus
);
894 unsigned long pci_address_to_pio(phys_addr_t address
)
896 struct pci_controller
*hose
, *tmp
;
898 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
899 if (address
>= hose
->io_base_phys
&&
900 address
< (hose
->io_base_phys
+ hose
->pci_io_size
)) {
902 (unsigned long)hose
->io_base_virt
- _IO_BASE
;
903 return base
+ (address
- hose
->io_base_phys
);
906 return (unsigned int)-1;
908 EXPORT_SYMBOL_GPL(pci_address_to_pio
);
911 #define IOBASE_BRIDGE_NUMBER 0
912 #define IOBASE_MEMORY 1
914 #define IOBASE_ISA_IO 3
915 #define IOBASE_ISA_MEM 4
917 long sys_pciconfig_iobase(long which
, unsigned long in_bus
,
918 unsigned long in_devfn
)
920 struct pci_controller
* hose
;
921 struct list_head
*ln
;
922 struct pci_bus
*bus
= NULL
;
923 struct device_node
*hose_node
;
925 /* Argh ! Please forgive me for that hack, but that's the
926 * simplest way to get existing XFree to not lockup on some
927 * G5 machines... So when something asks for bus 0 io base
928 * (bus 0 is HT root), we return the AGP one instead.
930 if (machine_is_compatible("MacRISC4"))
934 /* That syscall isn't quite compatible with PCI domains, but it's
935 * used on pre-domains setup. We return the first match
938 for (ln
= pci_root_buses
.next
; ln
!= &pci_root_buses
; ln
= ln
->next
) {
940 if (in_bus
>= bus
->number
&& in_bus
<= bus
->subordinate
)
944 if (bus
== NULL
|| bus
->sysdata
== NULL
)
947 hose_node
= (struct device_node
*)bus
->sysdata
;
948 hose
= PCI_DN(hose_node
)->phb
;
951 case IOBASE_BRIDGE_NUMBER
:
952 return (long)hose
->first_busno
;
954 return (long)hose
->pci_mem_offset
;
956 return (long)hose
->io_base_phys
;
958 return (long)isa_io_base
;
967 int pcibus_to_node(struct pci_bus
*bus
)
969 struct pci_controller
*phb
= pci_bus_to_host(bus
);
972 EXPORT_SYMBOL(pcibus_to_node
);