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[PATCH] w1: Make w1 connector notifications depend on connector.
[linux-2.6/verdex.git] / drivers / pci / hotplug / pciehp_hpc.c
blobd77138ecb0981ec827a6d482d96f31eb6c5acc43
1 /*
2 * PCI Express PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
27 *
28 */
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/signal.h>
34 #include <linux/jiffies.h>
35 #include <linux/timer.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
38
39 #include "../pci.h"
40 #include "pciehp.h"
41 #include <acpi/acpi.h>
42 #include <acpi/acpi_bus.h>
43 #include <acpi/actypes.h>
44 #include <linux/pci-acpi.h>
45 #ifdef DEBUG
46 #define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */
47 #define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */
48 #define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */
49 #define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */
50 #define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT)
51 #define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE)
52 /* Redefine this flagword to set debug level */
53 #define DEBUG_LEVEL DBG_K_STANDARD
54
55 #define DEFINE_DBG_BUFFER char __dbg_str_buf[256];
56
57 #define DBG_PRINT( dbg_flags, args... ) \
58 do { \
59 if ( DEBUG_LEVEL & ( dbg_flags ) ) \
60 { \
61 int len; \
62 len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \
63 __FILE__, __LINE__, __FUNCTION__ ); \
64 sprintf( __dbg_str_buf + len, args ); \
65 printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \
66 } \
67 } while (0)
68
69 #define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]");
70 #define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]");
71 #else
72 #define DEFINE_DBG_BUFFER
73 #define DBG_ENTER_ROUTINE
74 #define DBG_LEAVE_ROUTINE
75 #endif /* DEBUG */
76
77 struct ctrl_reg {
78 u8 cap_id;
79 u8 nxt_ptr;
80 u16 cap_reg;
81 u32 dev_cap;
82 u16 dev_ctrl;
83 u16 dev_status;
84 u32 lnk_cap;
85 u16 lnk_ctrl;
86 u16 lnk_status;
87 u32 slot_cap;
88 u16 slot_ctrl;
89 u16 slot_status;
90 u16 root_ctrl;
91 u16 rsvp;
92 u32 root_status;
93 } __attribute__ ((packed));
94
95 /* offsets to the controller registers based on the above structure layout */
96 enum ctrl_offsets {
97 PCIECAPID = offsetof(struct ctrl_reg, cap_id),
98 NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr),
99 CAPREG = offsetof(struct ctrl_reg, cap_reg),
100 DEVCAP = offsetof(struct ctrl_reg, dev_cap),
101 DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl),
102 DEVSTATUS = offsetof(struct ctrl_reg, dev_status),
103 LNKCAP = offsetof(struct ctrl_reg, lnk_cap),
104 LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl),
105 LNKSTATUS = offsetof(struct ctrl_reg, lnk_status),
106 SLOTCAP = offsetof(struct ctrl_reg, slot_cap),
107 SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl),
108 SLOTSTATUS = offsetof(struct ctrl_reg, slot_status),
109 ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl),
110 ROOTSTATUS = offsetof(struct ctrl_reg, root_status),
111 };
112 static int pcie_cap_base = 0; /* Base of the PCI Express capability item structure */
113
114 #define PCIE_CAP_ID(cb) ( cb + PCIECAPID )
115 #define NXT_CAP_PTR(cb) ( cb + NXTCAPPTR )
116 #define CAP_REG(cb) ( cb + CAPREG )
117 #define DEV_CAP(cb) ( cb + DEVCAP )
118 #define DEV_CTRL(cb) ( cb + DEVCTRL )
119 #define DEV_STATUS(cb) ( cb + DEVSTATUS )
120 #define LNK_CAP(cb) ( cb + LNKCAP )
121 #define LNK_CTRL(cb) ( cb + LNKCTRL )
122 #define LNK_STATUS(cb) ( cb + LNKSTATUS )
123 #define SLOT_CAP(cb) ( cb + SLOTCAP )
124 #define SLOT_CTRL(cb) ( cb + SLOTCTRL )
125 #define SLOT_STATUS(cb) ( cb + SLOTSTATUS )
126 #define ROOT_CTRL(cb) ( cb + ROOTCTRL )
127 #define ROOT_STATUS(cb) ( cb + ROOTSTATUS )
128
129 #define hp_register_read_word(pdev, reg , value) \
130 pci_read_config_word(pdev, reg, &value)
131
132 #define hp_register_read_dword(pdev, reg , value) \
133 pci_read_config_dword(pdev, reg, &value)
134
135 #define hp_register_write_word(pdev, reg , value) \
136 pci_write_config_word(pdev, reg, value)
137
138 #define hp_register_dwrite_word(pdev, reg , value) \
139 pci_write_config_dword(pdev, reg, value)
140
141 /* Field definitions in PCI Express Capabilities Register */
142 #define CAP_VER 0x000F
143 #define DEV_PORT_TYPE 0x00F0
144 #define SLOT_IMPL 0x0100
145 #define MSG_NUM 0x3E00
146
147 /* Device or Port Type */
148 #define NAT_ENDPT 0x00
149 #define LEG_ENDPT 0x01
150 #define ROOT_PORT 0x04
151 #define UP_STREAM 0x05
152 #define DN_STREAM 0x06
153 #define PCIE_PCI_BRDG 0x07
154 #define PCI_PCIE_BRDG 0x10
155
156 /* Field definitions in Device Capabilities Register */
157 #define DATTN_BUTTN_PRSN 0x1000
158 #define DATTN_LED_PRSN 0x2000
159 #define DPWR_LED_PRSN 0x4000
160
161 /* Field definitions in Link Capabilities Register */
162 #define MAX_LNK_SPEED 0x000F
163 #define MAX_LNK_WIDTH 0x03F0
164
165 /* Link Width Encoding */
166 #define LNK_X1 0x01
167 #define LNK_X2 0x02
168 #define LNK_X4 0x04
169 #define LNK_X8 0x08
170 #define LNK_X12 0x0C
171 #define LNK_X16 0x10
172 #define LNK_X32 0x20
173
174 /*Field definitions of Link Status Register */
175 #define LNK_SPEED 0x000F
176 #define NEG_LINK_WD 0x03F0
177 #define LNK_TRN_ERR 0x0400
178 #define LNK_TRN 0x0800
179 #define SLOT_CLK_CONF 0x1000
180
181 /* Field definitions in Slot Capabilities Register */
182 #define ATTN_BUTTN_PRSN 0x00000001
183 #define PWR_CTRL_PRSN 0x00000002
184 #define MRL_SENS_PRSN 0x00000004
185 #define ATTN_LED_PRSN 0x00000008
186 #define PWR_LED_PRSN 0x00000010
187 #define HP_SUPR_RM_SUP 0x00000020
188 #define HP_CAP 0x00000040
189 #define SLOT_PWR_VALUE 0x000003F8
190 #define SLOT_PWR_LIMIT 0x00000C00
191 #define PSN 0xFFF80000 /* PSN: Physical Slot Number */
192
193 /* Field definitions in Slot Control Register */
194 #define ATTN_BUTTN_ENABLE 0x0001
195 #define PWR_FAULT_DETECT_ENABLE 0x0002
196 #define MRL_DETECT_ENABLE 0x0004
197 #define PRSN_DETECT_ENABLE 0x0008
198 #define CMD_CMPL_INTR_ENABLE 0x0010
199 #define HP_INTR_ENABLE 0x0020
200 #define ATTN_LED_CTRL 0x00C0
201 #define PWR_LED_CTRL 0x0300
202 #define PWR_CTRL 0x0400
203
204 /* Attention indicator and Power indicator states */
205 #define LED_ON 0x01
206 #define LED_BLINK 0x10
207 #define LED_OFF 0x11
208
209 /* Power Control Command */
210 #define POWER_ON 0
211 #define POWER_OFF 0x0400
212
213 /* Field definitions in Slot Status Register */
214 #define ATTN_BUTTN_PRESSED 0x0001
215 #define PWR_FAULT_DETECTED 0x0002
216 #define MRL_SENS_CHANGED 0x0004
217 #define PRSN_DETECT_CHANGED 0x0008
218 #define CMD_COMPLETED 0x0010
219 #define MRL_STATE 0x0020
220 #define PRSN_STATE 0x0040
221
222 static spinlock_t hpc_event_lock;
223
224 DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */
225 static struct php_ctlr_state_s *php_ctlr_list_head; /* HPC state linked list */
226 static int ctlr_seq_num = 0; /* Controller sequence # */
227 static spinlock_t list_lock;
228
229 static irqreturn_t pcie_isr(int IRQ, void *dev_id, struct pt_regs *regs);
230
231 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds);
232
233 /* This is the interrupt polling timeout function. */
234 static void int_poll_timeout(unsigned long lphp_ctlr)
235 {
236 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *)lphp_ctlr;
237
238 DBG_ENTER_ROUTINE
239
240 if ( !php_ctlr ) {
241 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
242 return;
243 }
244
245 /* Poll for interrupt events. regs == NULL => polling */
246 pcie_isr( 0, (void *)php_ctlr, NULL );
247
248 init_timer(&php_ctlr->int_poll_timer);
249
250 if (!pciehp_poll_time)
251 pciehp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/
252
253 start_int_poll_timer(php_ctlr, pciehp_poll_time);
254
255 return;
256 }
257
258 /* This function starts the interrupt polling timer. */
259 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds)
260 {
261 if (!php_ctlr) {
262 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
263 return;
264 }
265
266 if ( ( seconds <= 0 ) || ( seconds > 60 ) )
267 seconds = 2; /* Clamp to sane value */
268
269 php_ctlr->int_poll_timer.function = &int_poll_timeout;
270 php_ctlr->int_poll_timer.data = (unsigned long)php_ctlr; /* Instance data */
271 php_ctlr->int_poll_timer.expires = jiffies + seconds * HZ;
272 add_timer(&php_ctlr->int_poll_timer);
273
274 return;
275 }
276
277 static int pcie_write_cmd(struct slot *slot, u16 cmd)
278 {
279 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
280 int retval = 0;
281 u16 slot_status;
282
283 DBG_ENTER_ROUTINE
284
285 if (!php_ctlr) {
286 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
287 return -1;
288 }
289
290 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status);
291 if (retval) {
292 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
293 return retval;
294 }
295
296 if ((slot_status & CMD_COMPLETED) == CMD_COMPLETED ) {
297 /* After 1 sec and CMD_COMPLETED still not set, just proceed forward to issue
298 the next command according to spec. Just print out the error message */
299 dbg("%s : CMD_COMPLETED not clear after 1 sec.\n", __FUNCTION__);
300 }
301
302 retval = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), cmd | CMD_CMPL_INTR_ENABLE);
303 if (retval) {
304 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
305 return retval;
306 }
307
308 DBG_LEAVE_ROUTINE
309 return retval;
310 }
311
312 static int hpc_check_lnk_status(struct controller *ctrl)
313 {
314 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
315 u16 lnk_status;
316 int retval = 0;
317
318 DBG_ENTER_ROUTINE
319
320 if (!php_ctlr) {
321 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
322 return -1;
323 }
324
325 retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS(ctrl->cap_base), lnk_status);
326
327 if (retval) {
328 err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__);
329 return retval;
330 }
331
332 dbg("%s: lnk_status = %x\n", __FUNCTION__, lnk_status);
333 if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) ||
334 !(lnk_status & NEG_LINK_WD)) {
335 err("%s : Link Training Error occurs \n", __FUNCTION__);
336 retval = -1;
337 return retval;
338 }
339
340 DBG_LEAVE_ROUTINE
341 return retval;
342 }
343
344
345 static int hpc_get_attention_status(struct slot *slot, u8 *status)
346 {
347 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
348 u16 slot_ctrl;
349 u8 atten_led_state;
350 int retval = 0;
351
352 DBG_ENTER_ROUTINE
353
354 if (!php_ctlr) {
355 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
356 return -1;
357 }
358
359 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
360
361 if (retval) {
362 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
363 return retval;
364 }
365
366 dbg("%s: SLOT_CTRL %x, value read %x\n", __FUNCTION__,SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
367
368 atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6;
369
370 switch (atten_led_state) {
371 case 0:
372 *status = 0xFF; /* Reserved */
373 break;
374 case 1:
375 *status = 1; /* On */
376 break;
377 case 2:
378 *status = 2; /* Blink */
379 break;
380 case 3:
381 *status = 0; /* Off */
382 break;
383 default:
384 *status = 0xFF;
385 break;
386 }
387
388 DBG_LEAVE_ROUTINE
389 return 0;
390 }
391
392 static int hpc_get_power_status(struct slot * slot, u8 *status)
393 {
394 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
395 u16 slot_ctrl;
396 u8 pwr_state;
397 int retval = 0;
398
399 DBG_ENTER_ROUTINE
400
401 if (!php_ctlr) {
402 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
403 return -1;
404 }
405
406 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
407
408 if (retval) {
409 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
410 return retval;
411 }
412 dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
413
414 pwr_state = (slot_ctrl & PWR_CTRL) >> 10;
415
416 switch (pwr_state) {
417 case 0:
418 *status = 1;
419 break;
420 case 1:
421 *status = 0;
422 break;
423 default:
424 *status = 0xFF;
425 break;
426 }
427
428 DBG_LEAVE_ROUTINE
429 return retval;
430 }
431
432
433 static int hpc_get_latch_status(struct slot *slot, u8 *status)
434 {
435 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
436 u16 slot_status;
437 int retval = 0;
438
439 DBG_ENTER_ROUTINE
440
441 if (!php_ctlr) {
442 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
443 return -1;
444 }
445
446 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status);
447
448 if (retval) {
449 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
450 return retval;
451 }
452
453 *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1;
454
455 DBG_LEAVE_ROUTINE
456 return 0;
457 }
458
459 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
460 {
461 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
462 u16 slot_status;
463 u8 card_state;
464 int retval = 0;
465
466 DBG_ENTER_ROUTINE
467
468 if (!php_ctlr) {
469 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
470 return -1;
471 }
472
473 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status);
474
475 if (retval) {
476 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
477 return retval;
478 }
479 card_state = (u8)((slot_status & PRSN_STATE) >> 6);
480 *status = (card_state == 1) ? 1 : 0;
481
482 DBG_LEAVE_ROUTINE
483 return 0;
484 }
485
486 static int hpc_query_power_fault(struct slot * slot)
487 {
488 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
489 u16 slot_status;
490 u8 pwr_fault;
491 int retval = 0;
492
493 DBG_ENTER_ROUTINE
494
495 if (!php_ctlr) {
496 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
497 return -1;
498 }
499
500 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status);
501
502 if (retval) {
503 err("%s : Cannot check for power fault\n", __FUNCTION__);
504 return retval;
505 }
506 pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1);
507
508 DBG_LEAVE_ROUTINE
509 return pwr_fault;
510 }
511
512 static int hpc_set_attention_status(struct slot *slot, u8 value)
513 {
514 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
515 u16 slot_cmd = 0;
516 u16 slot_ctrl;
517 int rc = 0;
518
519 DBG_ENTER_ROUTINE
520
521 if (!php_ctlr) {
522 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
523 return -1;
524 }
525
526 if (slot->hp_slot >= php_ctlr->num_slots) {
527 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
528 return -1;
529 }
530 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
531
532 if (rc) {
533 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
534 return rc;
535 }
536
537 switch (value) {
538 case 0 : /* turn off */
539 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x00C0;
540 break;
541 case 1: /* turn on */
542 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0040;
543 break;
544 case 2: /* turn blink */
545 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0080;
546 break;
547 default:
548 return -1;
549 }
550 if (!pciehp_poll_mode)
551 slot_cmd = slot_cmd | HP_INTR_ENABLE;
552
553 pcie_write_cmd(slot, slot_cmd);
554 dbg("%s: SLOT_CTRL %x write cmd %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
555
556 DBG_LEAVE_ROUTINE
557 return rc;
558 }
559
560
561 static void hpc_set_green_led_on(struct slot *slot)
562 {
563 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
564 u16 slot_cmd;
565 u16 slot_ctrl;
566 int rc = 0;
567
568 DBG_ENTER_ROUTINE
569
570 if (!php_ctlr) {
571 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
572 return ;
573 }
574
575 if (slot->hp_slot >= php_ctlr->num_slots) {
576 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
577 return ;
578 }
579
580 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
581
582 if (rc) {
583 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
584 return;
585 }
586 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0100;
587 if (!pciehp_poll_mode)
588 slot_cmd = slot_cmd | HP_INTR_ENABLE;
589
590 pcie_write_cmd(slot, slot_cmd);
591
592 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
593 DBG_LEAVE_ROUTINE
594 return;
595 }
596
597 static void hpc_set_green_led_off(struct slot *slot)
598 {
599 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
600 u16 slot_cmd;
601 u16 slot_ctrl;
602 int rc = 0;
603
604 DBG_ENTER_ROUTINE
605
606 if (!php_ctlr) {
607 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
608 return ;
609 }
610
611 if (slot->hp_slot >= php_ctlr->num_slots) {
612 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
613 return ;
614 }
615
616 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
617
618 if (rc) {
619 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
620 return;
621 }
622
623 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0300;
624
625 if (!pciehp_poll_mode)
626 slot_cmd = slot_cmd | HP_INTR_ENABLE;
627 pcie_write_cmd(slot, slot_cmd);
628 dbg("%s: SLOT_CTRL %x write cmd %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
629
630 DBG_LEAVE_ROUTINE
631 return;
632 }
633
634 static void hpc_set_green_led_blink(struct slot *slot)
635 {
636 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
637 u16 slot_cmd;
638 u16 slot_ctrl;
639 int rc = 0;
640
641 DBG_ENTER_ROUTINE
642
643 if (!php_ctlr) {
644 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
645 return ;
646 }
647
648 if (slot->hp_slot >= php_ctlr->num_slots) {
649 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
650 return ;
651 }
652
653 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
654
655 if (rc) {
656 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
657 return;
658 }
659
660 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0200;
661
662 if (!pciehp_poll_mode)
663 slot_cmd = slot_cmd | HP_INTR_ENABLE;
664 pcie_write_cmd(slot, slot_cmd);
665
666 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
667 DBG_LEAVE_ROUTINE
668 return;
669 }
670
671 int pcie_get_ctlr_slot_config(struct controller *ctrl,
672 int *num_ctlr_slots, /* number of slots in this HPC; only 1 in PCIE */
673 int *first_device_num, /* PCI dev num of the first slot in this PCIE */
674 int *physical_slot_num, /* phy slot num of the first slot in this PCIE */
675 u8 *ctrlcap)
676 {
677 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
678 u32 slot_cap;
679 int rc = 0;
680
681 DBG_ENTER_ROUTINE
682
683 if (!php_ctlr) {
684 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
685 return -1;
686 }
687
688 *first_device_num = 0;
689 *num_ctlr_slots = 1;
690
691 rc = hp_register_read_dword(php_ctlr->pci_dev, SLOT_CAP(ctrl->cap_base), slot_cap);
692
693 if (rc) {
694 err("%s : hp_register_read_dword SLOT_CAP failed\n", __FUNCTION__);
695 return -1;
696 }
697
698 *physical_slot_num = slot_cap >> 19;
699 dbg("%s: PSN %d \n", __FUNCTION__, *physical_slot_num);
700
701 *ctrlcap = slot_cap & 0x0000007f;
702
703 DBG_LEAVE_ROUTINE
704 return 0;
705 }
706
707 static void hpc_release_ctlr(struct controller *ctrl)
708 {
709 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
710 struct php_ctlr_state_s *p, *p_prev;
711
712 DBG_ENTER_ROUTINE
713
714 if (!php_ctlr) {
715 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
716 return ;
717 }
718
719 if (pciehp_poll_mode) {
720 del_timer(&php_ctlr->int_poll_timer);
721 } else {
722 if (php_ctlr->irq) {
723 free_irq(php_ctlr->irq, ctrl);
724 php_ctlr->irq = 0;
725 if (!pcie_mch_quirk)
726 pci_disable_msi(php_ctlr->pci_dev);
727 }
728 }
729 if (php_ctlr->pci_dev)
730 php_ctlr->pci_dev = NULL;
731
732 spin_lock(&list_lock);
733 p = php_ctlr_list_head;
734 p_prev = NULL;
735 while (p) {
736 if (p == php_ctlr) {
737 if (p_prev)
738 p_prev->pnext = p->pnext;
739 else
740 php_ctlr_list_head = p->pnext;
741 break;
742 } else {
743 p_prev = p;
744 p = p->pnext;
745 }
746 }
747 spin_unlock(&list_lock);
748
749 kfree(php_ctlr);
750
751 DBG_LEAVE_ROUTINE
752
753 }
754
755 static int hpc_power_on_slot(struct slot * slot)
756 {
757 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
758 u16 slot_cmd;
759 u16 slot_ctrl, slot_status;
760
761 int retval = 0;
762
763 DBG_ENTER_ROUTINE
764
765 if (!php_ctlr) {
766 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
767 return -1;
768 }
769
770 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
771 if (slot->hp_slot >= php_ctlr->num_slots) {
772 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
773 return -1;
774 }
775
776 /* Clear sticky power-fault bit from previous power failures */
777 hp_register_read_word(php_ctlr->pci_dev,
778 SLOT_STATUS(slot->ctrl->cap_base), slot_status);
779 slot_status &= PWR_FAULT_DETECTED;
780 if (slot_status)
781 hp_register_write_word(php_ctlr->pci_dev,
782 SLOT_STATUS(slot->ctrl->cap_base), slot_status);
783
784 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
785
786 if (retval) {
787 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
788 return retval;
789 }
790
791 slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_ON;
792
793 /* Enable detection that we turned off at slot power-off time */
794 if (!pciehp_poll_mode)
795 slot_cmd = slot_cmd |
796 PWR_FAULT_DETECT_ENABLE |
797 MRL_DETECT_ENABLE |
798 PRSN_DETECT_ENABLE |
799 HP_INTR_ENABLE;
800
801 retval = pcie_write_cmd(slot, slot_cmd);
802
803 if (retval) {
804 err("%s: Write %x command failed!\n", __FUNCTION__, slot_cmd);
805 return -1;
806 }
807 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
808
809 DBG_LEAVE_ROUTINE
810
811 return retval;
812 }
813
814 static int hpc_power_off_slot(struct slot * slot)
815 {
816 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
817 u16 slot_cmd;
818 u16 slot_ctrl;
819
820 int retval = 0;
821
822 DBG_ENTER_ROUTINE
823
824 if (!php_ctlr) {
825 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
826 return -1;
827 }
828
829 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
830 slot->hp_slot = 0;
831 if (slot->hp_slot >= php_ctlr->num_slots) {
832 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
833 return -1;
834 }
835 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
836
837 if (retval) {
838 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
839 return retval;
840 }
841
842 slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_OFF;
843
844 /*
845 * If we get MRL or presence detect interrupts now, the isr
846 * will notice the sticky power-fault bit too and issue power
847 * indicator change commands. This will lead to an endless loop
848 * of command completions, since the power-fault bit remains on
849 * till the slot is powered on again.
850 */
851 if (!pciehp_poll_mode)
852 slot_cmd = (slot_cmd &
853 ~PWR_FAULT_DETECT_ENABLE &
854 ~MRL_DETECT_ENABLE &
855 ~PRSN_DETECT_ENABLE) | HP_INTR_ENABLE;
856
857 retval = pcie_write_cmd(slot, slot_cmd);
858
859 if (retval) {
860 err("%s: Write command failed!\n", __FUNCTION__);
861 return -1;
862 }
863 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
864
865 DBG_LEAVE_ROUTINE
866
867 return retval;
868 }
869
870 static irqreturn_t pcie_isr(int IRQ, void *dev_id, struct pt_regs *regs)
871 {
872 struct controller *ctrl = NULL;
873 struct php_ctlr_state_s *php_ctlr;
874 u8 schedule_flag = 0;
875 u16 slot_status, intr_detect, intr_loc;
876 u16 temp_word;
877 int hp_slot = 0; /* only 1 slot per PCI Express port */
878 int rc = 0;
879
880 if (!dev_id)
881 return IRQ_NONE;
882
883 if (!pciehp_poll_mode) {
884 ctrl = dev_id;
885 php_ctlr = ctrl->hpc_ctlr_handle;
886 } else {
887 php_ctlr = dev_id;
888 ctrl = (struct controller *)php_ctlr->callback_instance_id;
889 }
890
891 if (!ctrl) {
892 dbg("%s: dev_id %p ctlr == NULL\n", __FUNCTION__, (void*) dev_id);
893 return IRQ_NONE;
894 }
895
896 if (!php_ctlr) {
897 dbg("%s: php_ctlr == NULL\n", __FUNCTION__);
898 return IRQ_NONE;
899 }
900
901 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
902 if (rc) {
903 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
904 return IRQ_NONE;
905 }
906
907 intr_detect = ( ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED | MRL_SENS_CHANGED |
908 PRSN_DETECT_CHANGED | CMD_COMPLETED );
909
910 intr_loc = slot_status & intr_detect;
911
912 /* Check to see if it was our interrupt */
913 if ( !intr_loc )
914 return IRQ_NONE;
915
916 dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc);
917 /* Mask Hot-plug Interrupt Enable */
918 if (!pciehp_poll_mode) {
919 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
920 if (rc) {
921 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
922 return IRQ_NONE;
923 }
924
925 dbg("%s: hp_register_read_word SLOT_CTRL with value %x\n", __FUNCTION__, temp_word);
926 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00;
927
928 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
929 if (rc) {
930 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
931 return IRQ_NONE;
932 }
933
934 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
935 if (rc) {
936 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
937 return IRQ_NONE;
938 }
939 dbg("%s: hp_register_read_word SLOT_STATUS with value %x\n", __FUNCTION__, slot_status);
940
941 /* Clear command complete interrupt caused by this write */
942 temp_word = 0x1f;
943 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
944 if (rc) {
945 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
946 return IRQ_NONE;
947 }
948 }
949
950 if (intr_loc & CMD_COMPLETED) {
951 /*
952 * Command Complete Interrupt Pending
953 */
954 wake_up_interruptible(&ctrl->queue);
955 }
956
957 if ((php_ctlr->switch_change_callback) && (intr_loc & MRL_SENS_CHANGED))
958 schedule_flag += php_ctlr->switch_change_callback(
959 hp_slot, php_ctlr->callback_instance_id);
960 if ((php_ctlr->attention_button_callback) && (intr_loc & ATTN_BUTTN_PRESSED))
961 schedule_flag += php_ctlr->attention_button_callback(
962 hp_slot, php_ctlr->callback_instance_id);
963 if ((php_ctlr->presence_change_callback) && (intr_loc & PRSN_DETECT_CHANGED))
964 schedule_flag += php_ctlr->presence_change_callback(
965 hp_slot , php_ctlr->callback_instance_id);
966 if ((php_ctlr->power_fault_callback) && (intr_loc & PWR_FAULT_DETECTED))
967 schedule_flag += php_ctlr->power_fault_callback(
968 hp_slot, php_ctlr->callback_instance_id);
969
970 /* Clear all events after serving them */
971 temp_word = 0x1F;
972 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
973 if (rc) {
974 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
975 return IRQ_NONE;
976 }
977 /* Unmask Hot-plug Interrupt Enable */
978 if (!pciehp_poll_mode) {
979 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
980 if (rc) {
981 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
982 return IRQ_NONE;
983 }
984
985 dbg("%s: Unmask Hot-plug Interrupt Enable\n", __FUNCTION__);
986 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
987
988 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
989 if (rc) {
990 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
991 return IRQ_NONE;
992 }
993
994 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
995 if (rc) {
996 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
997 return IRQ_NONE;
998 }
999
1000 /* Clear command complete interrupt caused by this write */
1001 temp_word = 0x1F;
1002 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
1003 if (rc) {
1004 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
1005 return IRQ_NONE;
1006 }
1007 dbg("%s: hp_register_write_word SLOT_STATUS with value %x\n", __FUNCTION__, temp_word);
1008 }
1009
1010 return IRQ_HANDLED;
1011 }
1012
1013 static int hpc_get_max_lnk_speed (struct slot *slot, enum pci_bus_speed *value)
1014 {
1015 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1016 enum pcie_link_speed lnk_speed;
1017 u32 lnk_cap;
1018 int retval = 0;
1019
1020 DBG_ENTER_ROUTINE
1021
1022 if (!php_ctlr) {
1023 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1024 return -1;
1025 }
1026
1027 if (slot->hp_slot >= php_ctlr->num_slots) {
1028 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1029 return -1;
1030 }
1031
1032 retval = hp_register_read_dword(php_ctlr->pci_dev, LNK_CAP(slot->ctrl->cap_base), lnk_cap);
1033
1034 if (retval) {
1035 err("%s : hp_register_read_dword LNK_CAP failed\n", __FUNCTION__);
1036 return retval;
1037 }
1038
1039 switch (lnk_cap & 0x000F) {
1040 case 1:
1041 lnk_speed = PCIE_2PT5GB;
1042 break;
1043 default:
1044 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
1045 break;
1046 }
1047
1048 *value = lnk_speed;
1049 dbg("Max link speed = %d\n", lnk_speed);
1050 DBG_LEAVE_ROUTINE
1051 return retval;
1052 }
1053
1054 static int hpc_get_max_lnk_width (struct slot *slot, enum pcie_link_width *value)
1055 {
1056 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1057 enum pcie_link_width lnk_wdth;
1058 u32 lnk_cap;
1059 int retval = 0;
1060
1061 DBG_ENTER_ROUTINE
1062
1063 if (!php_ctlr) {
1064 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1065 return -1;
1066 }
1067
1068 if (slot->hp_slot >= php_ctlr->num_slots) {
1069 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1070 return -1;
1071 }
1072
1073 retval = hp_register_read_dword(php_ctlr->pci_dev, LNK_CAP(slot->ctrl->cap_base), lnk_cap);
1074
1075 if (retval) {
1076 err("%s : hp_register_read_dword LNK_CAP failed\n", __FUNCTION__);
1077 return retval;
1078 }
1079
1080 switch ((lnk_cap & 0x03F0) >> 4){
1081 case 0:
1082 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
1083 break;
1084 case 1:
1085 lnk_wdth = PCIE_LNK_X1;
1086 break;
1087 case 2:
1088 lnk_wdth = PCIE_LNK_X2;
1089 break;
1090 case 4:
1091 lnk_wdth = PCIE_LNK_X4;
1092 break;
1093 case 8:
1094 lnk_wdth = PCIE_LNK_X8;
1095 break;
1096 case 12:
1097 lnk_wdth = PCIE_LNK_X12;
1098 break;
1099 case 16:
1100 lnk_wdth = PCIE_LNK_X16;
1101 break;
1102 case 32:
1103 lnk_wdth = PCIE_LNK_X32;
1104 break;
1105 default:
1106 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1107 break;
1108 }
1109
1110 *value = lnk_wdth;
1111 dbg("Max link width = %d\n", lnk_wdth);
1112 DBG_LEAVE_ROUTINE
1113 return retval;
1114 }
1115
1116 static int hpc_get_cur_lnk_speed (struct slot *slot, enum pci_bus_speed *value)
1117 {
1118 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1119 enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN;
1120 int retval = 0;
1121 u16 lnk_status;
1122
1123 DBG_ENTER_ROUTINE
1124
1125 if (!php_ctlr) {
1126 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1127 return -1;
1128 }
1129
1130 if (slot->hp_slot >= php_ctlr->num_slots) {
1131 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1132 return -1;
1133 }
1134
1135 retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS(slot->ctrl->cap_base), lnk_status);
1136
1137 if (retval) {
1138 err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__);
1139 return retval;
1140 }
1141
1142 switch (lnk_status & 0x0F) {
1143 case 1:
1144 lnk_speed = PCIE_2PT5GB;
1145 break;
1146 default:
1147 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
1148 break;
1149 }
1150
1151 *value = lnk_speed;
1152 dbg("Current link speed = %d\n", lnk_speed);
1153 DBG_LEAVE_ROUTINE
1154 return retval;
1155 }
1156
1157 static int hpc_get_cur_lnk_width (struct slot *slot, enum pcie_link_width *value)
1158 {
1159 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1160 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1161 int retval = 0;
1162 u16 lnk_status;
1163
1164 DBG_ENTER_ROUTINE
1165
1166 if (!php_ctlr) {
1167 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1168 return -1;
1169 }
1170
1171 if (slot->hp_slot >= php_ctlr->num_slots) {
1172 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1173 return -1;
1174 }
1175
1176 retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS(slot->ctrl->cap_base), lnk_status);
1177
1178 if (retval) {
1179 err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__);
1180 return retval;
1181 }
1182
1183 switch ((lnk_status & 0x03F0) >> 4){
1184 case 0:
1185 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
1186 break;
1187 case 1:
1188 lnk_wdth = PCIE_LNK_X1;
1189 break;
1190 case 2:
1191 lnk_wdth = PCIE_LNK_X2;
1192 break;
1193 case 4:
1194 lnk_wdth = PCIE_LNK_X4;
1195 break;
1196 case 8:
1197 lnk_wdth = PCIE_LNK_X8;
1198 break;
1199 case 12:
1200 lnk_wdth = PCIE_LNK_X12;
1201 break;
1202 case 16:
1203 lnk_wdth = PCIE_LNK_X16;
1204 break;
1205 case 32:
1206 lnk_wdth = PCIE_LNK_X32;
1207 break;
1208 default:
1209 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1210 break;
1211 }
1212
1213 *value = lnk_wdth;
1214 dbg("Current link width = %d\n", lnk_wdth);
1215 DBG_LEAVE_ROUTINE
1216 return retval;
1217 }
1218
1219 static struct hpc_ops pciehp_hpc_ops = {
1220 .power_on_slot = hpc_power_on_slot,
1221 .power_off_slot = hpc_power_off_slot,
1222 .set_attention_status = hpc_set_attention_status,
1223 .get_power_status = hpc_get_power_status,
1224 .get_attention_status = hpc_get_attention_status,
1225 .get_latch_status = hpc_get_latch_status,
1226 .get_adapter_status = hpc_get_adapter_status,
1227
1228 .get_max_bus_speed = hpc_get_max_lnk_speed,
1229 .get_cur_bus_speed = hpc_get_cur_lnk_speed,
1230 .get_max_lnk_width = hpc_get_max_lnk_width,
1231 .get_cur_lnk_width = hpc_get_cur_lnk_width,
1232
1233 .query_power_fault = hpc_query_power_fault,
1234 .green_led_on = hpc_set_green_led_on,
1235 .green_led_off = hpc_set_green_led_off,
1236 .green_led_blink = hpc_set_green_led_blink,
1237
1238 .release_ctlr = hpc_release_ctlr,
1239 .check_lnk_status = hpc_check_lnk_status,
1240 };
1241
1242 #ifdef CONFIG_ACPI
1243 int pciehp_acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev)
1244 {
1245 acpi_status status;
1246 acpi_handle chandle, handle = DEVICE_ACPI_HANDLE(&(dev->dev));
1247 struct pci_dev *pdev = dev;
1248 struct pci_bus *parent;
1249 struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
1250
1251 /*
1252 * Per PCI firmware specification, we should run the ACPI _OSC
1253 * method to get control of hotplug hardware before using it.
1254 * If an _OSC is missing, we look for an OSHP to do the same thing.
1255 * To handle different BIOS behavior, we look for _OSC and OSHP
1256 * within the scope of the hotplug controller and its parents, upto
1257 * the host bridge under which this controller exists.
1258 */
1259 while (!handle) {
1260 /*
1261 * This hotplug controller was not listed in the ACPI name
1262 * space at all. Try to get acpi handle of parent pci bus.
1263 */
1264 if (!pdev || !pdev->bus->parent)
1265 break;
1266 parent = pdev->bus->parent;
1267 dbg("Could not find %s in acpi namespace, trying parent\n",
1268 pci_name(pdev));
1269 if (!parent->self)
1270 /* Parent must be a host bridge */
1271 handle = acpi_get_pci_rootbridge_handle(
1272 pci_domain_nr(parent),
1273 parent->number);
1274 else
1275 handle = DEVICE_ACPI_HANDLE(
1276 &(parent->self->dev));
1277 pdev = parent->self;
1278 }
1279
1280 while (handle) {
1281 acpi_get_name(handle, ACPI_FULL_PATHNAME, &string);
1282 dbg("Trying to get hotplug control for %s \n",
1283 (char *)string.pointer);
1284 status = pci_osc_control_set(handle,
1285 OSC_PCI_EXPRESS_NATIVE_HP_CONTROL);
1286 if (status == AE_NOT_FOUND)
1287 status = acpi_run_oshp(handle);
1288 if (ACPI_SUCCESS(status)) {
1289 dbg("Gained control for hotplug HW for pci %s (%s)\n",
1290 pci_name(dev), (char *)string.pointer);
1291 kfree(string.pointer);
1292 return 0;
1293 }
1294 if (acpi_root_bridge(handle))
1295 break;
1296 chandle = handle;
1297 status = acpi_get_parent(chandle, &handle);
1298 if (ACPI_FAILURE(status))
1299 break;
1300 }
1301
1302 err("Cannot get control of hotplug hardware for pci %s\n",
1303 pci_name(dev));
1304
1305 kfree(string.pointer);
1306 return -1;
1307 }
1308 #endif
1309
1310
1311
1312 int pcie_init(struct controller * ctrl, struct pcie_device *dev)
1313 {
1314 struct php_ctlr_state_s *php_ctlr, *p;
1315 void *instance_id = ctrl;
1316 int rc;
1317 static int first = 1;
1318 u16 temp_word;
1319 u16 cap_reg;
1320 u16 intr_enable = 0;
1321 u32 slot_cap;
1322 int cap_base, saved_cap_base;
1323 u16 slot_status, slot_ctrl;
1324 struct pci_dev *pdev;
1325
1326 DBG_ENTER_ROUTINE
1327
1328 spin_lock_init(&list_lock);
1329 php_ctlr = (struct php_ctlr_state_s *) kmalloc(sizeof(struct php_ctlr_state_s), GFP_KERNEL);
1330
1331 if (!php_ctlr) { /* allocate controller state data */
1332 err("%s: HPC controller memory allocation error!\n", __FUNCTION__);
1333 goto abort;
1334 }
1335
1336 memset(php_ctlr, 0, sizeof(struct php_ctlr_state_s));
1337
1338 pdev = dev->port;
1339 php_ctlr->pci_dev = pdev; /* save pci_dev in context */
1340
1341 dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n",
1342 __FUNCTION__, pdev->vendor, pdev->device);
1343
1344 saved_cap_base = pcie_cap_base;
1345
1346 if ((cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP)) == 0) {
1347 dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __FUNCTION__);
1348 goto abort_free_ctlr;
1349 }
1350
1351 ctrl->cap_base = cap_base;
1352
1353 dbg("%s: pcie_cap_base %x\n", __FUNCTION__, pcie_cap_base);
1354
1355 rc = hp_register_read_word(pdev, CAP_REG(ctrl->cap_base), cap_reg);
1356 if (rc) {
1357 err("%s : hp_register_read_word CAP_REG failed\n", __FUNCTION__);
1358 goto abort_free_ctlr;
1359 }
1360 dbg("%s: CAP_REG offset %x cap_reg %x\n", __FUNCTION__, CAP_REG(ctrl->cap_base), cap_reg);
1361
1362 if (((cap_reg & SLOT_IMPL) == 0) || (((cap_reg & DEV_PORT_TYPE) != 0x0040)
1363 && ((cap_reg & DEV_PORT_TYPE) != 0x0060))) {
1364 dbg("%s : This is not a root port or the port is not connected to a slot\n", __FUNCTION__);
1365 goto abort_free_ctlr;
1366 }
1367
1368 rc = hp_register_read_dword(php_ctlr->pci_dev, SLOT_CAP(ctrl->cap_base), slot_cap);
1369 if (rc) {
1370 err("%s : hp_register_read_word CAP_REG failed\n", __FUNCTION__);
1371 goto abort_free_ctlr;
1372 }
1373 dbg("%s: SLOT_CAP offset %x slot_cap %x\n", __FUNCTION__, SLOT_CAP(ctrl->cap_base), slot_cap);
1374
1375 if (!(slot_cap & HP_CAP)) {
1376 dbg("%s : This slot is not hot-plug capable\n", __FUNCTION__);
1377 goto abort_free_ctlr;
1378 }
1379 /* For debugging purpose */
1380 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1381 if (rc) {
1382 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1383 goto abort_free_ctlr;
1384 }
1385 dbg("%s: SLOT_STATUS offset %x slot_status %x\n", __FUNCTION__, SLOT_STATUS(ctrl->cap_base), slot_status);
1386
1387 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), slot_ctrl);
1388 if (rc) {
1389 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
1390 goto abort_free_ctlr;
1391 }
1392 dbg("%s: SLOT_CTRL offset %x slot_ctrl %x\n", __FUNCTION__, SLOT_CTRL(ctrl->cap_base), slot_ctrl);
1393
1394 if (first) {
1395 spin_lock_init(&hpc_event_lock);
1396 first = 0;
1397 }
1398
1399 for ( rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++)
1400 if (pci_resource_len(pdev, rc) > 0)
1401 dbg("pci resource[%d] start=0x%lx(len=0x%lx)\n", rc,
1402 pci_resource_start(pdev, rc), pci_resource_len(pdev, rc));
1403
1404 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device,
1405 pdev->subsystem_vendor, pdev->subsystem_device);
1406
1407 mutex_init(&ctrl->crit_sect);
1408 /* setup wait queue */
1409 init_waitqueue_head(&ctrl->queue);
1410
1411 /* find the IRQ */
1412 php_ctlr->irq = dev->irq;
1413
1414 /* Save interrupt callback info */
1415 php_ctlr->attention_button_callback = pciehp_handle_attention_button;
1416 php_ctlr->switch_change_callback = pciehp_handle_switch_change;
1417 php_ctlr->presence_change_callback = pciehp_handle_presence_change;
1418 php_ctlr->power_fault_callback = pciehp_handle_power_fault;
1419 php_ctlr->callback_instance_id = instance_id;
1420
1421 /* return PCI Controller Info */
1422 php_ctlr->slot_device_offset = 0;
1423 php_ctlr->num_slots = 1;
1424
1425 /* Mask Hot-plug Interrupt Enable */
1426 rc = hp_register_read_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1427 if (rc) {
1428 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
1429 goto abort_free_ctlr;
1430 }
1431
1432 dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL(ctrl->cap_base), temp_word);
1433 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00;
1434
1435 rc = hp_register_write_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1436 if (rc) {
1437 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
1438 goto abort_free_ctlr;
1439 }
1440
1441 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1442 if (rc) {
1443 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1444 goto abort_free_ctlr;
1445 }
1446
1447 temp_word = 0x1F; /* Clear all events */
1448 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
1449 if (rc) {
1450 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
1451 goto abort_free_ctlr;
1452 }
1453
1454 if (pciehp_poll_mode) {/* Install interrupt polling code */
1455 /* Install and start the interrupt polling timer */
1456 init_timer(&php_ctlr->int_poll_timer);
1457 start_int_poll_timer( php_ctlr, 10 ); /* start with 10 second delay */
1458 } else {
1459 /* Installs the interrupt handler */
1460 rc = request_irq(php_ctlr->irq, pcie_isr, SA_SHIRQ, MY_NAME, (void *) ctrl);
1461 dbg("%s: request_irq %d for hpc%d (returns %d)\n", __FUNCTION__, php_ctlr->irq, ctlr_seq_num, rc);
1462 if (rc) {
1463 err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq);
1464 goto abort_free_ctlr;
1465 }
1466 }
1467
1468 dbg("pciehp ctrl b:d:f:irq=0x%x:%x:%x:%x\n", pdev->bus->number,
1469 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), dev->irq);
1470
1471 rc = hp_register_read_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1472 if (rc) {
1473 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
1474 goto abort_free_irq;
1475 }
1476
1477 intr_enable = intr_enable | PRSN_DETECT_ENABLE;
1478
1479 if (ATTN_BUTTN(slot_cap))
1480 intr_enable = intr_enable | ATTN_BUTTN_ENABLE;
1481
1482 if (POWER_CTRL(slot_cap))
1483 intr_enable = intr_enable | PWR_FAULT_DETECT_ENABLE;
1484
1485 if (MRL_SENS(slot_cap))
1486 intr_enable = intr_enable | MRL_DETECT_ENABLE;
1487
1488 temp_word = (temp_word & ~intr_enable) | intr_enable;
1489
1490 if (pciehp_poll_mode) {
1491 temp_word = (temp_word & ~HP_INTR_ENABLE) | 0x0;
1492 } else {
1493 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
1494 }
1495
1496 /* Unmask Hot-plug Interrupt Enable for the interrupt notification mechanism case */
1497 rc = hp_register_write_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1498 if (rc) {
1499 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
1500 goto abort_free_irq;
1501 }
1502 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1503 if (rc) {
1504 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1505 goto abort_disable_intr;
1506 }
1507
1508 temp_word = 0x1F; /* Clear all events */
1509 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
1510 if (rc) {
1511 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
1512 goto abort_disable_intr;
1513 }
1514
1515 if (pciehp_force) {
1516 dbg("Bypassing BIOS check for pciehp use on %s\n",
1517 pci_name(ctrl->pci_dev));
1518 } else {
1519 rc = pciehp_get_hp_hw_control_from_firmware(ctrl->pci_dev);
1520 if (rc)
1521 goto abort_disable_intr;
1522 }
1523
1524 /* Add this HPC instance into the HPC list */
1525 spin_lock(&list_lock);
1526 if (php_ctlr_list_head == 0) {
1527 php_ctlr_list_head = php_ctlr;
1528 p = php_ctlr_list_head;
1529 p->pnext = NULL;
1530 } else {
1531 p = php_ctlr_list_head;
1532
1533 while (p->pnext)
1534 p = p->pnext;
1535
1536 p->pnext = php_ctlr;
1537 }
1538 spin_unlock(&list_lock);
1539
1540 ctlr_seq_num++;
1541 ctrl->hpc_ctlr_handle = php_ctlr;
1542 ctrl->hpc_ops = &pciehp_hpc_ops;
1543
1544 DBG_LEAVE_ROUTINE
1545 return 0;
1546
1547 /* We end up here for the many possible ways to fail this API. */
1548 abort_disable_intr:
1549 rc = hp_register_read_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1550 if (!rc) {
1551 temp_word &= ~(intr_enable | HP_INTR_ENABLE);
1552 rc = hp_register_write_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1553 }
1554 if (rc)
1555 err("%s : disabling interrupts failed\n", __FUNCTION__);
1556
1557 abort_free_irq:
1558 if (pciehp_poll_mode)
1559 del_timer_sync(&php_ctlr->int_poll_timer);
1560 else
1561 free_irq(php_ctlr->irq, ctrl);
1562
1563 abort_free_ctlr:
1564 pcie_cap_base = saved_cap_base;
1565 kfree(php_ctlr);
1566 abort:
1567 DBG_LEAVE_ROUTINE
1568 return -1;
1569 }
Verdex Pro support