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[PATCH] w1: Make w1 connector notifications depend on connector.
[linux-2.6/verdex.git] / drivers / serial / mpsc.c
blob94681922ea0a6a2e874bef249520ce541a035ee4
1 /*
2 * Generic driver for the MPSC (UART mode) on Marvell parts (e.g., GT64240,
3 * GT64260, MV64340, MV64360, GT96100, ... ).
4 *
5 * Author: Mark A. Greer <mgreer@mvista.com>
6 *
7 * Based on an old MPSC driver that was in the linuxppc tree. It appears to
8 * have been created by Chris Zankel (formerly of MontaVista) but there
9 * is no proper Copyright so I'm not sure. Apparently, parts were also
10 * taken from PPCBoot (now U-Boot). Also based on drivers/serial/8250.c
11 * by Russell King.
12 *
13 * 2004 (c) MontaVista, Software, Inc. This file is licensed under
14 * the terms of the GNU General Public License version 2. This program
15 * is licensed "as is" without any warranty of any kind, whether express
16 * or implied.
17 */
18 /*
19 * The MPSC interface is much like a typical network controller's interface.
20 * That is, you set up separate rings of descriptors for transmitting and
21 * receiving data. There is also a pool of buffers with (one buffer per
22 * descriptor) that incoming data are dma'd into or outgoing data are dma'd
23 * out of.
24 *
25 * The MPSC requires two other controllers to be able to work. The Baud Rate
26 * Generator (BRG) provides a clock at programmable frequencies which determines
27 * the baud rate. The Serial DMA Controller (SDMA) takes incoming data from the
28 * MPSC and DMA's it into memory or DMA's outgoing data and passes it to the
29 * MPSC. It is actually the SDMA interrupt that the driver uses to keep the
30 * transmit and receive "engines" going (i.e., indicate data has been
31 * transmitted or received).
32 *
33 * NOTES:
34 *
35 * 1) Some chips have an erratum where several regs cannot be
36 * read. To work around that, we keep a local copy of those regs in
37 * 'mpsc_port_info'.
38 *
39 * 2) Some chips have an erratum where the ctlr will hang when the SDMA ctlr
40 * accesses system mem with coherency enabled. For that reason, the driver
41 * assumes that coherency for that ctlr has been disabled. This means
42 * that when in a cache coherent system, the driver has to manually manage
43 * the data cache on the areas that it touches because the dma_* macro are
44 * basically no-ops.
45 *
46 * 3) There is an erratum (on PPC) where you can't use the instruction to do
47 * a DMA_TO_DEVICE/cache clean so DMA_BIDIRECTIONAL/flushes are used in places
48 * where a DMA_TO_DEVICE/clean would have [otherwise] sufficed.
49 *
50 * 4) AFAICT, hardware flow control isn't supported by the controller --MAG.
51 */
52
53 #include <linux/config.h>
54
55 #if defined(CONFIG_SERIAL_MPSC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
56 #define SUPPORT_SYSRQ
57 #endif
58
59 #include <linux/module.h>
60 #include <linux/moduleparam.h>
61 #include <linux/tty.h>
62 #include <linux/tty_flip.h>
63 #include <linux/ioport.h>
64 #include <linux/init.h>
65 #include <linux/console.h>
66 #include <linux/sysrq.h>
67 #include <linux/serial.h>
68 #include <linux/serial_core.h>
69 #include <linux/delay.h>
70 #include <linux/device.h>
71 #include <linux/dma-mapping.h>
72 #include <linux/mv643xx.h>
73 #include <linux/platform_device.h>
74
75 #include <asm/io.h>
76 #include <asm/irq.h>
77
78 #if defined(CONFIG_SERIAL_MPSC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
79 #define SUPPORT_SYSRQ
80 #endif
81
82 #define MPSC_NUM_CTLRS 2
83
84 /*
85 * Descriptors and buffers must be cache line aligned.
86 * Buffers lengths must be multiple of cache line size.
87 * Number of Tx & Rx descriptors must be powers of 2.
88 */
89 #define MPSC_RXR_ENTRIES 32
90 #define MPSC_RXRE_SIZE dma_get_cache_alignment()
91 #define MPSC_RXR_SIZE (MPSC_RXR_ENTRIES * MPSC_RXRE_SIZE)
92 #define MPSC_RXBE_SIZE dma_get_cache_alignment()
93 #define MPSC_RXB_SIZE (MPSC_RXR_ENTRIES * MPSC_RXBE_SIZE)
94
95 #define MPSC_TXR_ENTRIES 32
96 #define MPSC_TXRE_SIZE dma_get_cache_alignment()
97 #define MPSC_TXR_SIZE (MPSC_TXR_ENTRIES * MPSC_TXRE_SIZE)
98 #define MPSC_TXBE_SIZE dma_get_cache_alignment()
99 #define MPSC_TXB_SIZE (MPSC_TXR_ENTRIES * MPSC_TXBE_SIZE)
100
101 #define MPSC_DMA_ALLOC_SIZE (MPSC_RXR_SIZE + MPSC_RXB_SIZE + \
102 MPSC_TXR_SIZE + MPSC_TXB_SIZE + \
103 dma_get_cache_alignment() /* for alignment */)
104
105 /* Rx and Tx Ring entry descriptors -- assume entry size is <= cacheline size */
106 struct mpsc_rx_desc {
107 u16 bufsize;
108 u16 bytecnt;
109 u32 cmdstat;
110 u32 link;
111 u32 buf_ptr;
112 } __attribute((packed));
113
114 struct mpsc_tx_desc {
115 u16 bytecnt;
116 u16 shadow;
117 u32 cmdstat;
118 u32 link;
119 u32 buf_ptr;
120 } __attribute((packed));
121
122 /*
123 * Some regs that have the erratum that you can't read them are are shared
124 * between the two MPSC controllers. This struct contains those shared regs.
125 */
126 struct mpsc_shared_regs {
127 phys_addr_t mpsc_routing_base_p;
128 phys_addr_t sdma_intr_base_p;
129
130 void __iomem *mpsc_routing_base;
131 void __iomem *sdma_intr_base;
132
133 u32 MPSC_MRR_m;
134 u32 MPSC_RCRR_m;
135 u32 MPSC_TCRR_m;
136 u32 SDMA_INTR_CAUSE_m;
137 u32 SDMA_INTR_MASK_m;
138 };
139
140 /* The main driver data structure */
141 struct mpsc_port_info {
142 struct uart_port port; /* Overlay uart_port structure */
143
144 /* Internal driver state for this ctlr */
145 u8 ready;
146 u8 rcv_data;
147 tcflag_t c_iflag; /* save termios->c_iflag */
148 tcflag_t c_cflag; /* save termios->c_cflag */
149
150 /* Info passed in from platform */
151 u8 mirror_regs; /* Need to mirror regs? */
152 u8 cache_mgmt; /* Need manual cache mgmt? */
153 u8 brg_can_tune; /* BRG has baud tuning? */
154 u32 brg_clk_src;
155 u16 mpsc_max_idle;
156 int default_baud;
157 int default_bits;
158 int default_parity;
159 int default_flow;
160
161 /* Physical addresses of various blocks of registers (from platform) */
162 phys_addr_t mpsc_base_p;
163 phys_addr_t sdma_base_p;
164 phys_addr_t brg_base_p;
165
166 /* Virtual addresses of various blocks of registers (from platform) */
167 void __iomem *mpsc_base;
168 void __iomem *sdma_base;
169 void __iomem *brg_base;
170
171 /* Descriptor ring and buffer allocations */
172 void *dma_region;
173 dma_addr_t dma_region_p;
174
175 dma_addr_t rxr; /* Rx descriptor ring */
176 dma_addr_t rxr_p; /* Phys addr of rxr */
177 u8 *rxb; /* Rx Ring I/O buf */
178 u8 *rxb_p; /* Phys addr of rxb */
179 u32 rxr_posn; /* First desc w/ Rx data */
180
181 dma_addr_t txr; /* Tx descriptor ring */
182 dma_addr_t txr_p; /* Phys addr of txr */
183 u8 *txb; /* Tx Ring I/O buf */
184 u8 *txb_p; /* Phys addr of txb */
185 int txr_head; /* Where new data goes */
186 int txr_tail; /* Where sent data comes off */
187
188 /* Mirrored values of regs we can't read (if 'mirror_regs' set) */
189 u32 MPSC_MPCR_m;
190 u32 MPSC_CHR_1_m;
191 u32 MPSC_CHR_2_m;
192 u32 MPSC_CHR_10_m;
193 u32 BRG_BCR_m;
194 struct mpsc_shared_regs *shared_regs;
195 };
196
197 /* Hooks to platform-specific code */
198 int mpsc_platform_register_driver(void);
199 void mpsc_platform_unregister_driver(void);
200
201 /* Hooks back in to mpsc common to be called by platform-specific code */
202 struct mpsc_port_info *mpsc_device_probe(int index);
203 struct mpsc_port_info *mpsc_device_remove(int index);
204
205 /* Main MPSC Configuration Register Offsets */
206 #define MPSC_MMCRL 0x0000
207 #define MPSC_MMCRH 0x0004
208 #define MPSC_MPCR 0x0008
209 #define MPSC_CHR_1 0x000c
210 #define MPSC_CHR_2 0x0010
211 #define MPSC_CHR_3 0x0014
212 #define MPSC_CHR_4 0x0018
213 #define MPSC_CHR_5 0x001c
214 #define MPSC_CHR_6 0x0020
215 #define MPSC_CHR_7 0x0024
216 #define MPSC_CHR_8 0x0028
217 #define MPSC_CHR_9 0x002c
218 #define MPSC_CHR_10 0x0030
219 #define MPSC_CHR_11 0x0034
220
221 #define MPSC_MPCR_FRZ (1 << 9)
222 #define MPSC_MPCR_CL_5 0
223 #define MPSC_MPCR_CL_6 1
224 #define MPSC_MPCR_CL_7 2
225 #define MPSC_MPCR_CL_8 3
226 #define MPSC_MPCR_SBL_1 0
227 #define MPSC_MPCR_SBL_2 1
228
229 #define MPSC_CHR_2_TEV (1<<1)
230 #define MPSC_CHR_2_TA (1<<7)
231 #define MPSC_CHR_2_TTCS (1<<9)
232 #define MPSC_CHR_2_REV (1<<17)
233 #define MPSC_CHR_2_RA (1<<23)
234 #define MPSC_CHR_2_CRD (1<<25)
235 #define MPSC_CHR_2_EH (1<<31)
236 #define MPSC_CHR_2_PAR_ODD 0
237 #define MPSC_CHR_2_PAR_SPACE 1
238 #define MPSC_CHR_2_PAR_EVEN 2
239 #define MPSC_CHR_2_PAR_MARK 3
240
241 /* MPSC Signal Routing */
242 #define MPSC_MRR 0x0000
243 #define MPSC_RCRR 0x0004
244 #define MPSC_TCRR 0x0008
245
246 /* Serial DMA Controller Interface Registers */
247 #define SDMA_SDC 0x0000
248 #define SDMA_SDCM 0x0008
249 #define SDMA_RX_DESC 0x0800
250 #define SDMA_RX_BUF_PTR 0x0808
251 #define SDMA_SCRDP 0x0810
252 #define SDMA_TX_DESC 0x0c00
253 #define SDMA_SCTDP 0x0c10
254 #define SDMA_SFTDP 0x0c14
255
256 #define SDMA_DESC_CMDSTAT_PE (1<<0)
257 #define SDMA_DESC_CMDSTAT_CDL (1<<1)
258 #define SDMA_DESC_CMDSTAT_FR (1<<3)
259 #define SDMA_DESC_CMDSTAT_OR (1<<6)
260 #define SDMA_DESC_CMDSTAT_BR (1<<9)
261 #define SDMA_DESC_CMDSTAT_MI (1<<10)
262 #define SDMA_DESC_CMDSTAT_A (1<<11)
263 #define SDMA_DESC_CMDSTAT_AM (1<<12)
264 #define SDMA_DESC_CMDSTAT_CT (1<<13)
265 #define SDMA_DESC_CMDSTAT_C (1<<14)
266 #define SDMA_DESC_CMDSTAT_ES (1<<15)
267 #define SDMA_DESC_CMDSTAT_L (1<<16)
268 #define SDMA_DESC_CMDSTAT_F (1<<17)
269 #define SDMA_DESC_CMDSTAT_P (1<<18)
270 #define SDMA_DESC_CMDSTAT_EI (1<<23)
271 #define SDMA_DESC_CMDSTAT_O (1<<31)
272
273 #define SDMA_DESC_DFLT (SDMA_DESC_CMDSTAT_O | \
274 SDMA_DESC_CMDSTAT_EI)
275
276 #define SDMA_SDC_RFT (1<<0)
277 #define SDMA_SDC_SFM (1<<1)
278 #define SDMA_SDC_BLMR (1<<6)
279 #define SDMA_SDC_BLMT (1<<7)
280 #define SDMA_SDC_POVR (1<<8)
281 #define SDMA_SDC_RIFB (1<<9)
282
283 #define SDMA_SDCM_ERD (1<<7)
284 #define SDMA_SDCM_AR (1<<15)
285 #define SDMA_SDCM_STD (1<<16)
286 #define SDMA_SDCM_TXD (1<<23)
287 #define SDMA_SDCM_AT (1<<31)
288
289 #define SDMA_0_CAUSE_RXBUF (1<<0)
290 #define SDMA_0_CAUSE_RXERR (1<<1)
291 #define SDMA_0_CAUSE_TXBUF (1<<2)
292 #define SDMA_0_CAUSE_TXEND (1<<3)
293 #define SDMA_1_CAUSE_RXBUF (1<<8)
294 #define SDMA_1_CAUSE_RXERR (1<<9)
295 #define SDMA_1_CAUSE_TXBUF (1<<10)
296 #define SDMA_1_CAUSE_TXEND (1<<11)
297
298 #define SDMA_CAUSE_RX_MASK (SDMA_0_CAUSE_RXBUF | SDMA_0_CAUSE_RXERR | \
299 SDMA_1_CAUSE_RXBUF | SDMA_1_CAUSE_RXERR)
300 #define SDMA_CAUSE_TX_MASK (SDMA_0_CAUSE_TXBUF | SDMA_0_CAUSE_TXEND | \
301 SDMA_1_CAUSE_TXBUF | SDMA_1_CAUSE_TXEND)
302
303 /* SDMA Interrupt registers */
304 #define SDMA_INTR_CAUSE 0x0000
305 #define SDMA_INTR_MASK 0x0080
306
307 /* Baud Rate Generator Interface Registers */
308 #define BRG_BCR 0x0000
309 #define BRG_BTR 0x0004
310
311 /*
312 * Define how this driver is known to the outside (we've been assigned a
313 * range on the "Low-density serial ports" major).
314 */
315 #define MPSC_MAJOR 204
316 #define MPSC_MINOR_START 44
317 #define MPSC_DRIVER_NAME "MPSC"
318 #define MPSC_DEVFS_NAME "ttymm/"
319 #define MPSC_DEV_NAME "ttyMM"
320 #define MPSC_VERSION "1.00"
321
322 static struct mpsc_port_info mpsc_ports[MPSC_NUM_CTLRS];
323 static struct mpsc_shared_regs mpsc_shared_regs;
324 static struct uart_driver mpsc_reg;
325
326 static void mpsc_start_rx(struct mpsc_port_info *pi);
327 static void mpsc_free_ring_mem(struct mpsc_port_info *pi);
328 static void mpsc_release_port(struct uart_port *port);
329 /*
330 ******************************************************************************
331 *
332 * Baud Rate Generator Routines (BRG)
333 *
334 ******************************************************************************
335 */
336 static void
337 mpsc_brg_init(struct mpsc_port_info *pi, u32 clk_src)
338 {
339 u32 v;
340
341 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
342 v = (v & ~(0xf << 18)) | ((clk_src & 0xf) << 18);
343
344 if (pi->brg_can_tune)
345 v &= ~(1 << 25);
346
347 if (pi->mirror_regs)
348 pi->BRG_BCR_m = v;
349 writel(v, pi->brg_base + BRG_BCR);
350
351 writel(readl(pi->brg_base + BRG_BTR) & 0xffff0000,
352 pi->brg_base + BRG_BTR);
353 return;
354 }
355
356 static void
357 mpsc_brg_enable(struct mpsc_port_info *pi)
358 {
359 u32 v;
360
361 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
362 v |= (1 << 16);
363
364 if (pi->mirror_regs)
365 pi->BRG_BCR_m = v;
366 writel(v, pi->brg_base + BRG_BCR);
367 return;
368 }
369
370 static void
371 mpsc_brg_disable(struct mpsc_port_info *pi)
372 {
373 u32 v;
374
375 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
376 v &= ~(1 << 16);
377
378 if (pi->mirror_regs)
379 pi->BRG_BCR_m = v;
380 writel(v, pi->brg_base + BRG_BCR);
381 return;
382 }
383
384 static inline void
385 mpsc_set_baudrate(struct mpsc_port_info *pi, u32 baud)
386 {
387 /*
388 * To set the baud, we adjust the CDV field in the BRG_BCR reg.
389 * From manual: Baud = clk / ((CDV+1)*2) ==> CDV = (clk / (baud*2)) - 1.
390 * However, the input clock is divided by 16 in the MPSC b/c of how
391 * 'MPSC_MMCRH' was set up so we have to divide the 'clk' used in our
392 * calculation by 16 to account for that. So the real calculation
393 * that accounts for the way the mpsc is set up is:
394 * CDV = (clk / (baud*2*16)) - 1 ==> CDV = (clk / (baud << 5)) - 1.
395 */
396 u32 cdv = (pi->port.uartclk / (baud << 5)) - 1;
397 u32 v;
398
399 mpsc_brg_disable(pi);
400 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
401 v = (v & 0xffff0000) | (cdv & 0xffff);
402
403 if (pi->mirror_regs)
404 pi->BRG_BCR_m = v;
405 writel(v, pi->brg_base + BRG_BCR);
406 mpsc_brg_enable(pi);
407
408 return;
409 }
410
411 /*
412 ******************************************************************************
413 *
414 * Serial DMA Routines (SDMA)
415 *
416 ******************************************************************************
417 */
418
419 static void
420 mpsc_sdma_burstsize(struct mpsc_port_info *pi, u32 burst_size)
421 {
422 u32 v;
423
424 pr_debug("mpsc_sdma_burstsize[%d]: burst_size: %d\n",
425 pi->port.line, burst_size);
426
427 burst_size >>= 3; /* Divide by 8 b/c reg values are 8-byte chunks */
428
429 if (burst_size < 2)
430 v = 0x0; /* 1 64-bit word */
431 else if (burst_size < 4)
432 v = 0x1; /* 2 64-bit words */
433 else if (burst_size < 8)
434 v = 0x2; /* 4 64-bit words */
435 else
436 v = 0x3; /* 8 64-bit words */
437
438 writel((readl(pi->sdma_base + SDMA_SDC) & (0x3 << 12)) | (v << 12),
439 pi->sdma_base + SDMA_SDC);
440 return;
441 }
442
443 static void
444 mpsc_sdma_init(struct mpsc_port_info *pi, u32 burst_size)
445 {
446 pr_debug("mpsc_sdma_init[%d]: burst_size: %d\n", pi->port.line,
447 burst_size);
448
449 writel((readl(pi->sdma_base + SDMA_SDC) & 0x3ff) | 0x03f,
450 pi->sdma_base + SDMA_SDC);
451 mpsc_sdma_burstsize(pi, burst_size);
452 return;
453 }
454
455 static inline u32
456 mpsc_sdma_intr_mask(struct mpsc_port_info *pi, u32 mask)
457 {
458 u32 old, v;
459
460 pr_debug("mpsc_sdma_intr_mask[%d]: mask: 0x%x\n", pi->port.line, mask);
461
462 old = v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m :
463 readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
464
465 mask &= 0xf;
466 if (pi->port.line)
467 mask <<= 8;
468 v &= ~mask;
469
470 if (pi->mirror_regs)
471 pi->shared_regs->SDMA_INTR_MASK_m = v;
472 writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
473
474 if (pi->port.line)
475 old >>= 8;
476 return old & 0xf;
477 }
478
479 static inline void
480 mpsc_sdma_intr_unmask(struct mpsc_port_info *pi, u32 mask)
481 {
482 u32 v;
483
484 pr_debug("mpsc_sdma_intr_unmask[%d]: mask: 0x%x\n", pi->port.line,mask);
485
486 v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m :
487 readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
488
489 mask &= 0xf;
490 if (pi->port.line)
491 mask <<= 8;
492 v |= mask;
493
494 if (pi->mirror_regs)
495 pi->shared_regs->SDMA_INTR_MASK_m = v;
496 writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
497 return;
498 }
499
500 static inline void
501 mpsc_sdma_intr_ack(struct mpsc_port_info *pi)
502 {
503 pr_debug("mpsc_sdma_intr_ack[%d]: Acknowledging IRQ\n", pi->port.line);
504
505 if (pi->mirror_regs)
506 pi->shared_regs->SDMA_INTR_CAUSE_m = 0;
507 writel(0, pi->shared_regs->sdma_intr_base + SDMA_INTR_CAUSE);
508 return;
509 }
510
511 static inline void
512 mpsc_sdma_set_rx_ring(struct mpsc_port_info *pi, struct mpsc_rx_desc *rxre_p)
513 {
514 pr_debug("mpsc_sdma_set_rx_ring[%d]: rxre_p: 0x%x\n",
515 pi->port.line, (u32) rxre_p);
516
517 writel((u32)rxre_p, pi->sdma_base + SDMA_SCRDP);
518 return;
519 }
520
521 static inline void
522 mpsc_sdma_set_tx_ring(struct mpsc_port_info *pi, struct mpsc_tx_desc *txre_p)
523 {
524 writel((u32)txre_p, pi->sdma_base + SDMA_SFTDP);
525 writel((u32)txre_p, pi->sdma_base + SDMA_SCTDP);
526 return;
527 }
528
529 static inline void
530 mpsc_sdma_cmd(struct mpsc_port_info *pi, u32 val)
531 {
532 u32 v;
533
534 v = readl(pi->sdma_base + SDMA_SDCM);
535 if (val)
536 v |= val;
537 else
538 v = 0;
539 wmb();
540 writel(v, pi->sdma_base + SDMA_SDCM);
541 wmb();
542 return;
543 }
544
545 static inline uint
546 mpsc_sdma_tx_active(struct mpsc_port_info *pi)
547 {
548 return readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_TXD;
549 }
550
551 static inline void
552 mpsc_sdma_start_tx(struct mpsc_port_info *pi)
553 {
554 struct mpsc_tx_desc *txre, *txre_p;
555
556 /* If tx isn't running & there's a desc ready to go, start it */
557 if (!mpsc_sdma_tx_active(pi)) {
558 txre = (struct mpsc_tx_desc *)(pi->txr +
559 (pi->txr_tail * MPSC_TXRE_SIZE));
560 dma_cache_sync((void *) txre, MPSC_TXRE_SIZE, DMA_FROM_DEVICE);
561 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
562 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
563 invalidate_dcache_range((ulong)txre,
564 (ulong)txre + MPSC_TXRE_SIZE);
565 #endif
566
567 if (be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O) {
568 txre_p = (struct mpsc_tx_desc *)(pi->txr_p +
569 (pi->txr_tail *
570 MPSC_TXRE_SIZE));
571
572 mpsc_sdma_set_tx_ring(pi, txre_p);
573 mpsc_sdma_cmd(pi, SDMA_SDCM_STD | SDMA_SDCM_TXD);
574 }
575 }
576
577 return;
578 }
579
580 static inline void
581 mpsc_sdma_stop(struct mpsc_port_info *pi)
582 {
583 pr_debug("mpsc_sdma_stop[%d]: Stopping SDMA\n", pi->port.line);
584
585 /* Abort any SDMA transfers */
586 mpsc_sdma_cmd(pi, 0);
587 mpsc_sdma_cmd(pi, SDMA_SDCM_AR | SDMA_SDCM_AT);
588
589 /* Clear the SDMA current and first TX and RX pointers */
590 mpsc_sdma_set_tx_ring(pi, NULL);
591 mpsc_sdma_set_rx_ring(pi, NULL);
592
593 /* Disable interrupts */
594 mpsc_sdma_intr_mask(pi, 0xf);
595 mpsc_sdma_intr_ack(pi);
596
597 return;
598 }
599
600 /*
601 ******************************************************************************
602 *
603 * Multi-Protocol Serial Controller Routines (MPSC)
604 *
605 ******************************************************************************
606 */
607
608 static void
609 mpsc_hw_init(struct mpsc_port_info *pi)
610 {
611 u32 v;
612
613 pr_debug("mpsc_hw_init[%d]: Initializing hardware\n", pi->port.line);
614
615 /* Set up clock routing */
616 if (pi->mirror_regs) {
617 v = pi->shared_regs->MPSC_MRR_m;
618 v &= ~0x1c7;
619 pi->shared_regs->MPSC_MRR_m = v;
620 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR);
621
622 v = pi->shared_regs->MPSC_RCRR_m;
623 v = (v & ~0xf0f) | 0x100;
624 pi->shared_regs->MPSC_RCRR_m = v;
625 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
626
627 v = pi->shared_regs->MPSC_TCRR_m;
628 v = (v & ~0xf0f) | 0x100;
629 pi->shared_regs->MPSC_TCRR_m = v;
630 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
631 }
632 else {
633 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_MRR);
634 v &= ~0x1c7;
635 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR);
636
637 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
638 v = (v & ~0xf0f) | 0x100;
639 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
640
641 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
642 v = (v & ~0xf0f) | 0x100;
643 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
644 }
645
646 /* Put MPSC in UART mode & enabel Tx/Rx egines */
647 writel(0x000004c4, pi->mpsc_base + MPSC_MMCRL);
648
649 /* No preamble, 16x divider, low-latency, */
650 writel(0x04400400, pi->mpsc_base + MPSC_MMCRH);
651
652 if (pi->mirror_regs) {
653 pi->MPSC_CHR_1_m = 0;
654 pi->MPSC_CHR_2_m = 0;
655 }
656 writel(0, pi->mpsc_base + MPSC_CHR_1);
657 writel(0, pi->mpsc_base + MPSC_CHR_2);
658 writel(pi->mpsc_max_idle, pi->mpsc_base + MPSC_CHR_3);
659 writel(0, pi->mpsc_base + MPSC_CHR_4);
660 writel(0, pi->mpsc_base + MPSC_CHR_5);
661 writel(0, pi->mpsc_base + MPSC_CHR_6);
662 writel(0, pi->mpsc_base + MPSC_CHR_7);
663 writel(0, pi->mpsc_base + MPSC_CHR_8);
664 writel(0, pi->mpsc_base + MPSC_CHR_9);
665 writel(0, pi->mpsc_base + MPSC_CHR_10);
666
667 return;
668 }
669
670 static inline void
671 mpsc_enter_hunt(struct mpsc_port_info *pi)
672 {
673 pr_debug("mpsc_enter_hunt[%d]: Hunting...\n", pi->port.line);
674
675 if (pi->mirror_regs) {
676 writel(pi->MPSC_CHR_2_m | MPSC_CHR_2_EH,
677 pi->mpsc_base + MPSC_CHR_2);
678 /* Erratum prevents reading CHR_2 so just delay for a while */
679 udelay(100);
680 }
681 else {
682 writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_EH,
683 pi->mpsc_base + MPSC_CHR_2);
684
685 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_EH)
686 udelay(10);
687 }
688
689 return;
690 }
691
692 static inline void
693 mpsc_freeze(struct mpsc_port_info *pi)
694 {
695 u32 v;
696
697 pr_debug("mpsc_freeze[%d]: Freezing\n", pi->port.line);
698
699 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
700 readl(pi->mpsc_base + MPSC_MPCR);
701 v |= MPSC_MPCR_FRZ;
702
703 if (pi->mirror_regs)
704 pi->MPSC_MPCR_m = v;
705 writel(v, pi->mpsc_base + MPSC_MPCR);
706 return;
707 }
708
709 static inline void
710 mpsc_unfreeze(struct mpsc_port_info *pi)
711 {
712 u32 v;
713
714 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
715 readl(pi->mpsc_base + MPSC_MPCR);
716 v &= ~MPSC_MPCR_FRZ;
717
718 if (pi->mirror_regs)
719 pi->MPSC_MPCR_m = v;
720 writel(v, pi->mpsc_base + MPSC_MPCR);
721
722 pr_debug("mpsc_unfreeze[%d]: Unfrozen\n", pi->port.line);
723 return;
724 }
725
726 static inline void
727 mpsc_set_char_length(struct mpsc_port_info *pi, u32 len)
728 {
729 u32 v;
730
731 pr_debug("mpsc_set_char_length[%d]: char len: %d\n", pi->port.line,len);
732
733 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
734 readl(pi->mpsc_base + MPSC_MPCR);
735 v = (v & ~(0x3 << 12)) | ((len & 0x3) << 12);
736
737 if (pi->mirror_regs)
738 pi->MPSC_MPCR_m = v;
739 writel(v, pi->mpsc_base + MPSC_MPCR);
740 return;
741 }
742
743 static inline void
744 mpsc_set_stop_bit_length(struct mpsc_port_info *pi, u32 len)
745 {
746 u32 v;
747
748 pr_debug("mpsc_set_stop_bit_length[%d]: stop bits: %d\n",
749 pi->port.line, len);
750
751 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
752 readl(pi->mpsc_base + MPSC_MPCR);
753
754 v = (v & ~(1 << 14)) | ((len & 0x1) << 14);
755
756 if (pi->mirror_regs)
757 pi->MPSC_MPCR_m = v;
758 writel(v, pi->mpsc_base + MPSC_MPCR);
759 return;
760 }
761
762 static inline void
763 mpsc_set_parity(struct mpsc_port_info *pi, u32 p)
764 {
765 u32 v;
766
767 pr_debug("mpsc_set_parity[%d]: parity bits: 0x%x\n", pi->port.line, p);
768
769 v = (pi->mirror_regs) ? pi->MPSC_CHR_2_m :
770 readl(pi->mpsc_base + MPSC_CHR_2);
771
772 p &= 0x3;
773 v = (v & ~0xc000c) | (p << 18) | (p << 2);
774
775 if (pi->mirror_regs)
776 pi->MPSC_CHR_2_m = v;
777 writel(v, pi->mpsc_base + MPSC_CHR_2);
778 return;
779 }
780
781 /*
782 ******************************************************************************
783 *
784 * Driver Init Routines
785 *
786 ******************************************************************************
787 */
788
789 static void
790 mpsc_init_hw(struct mpsc_port_info *pi)
791 {
792 pr_debug("mpsc_init_hw[%d]: Initializing\n", pi->port.line);
793
794 mpsc_brg_init(pi, pi->brg_clk_src);
795 mpsc_brg_enable(pi);
796 mpsc_sdma_init(pi, dma_get_cache_alignment()); /* burst a cacheline */
797 mpsc_sdma_stop(pi);
798 mpsc_hw_init(pi);
799
800 return;
801 }
802
803 static int
804 mpsc_alloc_ring_mem(struct mpsc_port_info *pi)
805 {
806 int rc = 0;
807
808 pr_debug("mpsc_alloc_ring_mem[%d]: Allocating ring mem\n",
809 pi->port.line);
810
811 if (!pi->dma_region) {
812 if (!dma_supported(pi->port.dev, 0xffffffff)) {
813 printk(KERN_ERR "MPSC: Inadequate DMA support\n");
814 rc = -ENXIO;
815 }
816 else if ((pi->dma_region = dma_alloc_noncoherent(pi->port.dev,
817 MPSC_DMA_ALLOC_SIZE, &pi->dma_region_p, GFP_KERNEL))
818 == NULL) {
819
820 printk(KERN_ERR "MPSC: Can't alloc Desc region\n");
821 rc = -ENOMEM;
822 }
823 }
824
825 return rc;
826 }
827
828 static void
829 mpsc_free_ring_mem(struct mpsc_port_info *pi)
830 {
831 pr_debug("mpsc_free_ring_mem[%d]: Freeing ring mem\n", pi->port.line);
832
833 if (pi->dma_region) {
834 dma_free_noncoherent(pi->port.dev, MPSC_DMA_ALLOC_SIZE,
835 pi->dma_region, pi->dma_region_p);
836 pi->dma_region = NULL;
837 pi->dma_region_p = (dma_addr_t) NULL;
838 }
839
840 return;
841 }
842
843 static void
844 mpsc_init_rings(struct mpsc_port_info *pi)
845 {
846 struct mpsc_rx_desc *rxre;
847 struct mpsc_tx_desc *txre;
848 dma_addr_t dp, dp_p;
849 u8 *bp, *bp_p;
850 int i;
851
852 pr_debug("mpsc_init_rings[%d]: Initializing rings\n", pi->port.line);
853
854 BUG_ON(pi->dma_region == NULL);
855
856 memset(pi->dma_region, 0, MPSC_DMA_ALLOC_SIZE);
857
858 /*
859 * Descriptors & buffers are multiples of cacheline size and must be
860 * cacheline aligned.
861 */
862 dp = ALIGN((u32) pi->dma_region, dma_get_cache_alignment());
863 dp_p = ALIGN((u32) pi->dma_region_p, dma_get_cache_alignment());
864
865 /*
866 * Partition dma region into rx ring descriptor, rx buffers,
867 * tx ring descriptors, and tx buffers.
868 */
869 pi->rxr = dp;
870 pi->rxr_p = dp_p;
871 dp += MPSC_RXR_SIZE;
872 dp_p += MPSC_RXR_SIZE;
873
874 pi->rxb = (u8 *) dp;
875 pi->rxb_p = (u8 *) dp_p;
876 dp += MPSC_RXB_SIZE;
877 dp_p += MPSC_RXB_SIZE;
878
879 pi->rxr_posn = 0;
880
881 pi->txr = dp;
882 pi->txr_p = dp_p;
883 dp += MPSC_TXR_SIZE;
884 dp_p += MPSC_TXR_SIZE;
885
886 pi->txb = (u8 *) dp;
887 pi->txb_p = (u8 *) dp_p;
888
889 pi->txr_head = 0;
890 pi->txr_tail = 0;
891
892 /* Init rx ring descriptors */
893 dp = pi->rxr;
894 dp_p = pi->rxr_p;
895 bp = pi->rxb;
896 bp_p = pi->rxb_p;
897
898 for (i = 0; i < MPSC_RXR_ENTRIES; i++) {
899 rxre = (struct mpsc_rx_desc *)dp;
900
901 rxre->bufsize = cpu_to_be16(MPSC_RXBE_SIZE);
902 rxre->bytecnt = cpu_to_be16(0);
903 rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O |
904 SDMA_DESC_CMDSTAT_EI |
905 SDMA_DESC_CMDSTAT_F |
906 SDMA_DESC_CMDSTAT_L);
907 rxre->link = cpu_to_be32(dp_p + MPSC_RXRE_SIZE);
908 rxre->buf_ptr = cpu_to_be32(bp_p);
909
910 dp += MPSC_RXRE_SIZE;
911 dp_p += MPSC_RXRE_SIZE;
912 bp += MPSC_RXBE_SIZE;
913 bp_p += MPSC_RXBE_SIZE;
914 }
915 rxre->link = cpu_to_be32(pi->rxr_p); /* Wrap last back to first */
916
917 /* Init tx ring descriptors */
918 dp = pi->txr;
919 dp_p = pi->txr_p;
920 bp = pi->txb;
921 bp_p = pi->txb_p;
922
923 for (i = 0; i < MPSC_TXR_ENTRIES; i++) {
924 txre = (struct mpsc_tx_desc *)dp;
925
926 txre->link = cpu_to_be32(dp_p + MPSC_TXRE_SIZE);
927 txre->buf_ptr = cpu_to_be32(bp_p);
928
929 dp += MPSC_TXRE_SIZE;
930 dp_p += MPSC_TXRE_SIZE;
931 bp += MPSC_TXBE_SIZE;
932 bp_p += MPSC_TXBE_SIZE;
933 }
934 txre->link = cpu_to_be32(pi->txr_p); /* Wrap last back to first */
935
936 dma_cache_sync((void *) pi->dma_region, MPSC_DMA_ALLOC_SIZE,
937 DMA_BIDIRECTIONAL);
938 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
939 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
940 flush_dcache_range((ulong)pi->dma_region,
941 (ulong)pi->dma_region + MPSC_DMA_ALLOC_SIZE);
942 #endif
943
944 return;
945 }
946
947 static void
948 mpsc_uninit_rings(struct mpsc_port_info *pi)
949 {
950 pr_debug("mpsc_uninit_rings[%d]: Uninitializing rings\n",pi->port.line);
951
952 BUG_ON(pi->dma_region == NULL);
953
954 pi->rxr = 0;
955 pi->rxr_p = 0;
956 pi->rxb = NULL;
957 pi->rxb_p = NULL;
958 pi->rxr_posn = 0;
959
960 pi->txr = 0;
961 pi->txr_p = 0;
962 pi->txb = NULL;
963 pi->txb_p = NULL;
964 pi->txr_head = 0;
965 pi->txr_tail = 0;
966
967 return;
968 }
969
970 static int
971 mpsc_make_ready(struct mpsc_port_info *pi)
972 {
973 int rc;
974
975 pr_debug("mpsc_make_ready[%d]: Making cltr ready\n", pi->port.line);
976
977 if (!pi->ready) {
978 mpsc_init_hw(pi);
979 if ((rc = mpsc_alloc_ring_mem(pi)))
980 return rc;
981 mpsc_init_rings(pi);
982 pi->ready = 1;
983 }
984
985 return 0;
986 }
987
988 /*
989 ******************************************************************************
990 *
991 * Interrupt Handling Routines
992 *
993 ******************************************************************************
994 */
995
996 static inline int
997 mpsc_rx_intr(struct mpsc_port_info *pi, struct pt_regs *regs)
998 {
999 struct mpsc_rx_desc *rxre;
1000 struct tty_struct *tty = pi->port.info->tty;
1001 u32 cmdstat, bytes_in, i;
1002 int rc = 0;
1003 u8 *bp;
1004 char flag = TTY_NORMAL;
1005
1006 pr_debug("mpsc_rx_intr[%d]: Handling Rx intr\n", pi->port.line);
1007
1008 rxre = (struct mpsc_rx_desc *)(pi->rxr + (pi->rxr_posn*MPSC_RXRE_SIZE));
1009
1010 dma_cache_sync((void *)rxre, MPSC_RXRE_SIZE, DMA_FROM_DEVICE);
1011 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1012 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1013 invalidate_dcache_range((ulong)rxre,
1014 (ulong)rxre + MPSC_RXRE_SIZE);
1015 #endif
1016
1017 /*
1018 * Loop through Rx descriptors handling ones that have been completed.
1019 */
1020 while (!((cmdstat = be32_to_cpu(rxre->cmdstat)) & SDMA_DESC_CMDSTAT_O)){
1021 bytes_in = be16_to_cpu(rxre->bytecnt);
1022
1023 /* Following use of tty struct directly is deprecated */
1024 if (unlikely(tty_buffer_request_room(tty, bytes_in) < bytes_in)) {
1025 if (tty->low_latency)
1026 tty_flip_buffer_push(tty);
1027 /*
1028 * If this failed then we will throw away the bytes
1029 * but must do so to clear interrupts.
1030 */
1031 }
1032
1033 bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE);
1034 dma_cache_sync((void *) bp, MPSC_RXBE_SIZE, DMA_FROM_DEVICE);
1035 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1036 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1037 invalidate_dcache_range((ulong)bp,
1038 (ulong)bp + MPSC_RXBE_SIZE);
1039 #endif
1040
1041 /*
1042 * Other than for parity error, the manual provides little
1043 * info on what data will be in a frame flagged by any of
1044 * these errors. For parity error, it is the last byte in
1045 * the buffer that had the error. As for the rest, I guess
1046 * we'll assume there is no data in the buffer.
1047 * If there is...it gets lost.
1048 */
1049 if (unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR |
1050 SDMA_DESC_CMDSTAT_FR | SDMA_DESC_CMDSTAT_OR))) {
1051
1052 pi->port.icount.rx++;
1053
1054 if (cmdstat & SDMA_DESC_CMDSTAT_BR) { /* Break */
1055 pi->port.icount.brk++;
1056
1057 if (uart_handle_break(&pi->port))
1058 goto next_frame;
1059 }
1060 else if (cmdstat & SDMA_DESC_CMDSTAT_FR)/* Framing */
1061 pi->port.icount.frame++;
1062 else if (cmdstat & SDMA_DESC_CMDSTAT_OR) /* Overrun */
1063 pi->port.icount.overrun++;
1064
1065 cmdstat &= pi->port.read_status_mask;
1066
1067 if (cmdstat & SDMA_DESC_CMDSTAT_BR)
1068 flag = TTY_BREAK;
1069 else if (cmdstat & SDMA_DESC_CMDSTAT_FR)
1070 flag = TTY_FRAME;
1071 else if (cmdstat & SDMA_DESC_CMDSTAT_OR)
1072 flag = TTY_OVERRUN;
1073 else if (cmdstat & SDMA_DESC_CMDSTAT_PE)
1074 flag = TTY_PARITY;
1075 }
1076
1077 if (uart_handle_sysrq_char(&pi->port, *bp, regs)) {
1078 bp++;
1079 bytes_in--;
1080 goto next_frame;
1081 }
1082
1083 if ((unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR |
1084 SDMA_DESC_CMDSTAT_FR | SDMA_DESC_CMDSTAT_OR))) &&
1085 !(cmdstat & pi->port.ignore_status_mask))
1086
1087 tty_insert_flip_char(tty, *bp, flag);
1088 else {
1089 for (i=0; i<bytes_in; i++)
1090 tty_insert_flip_char(tty, *bp++, TTY_NORMAL);
1091
1092 pi->port.icount.rx += bytes_in;
1093 }
1094
1095 next_frame:
1096 rxre->bytecnt = cpu_to_be16(0);
1097 wmb();
1098 rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O |
1099 SDMA_DESC_CMDSTAT_EI |
1100 SDMA_DESC_CMDSTAT_F |
1101 SDMA_DESC_CMDSTAT_L);
1102 wmb();
1103 dma_cache_sync((void *)rxre, MPSC_RXRE_SIZE, DMA_BIDIRECTIONAL);
1104 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1105 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1106 flush_dcache_range((ulong)rxre,
1107 (ulong)rxre + MPSC_RXRE_SIZE);
1108 #endif
1109
1110 /* Advance to next descriptor */
1111 pi->rxr_posn = (pi->rxr_posn + 1) & (MPSC_RXR_ENTRIES - 1);
1112 rxre = (struct mpsc_rx_desc *)(pi->rxr +
1113 (pi->rxr_posn * MPSC_RXRE_SIZE));
1114 dma_cache_sync((void *)rxre, MPSC_RXRE_SIZE, DMA_FROM_DEVICE);
1115 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1116 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1117 invalidate_dcache_range((ulong)rxre,
1118 (ulong)rxre + MPSC_RXRE_SIZE);
1119 #endif
1120
1121 rc = 1;
1122 }
1123
1124 /* Restart rx engine, if its stopped */
1125 if ((readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_ERD) == 0)
1126 mpsc_start_rx(pi);
1127
1128 tty_flip_buffer_push(tty);
1129 return rc;
1130 }
1131
1132 static inline void
1133 mpsc_setup_tx_desc(struct mpsc_port_info *pi, u32 count, u32 intr)
1134 {
1135 struct mpsc_tx_desc *txre;
1136
1137 txre = (struct mpsc_tx_desc *)(pi->txr +
1138 (pi->txr_head * MPSC_TXRE_SIZE));
1139
1140 txre->bytecnt = cpu_to_be16(count);
1141 txre->shadow = txre->bytecnt;
1142 wmb(); /* ensure cmdstat is last field updated */
1143 txre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O | SDMA_DESC_CMDSTAT_F |
1144 SDMA_DESC_CMDSTAT_L | ((intr) ?
1145 SDMA_DESC_CMDSTAT_EI
1146 : 0));
1147 wmb();
1148 dma_cache_sync((void *) txre, MPSC_TXRE_SIZE, DMA_BIDIRECTIONAL);
1149 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1150 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1151 flush_dcache_range((ulong)txre,
1152 (ulong)txre + MPSC_TXRE_SIZE);
1153 #endif
1154
1155 return;
1156 }
1157
1158 static inline void
1159 mpsc_copy_tx_data(struct mpsc_port_info *pi)
1160 {
1161 struct circ_buf *xmit = &pi->port.info->xmit;
1162 u8 *bp;
1163 u32 i;
1164
1165 /* Make sure the desc ring isn't full */
1166 while (CIRC_CNT(pi->txr_head, pi->txr_tail, MPSC_TXR_ENTRIES) <
1167 (MPSC_TXR_ENTRIES - 1)) {
1168 if (pi->port.x_char) {
1169 /*
1170 * Ideally, we should use the TCS field in
1171 * CHR_1 to put the x_char out immediately but
1172 * errata prevents us from being able to read
1173 * CHR_2 to know that its safe to write to
1174 * CHR_1. Instead, just put it in-band with
1175 * all the other Tx data.
1176 */
1177 bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
1178 *bp = pi->port.x_char;
1179 pi->port.x_char = 0;
1180 i = 1;
1181 }
1182 else if (!uart_circ_empty(xmit) && !uart_tx_stopped(&pi->port)){
1183 i = min((u32) MPSC_TXBE_SIZE,
1184 (u32) uart_circ_chars_pending(xmit));
1185 i = min(i, (u32) CIRC_CNT_TO_END(xmit->head, xmit->tail,
1186 UART_XMIT_SIZE));
1187 bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
1188 memcpy(bp, &xmit->buf[xmit->tail], i);
1189 xmit->tail = (xmit->tail + i) & (UART_XMIT_SIZE - 1);
1190
1191 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1192 uart_write_wakeup(&pi->port);
1193 }
1194 else /* All tx data copied into ring bufs */
1195 return;
1196
1197 dma_cache_sync((void *) bp, MPSC_TXBE_SIZE, DMA_BIDIRECTIONAL);
1198 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1199 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1200 flush_dcache_range((ulong)bp,
1201 (ulong)bp + MPSC_TXBE_SIZE);
1202 #endif
1203 mpsc_setup_tx_desc(pi, i, 1);
1204
1205 /* Advance to next descriptor */
1206 pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1);
1207 }
1208
1209 return;
1210 }
1211
1212 static inline int
1213 mpsc_tx_intr(struct mpsc_port_info *pi)
1214 {
1215 struct mpsc_tx_desc *txre;
1216 int rc = 0;
1217
1218 if (!mpsc_sdma_tx_active(pi)) {
1219 txre = (struct mpsc_tx_desc *)(pi->txr +
1220 (pi->txr_tail * MPSC_TXRE_SIZE));
1221
1222 dma_cache_sync((void *) txre, MPSC_TXRE_SIZE, DMA_FROM_DEVICE);
1223 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1224 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1225 invalidate_dcache_range((ulong)txre,
1226 (ulong)txre + MPSC_TXRE_SIZE);
1227 #endif
1228
1229 while (!(be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O)) {
1230 rc = 1;
1231 pi->port.icount.tx += be16_to_cpu(txre->bytecnt);
1232 pi->txr_tail = (pi->txr_tail+1) & (MPSC_TXR_ENTRIES-1);
1233
1234 /* If no more data to tx, fall out of loop */
1235 if (pi->txr_head == pi->txr_tail)
1236 break;
1237
1238 txre = (struct mpsc_tx_desc *)(pi->txr +
1239 (pi->txr_tail * MPSC_TXRE_SIZE));
1240 dma_cache_sync((void *) txre, MPSC_TXRE_SIZE,
1241 DMA_FROM_DEVICE);
1242 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1243 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1244 invalidate_dcache_range((ulong)txre,
1245 (ulong)txre + MPSC_TXRE_SIZE);
1246 #endif
1247 }
1248
1249 mpsc_copy_tx_data(pi);
1250 mpsc_sdma_start_tx(pi); /* start next desc if ready */
1251 }
1252
1253 return rc;
1254 }
1255
1256 /*
1257 * This is the driver's interrupt handler. To avoid a race, we first clear
1258 * the interrupt, then handle any completed Rx/Tx descriptors. When done
1259 * handling those descriptors, we restart the Rx/Tx engines if they're stopped.
1260 */
1261 static irqreturn_t
1262 mpsc_sdma_intr(int irq, void *dev_id, struct pt_regs *regs)
1263 {
1264 struct mpsc_port_info *pi = dev_id;
1265 ulong iflags;
1266 int rc = IRQ_NONE;
1267
1268 pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Received\n",pi->port.line);
1269
1270 spin_lock_irqsave(&pi->port.lock, iflags);
1271 mpsc_sdma_intr_ack(pi);
1272 if (mpsc_rx_intr(pi, regs))
1273 rc = IRQ_HANDLED;
1274 if (mpsc_tx_intr(pi))
1275 rc = IRQ_HANDLED;
1276 spin_unlock_irqrestore(&pi->port.lock, iflags);
1277
1278 pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Handled\n", pi->port.line);
1279 return rc;
1280 }
1281
1282 /*
1283 ******************************************************************************
1284 *
1285 * serial_core.c Interface routines
1286 *
1287 ******************************************************************************
1288 */
1289 static uint
1290 mpsc_tx_empty(struct uart_port *port)
1291 {
1292 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1293 ulong iflags;
1294 uint rc;
1295
1296 spin_lock_irqsave(&pi->port.lock, iflags);
1297 rc = mpsc_sdma_tx_active(pi) ? 0 : TIOCSER_TEMT;
1298 spin_unlock_irqrestore(&pi->port.lock, iflags);
1299
1300 return rc;
1301 }
1302
1303 static void
1304 mpsc_set_mctrl(struct uart_port *port, uint mctrl)
1305 {
1306 /* Have no way to set modem control lines AFAICT */
1307 return;
1308 }
1309
1310 static uint
1311 mpsc_get_mctrl(struct uart_port *port)
1312 {
1313 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1314 u32 mflags, status;
1315
1316 status = (pi->mirror_regs) ? pi->MPSC_CHR_10_m :
1317 readl(pi->mpsc_base + MPSC_CHR_10);
1318
1319 mflags = 0;
1320 if (status & 0x1)
1321 mflags |= TIOCM_CTS;
1322 if (status & 0x2)
1323 mflags |= TIOCM_CAR;
1324
1325 return mflags | TIOCM_DSR; /* No way to tell if DSR asserted */
1326 }
1327
1328 static void
1329 mpsc_stop_tx(struct uart_port *port)
1330 {
1331 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1332
1333 pr_debug("mpsc_stop_tx[%d]\n", port->line);
1334
1335 mpsc_freeze(pi);
1336 return;
1337 }
1338
1339 static void
1340 mpsc_start_tx(struct uart_port *port)
1341 {
1342 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1343
1344 mpsc_unfreeze(pi);
1345 mpsc_copy_tx_data(pi);
1346 mpsc_sdma_start_tx(pi);
1347
1348 pr_debug("mpsc_start_tx[%d]\n", port->line);
1349 return;
1350 }
1351
1352 static void
1353 mpsc_start_rx(struct mpsc_port_info *pi)
1354 {
1355 pr_debug("mpsc_start_rx[%d]: Starting...\n", pi->port.line);
1356
1357 /* Issue a Receive Abort to clear any receive errors */
1358 writel(MPSC_CHR_2_RA, pi->mpsc_base + MPSC_CHR_2);
1359 if (pi->rcv_data) {
1360 mpsc_enter_hunt(pi);
1361 mpsc_sdma_cmd(pi, SDMA_SDCM_ERD);
1362 }
1363 return;
1364 }
1365
1366 static void
1367 mpsc_stop_rx(struct uart_port *port)
1368 {
1369 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1370
1371 pr_debug("mpsc_stop_rx[%d]: Stopping...\n", port->line);
1372
1373 mpsc_sdma_cmd(pi, SDMA_SDCM_AR);
1374 return;
1375 }
1376
1377 static void
1378 mpsc_enable_ms(struct uart_port *port)
1379 {
1380 return; /* Not supported */
1381 }
1382
1383 static void
1384 mpsc_break_ctl(struct uart_port *port, int ctl)
1385 {
1386 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1387 ulong flags;
1388 u32 v;
1389
1390 v = ctl ? 0x00ff0000 : 0;
1391
1392 spin_lock_irqsave(&pi->port.lock, flags);
1393 if (pi->mirror_regs)
1394 pi->MPSC_CHR_1_m = v;
1395 writel(v, pi->mpsc_base + MPSC_CHR_1);
1396 spin_unlock_irqrestore(&pi->port.lock, flags);
1397
1398 return;
1399 }
1400
1401 static int
1402 mpsc_startup(struct uart_port *port)
1403 {
1404 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1405 u32 flag = 0;
1406 int rc;
1407
1408 pr_debug("mpsc_startup[%d]: Starting up MPSC, irq: %d\n",
1409 port->line, pi->port.irq);
1410
1411 if ((rc = mpsc_make_ready(pi)) == 0) {
1412 /* Setup IRQ handler */
1413 mpsc_sdma_intr_ack(pi);
1414
1415 /* If irq's are shared, need to set flag */
1416 if (mpsc_ports[0].port.irq == mpsc_ports[1].port.irq)
1417 flag = SA_SHIRQ;
1418
1419 if (request_irq(pi->port.irq, mpsc_sdma_intr, flag,
1420 "mpsc-sdma", pi))
1421 printk(KERN_ERR "MPSC: Can't get SDMA IRQ %d\n",
1422 pi->port.irq);
1423
1424 mpsc_sdma_intr_unmask(pi, 0xf);
1425 mpsc_sdma_set_rx_ring(pi, (struct mpsc_rx_desc *)(pi->rxr_p +
1426 (pi->rxr_posn * MPSC_RXRE_SIZE)));
1427 }
1428
1429 return rc;
1430 }
1431
1432 static void
1433 mpsc_shutdown(struct uart_port *port)
1434 {
1435 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1436
1437 pr_debug("mpsc_shutdown[%d]: Shutting down MPSC\n", port->line);
1438
1439 mpsc_sdma_stop(pi);
1440 free_irq(pi->port.irq, pi);
1441 return;
1442 }
1443
1444 static void
1445 mpsc_set_termios(struct uart_port *port, struct termios *termios,
1446 struct termios *old)
1447 {
1448 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1449 u32 baud;
1450 ulong flags;
1451 u32 chr_bits, stop_bits, par;
1452
1453 pi->c_iflag = termios->c_iflag;
1454 pi->c_cflag = termios->c_cflag;
1455
1456 switch (termios->c_cflag & CSIZE) {
1457 case CS5:
1458 chr_bits = MPSC_MPCR_CL_5;
1459 break;
1460 case CS6:
1461 chr_bits = MPSC_MPCR_CL_6;
1462 break;
1463 case CS7:
1464 chr_bits = MPSC_MPCR_CL_7;
1465 break;
1466 case CS8:
1467 default:
1468 chr_bits = MPSC_MPCR_CL_8;
1469 break;
1470 }
1471
1472 if (termios->c_cflag & CSTOPB)
1473 stop_bits = MPSC_MPCR_SBL_2;
1474 else
1475 stop_bits = MPSC_MPCR_SBL_1;
1476
1477 par = MPSC_CHR_2_PAR_EVEN;
1478 if (termios->c_cflag & PARENB)
1479 if (termios->c_cflag & PARODD)
1480 par = MPSC_CHR_2_PAR_ODD;
1481 #ifdef CMSPAR
1482 if (termios->c_cflag & CMSPAR) {
1483 if (termios->c_cflag & PARODD)
1484 par = MPSC_CHR_2_PAR_MARK;
1485 else
1486 par = MPSC_CHR_2_PAR_SPACE;
1487 }
1488 #endif
1489
1490 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk);
1491
1492 spin_lock_irqsave(&pi->port.lock, flags);
1493
1494 uart_update_timeout(port, termios->c_cflag, baud);
1495
1496 mpsc_set_char_length(pi, chr_bits);
1497 mpsc_set_stop_bit_length(pi, stop_bits);
1498 mpsc_set_parity(pi, par);
1499 mpsc_set_baudrate(pi, baud);
1500
1501 /* Characters/events to read */
1502 pi->rcv_data = 1;
1503 pi->port.read_status_mask = SDMA_DESC_CMDSTAT_OR;
1504
1505 if (termios->c_iflag & INPCK)
1506 pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_PE |
1507 SDMA_DESC_CMDSTAT_FR;
1508
1509 if (termios->c_iflag & (BRKINT | PARMRK))
1510 pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_BR;
1511
1512 /* Characters/events to ignore */
1513 pi->port.ignore_status_mask = 0;
1514
1515 if (termios->c_iflag & IGNPAR)
1516 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_PE |
1517 SDMA_DESC_CMDSTAT_FR;
1518
1519 if (termios->c_iflag & IGNBRK) {
1520 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_BR;
1521
1522 if (termios->c_iflag & IGNPAR)
1523 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_OR;
1524 }
1525
1526 /* Ignore all chars if CREAD not set */
1527 if (!(termios->c_cflag & CREAD))
1528 pi->rcv_data = 0;
1529 else
1530 mpsc_start_rx(pi);
1531
1532 spin_unlock_irqrestore(&pi->port.lock, flags);
1533 return;
1534 }
1535
1536 static const char *
1537 mpsc_type(struct uart_port *port)
1538 {
1539 pr_debug("mpsc_type[%d]: port type: %s\n", port->line,MPSC_DRIVER_NAME);
1540 return MPSC_DRIVER_NAME;
1541 }
1542
1543 static int
1544 mpsc_request_port(struct uart_port *port)
1545 {
1546 /* Should make chip/platform specific call */
1547 return 0;
1548 }
1549
1550 static void
1551 mpsc_release_port(struct uart_port *port)
1552 {
1553 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1554
1555 if (pi->ready) {
1556 mpsc_uninit_rings(pi);
1557 mpsc_free_ring_mem(pi);
1558 pi->ready = 0;
1559 }
1560
1561 return;
1562 }
1563
1564 static void
1565 mpsc_config_port(struct uart_port *port, int flags)
1566 {
1567 return;
1568 }
1569
1570 static int
1571 mpsc_verify_port(struct uart_port *port, struct serial_struct *ser)
1572 {
1573 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1574 int rc = 0;
1575
1576 pr_debug("mpsc_verify_port[%d]: Verifying port data\n", pi->port.line);
1577
1578 if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPSC)
1579 rc = -EINVAL;
1580 else if (pi->port.irq != ser->irq)
1581 rc = -EINVAL;
1582 else if (ser->io_type != SERIAL_IO_MEM)
1583 rc = -EINVAL;
1584 else if (pi->port.uartclk / 16 != ser->baud_base) /* Not sure */
1585 rc = -EINVAL;
1586 else if ((void *)pi->port.mapbase != ser->iomem_base)
1587 rc = -EINVAL;
1588 else if (pi->port.iobase != ser->port)
1589 rc = -EINVAL;
1590 else if (ser->hub6 != 0)
1591 rc = -EINVAL;
1592
1593 return rc;
1594 }
1595
1596 static struct uart_ops mpsc_pops = {
1597 .tx_empty = mpsc_tx_empty,
1598 .set_mctrl = mpsc_set_mctrl,
1599 .get_mctrl = mpsc_get_mctrl,
1600 .stop_tx = mpsc_stop_tx,
1601 .start_tx = mpsc_start_tx,
1602 .stop_rx = mpsc_stop_rx,
1603 .enable_ms = mpsc_enable_ms,
1604 .break_ctl = mpsc_break_ctl,
1605 .startup = mpsc_startup,
1606 .shutdown = mpsc_shutdown,
1607 .set_termios = mpsc_set_termios,
1608 .type = mpsc_type,
1609 .release_port = mpsc_release_port,
1610 .request_port = mpsc_request_port,
1611 .config_port = mpsc_config_port,
1612 .verify_port = mpsc_verify_port,
1613 };
1614
1615 /*
1616 ******************************************************************************
1617 *
1618 * Console Interface Routines
1619 *
1620 ******************************************************************************
1621 */
1622
1623 #ifdef CONFIG_SERIAL_MPSC_CONSOLE
1624 static void
1625 mpsc_console_write(struct console *co, const char *s, uint count)
1626 {
1627 struct mpsc_port_info *pi = &mpsc_ports[co->index];
1628 u8 *bp, *dp, add_cr = 0;
1629 int i;
1630
1631 while (mpsc_sdma_tx_active(pi))
1632 udelay(100);
1633
1634 while (count > 0) {
1635 bp = dp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
1636
1637 for (i = 0; i < MPSC_TXBE_SIZE; i++) {
1638 if (count == 0)
1639 break;
1640
1641 if (add_cr) {
1642 *(dp++) = '\r';
1643 add_cr = 0;
1644 }
1645 else {
1646 *(dp++) = *s;
1647
1648 if (*(s++) == '\n') { /* add '\r' after '\n' */
1649 add_cr = 1;
1650 count++;
1651 }
1652 }
1653
1654 count--;
1655 }
1656
1657 dma_cache_sync((void *) bp, MPSC_TXBE_SIZE, DMA_BIDIRECTIONAL);
1658 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1659 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1660 flush_dcache_range((ulong)bp,
1661 (ulong)bp + MPSC_TXBE_SIZE);
1662 #endif
1663 mpsc_setup_tx_desc(pi, i, 0);
1664 pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1);
1665 mpsc_sdma_start_tx(pi);
1666
1667 while (mpsc_sdma_tx_active(pi))
1668 udelay(100);
1669
1670 pi->txr_tail = (pi->txr_tail + 1) & (MPSC_TXR_ENTRIES - 1);
1671 }
1672
1673 return;
1674 }
1675
1676 static int __init
1677 mpsc_console_setup(struct console *co, char *options)
1678 {
1679 struct mpsc_port_info *pi;
1680 int baud, bits, parity, flow;
1681
1682 pr_debug("mpsc_console_setup[%d]: options: %s\n", co->index, options);
1683
1684 if (co->index >= MPSC_NUM_CTLRS)
1685 co->index = 0;
1686
1687 pi = &mpsc_ports[co->index];
1688
1689 baud = pi->default_baud;
1690 bits = pi->default_bits;
1691 parity = pi->default_parity;
1692 flow = pi->default_flow;
1693
1694 if (!pi->port.ops)
1695 return -ENODEV;
1696
1697 spin_lock_init(&pi->port.lock); /* Temporary fix--copied from 8250.c */
1698
1699 if (options)
1700 uart_parse_options(options, &baud, &parity, &bits, &flow);
1701
1702 return uart_set_options(&pi->port, co, baud, parity, bits, flow);
1703 }
1704
1705 static struct console mpsc_console = {
1706 .name = MPSC_DEV_NAME,
1707 .write = mpsc_console_write,
1708 .device = uart_console_device,
1709 .setup = mpsc_console_setup,
1710 .flags = CON_PRINTBUFFER,
1711 .index = -1,
1712 .data = &mpsc_reg,
1713 };
1714
1715 static int __init
1716 mpsc_late_console_init(void)
1717 {
1718 pr_debug("mpsc_late_console_init: Enter\n");
1719
1720 if (!(mpsc_console.flags & CON_ENABLED))
1721 register_console(&mpsc_console);
1722 return 0;
1723 }
1724
1725 late_initcall(mpsc_late_console_init);
1726
1727 #define MPSC_CONSOLE &mpsc_console
1728 #else
1729 #define MPSC_CONSOLE NULL
1730 #endif
1731 /*
1732 ******************************************************************************
1733 *
1734 * Dummy Platform Driver to extract & map shared register regions
1735 *
1736 ******************************************************************************
1737 */
1738 static void
1739 mpsc_resource_err(char *s)
1740 {
1741 printk(KERN_WARNING "MPSC: Platform device resource error in %s\n", s);
1742 return;
1743 }
1744
1745 static int
1746 mpsc_shared_map_regs(struct platform_device *pd)
1747 {
1748 struct resource *r;
1749
1750 if ((r = platform_get_resource(pd, IORESOURCE_MEM,
1751 MPSC_ROUTING_BASE_ORDER)) && request_mem_region(r->start,
1752 MPSC_ROUTING_REG_BLOCK_SIZE, "mpsc_routing_regs")) {
1753
1754 mpsc_shared_regs.mpsc_routing_base = ioremap(r->start,
1755 MPSC_ROUTING_REG_BLOCK_SIZE);
1756 mpsc_shared_regs.mpsc_routing_base_p = r->start;
1757 }
1758 else {
1759 mpsc_resource_err("MPSC routing base");
1760 return -ENOMEM;
1761 }
1762
1763 if ((r = platform_get_resource(pd, IORESOURCE_MEM,
1764 MPSC_SDMA_INTR_BASE_ORDER)) && request_mem_region(r->start,
1765 MPSC_SDMA_INTR_REG_BLOCK_SIZE, "sdma_intr_regs")) {
1766
1767 mpsc_shared_regs.sdma_intr_base = ioremap(r->start,
1768 MPSC_SDMA_INTR_REG_BLOCK_SIZE);
1769 mpsc_shared_regs.sdma_intr_base_p = r->start;
1770 }
1771 else {
1772 iounmap(mpsc_shared_regs.mpsc_routing_base);
1773 release_mem_region(mpsc_shared_regs.mpsc_routing_base_p,
1774 MPSC_ROUTING_REG_BLOCK_SIZE);
1775 mpsc_resource_err("SDMA intr base");
1776 return -ENOMEM;
1777 }
1778
1779 return 0;
1780 }
1781
1782 static void
1783 mpsc_shared_unmap_regs(void)
1784 {
1785 if (!mpsc_shared_regs.mpsc_routing_base) {
1786 iounmap(mpsc_shared_regs.mpsc_routing_base);
1787 release_mem_region(mpsc_shared_regs.mpsc_routing_base_p,
1788 MPSC_ROUTING_REG_BLOCK_SIZE);
1789 }
1790 if (!mpsc_shared_regs.sdma_intr_base) {
1791 iounmap(mpsc_shared_regs.sdma_intr_base);
1792 release_mem_region(mpsc_shared_regs.sdma_intr_base_p,
1793 MPSC_SDMA_INTR_REG_BLOCK_SIZE);
1794 }
1795
1796 mpsc_shared_regs.mpsc_routing_base = NULL;
1797 mpsc_shared_regs.sdma_intr_base = NULL;
1798
1799 mpsc_shared_regs.mpsc_routing_base_p = 0;
1800 mpsc_shared_regs.sdma_intr_base_p = 0;
1801
1802 return;
1803 }
1804
1805 static int
1806 mpsc_shared_drv_probe(struct platform_device *dev)
1807 {
1808 struct mpsc_shared_pdata *pdata;
1809 int rc = -ENODEV;
1810
1811 if (dev->id == 0) {
1812 if (!(rc = mpsc_shared_map_regs(dev))) {
1813 pdata = (struct mpsc_shared_pdata *)dev->dev.platform_data;
1814
1815 mpsc_shared_regs.MPSC_MRR_m = pdata->mrr_val;
1816 mpsc_shared_regs.MPSC_RCRR_m= pdata->rcrr_val;
1817 mpsc_shared_regs.MPSC_TCRR_m= pdata->tcrr_val;
1818 mpsc_shared_regs.SDMA_INTR_CAUSE_m =
1819 pdata->intr_cause_val;
1820 mpsc_shared_regs.SDMA_INTR_MASK_m =
1821 pdata->intr_mask_val;
1822
1823 rc = 0;
1824 }
1825 }
1826
1827 return rc;
1828 }
1829
1830 static int
1831 mpsc_shared_drv_remove(struct platform_device *dev)
1832 {
1833 int rc = -ENODEV;
1834
1835 if (dev->id == 0) {
1836 mpsc_shared_unmap_regs();
1837 mpsc_shared_regs.MPSC_MRR_m = 0;
1838 mpsc_shared_regs.MPSC_RCRR_m = 0;
1839 mpsc_shared_regs.MPSC_TCRR_m = 0;
1840 mpsc_shared_regs.SDMA_INTR_CAUSE_m = 0;
1841 mpsc_shared_regs.SDMA_INTR_MASK_m = 0;
1842 rc = 0;
1843 }
1844
1845 return rc;
1846 }
1847
1848 static struct platform_driver mpsc_shared_driver = {
1849 .probe = mpsc_shared_drv_probe,
1850 .remove = mpsc_shared_drv_remove,
1851 .driver = {
1852 .name = MPSC_SHARED_NAME,
1853 },
1854 };
1855
1856 /*
1857 ******************************************************************************
1858 *
1859 * Driver Interface Routines
1860 *
1861 ******************************************************************************
1862 */
1863 static struct uart_driver mpsc_reg = {
1864 .owner = THIS_MODULE,
1865 .driver_name = MPSC_DRIVER_NAME,
1866 .devfs_name = MPSC_DEVFS_NAME,
1867 .dev_name = MPSC_DEV_NAME,
1868 .major = MPSC_MAJOR,
1869 .minor = MPSC_MINOR_START,
1870 .nr = MPSC_NUM_CTLRS,
1871 .cons = MPSC_CONSOLE,
1872 };
1873
1874 static int
1875 mpsc_drv_map_regs(struct mpsc_port_info *pi, struct platform_device *pd)
1876 {
1877 struct resource *r;
1878
1879 if ((r = platform_get_resource(pd, IORESOURCE_MEM, MPSC_BASE_ORDER)) &&
1880 request_mem_region(r->start, MPSC_REG_BLOCK_SIZE, "mpsc_regs")){
1881
1882 pi->mpsc_base = ioremap(r->start, MPSC_REG_BLOCK_SIZE);
1883 pi->mpsc_base_p = r->start;
1884 }
1885 else {
1886 mpsc_resource_err("MPSC base");
1887 return -ENOMEM;
1888 }
1889
1890 if ((r = platform_get_resource(pd, IORESOURCE_MEM,
1891 MPSC_SDMA_BASE_ORDER)) && request_mem_region(r->start,
1892 MPSC_SDMA_REG_BLOCK_SIZE, "sdma_regs")) {
1893
1894 pi->sdma_base = ioremap(r->start,MPSC_SDMA_REG_BLOCK_SIZE);
1895 pi->sdma_base_p = r->start;
1896 }
1897 else {
1898 mpsc_resource_err("SDMA base");
1899 return -ENOMEM;
1900 }
1901
1902 if ((r = platform_get_resource(pd,IORESOURCE_MEM,MPSC_BRG_BASE_ORDER))
1903 && request_mem_region(r->start, MPSC_BRG_REG_BLOCK_SIZE,
1904 "brg_regs")) {
1905
1906 pi->brg_base = ioremap(r->start, MPSC_BRG_REG_BLOCK_SIZE);
1907 pi->brg_base_p = r->start;
1908 }
1909 else {
1910 mpsc_resource_err("BRG base");
1911 return -ENOMEM;
1912 }
1913
1914 return 0;
1915 }
1916
1917 static void
1918 mpsc_drv_unmap_regs(struct mpsc_port_info *pi)
1919 {
1920 if (!pi->mpsc_base) {
1921 iounmap(pi->mpsc_base);
1922 release_mem_region(pi->mpsc_base_p, MPSC_REG_BLOCK_SIZE);
1923 }
1924 if (!pi->sdma_base) {
1925 iounmap(pi->sdma_base);
1926 release_mem_region(pi->sdma_base_p, MPSC_SDMA_REG_BLOCK_SIZE);
1927 }
1928 if (!pi->brg_base) {
1929 iounmap(pi->brg_base);
1930 release_mem_region(pi->brg_base_p, MPSC_BRG_REG_BLOCK_SIZE);
1931 }
1932
1933 pi->mpsc_base = NULL;
1934 pi->sdma_base = NULL;
1935 pi->brg_base = NULL;
1936
1937 pi->mpsc_base_p = 0;
1938 pi->sdma_base_p = 0;
1939 pi->brg_base_p = 0;
1940
1941 return;
1942 }
1943
1944 static void
1945 mpsc_drv_get_platform_data(struct mpsc_port_info *pi,
1946 struct platform_device *pd, int num)
1947 {
1948 struct mpsc_pdata *pdata;
1949
1950 pdata = (struct mpsc_pdata *)pd->dev.platform_data;
1951
1952 pi->port.uartclk = pdata->brg_clk_freq;
1953 pi->port.iotype = UPIO_MEM;
1954 pi->port.line = num;
1955 pi->port.type = PORT_MPSC;
1956 pi->port.fifosize = MPSC_TXBE_SIZE;
1957 pi->port.membase = pi->mpsc_base;
1958 pi->port.mapbase = (ulong)pi->mpsc_base;
1959 pi->port.ops = &mpsc_pops;
1960
1961 pi->mirror_regs = pdata->mirror_regs;
1962 pi->cache_mgmt = pdata->cache_mgmt;
1963 pi->brg_can_tune = pdata->brg_can_tune;
1964 pi->brg_clk_src = pdata->brg_clk_src;
1965 pi->mpsc_max_idle = pdata->max_idle;
1966 pi->default_baud = pdata->default_baud;
1967 pi->default_bits = pdata->default_bits;
1968 pi->default_parity = pdata->default_parity;
1969 pi->default_flow = pdata->default_flow;
1970
1971 /* Initial values of mirrored regs */
1972 pi->MPSC_CHR_1_m = pdata->chr_1_val;
1973 pi->MPSC_CHR_2_m = pdata->chr_2_val;
1974 pi->MPSC_CHR_10_m = pdata->chr_10_val;
1975 pi->MPSC_MPCR_m = pdata->mpcr_val;
1976 pi->BRG_BCR_m = pdata->bcr_val;
1977
1978 pi->shared_regs = &mpsc_shared_regs;
1979
1980 pi->port.irq = platform_get_irq(pd, 0);
1981
1982 return;
1983 }
1984
1985 static int
1986 mpsc_drv_probe(struct platform_device *dev)
1987 {
1988 struct mpsc_port_info *pi;
1989 int rc = -ENODEV;
1990
1991 pr_debug("mpsc_drv_probe: Adding MPSC %d\n", dev->id);
1992
1993 if (dev->id < MPSC_NUM_CTLRS) {
1994 pi = &mpsc_ports[dev->id];
1995
1996 if (!(rc = mpsc_drv_map_regs(pi, dev))) {
1997 mpsc_drv_get_platform_data(pi, dev, dev->id);
1998
1999 if (!(rc = mpsc_make_ready(pi)))
2000 if (!(rc = uart_add_one_port(&mpsc_reg,
2001 &pi->port)))
2002 rc = 0;
2003 else {
2004 mpsc_release_port(
2005 (struct uart_port *)pi);
2006 mpsc_drv_unmap_regs(pi);
2007 }
2008 else
2009 mpsc_drv_unmap_regs(pi);
2010 }
2011 }
2012
2013 return rc;
2014 }
2015
2016 static int
2017 mpsc_drv_remove(struct platform_device *dev)
2018 {
2019 pr_debug("mpsc_drv_exit: Removing MPSC %d\n", dev->id);
2020
2021 if (dev->id < MPSC_NUM_CTLRS) {
2022 uart_remove_one_port(&mpsc_reg, &mpsc_ports[dev->id].port);
2023 mpsc_release_port((struct uart_port *)&mpsc_ports[dev->id].port);
2024 mpsc_drv_unmap_regs(&mpsc_ports[dev->id]);
2025 return 0;
2026 }
2027 else
2028 return -ENODEV;
2029 }
2030
2031 static struct platform_driver mpsc_driver = {
2032 .probe = mpsc_drv_probe,
2033 .remove = mpsc_drv_remove,
2034 .driver = {
2035 .name = MPSC_CTLR_NAME,
2036 },
2037 };
2038
2039 static int __init
2040 mpsc_drv_init(void)
2041 {
2042 int rc;
2043
2044 printk(KERN_INFO "Serial: MPSC driver $Revision: 1.00 $\n");
2045
2046 memset(mpsc_ports, 0, sizeof(mpsc_ports));
2047 memset(&mpsc_shared_regs, 0, sizeof(mpsc_shared_regs));
2048
2049 if (!(rc = uart_register_driver(&mpsc_reg))) {
2050 if (!(rc = platform_driver_register(&mpsc_shared_driver))) {
2051 if ((rc = platform_driver_register(&mpsc_driver))) {
2052 platform_driver_unregister(&mpsc_shared_driver);
2053 uart_unregister_driver(&mpsc_reg);
2054 }
2055 }
2056 else
2057 uart_unregister_driver(&mpsc_reg);
2058 }
2059
2060 return rc;
2061
2062 }
2063
2064 static void __exit
2065 mpsc_drv_exit(void)
2066 {
2067 platform_driver_unregister(&mpsc_driver);
2068 platform_driver_unregister(&mpsc_shared_driver);
2069 uart_unregister_driver(&mpsc_reg);
2070 memset(mpsc_ports, 0, sizeof(mpsc_ports));
2071 memset(&mpsc_shared_regs, 0, sizeof(mpsc_shared_regs));
2072 return;
2073 }
2074
2075 module_init(mpsc_drv_init);
2076 module_exit(mpsc_drv_exit);
2077
2078 MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
2079 MODULE_DESCRIPTION("Generic Marvell MPSC serial/UART driver $Revision: 1.00 $");
2080 MODULE_VERSION(MPSC_VERSION);
2081 MODULE_LICENSE("GPL");
2082 MODULE_ALIAS_CHARDEV_MAJOR(MPSC_MAJOR);
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