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[PATCH] w1: Make w1 connector notifications depend on connector.
[linux-2.6/verdex.git] / drivers / video / aty / aty128fb.c
blobf7bbff4ddc6afcb06dc82ef812c716fb1281d62a
1 /* $Id: aty128fb.c,v 1.1.1.1.36.1 1999/12/11 09:03:05 Exp $
2 * linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128
3 *
4 * Copyright (C) 1999-2003, Brad Douglas <brad@neruo.com>
5 * Copyright (C) 1999, Anthony Tong <atong@uiuc.edu>
6 *
7 * Ani Joshi / Jeff Garzik
8 * - Code cleanup
9 *
10 * Michel Danzer <michdaen@iiic.ethz.ch>
11 * - 15/16 bit cleanup
12 * - fix panning
13 *
14 * Benjamin Herrenschmidt
15 * - pmac-specific PM stuff
16 * - various fixes & cleanups
17 *
18 * Andreas Hundt <andi@convergence.de>
19 * - FB_ACTIVATE fixes
20 *
21 * Paul Mackerras <paulus@samba.org>
22 * - Convert to new framebuffer API,
23 * fix colormap setting at 16 bits/pixel (565)
24 *
25 * Paul Mundt
26 * - PCI hotplug
27 *
28 * Jon Smirl <jonsmirl@yahoo.com>
29 * - PCI ID update
30 * - replace ROM BIOS search
31 *
32 * Based off of Geert's atyfb.c and vfb.c.
33 *
34 * TODO:
35 * - monitor sensing (DDC)
36 * - virtual display
37 * - other platform support (only ppc/x86 supported)
38 * - hardware cursor support
39 *
40 * Please cc: your patches to brad@neruo.com.
41 */
42
43 /*
44 * A special note of gratitude to ATI's devrel for providing documentation,
45 * example code and hardware. Thanks Nitya. -atong and brad
46 */
47
48
49 #include <linux/config.h>
50 #include <linux/module.h>
51 #include <linux/moduleparam.h>
52 #include <linux/kernel.h>
53 #include <linux/errno.h>
54 #include <linux/string.h>
55 #include <linux/mm.h>
56 #include <linux/tty.h>
57 #include <linux/slab.h>
58 #include <linux/vmalloc.h>
59 #include <linux/delay.h>
60 #include <linux/interrupt.h>
61 #include <asm/uaccess.h>
62 #include <linux/fb.h>
63 #include <linux/init.h>
64 #include <linux/pci.h>
65 #include <linux/ioport.h>
66 #include <linux/console.h>
67 #include <asm/io.h>
68
69 #ifdef CONFIG_PPC_PMAC
70 #include <asm/machdep.h>
71 #include <asm/pmac_feature.h>
72 #include <asm/prom.h>
73 #include <asm/pci-bridge.h>
74 #include "../macmodes.h"
75 #endif
76
77 #ifdef CONFIG_PMAC_BACKLIGHT
78 #include <asm/backlight.h>
79 #endif
80
81 #ifdef CONFIG_BOOTX_TEXT
82 #include <asm/btext.h>
83 #endif /* CONFIG_BOOTX_TEXT */
84
85 #ifdef CONFIG_MTRR
86 #include <asm/mtrr.h>
87 #endif
88
89 #include <video/aty128.h>
90
91 /* Debug flag */
92 #undef DEBUG
93
94 #ifdef DEBUG
95 #define DBG(fmt, args...) printk(KERN_DEBUG "aty128fb: %s " fmt, __FUNCTION__, ##args);
96 #else
97 #define DBG(fmt, args...)
98 #endif
99
100 #ifndef CONFIG_PPC_PMAC
101 /* default mode */
102 static struct fb_var_screeninfo default_var __initdata = {
103 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
104 640, 480, 640, 480, 0, 0, 8, 0,
105 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
106 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
107 0, FB_VMODE_NONINTERLACED
108 };
109
110 #else /* CONFIG_PPC_PMAC */
111 /* default to 1024x768 at 75Hz on PPC - this will work
112 * on the iMac, the usual 640x480 @ 60Hz doesn't. */
113 static struct fb_var_screeninfo default_var = {
114 /* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */
115 1024, 768, 1024, 768, 0, 0, 8, 0,
116 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
117 0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3,
118 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
119 FB_VMODE_NONINTERLACED
120 };
121 #endif /* CONFIG_PPC_PMAC */
122
123 /* default modedb mode */
124 /* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */
125 static struct fb_videomode defaultmode __initdata = {
126 .refresh = 60,
127 .xres = 640,
128 .yres = 480,
129 .pixclock = 39722,
130 .left_margin = 48,
131 .right_margin = 16,
132 .upper_margin = 33,
133 .lower_margin = 10,
134 .hsync_len = 96,
135 .vsync_len = 2,
136 .sync = 0,
137 .vmode = FB_VMODE_NONINTERLACED
138 };
139
140 /* Chip generations */
141 enum {
142 rage_128,
143 rage_128_pci,
144 rage_128_pro,
145 rage_128_pro_pci,
146 rage_M3,
147 rage_M3_pci,
148 rage_M4,
149 rage_128_ultra,
150 };
151
152 /* Must match above enum */
153 static const char *r128_family[] __devinitdata = {
154 "AGP",
155 "PCI",
156 "PRO AGP",
157 "PRO PCI",
158 "M3 AGP",
159 "M3 PCI",
160 "M4 AGP",
161 "Ultra AGP",
162 };
163
164 /*
165 * PCI driver prototypes
166 */
167 static int aty128_probe(struct pci_dev *pdev,
168 const struct pci_device_id *ent);
169 static void aty128_remove(struct pci_dev *pdev);
170 static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state);
171 static int aty128_pci_resume(struct pci_dev *pdev);
172 static int aty128_do_resume(struct pci_dev *pdev);
173
174 /* supported Rage128 chipsets */
175 static struct pci_device_id aty128_pci_tbl[] = {
176 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LE,
177 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3_pci },
178 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LF,
179 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3 },
180 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_MF,
181 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
182 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_ML,
183 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
184 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PA,
185 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
186 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PB,
187 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
188 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PC,
189 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
190 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PD,
191 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
192 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PE,
193 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
194 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PF,
195 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
196 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PG,
197 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
198 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PH,
199 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
200 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PI,
201 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
202 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PJ,
203 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
204 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PK,
205 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
206 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PL,
207 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
208 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PM,
209 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
210 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PN,
211 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
212 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PO,
213 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
214 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PP,
215 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
216 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PQ,
217 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
218 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PR,
219 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
220 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PS,
221 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
222 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PT,
223 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
224 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PU,
225 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
226 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PV,
227 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
228 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PW,
229 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
230 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PX,
231 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
232 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RE,
233 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
234 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RF,
235 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
236 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RG,
237 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
238 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RK,
239 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
240 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RL,
241 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
242 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SE,
243 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
244 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SF,
245 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
246 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SG,
247 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
248 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SH,
249 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
250 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SK,
251 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
252 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SL,
253 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
254 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SM,
255 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
256 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SN,
257 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
258 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TF,
259 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
260 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TL,
261 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
262 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TR,
263 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
264 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TS,
265 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
266 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TT,
267 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
268 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TU,
269 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
270 { 0, }
271 };
272
273 MODULE_DEVICE_TABLE(pci, aty128_pci_tbl);
274
275 static struct pci_driver aty128fb_driver = {
276 .name = "aty128fb",
277 .id_table = aty128_pci_tbl,
278 .probe = aty128_probe,
279 .remove = __devexit_p(aty128_remove),
280 .suspend = aty128_pci_suspend,
281 .resume = aty128_pci_resume,
282 };
283
284 /* packed BIOS settings */
285 #ifndef CONFIG_PPC
286 typedef struct {
287 u8 clock_chip_type;
288 u8 struct_size;
289 u8 accelerator_entry;
290 u8 VGA_entry;
291 u16 VGA_table_offset;
292 u16 POST_table_offset;
293 u16 XCLK;
294 u16 MCLK;
295 u8 num_PLL_blocks;
296 u8 size_PLL_blocks;
297 u16 PCLK_ref_freq;
298 u16 PCLK_ref_divider;
299 u32 PCLK_min_freq;
300 u32 PCLK_max_freq;
301 u16 MCLK_ref_freq;
302 u16 MCLK_ref_divider;
303 u32 MCLK_min_freq;
304 u32 MCLK_max_freq;
305 u16 XCLK_ref_freq;
306 u16 XCLK_ref_divider;
307 u32 XCLK_min_freq;
308 u32 XCLK_max_freq;
309 } __attribute__ ((packed)) PLL_BLOCK;
310 #endif /* !CONFIG_PPC */
311
312 /* onboard memory information */
313 struct aty128_meminfo {
314 u8 ML;
315 u8 MB;
316 u8 Trcd;
317 u8 Trp;
318 u8 Twr;
319 u8 CL;
320 u8 Tr2w;
321 u8 LoopLatency;
322 u8 DspOn;
323 u8 Rloop;
324 const char *name;
325 };
326
327 /* various memory configurations */
328 static const struct aty128_meminfo sdr_128 =
329 { 4, 4, 3, 3, 1, 3, 1, 16, 30, 16, "128-bit SDR SGRAM (1:1)" };
330 static const struct aty128_meminfo sdr_64 =
331 { 4, 8, 3, 3, 1, 3, 1, 17, 46, 17, "64-bit SDR SGRAM (1:1)" };
332 static const struct aty128_meminfo sdr_sgram =
333 { 4, 4, 1, 2, 1, 2, 1, 16, 24, 16, "64-bit SDR SGRAM (2:1)" };
334 static const struct aty128_meminfo ddr_sgram =
335 { 4, 4, 3, 3, 2, 3, 1, 16, 31, 16, "64-bit DDR SGRAM" };
336
337 static struct fb_fix_screeninfo aty128fb_fix __initdata = {
338 .id = "ATY Rage128",
339 .type = FB_TYPE_PACKED_PIXELS,
340 .visual = FB_VISUAL_PSEUDOCOLOR,
341 .xpanstep = 8,
342 .ypanstep = 1,
343 .mmio_len = 0x2000,
344 .accel = FB_ACCEL_ATI_RAGE128,
345 };
346
347 static char *mode_option __initdata = NULL;
348
349 #ifdef CONFIG_PPC_PMAC
350 static int default_vmode __initdata = VMODE_1024_768_60;
351 static int default_cmode __initdata = CMODE_8;
352 #endif
353
354 static int default_crt_on __initdata = 0;
355 static int default_lcd_on __initdata = 1;
356
357 #ifdef CONFIG_MTRR
358 static int mtrr = 1;
359 #endif
360
361 /* PLL constants */
362 struct aty128_constants {
363 u32 ref_clk;
364 u32 ppll_min;
365 u32 ppll_max;
366 u32 ref_divider;
367 u32 xclk;
368 u32 fifo_width;
369 u32 fifo_depth;
370 };
371
372 struct aty128_crtc {
373 u32 gen_cntl;
374 u32 h_total, h_sync_strt_wid;
375 u32 v_total, v_sync_strt_wid;
376 u32 pitch;
377 u32 offset, offset_cntl;
378 u32 xoffset, yoffset;
379 u32 vxres, vyres;
380 u32 depth, bpp;
381 };
382
383 struct aty128_pll {
384 u32 post_divider;
385 u32 feedback_divider;
386 u32 vclk;
387 };
388
389 struct aty128_ddafifo {
390 u32 dda_config;
391 u32 dda_on_off;
392 };
393
394 /* register values for a specific mode */
395 struct aty128fb_par {
396 struct aty128_crtc crtc;
397 struct aty128_pll pll;
398 struct aty128_ddafifo fifo_reg;
399 u32 accel_flags;
400 struct aty128_constants constants; /* PLL and others */
401 void __iomem *regbase; /* remapped mmio */
402 u32 vram_size; /* onboard video ram */
403 int chip_gen;
404 const struct aty128_meminfo *mem; /* onboard mem info */
405 #ifdef CONFIG_MTRR
406 struct { int vram; int vram_valid; } mtrr;
407 #endif
408 int blitter_may_be_busy;
409 int fifo_slots; /* free slots in FIFO (64 max) */
410
411 int pm_reg;
412 int crt_on, lcd_on;
413 struct pci_dev *pdev;
414 struct fb_info *next;
415 int asleep;
416 int lock_blank;
417
418 u8 red[32]; /* see aty128fb_setcolreg */
419 u8 green[64];
420 u8 blue[32];
421 u32 pseudo_palette[16]; /* used for TRUECOLOR */
422 };
423
424
425 #define round_div(n, d) ((n+(d/2))/d)
426
427 static int aty128fb_check_var(struct fb_var_screeninfo *var,
428 struct fb_info *info);
429 static int aty128fb_set_par(struct fb_info *info);
430 static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
431 u_int transp, struct fb_info *info);
432 static int aty128fb_pan_display(struct fb_var_screeninfo *var,
433 struct fb_info *fb);
434 static int aty128fb_blank(int blank, struct fb_info *fb);
435 static int aty128fb_ioctl(struct fb_info *info, u_int cmd, unsigned long arg);
436 static int aty128fb_sync(struct fb_info *info);
437
438 /*
439 * Internal routines
440 */
441
442 static int aty128_encode_var(struct fb_var_screeninfo *var,
443 const struct aty128fb_par *par);
444 static int aty128_decode_var(struct fb_var_screeninfo *var,
445 struct aty128fb_par *par);
446 #if 0
447 static void __init aty128_get_pllinfo(struct aty128fb_par *par,
448 void __iomem *bios);
449 static void __init __iomem *aty128_map_ROM(struct pci_dev *pdev, const struct aty128fb_par *par);
450 #endif
451 static void aty128_timings(struct aty128fb_par *par);
452 static void aty128_init_engine(struct aty128fb_par *par);
453 static void aty128_reset_engine(const struct aty128fb_par *par);
454 static void aty128_flush_pixel_cache(const struct aty128fb_par *par);
455 static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par);
456 static void wait_for_fifo(u16 entries, struct aty128fb_par *par);
457 static void wait_for_idle(struct aty128fb_par *par);
458 static u32 depth_to_dst(u32 depth);
459
460 #define BIOS_IN8(v) (readb(bios + (v)))
461 #define BIOS_IN16(v) (readb(bios + (v)) | \
462 (readb(bios + (v) + 1) << 8))
463 #define BIOS_IN32(v) (readb(bios + (v)) | \
464 (readb(bios + (v) + 1) << 8) | \
465 (readb(bios + (v) + 2) << 16) | \
466 (readb(bios + (v) + 3) << 24))
467
468
469 static struct fb_ops aty128fb_ops = {
470 .owner = THIS_MODULE,
471 .fb_check_var = aty128fb_check_var,
472 .fb_set_par = aty128fb_set_par,
473 .fb_setcolreg = aty128fb_setcolreg,
474 .fb_pan_display = aty128fb_pan_display,
475 .fb_blank = aty128fb_blank,
476 .fb_ioctl = aty128fb_ioctl,
477 .fb_sync = aty128fb_sync,
478 .fb_fillrect = cfb_fillrect,
479 .fb_copyarea = cfb_copyarea,
480 .fb_imageblit = cfb_imageblit,
481 };
482
483 #ifdef CONFIG_PMAC_BACKLIGHT
484 static int aty128_set_backlight_enable(int on, int level, void* data);
485 static int aty128_set_backlight_level(int level, void* data);
486
487 static struct backlight_controller aty128_backlight_controller = {
488 aty128_set_backlight_enable,
489 aty128_set_backlight_level
490 };
491 #endif /* CONFIG_PMAC_BACKLIGHT */
492
493 /*
494 * Functions to read from/write to the mmio registers
495 * - endian conversions may possibly be avoided by
496 * using the other register aperture. TODO.
497 */
498 static inline u32 _aty_ld_le32(volatile unsigned int regindex,
499 const struct aty128fb_par *par)
500 {
501 return readl (par->regbase + regindex);
502 }
503
504 static inline void _aty_st_le32(volatile unsigned int regindex, u32 val,
505 const struct aty128fb_par *par)
506 {
507 writel (val, par->regbase + regindex);
508 }
509
510 static inline u8 _aty_ld_8(unsigned int regindex,
511 const struct aty128fb_par *par)
512 {
513 return readb (par->regbase + regindex);
514 }
515
516 static inline void _aty_st_8(unsigned int regindex, u8 val,
517 const struct aty128fb_par *par)
518 {
519 writeb (val, par->regbase + regindex);
520 }
521
522 #define aty_ld_le32(regindex) _aty_ld_le32(regindex, par)
523 #define aty_st_le32(regindex, val) _aty_st_le32(regindex, val, par)
524 #define aty_ld_8(regindex) _aty_ld_8(regindex, par)
525 #define aty_st_8(regindex, val) _aty_st_8(regindex, val, par)
526
527 /*
528 * Functions to read from/write to the pll registers
529 */
530
531 #define aty_ld_pll(pll_index) _aty_ld_pll(pll_index, par)
532 #define aty_st_pll(pll_index, val) _aty_st_pll(pll_index, val, par)
533
534
535 static u32 _aty_ld_pll(unsigned int pll_index,
536 const struct aty128fb_par *par)
537 {
538 aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x3F);
539 return aty_ld_le32(CLOCK_CNTL_DATA);
540 }
541
542
543 static void _aty_st_pll(unsigned int pll_index, u32 val,
544 const struct aty128fb_par *par)
545 {
546 aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN);
547 aty_st_le32(CLOCK_CNTL_DATA, val);
548 }
549
550
551 /* return true when the PLL has completed an atomic update */
552 static int aty_pll_readupdate(const struct aty128fb_par *par)
553 {
554 return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R);
555 }
556
557
558 static void aty_pll_wait_readupdate(const struct aty128fb_par *par)
559 {
560 unsigned long timeout = jiffies + HZ/100; // should be more than enough
561 int reset = 1;
562
563 while (time_before(jiffies, timeout))
564 if (aty_pll_readupdate(par)) {
565 reset = 0;
566 break;
567 }
568
569 if (reset) /* reset engine?? */
570 printk(KERN_DEBUG "aty128fb: PLL write timeout!\n");
571 }
572
573
574 /* tell PLL to update */
575 static void aty_pll_writeupdate(const struct aty128fb_par *par)
576 {
577 aty_pll_wait_readupdate(par);
578
579 aty_st_pll(PPLL_REF_DIV,
580 aty_ld_pll(PPLL_REF_DIV) | PPLL_ATOMIC_UPDATE_W);
581 }
582
583
584 /* write to the scratch register to test r/w functionality */
585 static int __init register_test(const struct aty128fb_par *par)
586 {
587 u32 val;
588 int flag = 0;
589
590 val = aty_ld_le32(BIOS_0_SCRATCH);
591
592 aty_st_le32(BIOS_0_SCRATCH, 0x55555555);
593 if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) {
594 aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA);
595
596 if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA)
597 flag = 1;
598 }
599
600 aty_st_le32(BIOS_0_SCRATCH, val); // restore value
601 return flag;
602 }
603
604
605 /*
606 * Accelerator engine functions
607 */
608 static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par)
609 {
610 int i;
611
612 for (;;) {
613 for (i = 0; i < 2000000; i++) {
614 par->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff;
615 if (par->fifo_slots >= entries)
616 return;
617 }
618 aty128_reset_engine(par);
619 }
620 }
621
622
623 static void wait_for_idle(struct aty128fb_par *par)
624 {
625 int i;
626
627 do_wait_for_fifo(64, par);
628
629 for (;;) {
630 for (i = 0; i < 2000000; i++) {
631 if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) {
632 aty128_flush_pixel_cache(par);
633 par->blitter_may_be_busy = 0;
634 return;
635 }
636 }
637 aty128_reset_engine(par);
638 }
639 }
640
641
642 static void wait_for_fifo(u16 entries, struct aty128fb_par *par)
643 {
644 if (par->fifo_slots < entries)
645 do_wait_for_fifo(64, par);
646 par->fifo_slots -= entries;
647 }
648
649
650 static void aty128_flush_pixel_cache(const struct aty128fb_par *par)
651 {
652 int i;
653 u32 tmp;
654
655 tmp = aty_ld_le32(PC_NGUI_CTLSTAT);
656 tmp &= ~(0x00ff);
657 tmp |= 0x00ff;
658 aty_st_le32(PC_NGUI_CTLSTAT, tmp);
659
660 for (i = 0; i < 2000000; i++)
661 if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY))
662 break;
663 }
664
665
666 static void aty128_reset_engine(const struct aty128fb_par *par)
667 {
668 u32 gen_reset_cntl, clock_cntl_index, mclk_cntl;
669
670 aty128_flush_pixel_cache(par);
671
672 clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX);
673 mclk_cntl = aty_ld_pll(MCLK_CNTL);
674
675 aty_st_pll(MCLK_CNTL, mclk_cntl | 0x00030000);
676
677 gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL);
678 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI);
679 aty_ld_le32(GEN_RESET_CNTL);
680 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl & ~(SOFT_RESET_GUI));
681 aty_ld_le32(GEN_RESET_CNTL);
682
683 aty_st_pll(MCLK_CNTL, mclk_cntl);
684 aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index);
685 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl);
686
687 /* use old pio mode */
688 aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4);
689
690 DBG("engine reset");
691 }
692
693
694 static void aty128_init_engine(struct aty128fb_par *par)
695 {
696 u32 pitch_value;
697
698 wait_for_idle(par);
699
700 /* 3D scaler not spoken here */
701 wait_for_fifo(1, par);
702 aty_st_le32(SCALE_3D_CNTL, 0x00000000);
703
704 aty128_reset_engine(par);
705
706 pitch_value = par->crtc.pitch;
707 if (par->crtc.bpp == 24) {
708 pitch_value = pitch_value * 3;
709 }
710
711 wait_for_fifo(4, par);
712 /* setup engine offset registers */
713 aty_st_le32(DEFAULT_OFFSET, 0x00000000);
714
715 /* setup engine pitch registers */
716 aty_st_le32(DEFAULT_PITCH, pitch_value);
717
718 /* set the default scissor register to max dimensions */
719 aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF);
720
721 /* set the drawing controls registers */
722 aty_st_le32(DP_GUI_MASTER_CNTL,
723 GMC_SRC_PITCH_OFFSET_DEFAULT |
724 GMC_DST_PITCH_OFFSET_DEFAULT |
725 GMC_SRC_CLIP_DEFAULT |
726 GMC_DST_CLIP_DEFAULT |
727 GMC_BRUSH_SOLIDCOLOR |
728 (depth_to_dst(par->crtc.depth) << 8) |
729 GMC_SRC_DSTCOLOR |
730 GMC_BYTE_ORDER_MSB_TO_LSB |
731 GMC_DP_CONVERSION_TEMP_6500 |
732 ROP3_PATCOPY |
733 GMC_DP_SRC_RECT |
734 GMC_3D_FCN_EN_CLR |
735 GMC_DST_CLR_CMP_FCN_CLEAR |
736 GMC_AUX_CLIP_CLEAR |
737 GMC_WRITE_MASK_SET);
738
739 wait_for_fifo(8, par);
740 /* clear the line drawing registers */
741 aty_st_le32(DST_BRES_ERR, 0);
742 aty_st_le32(DST_BRES_INC, 0);
743 aty_st_le32(DST_BRES_DEC, 0);
744
745 /* set brush color registers */
746 aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */
747 aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */
748
749 /* set source color registers */
750 aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF); /* white */
751 aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000); /* black */
752
753 /* default write mask */
754 aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF);
755
756 /* Wait for all the writes to be completed before returning */
757 wait_for_idle(par);
758 }
759
760
761 /* convert depth values to their register representation */
762 static u32 depth_to_dst(u32 depth)
763 {
764 if (depth <= 8)
765 return DST_8BPP;
766 else if (depth <= 15)
767 return DST_15BPP;
768 else if (depth == 16)
769 return DST_16BPP;
770 else if (depth <= 24)
771 return DST_24BPP;
772 else if (depth <= 32)
773 return DST_32BPP;
774
775 return -EINVAL;
776 }
777
778 /*
779 * PLL informations retreival
780 */
781
782
783 #ifndef __sparc__
784 static void __iomem * __init aty128_map_ROM(const struct aty128fb_par *par, struct pci_dev *dev)
785 {
786 u16 dptr;
787 u8 rom_type;
788 void __iomem *bios;
789 size_t rom_size;
790
791 /* Fix from ATI for problem with Rage128 hardware not leaving ROM enabled */
792 unsigned int temp;
793 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
794 temp &= 0x00ffffffu;
795 temp |= 0x04 << 24;
796 aty_st_le32(RAGE128_MPP_TB_CONFIG, temp);
797 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
798
799 bios = pci_map_rom(dev, &rom_size);
800
801 if (!bios) {
802 printk(KERN_ERR "aty128fb: ROM failed to map\n");
803 return NULL;
804 }
805
806 /* Very simple test to make sure it appeared */
807 if (BIOS_IN16(0) != 0xaa55) {
808 printk(KERN_DEBUG "aty128fb: Invalid ROM signature %x should "
809 " be 0xaa55\n", BIOS_IN16(0));
810 goto failed;
811 }
812
813 /* Look for the PCI data to check the ROM type */
814 dptr = BIOS_IN16(0x18);
815
816 /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
817 * for now, until I've verified this works everywhere. The goal here is more
818 * to phase out Open Firmware images.
819 *
820 * Currently, we only look at the first PCI data, we could iteratre and deal with
821 * them all, and we should use fb_bios_start relative to start of image and not
822 * relative start of ROM, but so far, I never found a dual-image ATI card
823 *
824 * typedef struct {
825 * u32 signature; + 0x00
826 * u16 vendor; + 0x04
827 * u16 device; + 0x06
828 * u16 reserved_1; + 0x08
829 * u16 dlen; + 0x0a
830 * u8 drevision; + 0x0c
831 * u8 class_hi; + 0x0d
832 * u16 class_lo; + 0x0e
833 * u16 ilen; + 0x10
834 * u16 irevision; + 0x12
835 * u8 type; + 0x14
836 * u8 indicator; + 0x15
837 * u16 reserved_2; + 0x16
838 * } pci_data_t;
839 */
840 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
841 printk(KERN_WARNING "aty128fb: PCI DATA signature in ROM incorrect: %08x\n",
842 BIOS_IN32(dptr));
843 goto anyway;
844 }
845 rom_type = BIOS_IN8(dptr + 0x14);
846 switch(rom_type) {
847 case 0:
848 printk(KERN_INFO "aty128fb: Found Intel x86 BIOS ROM Image\n");
849 break;
850 case 1:
851 printk(KERN_INFO "aty128fb: Found Open Firmware ROM Image\n");
852 goto failed;
853 case 2:
854 printk(KERN_INFO "aty128fb: Found HP PA-RISC ROM Image\n");
855 goto failed;
856 default:
857 printk(KERN_INFO "aty128fb: Found unknown type %d ROM Image\n", rom_type);
858 goto failed;
859 }
860 anyway:
861 return bios;
862
863 failed:
864 pci_unmap_rom(dev, bios);
865 return NULL;
866 }
867
868 static void __init aty128_get_pllinfo(struct aty128fb_par *par, unsigned char __iomem *bios)
869 {
870 unsigned int bios_hdr;
871 unsigned int bios_pll;
872
873 bios_hdr = BIOS_IN16(0x48);
874 bios_pll = BIOS_IN16(bios_hdr + 0x30);
875
876 par->constants.ppll_max = BIOS_IN32(bios_pll + 0x16);
877 par->constants.ppll_min = BIOS_IN32(bios_pll + 0x12);
878 par->constants.xclk = BIOS_IN16(bios_pll + 0x08);
879 par->constants.ref_divider = BIOS_IN16(bios_pll + 0x10);
880 par->constants.ref_clk = BIOS_IN16(bios_pll + 0x0e);
881
882 DBG("ppll_max %d ppll_min %d xclk %d ref_divider %d ref clock %d\n",
883 par->constants.ppll_max, par->constants.ppll_min,
884 par->constants.xclk, par->constants.ref_divider,
885 par->constants.ref_clk);
886
887 }
888
889 #ifdef CONFIG_X86
890 static void __iomem * __devinit aty128_find_mem_vbios(struct aty128fb_par *par)
891 {
892 /* I simplified this code as we used to miss the signatures in
893 * a lot of case. It's now closer to XFree, we just don't check
894 * for signatures at all... Something better will have to be done
895 * if we end up having conflicts
896 */
897 u32 segstart;
898 unsigned char __iomem *rom_base = NULL;
899
900 for (segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
901 rom_base = ioremap(segstart, 0x10000);
902 if (rom_base == NULL)
903 return NULL;
904 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
905 break;
906 iounmap(rom_base);
907 rom_base = NULL;
908 }
909 return rom_base;
910 }
911 #endif
912 #endif /* ndef(__sparc__) */
913
914 /* fill in known card constants if pll_block is not available */
915 static void __init aty128_timings(struct aty128fb_par *par)
916 {
917 #ifdef CONFIG_PPC_OF
918 /* instead of a table lookup, assume OF has properly
919 * setup the PLL registers and use their values
920 * to set the XCLK values and reference divider values */
921
922 u32 x_mpll_ref_fb_div;
923 u32 xclk_cntl;
924 u32 Nx, M;
925 unsigned PostDivSet[] = { 0, 1, 2, 4, 8, 3, 6, 12 };
926 #endif
927
928 if (!par->constants.ref_clk)
929 par->constants.ref_clk = 2950;
930
931 #ifdef CONFIG_PPC_OF
932 x_mpll_ref_fb_div = aty_ld_pll(X_MPLL_REF_FB_DIV);
933 xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7;
934 Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8;
935 M = x_mpll_ref_fb_div & 0x0000ff;
936
937 par->constants.xclk = round_div((2 * Nx * par->constants.ref_clk),
938 (M * PostDivSet[xclk_cntl]));
939
940 par->constants.ref_divider =
941 aty_ld_pll(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
942 #endif
943
944 if (!par->constants.ref_divider) {
945 par->constants.ref_divider = 0x3b;
946
947 aty_st_pll(X_MPLL_REF_FB_DIV, 0x004c4c1e);
948 aty_pll_writeupdate(par);
949 }
950 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider);
951 aty_pll_writeupdate(par);
952
953 /* from documentation */
954 if (!par->constants.ppll_min)
955 par->constants.ppll_min = 12500;
956 if (!par->constants.ppll_max)
957 par->constants.ppll_max = 25000; /* 23000 on some cards? */
958 if (!par->constants.xclk)
959 par->constants.xclk = 0x1d4d; /* same as mclk */
960
961 par->constants.fifo_width = 128;
962 par->constants.fifo_depth = 32;
963
964 switch (aty_ld_le32(MEM_CNTL) & 0x3) {
965 case 0:
966 par->mem = &sdr_128;
967 break;
968 case 1:
969 par->mem = &sdr_sgram;
970 break;
971 case 2:
972 par->mem = &ddr_sgram;
973 break;
974 default:
975 par->mem = &sdr_sgram;
976 }
977 }
978
979
980
981 /*
982 * CRTC programming
983 */
984
985 /* Program the CRTC registers */
986 static void aty128_set_crtc(const struct aty128_crtc *crtc,
987 const struct aty128fb_par *par)
988 {
989 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl);
990 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total);
991 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid);
992 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total);
993 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid);
994 aty_st_le32(CRTC_PITCH, crtc->pitch);
995 aty_st_le32(CRTC_OFFSET, crtc->offset);
996 aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl);
997 /* Disable ATOMIC updating. Is this the right place? */
998 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~(0x00030000));
999 }
1000
1001
1002 static int aty128_var_to_crtc(const struct fb_var_screeninfo *var,
1003 struct aty128_crtc *crtc,
1004 const struct aty128fb_par *par)
1005 {
1006 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp, dst;
1007 u32 left, right, upper, lower, hslen, vslen, sync, vmode;
1008 u32 h_total, h_disp, h_sync_strt, h_sync_wid, h_sync_pol;
1009 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1010 u32 depth, bytpp;
1011 u8 mode_bytpp[7] = { 0, 0, 1, 2, 2, 3, 4 };
1012
1013 /* input */
1014 xres = var->xres;
1015 yres = var->yres;
1016 vxres = var->xres_virtual;
1017 vyres = var->yres_virtual;
1018 xoffset = var->xoffset;
1019 yoffset = var->yoffset;
1020 bpp = var->bits_per_pixel;
1021 left = var->left_margin;
1022 right = var->right_margin;
1023 upper = var->upper_margin;
1024 lower = var->lower_margin;
1025 hslen = var->hsync_len;
1026 vslen = var->vsync_len;
1027 sync = var->sync;
1028 vmode = var->vmode;
1029
1030 if (bpp != 16)
1031 depth = bpp;
1032 else
1033 depth = (var->green.length == 6) ? 16 : 15;
1034
1035 /* check for mode eligibility
1036 * accept only non interlaced modes */
1037 if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
1038 return -EINVAL;
1039
1040 /* convert (and round up) and validate */
1041 xres = (xres + 7) & ~7;
1042 xoffset = (xoffset + 7) & ~7;
1043
1044 if (vxres < xres + xoffset)
1045 vxres = xres + xoffset;
1046
1047 if (vyres < yres + yoffset)
1048 vyres = yres + yoffset;
1049
1050 /* convert depth into ATI register depth */
1051 dst = depth_to_dst(depth);
1052
1053 if (dst == -EINVAL) {
1054 printk(KERN_ERR "aty128fb: Invalid depth or RGBA\n");
1055 return -EINVAL;
1056 }
1057
1058 /* convert register depth to bytes per pixel */
1059 bytpp = mode_bytpp[dst];
1060
1061 /* make sure there is enough video ram for the mode */
1062 if ((u32)(vxres * vyres * bytpp) > par->vram_size) {
1063 printk(KERN_ERR "aty128fb: Not enough memory for mode\n");
1064 return -EINVAL;
1065 }
1066
1067 h_disp = (xres >> 3) - 1;
1068 h_total = (((xres + right + hslen + left) >> 3) - 1) & 0xFFFFL;
1069
1070 v_disp = yres - 1;
1071 v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL;
1072
1073 /* check to make sure h_total and v_total are in range */
1074 if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) {
1075 printk(KERN_ERR "aty128fb: invalid width ranges\n");
1076 return -EINVAL;
1077 }
1078
1079 h_sync_wid = (hslen + 7) >> 3;
1080 if (h_sync_wid == 0)
1081 h_sync_wid = 1;
1082 else if (h_sync_wid > 0x3f) /* 0x3f = max hwidth */
1083 h_sync_wid = 0x3f;
1084
1085 h_sync_strt = (h_disp << 3) + right;
1086
1087 v_sync_wid = vslen;
1088 if (v_sync_wid == 0)
1089 v_sync_wid = 1;
1090 else if (v_sync_wid > 0x1f) /* 0x1f = max vwidth */
1091 v_sync_wid = 0x1f;
1092
1093 v_sync_strt = v_disp + lower;
1094
1095 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1096 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1097
1098 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1099
1100 crtc->gen_cntl = 0x3000000L | c_sync | (dst << 8);
1101
1102 crtc->h_total = h_total | (h_disp << 16);
1103 crtc->v_total = v_total | (v_disp << 16);
1104
1105 crtc->h_sync_strt_wid = h_sync_strt | (h_sync_wid << 16) |
1106 (h_sync_pol << 23);
1107 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) |
1108 (v_sync_pol << 23);
1109
1110 crtc->pitch = vxres >> 3;
1111
1112 crtc->offset = 0;
1113
1114 if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
1115 crtc->offset_cntl = 0x00010000;
1116 else
1117 crtc->offset_cntl = 0;
1118
1119 crtc->vxres = vxres;
1120 crtc->vyres = vyres;
1121 crtc->xoffset = xoffset;
1122 crtc->yoffset = yoffset;
1123 crtc->depth = depth;
1124 crtc->bpp = bpp;
1125
1126 return 0;
1127 }
1128
1129
1130 static int aty128_pix_width_to_var(int pix_width, struct fb_var_screeninfo *var)
1131 {
1132
1133 /* fill in pixel info */
1134 var->red.msb_right = 0;
1135 var->green.msb_right = 0;
1136 var->blue.offset = 0;
1137 var->blue.msb_right = 0;
1138 var->transp.offset = 0;
1139 var->transp.length = 0;
1140 var->transp.msb_right = 0;
1141 switch (pix_width) {
1142 case CRTC_PIX_WIDTH_8BPP:
1143 var->bits_per_pixel = 8;
1144 var->red.offset = 0;
1145 var->red.length = 8;
1146 var->green.offset = 0;
1147 var->green.length = 8;
1148 var->blue.length = 8;
1149 break;
1150 case CRTC_PIX_WIDTH_15BPP:
1151 var->bits_per_pixel = 16;
1152 var->red.offset = 10;
1153 var->red.length = 5;
1154 var->green.offset = 5;
1155 var->green.length = 5;
1156 var->blue.length = 5;
1157 break;
1158 case CRTC_PIX_WIDTH_16BPP:
1159 var->bits_per_pixel = 16;
1160 var->red.offset = 11;
1161 var->red.length = 5;
1162 var->green.offset = 5;
1163 var->green.length = 6;
1164 var->blue.length = 5;
1165 break;
1166 case CRTC_PIX_WIDTH_24BPP:
1167 var->bits_per_pixel = 24;
1168 var->red.offset = 16;
1169 var->red.length = 8;
1170 var->green.offset = 8;
1171 var->green.length = 8;
1172 var->blue.length = 8;
1173 break;
1174 case CRTC_PIX_WIDTH_32BPP:
1175 var->bits_per_pixel = 32;
1176 var->red.offset = 16;
1177 var->red.length = 8;
1178 var->green.offset = 8;
1179 var->green.length = 8;
1180 var->blue.length = 8;
1181 var->transp.offset = 24;
1182 var->transp.length = 8;
1183 break;
1184 default:
1185 printk(KERN_ERR "aty128fb: Invalid pixel width\n");
1186 return -EINVAL;
1187 }
1188
1189 return 0;
1190 }
1191
1192
1193 static int aty128_crtc_to_var(const struct aty128_crtc *crtc,
1194 struct fb_var_screeninfo *var)
1195 {
1196 u32 xres, yres, left, right, upper, lower, hslen, vslen, sync;
1197 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
1198 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1199 u32 pix_width;
1200
1201 /* fun with masking */
1202 h_total = crtc->h_total & 0x1ff;
1203 h_disp = (crtc->h_total >> 16) & 0xff;
1204 h_sync_strt = (crtc->h_sync_strt_wid >> 3) & 0x1ff;
1205 h_sync_dly = crtc->h_sync_strt_wid & 0x7;
1206 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x3f;
1207 h_sync_pol = (crtc->h_sync_strt_wid >> 23) & 0x1;
1208 v_total = crtc->v_total & 0x7ff;
1209 v_disp = (crtc->v_total >> 16) & 0x7ff;
1210 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1211 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1212 v_sync_pol = (crtc->v_sync_strt_wid >> 23) & 0x1;
1213 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1214 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1215
1216 /* do conversions */
1217 xres = (h_disp + 1) << 3;
1218 yres = v_disp + 1;
1219 left = ((h_total - h_sync_strt - h_sync_wid) << 3) - h_sync_dly;
1220 right = ((h_sync_strt - h_disp) << 3) + h_sync_dly;
1221 hslen = h_sync_wid << 3;
1222 upper = v_total - v_sync_strt - v_sync_wid;
1223 lower = v_sync_strt - v_disp;
1224 vslen = v_sync_wid;
1225 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1226 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1227 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1228
1229 aty128_pix_width_to_var(pix_width, var);
1230
1231 var->xres = xres;
1232 var->yres = yres;
1233 var->xres_virtual = crtc->vxres;
1234 var->yres_virtual = crtc->vyres;
1235 var->xoffset = crtc->xoffset;
1236 var->yoffset = crtc->yoffset;
1237 var->left_margin = left;
1238 var->right_margin = right;
1239 var->upper_margin = upper;
1240 var->lower_margin = lower;
1241 var->hsync_len = hslen;
1242 var->vsync_len = vslen;
1243 var->sync = sync;
1244 var->vmode = FB_VMODE_NONINTERLACED;
1245
1246 return 0;
1247 }
1248
1249 static void aty128_set_crt_enable(struct aty128fb_par *par, int on)
1250 {
1251 if (on) {
1252 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) | CRT_CRTC_ON);
1253 aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) | DAC_PALETTE2_SNOOP_EN));
1254 } else
1255 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) & ~CRT_CRTC_ON);
1256 }
1257
1258 static void aty128_set_lcd_enable(struct aty128fb_par *par, int on)
1259 {
1260 u32 reg;
1261
1262 if (on) {
1263 reg = aty_ld_le32(LVDS_GEN_CNTL);
1264 reg |= LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION;
1265 reg &= ~LVDS_DISPLAY_DIS;
1266 aty_st_le32(LVDS_GEN_CNTL, reg);
1267 #ifdef CONFIG_PMAC_BACKLIGHT
1268 aty128_set_backlight_enable(get_backlight_enable(),
1269 get_backlight_level(), par);
1270 #endif
1271 } else {
1272 #ifdef CONFIG_PMAC_BACKLIGHT
1273 aty128_set_backlight_enable(0, 0, par);
1274 #endif
1275 reg = aty_ld_le32(LVDS_GEN_CNTL);
1276 reg |= LVDS_DISPLAY_DIS;
1277 aty_st_le32(LVDS_GEN_CNTL, reg);
1278 mdelay(100);
1279 reg &= ~(LVDS_ON /*| LVDS_EN*/);
1280 aty_st_le32(LVDS_GEN_CNTL, reg);
1281 }
1282 }
1283
1284 static void aty128_set_pll(struct aty128_pll *pll, const struct aty128fb_par *par)
1285 {
1286 u32 div3;
1287
1288 unsigned char post_conv[] = /* register values for post dividers */
1289 { 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 };
1290
1291 /* select PPLL_DIV_3 */
1292 aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8));
1293
1294 /* reset PLL */
1295 aty_st_pll(PPLL_CNTL,
1296 aty_ld_pll(PPLL_CNTL) | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN);
1297
1298 /* write the reference divider */
1299 aty_pll_wait_readupdate(par);
1300 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider & 0x3ff);
1301 aty_pll_writeupdate(par);
1302
1303 div3 = aty_ld_pll(PPLL_DIV_3);
1304 div3 &= ~PPLL_FB3_DIV_MASK;
1305 div3 |= pll->feedback_divider;
1306 div3 &= ~PPLL_POST3_DIV_MASK;
1307 div3 |= post_conv[pll->post_divider] << 16;
1308
1309 /* write feedback and post dividers */
1310 aty_pll_wait_readupdate(par);
1311 aty_st_pll(PPLL_DIV_3, div3);
1312 aty_pll_writeupdate(par);
1313
1314 aty_pll_wait_readupdate(par);
1315 aty_st_pll(HTOTAL_CNTL, 0); /* no horiz crtc adjustment */
1316 aty_pll_writeupdate(par);
1317
1318 /* clear the reset, just in case */
1319 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~PPLL_RESET);
1320 }
1321
1322
1323 static int aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll,
1324 const struct aty128fb_par *par)
1325 {
1326 const struct aty128_constants c = par->constants;
1327 unsigned char post_dividers[] = {1,2,4,8,3,6,12};
1328 u32 output_freq;
1329 u32 vclk; /* in .01 MHz */
1330 int i = 0;
1331 u32 n, d;
1332
1333 vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */
1334
1335 /* adjust pixel clock if necessary */
1336 if (vclk > c.ppll_max)
1337 vclk = c.ppll_max;
1338 if (vclk * 12 < c.ppll_min)
1339 vclk = c.ppll_min/12;
1340
1341 /* now, find an acceptable divider */
1342 for (i = 0; i < sizeof(post_dividers); i++) {
1343 output_freq = post_dividers[i] * vclk;
1344 if (output_freq >= c.ppll_min && output_freq <= c.ppll_max) {
1345 pll->post_divider = post_dividers[i];
1346 break;
1347 }
1348 }
1349
1350 /* calculate feedback divider */
1351 n = c.ref_divider * output_freq;
1352 d = c.ref_clk;
1353
1354 pll->feedback_divider = round_div(n, d);
1355 pll->vclk = vclk;
1356
1357 DBG("post %d feedback %d vlck %d output %d ref_divider %d "
1358 "vclk_per: %d\n", pll->post_divider,
1359 pll->feedback_divider, vclk, output_freq,
1360 c.ref_divider, period_in_ps);
1361
1362 return 0;
1363 }
1364
1365
1366 static int aty128_pll_to_var(const struct aty128_pll *pll, struct fb_var_screeninfo *var)
1367 {
1368 var->pixclock = 100000000 / pll->vclk;
1369
1370 return 0;
1371 }
1372
1373
1374 static void aty128_set_fifo(const struct aty128_ddafifo *dsp,
1375 const struct aty128fb_par *par)
1376 {
1377 aty_st_le32(DDA_CONFIG, dsp->dda_config);
1378 aty_st_le32(DDA_ON_OFF, dsp->dda_on_off);
1379 }
1380
1381
1382 static int aty128_ddafifo(struct aty128_ddafifo *dsp,
1383 const struct aty128_pll *pll,
1384 u32 depth,
1385 const struct aty128fb_par *par)
1386 {
1387 const struct aty128_meminfo *m = par->mem;
1388 u32 xclk = par->constants.xclk;
1389 u32 fifo_width = par->constants.fifo_width;
1390 u32 fifo_depth = par->constants.fifo_depth;
1391 s32 x, b, p, ron, roff;
1392 u32 n, d, bpp;
1393
1394 /* round up to multiple of 8 */
1395 bpp = (depth+7) & ~7;
1396
1397 n = xclk * fifo_width;
1398 d = pll->vclk * bpp;
1399 x = round_div(n, d);
1400
1401 ron = 4 * m->MB +
1402 3 * ((m->Trcd - 2 > 0) ? m->Trcd - 2 : 0) +
1403 2 * m->Trp +
1404 m->Twr +
1405 m->CL +
1406 m->Tr2w +
1407 x;
1408
1409 DBG("x %x\n", x);
1410
1411 b = 0;
1412 while (x) {
1413 x >>= 1;
1414 b++;
1415 }
1416 p = b + 1;
1417
1418 ron <<= (11 - p);
1419
1420 n <<= (11 - p);
1421 x = round_div(n, d);
1422 roff = x * (fifo_depth - 4);
1423
1424 if ((ron + m->Rloop) >= roff) {
1425 printk(KERN_ERR "aty128fb: Mode out of range!\n");
1426 return -EINVAL;
1427 }
1428
1429 DBG("p: %x rloop: %x x: %x ron: %x roff: %x\n",
1430 p, m->Rloop, x, ron, roff);
1431
1432 dsp->dda_config = p << 16 | m->Rloop << 20 | x;
1433 dsp->dda_on_off = ron << 16 | roff;
1434
1435 return 0;
1436 }
1437
1438
1439 /*
1440 * This actually sets the video mode.
1441 */
1442 static int aty128fb_set_par(struct fb_info *info)
1443 {
1444 struct aty128fb_par *par = info->par;
1445 u32 config;
1446 int err;
1447
1448 if ((err = aty128_decode_var(&info->var, par)) != 0)
1449 return err;
1450
1451 if (par->blitter_may_be_busy)
1452 wait_for_idle(par);
1453
1454 /* clear all registers that may interfere with mode setting */
1455 aty_st_le32(OVR_CLR, 0);
1456 aty_st_le32(OVR_WID_LEFT_RIGHT, 0);
1457 aty_st_le32(OVR_WID_TOP_BOTTOM, 0);
1458 aty_st_le32(OV0_SCALE_CNTL, 0);
1459 aty_st_le32(MPP_TB_CONFIG, 0);
1460 aty_st_le32(MPP_GP_CONFIG, 0);
1461 aty_st_le32(SUBPIC_CNTL, 0);
1462 aty_st_le32(VIPH_CONTROL, 0);
1463 aty_st_le32(I2C_CNTL_1, 0); /* turn off i2c */
1464 aty_st_le32(GEN_INT_CNTL, 0); /* turn off interrupts */
1465 aty_st_le32(CAP0_TRIG_CNTL, 0);
1466 aty_st_le32(CAP1_TRIG_CNTL, 0);
1467
1468 aty_st_8(CRTC_EXT_CNTL + 1, 4); /* turn video off */
1469
1470 aty128_set_crtc(&par->crtc, par);
1471 aty128_set_pll(&par->pll, par);
1472 aty128_set_fifo(&par->fifo_reg, par);
1473
1474 config = aty_ld_le32(CONFIG_CNTL) & ~3;
1475
1476 #if defined(__BIG_ENDIAN)
1477 if (par->crtc.bpp == 32)
1478 config |= 2; /* make aperture do 32 bit swapping */
1479 else if (par->crtc.bpp == 16)
1480 config |= 1; /* make aperture do 16 bit swapping */
1481 #endif
1482
1483 aty_st_le32(CONFIG_CNTL, config);
1484 aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */
1485
1486 info->fix.line_length = (par->crtc.vxres * par->crtc.bpp) >> 3;
1487 info->fix.visual = par->crtc.bpp == 8 ? FB_VISUAL_PSEUDOCOLOR
1488 : FB_VISUAL_DIRECTCOLOR;
1489
1490 if (par->chip_gen == rage_M3) {
1491 aty128_set_crt_enable(par, par->crt_on);
1492 aty128_set_lcd_enable(par, par->lcd_on);
1493 }
1494 if (par->accel_flags & FB_ACCELF_TEXT)
1495 aty128_init_engine(par);
1496
1497 #ifdef CONFIG_BOOTX_TEXT
1498 btext_update_display(info->fix.smem_start,
1499 (((par->crtc.h_total>>16) & 0xff)+1)*8,
1500 ((par->crtc.v_total>>16) & 0x7ff)+1,
1501 par->crtc.bpp,
1502 par->crtc.vxres*par->crtc.bpp/8);
1503 #endif /* CONFIG_BOOTX_TEXT */
1504
1505 return 0;
1506 }
1507
1508 /*
1509 * encode/decode the User Defined Part of the Display
1510 */
1511
1512 static int aty128_decode_var(struct fb_var_screeninfo *var, struct aty128fb_par *par)
1513 {
1514 int err;
1515 struct aty128_crtc crtc;
1516 struct aty128_pll pll;
1517 struct aty128_ddafifo fifo_reg;
1518
1519 if ((err = aty128_var_to_crtc(var, &crtc, par)))
1520 return err;
1521
1522 if ((err = aty128_var_to_pll(var->pixclock, &pll, par)))
1523 return err;
1524
1525 if ((err = aty128_ddafifo(&fifo_reg, &pll, crtc.depth, par)))
1526 return err;
1527
1528 par->crtc = crtc;
1529 par->pll = pll;
1530 par->fifo_reg = fifo_reg;
1531 par->accel_flags = var->accel_flags;
1532
1533 return 0;
1534 }
1535
1536
1537 static int aty128_encode_var(struct fb_var_screeninfo *var,
1538 const struct aty128fb_par *par)
1539 {
1540 int err;
1541
1542 if ((err = aty128_crtc_to_var(&par->crtc, var)))
1543 return err;
1544
1545 if ((err = aty128_pll_to_var(&par->pll, var)))
1546 return err;
1547
1548 var->nonstd = 0;
1549 var->activate = 0;
1550
1551 var->height = -1;
1552 var->width = -1;
1553 var->accel_flags = par->accel_flags;
1554
1555 return 0;
1556 }
1557
1558
1559 static int aty128fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1560 {
1561 struct aty128fb_par par;
1562 int err;
1563
1564 par = *(struct aty128fb_par *)info->par;
1565 if ((err = aty128_decode_var(var, &par)) != 0)
1566 return err;
1567 aty128_encode_var(var, &par);
1568 return 0;
1569 }
1570
1571
1572 /*
1573 * Pan or Wrap the Display
1574 */
1575 static int aty128fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *fb)
1576 {
1577 struct aty128fb_par *par = fb->par;
1578 u32 xoffset, yoffset;
1579 u32 offset;
1580 u32 xres, yres;
1581
1582 xres = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3;
1583 yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1;
1584
1585 xoffset = (var->xoffset +7) & ~7;
1586 yoffset = var->yoffset;
1587
1588 if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres)
1589 return -EINVAL;
1590
1591 par->crtc.xoffset = xoffset;
1592 par->crtc.yoffset = yoffset;
1593
1594 offset = ((yoffset * par->crtc.vxres + xoffset)*(par->crtc.bpp >> 3)) & ~7;
1595
1596 if (par->crtc.bpp == 24)
1597 offset += 8 * (offset % 3); /* Must be multiple of 8 and 3 */
1598
1599 aty_st_le32(CRTC_OFFSET, offset);
1600
1601 return 0;
1602 }
1603
1604
1605 /*
1606 * Helper function to store a single palette register
1607 */
1608 static void aty128_st_pal(u_int regno, u_int red, u_int green, u_int blue,
1609 struct aty128fb_par *par)
1610 {
1611 if (par->chip_gen == rage_M3) {
1612 #if 0
1613 /* Note: For now, on M3, we set palette on both heads, which may
1614 * be useless. Can someone with a M3 check this ?
1615 *
1616 * This code would still be useful if using the second CRTC to
1617 * do mirroring
1618 */
1619
1620 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PALETTE_ACCESS_CNTL);
1621 aty_st_8(PALETTE_INDEX, regno);
1622 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
1623 #endif
1624 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & ~DAC_PALETTE_ACCESS_CNTL);
1625 }
1626
1627 aty_st_8(PALETTE_INDEX, regno);
1628 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
1629 }
1630
1631 static int aty128fb_sync(struct fb_info *info)
1632 {
1633 struct aty128fb_par *par = info->par;
1634
1635 if (par->blitter_may_be_busy)
1636 wait_for_idle(par);
1637 return 0;
1638 }
1639
1640 #ifndef MODULE
1641 static int __init aty128fb_setup(char *options)
1642 {
1643 char *this_opt;
1644
1645 if (!options || !*options)
1646 return 0;
1647
1648 while ((this_opt = strsep(&options, ",")) != NULL) {
1649 if (!strncmp(this_opt, "lcd:", 4)) {
1650 default_lcd_on = simple_strtoul(this_opt+4, NULL, 0);
1651 continue;
1652 } else if (!strncmp(this_opt, "crt:", 4)) {
1653 default_crt_on = simple_strtoul(this_opt+4, NULL, 0);
1654 continue;
1655 }
1656 #ifdef CONFIG_MTRR
1657 if(!strncmp(this_opt, "nomtrr", 6)) {
1658 mtrr = 0;
1659 continue;
1660 }
1661 #endif
1662 #ifdef CONFIG_PPC_PMAC
1663 /* vmode and cmode deprecated */
1664 if (!strncmp(this_opt, "vmode:", 6)) {
1665 unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0);
1666 if (vmode > 0 && vmode <= VMODE_MAX)
1667 default_vmode = vmode;
1668 continue;
1669 } else if (!strncmp(this_opt, "cmode:", 6)) {
1670 unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0);
1671 switch (cmode) {
1672 case 0:
1673 case 8:
1674 default_cmode = CMODE_8;
1675 break;
1676 case 15:
1677 case 16:
1678 default_cmode = CMODE_16;
1679 break;
1680 case 24:
1681 case 32:
1682 default_cmode = CMODE_32;
1683 break;
1684 }
1685 continue;
1686 }
1687 #endif /* CONFIG_PPC_PMAC */
1688 mode_option = this_opt;
1689 }
1690 return 0;
1691 }
1692 #endif /* MODULE */
1693
1694
1695 /*
1696 * Initialisation
1697 */
1698
1699 #ifdef CONFIG_PPC_PMAC
1700 static void aty128_early_resume(void *data)
1701 {
1702 struct aty128fb_par *par = data;
1703
1704 if (try_acquire_console_sem())
1705 return;
1706 aty128_do_resume(par->pdev);
1707 release_console_sem();
1708 }
1709 #endif /* CONFIG_PPC_PMAC */
1710
1711 static int __init aty128_init(struct pci_dev *pdev, const struct pci_device_id *ent)
1712 {
1713 struct fb_info *info = pci_get_drvdata(pdev);
1714 struct aty128fb_par *par = info->par;
1715 struct fb_var_screeninfo var;
1716 char video_card[DEVICE_NAME_SIZE];
1717 u8 chip_rev;
1718 u32 dac;
1719
1720 if (!par->vram_size) /* may have already been probed */
1721 par->vram_size = aty_ld_le32(CONFIG_MEMSIZE) & 0x03FFFFFF;
1722
1723 /* Get the chip revision */
1724 chip_rev = (aty_ld_le32(CONFIG_CNTL) >> 16) & 0x1F;
1725
1726 strcpy(video_card, "Rage128 XX ");
1727 video_card[8] = ent->device >> 8;
1728 video_card[9] = ent->device & 0xFF;
1729
1730 /* range check to make sure */
1731 if (ent->driver_data < ARRAY_SIZE(r128_family))
1732 strncat(video_card, r128_family[ent->driver_data], sizeof(video_card));
1733
1734 printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] ", video_card, chip_rev);
1735
1736 if (par->vram_size % (1024 * 1024) == 0)
1737 printk("%dM %s\n", par->vram_size / (1024*1024), par->mem->name);
1738 else
1739 printk("%dk %s\n", par->vram_size / 1024, par->mem->name);
1740
1741 par->chip_gen = ent->driver_data;
1742
1743 /* fill in info */
1744 info->fbops = &aty128fb_ops;
1745 info->flags = FBINFO_FLAG_DEFAULT;
1746
1747 par->lcd_on = default_lcd_on;
1748 par->crt_on = default_crt_on;
1749
1750 var = default_var;
1751 #ifdef CONFIG_PPC_PMAC
1752 if (machine_is(powermac)) {
1753 /* Indicate sleep capability */
1754 if (par->chip_gen == rage_M3) {
1755 pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, NULL, 0, 1);
1756 pmac_set_early_video_resume(aty128_early_resume, par);
1757 }
1758
1759 /* Find default mode */
1760 if (mode_option) {
1761 if (!mac_find_mode(&var, info, mode_option, 8))
1762 var = default_var;
1763 } else {
1764 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
1765 default_vmode = VMODE_1024_768_60;
1766
1767 /* iMacs need that resolution
1768 * PowerMac2,1 first r128 iMacs
1769 * PowerMac2,2 summer 2000 iMacs
1770 * PowerMac4,1 january 2001 iMacs "flower power"
1771 */
1772 if (machine_is_compatible("PowerMac2,1") ||
1773 machine_is_compatible("PowerMac2,2") ||
1774 machine_is_compatible("PowerMac4,1"))
1775 default_vmode = VMODE_1024_768_75;
1776
1777 /* iBook SE */
1778 if (machine_is_compatible("PowerBook2,2"))
1779 default_vmode = VMODE_800_600_60;
1780
1781 /* PowerBook Firewire (Pismo), iBook Dual USB */
1782 if (machine_is_compatible("PowerBook3,1") ||
1783 machine_is_compatible("PowerBook4,1"))
1784 default_vmode = VMODE_1024_768_60;
1785
1786 /* PowerBook Titanium */
1787 if (machine_is_compatible("PowerBook3,2"))
1788 default_vmode = VMODE_1152_768_60;
1789
1790 if (default_cmode > 16)
1791 default_cmode = CMODE_32;
1792 else if (default_cmode > 8)
1793 default_cmode = CMODE_16;
1794 else
1795 default_cmode = CMODE_8;
1796
1797 if (mac_vmode_to_var(default_vmode, default_cmode, &var))
1798 var = default_var;
1799 }
1800 } else
1801 #endif /* CONFIG_PPC_PMAC */
1802 {
1803 if (mode_option)
1804 if (fb_find_mode(&var, info, mode_option, NULL,
1805 0, &defaultmode, 8) == 0)
1806 var = default_var;
1807 }
1808
1809 var.accel_flags &= ~FB_ACCELF_TEXT;
1810 // var.accel_flags |= FB_ACCELF_TEXT;/* FIXME Will add accel later */
1811
1812 if (aty128fb_check_var(&var, info)) {
1813 printk(KERN_ERR "aty128fb: Cannot set default mode.\n");
1814 return 0;
1815 }
1816
1817 /* setup the DAC the way we like it */
1818 dac = aty_ld_le32(DAC_CNTL);
1819 dac |= (DAC_8BIT_EN | DAC_RANGE_CNTL);
1820 dac |= DAC_MASK;
1821 if (par->chip_gen == rage_M3)
1822 dac |= DAC_PALETTE2_SNOOP_EN;
1823 aty_st_le32(DAC_CNTL, dac);
1824
1825 /* turn off bus mastering, just in case */
1826 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS);
1827
1828 info->var = var;
1829 fb_alloc_cmap(&info->cmap, 256, 0);
1830
1831 var.activate = FB_ACTIVATE_NOW;
1832
1833 aty128_init_engine(par);
1834
1835 if (register_framebuffer(info) < 0)
1836 return 0;
1837
1838 #ifdef CONFIG_PMAC_BACKLIGHT
1839 /* Could be extended to Rage128Pro LVDS output too */
1840 if (par->chip_gen == rage_M3)
1841 register_backlight_controller(&aty128_backlight_controller, par, "ati");
1842 #endif /* CONFIG_PMAC_BACKLIGHT */
1843
1844 par->pm_reg = pci_find_capability(pdev, PCI_CAP_ID_PM);
1845 par->pdev = pdev;
1846 par->asleep = 0;
1847 par->lock_blank = 0;
1848
1849 printk(KERN_INFO "fb%d: %s frame buffer device on %s\n",
1850 info->node, info->fix.id, video_card);
1851
1852 return 1; /* success! */
1853 }
1854
1855 #ifdef CONFIG_PCI
1856 /* register a card ++ajoshi */
1857 static int __init aty128_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1858 {
1859 unsigned long fb_addr, reg_addr;
1860 struct aty128fb_par *par;
1861 struct fb_info *info;
1862 int err;
1863 #ifndef __sparc__
1864 void __iomem *bios = NULL;
1865 #endif
1866
1867 /* Enable device in PCI config */
1868 if ((err = pci_enable_device(pdev))) {
1869 printk(KERN_ERR "aty128fb: Cannot enable PCI device: %d\n",
1870 err);
1871 return -ENODEV;
1872 }
1873
1874 fb_addr = pci_resource_start(pdev, 0);
1875 if (!request_mem_region(fb_addr, pci_resource_len(pdev, 0),
1876 "aty128fb FB")) {
1877 printk(KERN_ERR "aty128fb: cannot reserve frame "
1878 "buffer memory\n");
1879 return -ENODEV;
1880 }
1881
1882 reg_addr = pci_resource_start(pdev, 2);
1883 if (!request_mem_region(reg_addr, pci_resource_len(pdev, 2),
1884 "aty128fb MMIO")) {
1885 printk(KERN_ERR "aty128fb: cannot reserve MMIO region\n");
1886 goto err_free_fb;
1887 }
1888
1889 /* We have the resources. Now virtualize them */
1890 info = framebuffer_alloc(sizeof(struct aty128fb_par), &pdev->dev);
1891 if (info == NULL) {
1892 printk(KERN_ERR "aty128fb: can't alloc fb_info_aty128\n");
1893 goto err_free_mmio;
1894 }
1895 par = info->par;
1896
1897 info->pseudo_palette = par->pseudo_palette;
1898 info->fix = aty128fb_fix;
1899
1900 /* Virtualize mmio region */
1901 info->fix.mmio_start = reg_addr;
1902 par->regbase = ioremap(reg_addr, pci_resource_len(pdev, 2));
1903 if (!par->regbase)
1904 goto err_free_info;
1905
1906 /* Grab memory size from the card */
1907 // How does this relate to the resource length from the PCI hardware?
1908 par->vram_size = aty_ld_le32(CONFIG_MEMSIZE) & 0x03FFFFFF;
1909
1910 /* Virtualize the framebuffer */
1911 info->screen_base = ioremap(fb_addr, par->vram_size);
1912 if (!info->screen_base)
1913 goto err_unmap_out;
1914
1915 /* Set up info->fix */
1916 info->fix = aty128fb_fix;
1917 info->fix.smem_start = fb_addr;
1918 info->fix.smem_len = par->vram_size;
1919 info->fix.mmio_start = reg_addr;
1920
1921 /* If we can't test scratch registers, something is seriously wrong */
1922 if (!register_test(par)) {
1923 printk(KERN_ERR "aty128fb: Can't write to video register!\n");
1924 goto err_out;
1925 }
1926
1927 #ifndef __sparc__
1928 bios = aty128_map_ROM(par, pdev);
1929 #ifdef CONFIG_X86
1930 if (bios == NULL)
1931 bios = aty128_find_mem_vbios(par);
1932 #endif
1933 if (bios == NULL)
1934 printk(KERN_INFO "aty128fb: BIOS not located, guessing timings.\n");
1935 else {
1936 printk(KERN_INFO "aty128fb: Rage128 BIOS located\n");
1937 aty128_get_pllinfo(par, bios);
1938 pci_unmap_rom(pdev, bios);
1939 }
1940 #endif /* __sparc__ */
1941
1942 aty128_timings(par);
1943 pci_set_drvdata(pdev, info);
1944
1945 if (!aty128_init(pdev, ent))
1946 goto err_out;
1947
1948 #ifdef CONFIG_MTRR
1949 if (mtrr) {
1950 par->mtrr.vram = mtrr_add(info->fix.smem_start,
1951 par->vram_size, MTRR_TYPE_WRCOMB, 1);
1952 par->mtrr.vram_valid = 1;
1953 /* let there be speed */
1954 printk(KERN_INFO "aty128fb: Rage128 MTRR set to ON\n");
1955 }
1956 #endif /* CONFIG_MTRR */
1957 return 0;
1958
1959 err_out:
1960 iounmap(info->screen_base);
1961 err_unmap_out:
1962 iounmap(par->regbase);
1963 err_free_info:
1964 framebuffer_release(info);
1965 err_free_mmio:
1966 release_mem_region(pci_resource_start(pdev, 2),
1967 pci_resource_len(pdev, 2));
1968 err_free_fb:
1969 release_mem_region(pci_resource_start(pdev, 0),
1970 pci_resource_len(pdev, 0));
1971 return -ENODEV;
1972 }
1973
1974 static void __devexit aty128_remove(struct pci_dev *pdev)
1975 {
1976 struct fb_info *info = pci_get_drvdata(pdev);
1977 struct aty128fb_par *par;
1978
1979 if (!info)
1980 return;
1981
1982 par = info->par;
1983
1984 unregister_framebuffer(info);
1985 #ifdef CONFIG_MTRR
1986 if (par->mtrr.vram_valid)
1987 mtrr_del(par->mtrr.vram, info->fix.smem_start,
1988 par->vram_size);
1989 #endif /* CONFIG_MTRR */
1990 iounmap(par->regbase);
1991 iounmap(info->screen_base);
1992
1993 release_mem_region(pci_resource_start(pdev, 0),
1994 pci_resource_len(pdev, 0));
1995 release_mem_region(pci_resource_start(pdev, 2),
1996 pci_resource_len(pdev, 2));
1997 framebuffer_release(info);
1998 }
1999 #endif /* CONFIG_PCI */
2000
2001
2002
2003 /*
2004 * Blank the display.
2005 */
2006 static int aty128fb_blank(int blank, struct fb_info *fb)
2007 {
2008 struct aty128fb_par *par = fb->par;
2009 u8 state = 0;
2010
2011 if (par->lock_blank || par->asleep)
2012 return 0;
2013
2014 #ifdef CONFIG_PMAC_BACKLIGHT
2015 if (machine_is(powermac) && blank)
2016 set_backlight_enable(0);
2017 #endif /* CONFIG_PMAC_BACKLIGHT */
2018
2019 if (blank & FB_BLANK_VSYNC_SUSPEND)
2020 state |= 2;
2021 if (blank & FB_BLANK_HSYNC_SUSPEND)
2022 state |= 1;
2023 if (blank & FB_BLANK_POWERDOWN)
2024 state |= 4;
2025
2026 aty_st_8(CRTC_EXT_CNTL+1, state);
2027
2028 if (par->chip_gen == rage_M3) {
2029 aty128_set_crt_enable(par, par->crt_on && !blank);
2030 aty128_set_lcd_enable(par, par->lcd_on && !blank);
2031 }
2032 #ifdef CONFIG_PMAC_BACKLIGHT
2033 if (machine_is(powermac) && !blank)
2034 set_backlight_enable(1);
2035 #endif /* CONFIG_PMAC_BACKLIGHT */
2036 return 0;
2037 }
2038
2039 /*
2040 * Set a single color register. The values supplied are already
2041 * rounded down to the hardware's capabilities (according to the
2042 * entries in the var structure). Return != 0 for invalid regno.
2043 */
2044 static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2045 u_int transp, struct fb_info *info)
2046 {
2047 struct aty128fb_par *par = info->par;
2048
2049 if (regno > 255
2050 || (par->crtc.depth == 16 && regno > 63)
2051 || (par->crtc.depth == 15 && regno > 31))
2052 return 1;
2053
2054 red >>= 8;
2055 green >>= 8;
2056 blue >>= 8;
2057
2058 if (regno < 16) {
2059 int i;
2060 u32 *pal = info->pseudo_palette;
2061
2062 switch (par->crtc.depth) {
2063 case 15:
2064 pal[regno] = (regno << 10) | (regno << 5) | regno;
2065 break;
2066 case 16:
2067 pal[regno] = (regno << 11) | (regno << 6) | regno;
2068 break;
2069 case 24:
2070 pal[regno] = (regno << 16) | (regno << 8) | regno;
2071 break;
2072 case 32:
2073 i = (regno << 8) | regno;
2074 pal[regno] = (i << 16) | i;
2075 break;
2076 }
2077 }
2078
2079 if (par->crtc.depth == 16 && regno > 0) {
2080 /*
2081 * With the 5-6-5 split of bits for RGB at 16 bits/pixel, we
2082 * have 32 slots for R and B values but 64 slots for G values.
2083 * Thus the R and B values go in one slot but the G value
2084 * goes in a different slot, and we have to avoid disturbing
2085 * the other fields in the slots we touch.
2086 */
2087 par->green[regno] = green;
2088 if (regno < 32) {
2089 par->red[regno] = red;
2090 par->blue[regno] = blue;
2091 aty128_st_pal(regno * 8, red, par->green[regno*2],
2092 blue, par);
2093 }
2094 red = par->red[regno/2];
2095 blue = par->blue[regno/2];
2096 regno <<= 2;
2097 } else if (par->crtc.bpp == 16)
2098 regno <<= 3;
2099 aty128_st_pal(regno, red, green, blue, par);
2100
2101 return 0;
2102 }
2103
2104 #define ATY_MIRROR_LCD_ON 0x00000001
2105 #define ATY_MIRROR_CRT_ON 0x00000002
2106
2107 /* out param: u32* backlight value: 0 to 15 */
2108 #define FBIO_ATY128_GET_MIRROR _IOR('@', 1, __u32)
2109 /* in param: u32* backlight value: 0 to 15 */
2110 #define FBIO_ATY128_SET_MIRROR _IOW('@', 2, __u32)
2111
2112 static int aty128fb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
2113 {
2114 struct aty128fb_par *par = info->par;
2115 u32 value;
2116 int rc;
2117
2118 switch (cmd) {
2119 case FBIO_ATY128_SET_MIRROR:
2120 if (par->chip_gen != rage_M3)
2121 return -EINVAL;
2122 rc = get_user(value, (__u32 __user *)arg);
2123 if (rc)
2124 return rc;
2125 par->lcd_on = (value & 0x01) != 0;
2126 par->crt_on = (value & 0x02) != 0;
2127 if (!par->crt_on && !par->lcd_on)
2128 par->lcd_on = 1;
2129 aty128_set_crt_enable(par, par->crt_on);
2130 aty128_set_lcd_enable(par, par->lcd_on);
2131 return 0;
2132 case FBIO_ATY128_GET_MIRROR:
2133 if (par->chip_gen != rage_M3)
2134 return -EINVAL;
2135 value = (par->crt_on << 1) | par->lcd_on;
2136 return put_user(value, (__u32 __user *)arg);
2137 }
2138 return -EINVAL;
2139 }
2140
2141 #ifdef CONFIG_PMAC_BACKLIGHT
2142 static int backlight_conv[] = {
2143 0xff, 0xc0, 0xb5, 0xaa, 0x9f, 0x94, 0x89, 0x7e,
2144 0x73, 0x68, 0x5d, 0x52, 0x47, 0x3c, 0x31, 0x24
2145 };
2146
2147 /* We turn off the LCD completely instead of just dimming the backlight.
2148 * This provides greater power saving and the display is useless without
2149 * backlight anyway
2150 */
2151 #define BACKLIGHT_LVDS_OFF
2152 /* That one prevents proper CRT output with LCD off */
2153 #undef BACKLIGHT_DAC_OFF
2154
2155 static int aty128_set_backlight_enable(int on, int level, void *data)
2156 {
2157 struct aty128fb_par *par = data;
2158 unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL);
2159
2160 if (!par->lcd_on)
2161 on = 0;
2162 reg |= LVDS_BL_MOD_EN | LVDS_BLON;
2163 if (on && level > BACKLIGHT_OFF) {
2164 reg |= LVDS_DIGION;
2165 if (!(reg & LVDS_ON)) {
2166 reg &= ~LVDS_BLON;
2167 aty_st_le32(LVDS_GEN_CNTL, reg);
2168 (void)aty_ld_le32(LVDS_GEN_CNTL);
2169 mdelay(10);
2170 reg |= LVDS_BLON;
2171 aty_st_le32(LVDS_GEN_CNTL, reg);
2172 }
2173 reg &= ~LVDS_BL_MOD_LEVEL_MASK;
2174 reg |= (backlight_conv[level] << LVDS_BL_MOD_LEVEL_SHIFT);
2175 #ifdef BACKLIGHT_LVDS_OFF
2176 reg |= LVDS_ON | LVDS_EN;
2177 reg &= ~LVDS_DISPLAY_DIS;
2178 #endif
2179 aty_st_le32(LVDS_GEN_CNTL, reg);
2180 #ifdef BACKLIGHT_DAC_OFF
2181 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN));
2182 #endif
2183 } else {
2184 reg &= ~LVDS_BL_MOD_LEVEL_MASK;
2185 reg |= (backlight_conv[0] << LVDS_BL_MOD_LEVEL_SHIFT);
2186 #ifdef BACKLIGHT_LVDS_OFF
2187 reg |= LVDS_DISPLAY_DIS;
2188 aty_st_le32(LVDS_GEN_CNTL, reg);
2189 (void)aty_ld_le32(LVDS_GEN_CNTL);
2190 udelay(10);
2191 reg &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION);
2192 #endif
2193 aty_st_le32(LVDS_GEN_CNTL, reg);
2194 #ifdef BACKLIGHT_DAC_OFF
2195 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN);
2196 #endif
2197 }
2198
2199 return 0;
2200 }
2201
2202 static int aty128_set_backlight_level(int level, void* data)
2203 {
2204 return aty128_set_backlight_enable(1, level, data);
2205 }
2206 #endif /* CONFIG_PMAC_BACKLIGHT */
2207
2208 #if 0
2209 /*
2210 * Accelerated functions
2211 */
2212
2213 static inline void aty128_rectcopy(int srcx, int srcy, int dstx, int dsty,
2214 u_int width, u_int height,
2215 struct fb_info_aty128 *par)
2216 {
2217 u32 save_dp_datatype, save_dp_cntl, dstval;
2218
2219 if (!width || !height)
2220 return;
2221
2222 dstval = depth_to_dst(par->current_par.crtc.depth);
2223 if (dstval == DST_24BPP) {
2224 srcx *= 3;
2225 dstx *= 3;
2226 width *= 3;
2227 } else if (dstval == -EINVAL) {
2228 printk("aty128fb: invalid depth or RGBA\n");
2229 return;
2230 }
2231
2232 wait_for_fifo(2, par);
2233 save_dp_datatype = aty_ld_le32(DP_DATATYPE);
2234 save_dp_cntl = aty_ld_le32(DP_CNTL);
2235
2236 wait_for_fifo(6, par);
2237 aty_st_le32(SRC_Y_X, (srcy << 16) | srcx);
2238 aty_st_le32(DP_MIX, ROP3_SRCCOPY | DP_SRC_RECT);
2239 aty_st_le32(DP_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM);
2240 aty_st_le32(DP_DATATYPE, save_dp_datatype | dstval | SRC_DSTCOLOR);
2241
2242 aty_st_le32(DST_Y_X, (dsty << 16) | dstx);
2243 aty_st_le32(DST_HEIGHT_WIDTH, (height << 16) | width);
2244
2245 par->blitter_may_be_busy = 1;
2246
2247 wait_for_fifo(2, par);
2248 aty_st_le32(DP_DATATYPE, save_dp_datatype);
2249 aty_st_le32(DP_CNTL, save_dp_cntl);
2250 }
2251
2252
2253 /*
2254 * Text mode accelerated functions
2255 */
2256
2257 static void fbcon_aty128_bmove(struct display *p, int sy, int sx, int dy, int dx,
2258 int height, int width)
2259 {
2260 sx *= fontwidth(p);
2261 sy *= fontheight(p);
2262 dx *= fontwidth(p);
2263 dy *= fontheight(p);
2264 width *= fontwidth(p);
2265 height *= fontheight(p);
2266
2267 aty128_rectcopy(sx, sy, dx, dy, width, height,
2268 (struct fb_info_aty128 *)p->fb_info);
2269 }
2270 #endif /* 0 */
2271
2272 static void aty128_set_suspend(struct aty128fb_par *par, int suspend)
2273 {
2274 u32 pmgt;
2275 u16 pwr_command;
2276 struct pci_dev *pdev = par->pdev;
2277
2278 if (!par->pm_reg)
2279 return;
2280
2281 /* Set the chip into the appropriate suspend mode (we use D2,
2282 * D3 would require a complete re-initialisation of the chip,
2283 * including PCI config registers, clocks, AGP configuration, ...)
2284 */
2285 if (suspend) {
2286 /* Make sure CRTC2 is reset. Remove that the day we decide to
2287 * actually use CRTC2 and replace it with real code for disabling
2288 * the CRTC2 output during sleep
2289 */
2290 aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) &
2291 ~(CRTC2_EN));
2292
2293 /* Set the power management mode to be PCI based */
2294 /* Use this magic value for now */
2295 pmgt = 0x0c005407;
2296 aty_st_pll(POWER_MANAGEMENT, pmgt);
2297 (void)aty_ld_pll(POWER_MANAGEMENT);
2298 aty_st_le32(BUS_CNTL1, 0x00000010);
2299 aty_st_le32(MEM_POWER_MISC, 0x0c830000);
2300 mdelay(100);
2301 pci_read_config_word(pdev, par->pm_reg+PCI_PM_CTRL, &pwr_command);
2302 /* Switch PCI power management to D2 */
2303 pci_write_config_word(pdev, par->pm_reg+PCI_PM_CTRL,
2304 (pwr_command & ~PCI_PM_CTRL_STATE_MASK) | 2);
2305 pci_read_config_word(pdev, par->pm_reg+PCI_PM_CTRL, &pwr_command);
2306 } else {
2307 /* Switch back PCI power management to D0 */
2308 mdelay(100);
2309 pci_write_config_word(pdev, par->pm_reg+PCI_PM_CTRL, 0);
2310 pci_read_config_word(pdev, par->pm_reg+PCI_PM_CTRL, &pwr_command);
2311 mdelay(100);
2312 }
2313 }
2314
2315 static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2316 {
2317 struct fb_info *info = pci_get_drvdata(pdev);
2318 struct aty128fb_par *par = info->par;
2319
2320 /* We don't do anything but D2, for now we return 0, but
2321 * we may want to change that. How do we know if the BIOS
2322 * can properly take care of D3 ? Also, with swsusp, we
2323 * know we'll be rebooted, ...
2324 */
2325 #ifndef CONFIG_PPC_PMAC
2326 /* HACK ALERT ! Once I find a proper way to say to each driver
2327 * individually what will happen with it's PCI slot, I'll change
2328 * that. On laptops, the AGP slot is just unclocked, so D2 is
2329 * expected, while on desktops, the card is powered off
2330 */
2331 return 0;
2332 #endif /* CONFIG_PPC_PMAC */
2333
2334 if (state.event == pdev->dev.power.power_state.event)
2335 return 0;
2336
2337 printk(KERN_DEBUG "aty128fb: suspending...\n");
2338
2339 acquire_console_sem();
2340
2341 fb_set_suspend(info, 1);
2342
2343 /* Make sure engine is reset */
2344 wait_for_idle(par);
2345 aty128_reset_engine(par);
2346 wait_for_idle(par);
2347
2348 /* Blank display and LCD */
2349 aty128fb_blank(VESA_POWERDOWN, info);
2350
2351 /* Sleep */
2352 par->asleep = 1;
2353 par->lock_blank = 1;
2354
2355 #ifdef CONFIG_PPC_PMAC
2356 /* On powermac, we have hooks to properly suspend/resume AGP now,
2357 * use them here. We'll ultimately need some generic support here,
2358 * but the generic code isn't quite ready for that yet
2359 */
2360 pmac_suspend_agp_for_card(pdev);
2361 #endif /* CONFIG_PPC_PMAC */
2362
2363 /* We need a way to make sure the fbdev layer will _not_ touch the
2364 * framebuffer before we put the chip to suspend state. On 2.4, I
2365 * used dummy fb ops, 2.5 need proper support for this at the
2366 * fbdev level
2367 */
2368 if (state.event != PM_EVENT_ON)
2369 aty128_set_suspend(par, 1);
2370
2371 release_console_sem();
2372
2373 pdev->dev.power.power_state = state;
2374
2375 return 0;
2376 }
2377
2378 static int aty128_do_resume(struct pci_dev *pdev)
2379 {
2380 struct fb_info *info = pci_get_drvdata(pdev);
2381 struct aty128fb_par *par = info->par;
2382
2383 if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2384 return 0;
2385
2386 /* Wakeup chip */
2387 aty128_set_suspend(par, 0);
2388 par->asleep = 0;
2389
2390 /* Restore display & engine */
2391 aty128_reset_engine(par);
2392 wait_for_idle(par);
2393 aty128fb_set_par(info);
2394 fb_pan_display(info, &info->var);
2395 fb_set_cmap(&info->cmap, info);
2396
2397 /* Refresh */
2398 fb_set_suspend(info, 0);
2399
2400 /* Unblank */
2401 par->lock_blank = 0;
2402 aty128fb_blank(0, info);
2403
2404 #ifdef CONFIG_PPC_PMAC
2405 /* On powermac, we have hooks to properly suspend/resume AGP now,
2406 * use them here. We'll ultimately need some generic support here,
2407 * but the generic code isn't quite ready for that yet
2408 */
2409 pmac_resume_agp_for_card(pdev);
2410 #endif /* CONFIG_PPC_PMAC */
2411
2412 pdev->dev.power.power_state = PMSG_ON;
2413
2414 printk(KERN_DEBUG "aty128fb: resumed !\n");
2415
2416 return 0;
2417 }
2418
2419 static int aty128_pci_resume(struct pci_dev *pdev)
2420 {
2421 int rc;
2422
2423 acquire_console_sem();
2424 rc = aty128_do_resume(pdev);
2425 release_console_sem();
2426
2427 return rc;
2428 }
2429
2430
2431 static int __init aty128fb_init(void)
2432 {
2433 #ifndef MODULE
2434 char *option = NULL;
2435
2436 if (fb_get_options("aty128fb", &option))
2437 return -ENODEV;
2438 aty128fb_setup(option);
2439 #endif
2440
2441 return pci_register_driver(&aty128fb_driver);
2442 }
2443
2444 static void __exit aty128fb_exit(void)
2445 {
2446 pci_unregister_driver(&aty128fb_driver);
2447 }
2448
2449 module_init(aty128fb_init);
2450
2451 module_exit(aty128fb_exit);
2452
2453 MODULE_AUTHOR("(c)1999-2003 Brad Douglas <brad@neruo.com>");
2454 MODULE_DESCRIPTION("FBDev driver for ATI Rage128 / Pro cards");
2455 MODULE_LICENSE("GPL");
2456 module_param(mode_option, charp, 0);
2457 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2458 #ifdef CONFIG_MTRR
2459 module_param_named(nomtrr, mtrr, invbool, 0);
2460 MODULE_PARM_DESC(nomtrr, "bool: Disable MTRR support (0 or 1=disabled) (default=0)");
2461 #endif
2462
Verdex Pro support