drivers/video/chipsfb.c

   1 /*
   2  *  drivers/video/chipsfb.c -- frame buffer device for
   3  *  Chips & Technologies 65550 chip.
   4  *
   5  *  Copyright (C) 1998-2002 Paul Mackerras
   6  *
   7  *  This file is derived from the Powermac "chips" driver:
   8  *  Copyright (C) 1997 Fabio Riccardi.
   9  *  And from the frame buffer device for Open Firmware-initialized devices:
  10  *  Copyright (C) 1997 Geert Uytterhoeven.
  11  *
  12  *  This file is subject to the terms and conditions of the GNU General Public
  13  *  License. See the file COPYING in the main directory of this archive for
  14  *  more details.
  15  */
  16
  17 #include <linux/config.h>
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/string.h>
  22 #include <linux/mm.h>
  23 #include <linux/tty.h>
  24 #include <linux/slab.h>
  25 #include <linux/vmalloc.h>
  26 #include <linux/delay.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/fb.h>
  29 #include <linux/init.h>
  30 #include <linux/pci.h>
  31 #include <linux/console.h>
  32 #include <asm/io.h>
  33
  34 #ifdef CONFIG_PMAC_BACKLIGHT
  35 #include <asm/backlight.h>
  36 #endif
  37
  38 /*
  39  * Since we access the display with inb/outb to fixed port numbers,
  40  * we can only handle one 6555x chip.  -- paulus
  41  */
  42 #define write_ind(num, val, ap, dp)     do { \
  43         outb((num), (ap)); outb((val), (dp)); \
  44 } while (0)
  45 #define read_ind(num, var, ap, dp)      do { \
  46         outb((num), (ap)); var = inb((dp)); \
  47 } while (0)
  48
  49 /* extension registers */
  50 #define write_xr(num, val)      write_ind(num, val, 0x3d6, 0x3d7)
  51 #define read_xr(num, var)       read_ind(num, var, 0x3d6, 0x3d7)
  52 /* flat panel registers */
  53 #define write_fr(num, val)      write_ind(num, val, 0x3d0, 0x3d1)
  54 #define read_fr(num, var)       read_ind(num, var, 0x3d0, 0x3d1)
  55 /* CRTC registers */
  56 #define write_cr(num, val)      write_ind(num, val, 0x3d4, 0x3d5)
  57 #define read_cr(num, var)       read_ind(num, var, 0x3d4, 0x3d5)
  58 /* graphics registers */
  59 #define write_gr(num, val)      write_ind(num, val, 0x3ce, 0x3cf)
  60 #define read_gr(num, var)       read_ind(num, var, 0x3ce, 0x3cf)
  61 /* sequencer registers */
  62 #define write_sr(num, val)      write_ind(num, val, 0x3c4, 0x3c5)
  63 #define read_sr(num, var)       read_ind(num, var, 0x3c4, 0x3c5)
  64 /* attribute registers - slightly strange */
  65 #define write_ar(num, val)      do { \
  66         inb(0x3da); write_ind(num, val, 0x3c0, 0x3c0); \
  67 } while (0)
  68 #define read_ar(num, var)       do { \
  69         inb(0x3da); read_ind(num, var, 0x3c0, 0x3c1); \
  70 } while (0)
  71
  72 /*
  73  * Exported functions
  74  */
  75 int chips_init(void);
  76
  77 static int chipsfb_pci_init(struct pci_dev *dp, const struct pci_device_id *);
  78 static int chipsfb_check_var(struct fb_var_screeninfo *var,
  79                              struct fb_info *info);
  80 static int chipsfb_set_par(struct fb_info *info);
  81 static int chipsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
  82                              u_int transp, struct fb_info *info);
  83 static int chipsfb_blank(int blank, struct fb_info *info);
  84
  85 static struct fb_ops chipsfb_ops = {
  86         .owner          = THIS_MODULE,
  87         .fb_check_var   = chipsfb_check_var,
  88         .fb_set_par     = chipsfb_set_par,
  89         .fb_setcolreg   = chipsfb_setcolreg,
  90         .fb_blank       = chipsfb_blank,
  91         .fb_fillrect    = cfb_fillrect,
  92         .fb_copyarea    = cfb_copyarea,
  93         .fb_imageblit   = cfb_imageblit,
  94 };
  95
  96 static int chipsfb_check_var(struct fb_var_screeninfo *var,
  97                              struct fb_info *info)
  98 {
  99         if (var->xres > 800 || var->yres > 600
 100             || var->xres_virtual > 800 || var->yres_virtual > 600
 101             || (var->bits_per_pixel != 8 && var->bits_per_pixel != 16)
 102             || var->nonstd
 103             || (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
 104                 return -EINVAL;
 105
 106         var->xres = var->xres_virtual = 800;
 107         var->yres = var->yres_virtual = 600;
 108
 109         return 0;
 110 }
 111
 112 static int chipsfb_set_par(struct fb_info *info)
 113 {
 114         if (info->var.bits_per_pixel == 16) {
 115                 write_cr(0x13, 200);            // Set line length (doublewords)
 116                 write_xr(0x81, 0x14);           // 15 bit (555) color mode
 117                 write_xr(0x82, 0x00);           // Disable palettes
 118                 write_xr(0x20, 0x10);           // 16 bit blitter mode
 119
 120                 info->fix.line_length = 800*2;
 121                 info->fix.visual = FB_VISUAL_TRUECOLOR;
 122
 123                 info->var.red.offset = 10;
 124                 info->var.green.offset = 5;
 125                 info->var.blue.offset = 0;
 126                 info->var.red.length = info->var.green.length =
 127                         info->var.blue.length = 5;
 128
 129         } else {
 130                 /* p->var.bits_per_pixel == 8 */
 131                 write_cr(0x13, 100);            // Set line length (doublewords)
 132                 write_xr(0x81, 0x12);           // 8 bit color mode
 133                 write_xr(0x82, 0x08);           // Graphics gamma enable
 134                 write_xr(0x20, 0x00);           // 8 bit blitter mode
 135
 136                 info->fix.line_length = 800;
 137                 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
 138
 139                 info->var.red.offset = info->var.green.offset =
 140                         info->var.blue.offset = 0;
 141                 info->var.red.length = info->var.green.length =
 142                         info->var.blue.length = 8;
 143
 144         }
 145         return 0;
 146 }
 147
 148 static int chipsfb_blank(int blank, struct fb_info *info)
 149 {
 150 #ifdef CONFIG_PMAC_BACKLIGHT
 151         // used to disable backlight only for blank > 1, but it seems
 152         // useful at blank = 1 too (saves battery, extends backlight life)
 153         set_backlight_enable(!blank);
 154 #endif /* CONFIG_PMAC_BACKLIGHT */
 155
 156         return 1;       /* get fb_blank to set the colormap to all black */
 157 }
 158
 159 static int chipsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 160                              u_int transp, struct fb_info *info)
 161 {
 162         if (regno > 255)
 163                 return 1;
 164         red >>= 8;
 165         green >>= 8;
 166         blue >>= 8;
 167         outb(regno, 0x3c8);
 168         udelay(1);
 169         outb(red, 0x3c9);
 170         outb(green, 0x3c9);
 171         outb(blue, 0x3c9);
 172
 173         return 0;
 174 }
 175
 176 struct chips_init_reg {
 177         unsigned char addr;
 178         unsigned char data;
 179 };
 180
 181 static struct chips_init_reg chips_init_sr[] = {
 182         { 0x00, 0x03 },
 183         { 0x01, 0x01 },
 184         { 0x02, 0x0f },
 185         { 0x04, 0x0e }
 186 };
 187
 188 static struct chips_init_reg chips_init_gr[] = {
 189         { 0x05, 0x00 },
 190         { 0x06, 0x0d },
 191         { 0x08, 0xff }
 192 };
 193
 194 static struct chips_init_reg chips_init_ar[] = {
 195         { 0x10, 0x01 },
 196         { 0x12, 0x0f },
 197         { 0x13, 0x00 }
 198 };
 199
 200 static struct chips_init_reg chips_init_cr[] = {
 201         { 0x00, 0x7f },
 202         { 0x01, 0x63 },
 203         { 0x02, 0x63 },
 204         { 0x03, 0x83 },
 205         { 0x04, 0x66 },
 206         { 0x05, 0x10 },
 207         { 0x06, 0x72 },
 208         { 0x07, 0x3e },
 209         { 0x08, 0x00 },
 210         { 0x09, 0x40 },
 211         { 0x0c, 0x00 },
 212         { 0x0d, 0x00 },
 213         { 0x10, 0x59 },
 214         { 0x11, 0x0d },
 215         { 0x12, 0x57 },
 216         { 0x13, 0x64 },
 217         { 0x14, 0x00 },
 218         { 0x15, 0x57 },
 219         { 0x16, 0x73 },
 220         { 0x17, 0xe3 },
 221         { 0x18, 0xff },
 222         { 0x30, 0x02 },
 223         { 0x31, 0x02 },
 224         { 0x32, 0x02 },
 225         { 0x33, 0x02 },
 226         { 0x40, 0x00 },
 227         { 0x41, 0x00 },
 228         { 0x40, 0x80 }
 229 };
 230
 231 static struct chips_init_reg chips_init_fr[] = {
 232         { 0x01, 0x02 },
 233         { 0x03, 0x08 },
 234         { 0x04, 0x81 },
 235         { 0x05, 0x21 },
 236         { 0x08, 0x0c },
 237         { 0x0a, 0x74 },
 238         { 0x0b, 0x11 },
 239         { 0x10, 0x0c },
 240         { 0x11, 0xe0 },
 241         /* { 0x12, 0x40 }, -- 3400 needs 40, 2400 needs 48, no way to tell */
 242         { 0x20, 0x63 },
 243         { 0x21, 0x68 },
 244         { 0x22, 0x19 },
 245         { 0x23, 0x7f },
 246         { 0x24, 0x68 },
 247         { 0x26, 0x00 },
 248         { 0x27, 0x0f },
 249         { 0x30, 0x57 },
 250         { 0x31, 0x58 },
 251         { 0x32, 0x0d },
 252         { 0x33, 0x72 },
 253         { 0x34, 0x02 },
 254         { 0x35, 0x22 },
 255         { 0x36, 0x02 },
 256         { 0x37, 0x00 }
 257 };
 258
 259 static struct chips_init_reg chips_init_xr[] = {
 260         { 0xce, 0x00 },         /* set default memory clock */
 261         { 0xcc, 0x43 },         /* memory clock ratio */
 262         { 0xcd, 0x18 },
 263         { 0xce, 0xa1 },
 264         { 0xc8, 0x84 },
 265         { 0xc9, 0x0a },
 266         { 0xca, 0x00 },
 267         { 0xcb, 0x20 },
 268         { 0xcf, 0x06 },
 269         { 0xd0, 0x0e },
 270         { 0x09, 0x01 },
 271         { 0x0a, 0x02 },
 272         { 0x0b, 0x01 },
 273         { 0x20, 0x00 },
 274         { 0x40, 0x03 },
 275         { 0x41, 0x01 },
 276         { 0x42, 0x00 },
 277         { 0x80, 0x82 },
 278         { 0x81, 0x12 },
 279         { 0x82, 0x08 },
 280         { 0xa0, 0x00 },
 281         { 0xa8, 0x00 }
 282 };
 283
 284 static void __init chips_hw_init(void)
 285 {
 286         int i;
 287
 288         for (i = 0; i < ARRAY_SIZE(chips_init_xr); ++i)
 289                 write_xr(chips_init_xr[i].addr, chips_init_xr[i].data);
 290         outb(0x29, 0x3c2); /* set misc output reg */
 291         for (i = 0; i < ARRAY_SIZE(chips_init_sr); ++i)
 292                 write_sr(chips_init_sr[i].addr, chips_init_sr[i].data);
 293         for (i = 0; i < ARRAY_SIZE(chips_init_gr); ++i)
 294                 write_gr(chips_init_gr[i].addr, chips_init_gr[i].data);
 295         for (i = 0; i < ARRAY_SIZE(chips_init_ar); ++i)
 296                 write_ar(chips_init_ar[i].addr, chips_init_ar[i].data);
 297         for (i = 0; i < ARRAY_SIZE(chips_init_cr); ++i)
 298                 write_cr(chips_init_cr[i].addr, chips_init_cr[i].data);
 299         for (i = 0; i < ARRAY_SIZE(chips_init_fr); ++i)
 300                 write_fr(chips_init_fr[i].addr, chips_init_fr[i].data);
 301 }
 302
 303 static struct fb_fix_screeninfo chipsfb_fix __initdata = {
 304         .id =           "C&T 65550",
 305         .type =         FB_TYPE_PACKED_PIXELS,
 306         .visual =       FB_VISUAL_PSEUDOCOLOR,
 307         .accel =        FB_ACCEL_NONE,
 308         .line_length =  800,
 309
 310 // FIXME: Assumes 1MB frame buffer, but 65550 supports 1MB or 2MB.
 311 // * "3500" PowerBook G3 (the original PB G3) has 2MB.
 312 // * 2400 has 1MB composed of 2 Mitsubishi M5M4V4265CTP DRAM chips.
 313 //   Motherboard actually supports 2MB -- there are two blank locations
 314 //   for a second pair of DRAMs.  (Thanks, Apple!)
 315 // * 3400 has 1MB (I think).  Don't know if it's expandable.
 316 // -- Tim Seufert
 317         .smem_len =     0x100000,       /* 1MB */
 318 };
 319
 320 static struct fb_var_screeninfo chipsfb_var __initdata = {
 321         .xres = 800,
 322         .yres = 600,
 323         .xres_virtual = 800,
 324         .yres_virtual = 600,
 325         .bits_per_pixel = 8,
 326         .red = { .length = 8 },
 327         .green = { .length = 8 },
 328         .blue = { .length = 8 },
 329         .height = -1,
 330         .width = -1,
 331         .vmode = FB_VMODE_NONINTERLACED,
 332         .pixclock = 10000,
 333         .left_margin = 16,
 334         .right_margin = 16,
 335         .upper_margin = 16,
 336         .lower_margin = 16,
 337         .hsync_len = 8,
 338         .vsync_len = 8,
 339 };
 340
 341 static void __init init_chips(struct fb_info *p, unsigned long addr)
 342 {
 343         memset(p->screen_base, 0, 0x100000);
 344
 345         p->fix = chipsfb_fix;
 346         p->fix.smem_start = addr;
 347
 348         p->var = chipsfb_var;
 349
 350         p->fbops = &chipsfb_ops;
 351         p->flags = FBINFO_DEFAULT;
 352
 353         fb_alloc_cmap(&p->cmap, 256, 0);
 354
 355         chips_hw_init();
 356 }
 357
 358 static int __devinit
 359 chipsfb_pci_init(struct pci_dev *dp, const struct pci_device_id *ent)
 360 {
 361         struct fb_info *p;
 362         unsigned long addr, size;
 363         unsigned short cmd;
 364         int rc = -ENODEV;
 365
 366         if (pci_enable_device(dp) < 0) {
 367                 dev_err(&dp->dev, "Cannot enable PCI device\n");
 368                 goto err_out;
 369         }
 370
 371         if ((dp->resource[0].flags & IORESOURCE_MEM) == 0)
 372                 goto err_disable;
 373         addr = pci_resource_start(dp, 0);
 374         size = pci_resource_len(dp, 0);
 375         if (addr == 0)
 376                 goto err_disable;
 377
 378         p = framebuffer_alloc(0, &dp->dev);
 379         if (p == NULL) {
 380                 dev_err(&dp->dev, "Cannot allocate framebuffer structure\n");
 381                 rc = -ENOMEM;
 382                 goto err_disable;
 383         }
 384
 385         if (pci_request_region(dp, 0, "chipsfb") != 0) {
 386                 dev_err(&dp->dev, "Cannot request framebuffer\n");
 387                 rc = -EBUSY;
 388                 goto err_release_fb;
 389         }
 390
 391 #ifdef __BIG_ENDIAN
 392         addr += 0x800000;       // Use big-endian aperture
 393 #endif
 394
 395         /* we should use pci_enable_device here, but,
 396            the device doesn't declare its I/O ports in its BARs
 397            so pci_enable_device won't turn on I/O responses */
 398         pci_read_config_word(dp, PCI_COMMAND, &cmd);
 399         cmd |= 3;       /* enable memory and IO space */
 400         pci_write_config_word(dp, PCI_COMMAND, cmd);
 401
 402 #ifdef CONFIG_PMAC_BACKLIGHT
 403         /* turn on the backlight */
 404         set_backlight_enable(1);
 405 #endif /* CONFIG_PMAC_BACKLIGHT */
 406
 407 #ifdef CONFIG_PPC
 408         p->screen_base = __ioremap(addr, 0x200000, _PAGE_NO_CACHE);
 409 #else
 410         p->screen_base = ioremap(addr, 0x200000);
 411 #endif
 412         if (p->screen_base == NULL) {
 413                 dev_err(&dp->dev, "Cannot map framebuffer\n");
 414                 rc = -ENOMEM;
 415                 goto err_release_pci;
 416         }
 417
 418         pci_set_drvdata(dp, p);
 419         p->device = &dp->dev;
 420
 421         init_chips(p, addr);
 422
 423         if (register_framebuffer(p) < 0) {
 424                 dev_err(&dp->dev,"C&T 65550 framebuffer failed to register\n");
 425                 goto err_unmap;
 426         }
 427
 428         dev_info(&dp->dev,"fb%d: Chips 65550 frame buffer"
 429                  " (%dK RAM detected)\n",
 430                  p->node, p->fix.smem_len / 1024);
 431
 432         return 0;
 433
 434  err_unmap:
 435         iounmap(p->screen_base);
 436  err_release_pci:
 437         pci_release_region(dp, 0);
 438  err_release_fb:
 439         framebuffer_release(p);
 440  err_disable:
 441  err_out:
 442         return rc;
 443 }
 444
 445 static void __devexit chipsfb_remove(struct pci_dev *dp)
 446 {
 447         struct fb_info *p = pci_get_drvdata(dp);
 448
 449         if (p->screen_base == NULL)
 450                 return;
 451         unregister_framebuffer(p);
 452         iounmap(p->screen_base);
 453         p->screen_base = NULL;
 454         pci_release_region(dp, 0);
 455 }
 456
 457 #ifdef CONFIG_PM
 458 static int chipsfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
 459 {
 460         struct fb_info *p = pci_get_drvdata(pdev);
 461
 462         if (state.event == pdev->dev.power.power_state.event)
 463                 return 0;
 464         if (state.event != PM_SUSPEND_MEM)
 465                 goto done;
 466
 467         acquire_console_sem();
 468         chipsfb_blank(1, p);
 469         fb_set_suspend(p, 1);
 470         release_console_sem();
 471  done:
 472         pdev->dev.power.power_state = state;
 473         return 0;
 474 }
 475
 476 static int chipsfb_pci_resume(struct pci_dev *pdev)
 477 {
 478         struct fb_info *p = pci_get_drvdata(pdev);
 479
 480         acquire_console_sem();
 481         fb_set_suspend(p, 0);
 482         chipsfb_blank(0, p);
 483         release_console_sem();
 484
 485         pdev->dev.power.power_state = PMSG_ON;
 486         return 0;
 487 }
 488 #endif /* CONFIG_PM */
 489
 490
 491 static struct pci_device_id chipsfb_pci_tbl[] = {
 492         { PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_65550, PCI_ANY_ID, PCI_ANY_ID },
 493         { 0 }
 494 };
 495
 496 MODULE_DEVICE_TABLE(pci, chipsfb_pci_tbl);
 497
 498 static struct pci_driver chipsfb_driver = {
 499         .name =         "chipsfb",
 500         .id_table =     chipsfb_pci_tbl,
 501         .probe =        chipsfb_pci_init,
 502         .remove =       __devexit_p(chipsfb_remove),
 503 #ifdef CONFIG_PM
 504         .suspend =      chipsfb_pci_suspend,
 505         .resume =       chipsfb_pci_resume,
 506 #endif
 507 };
 508
 509 int __init chips_init(void)
 510 {
 511         if (fb_get_options("chipsfb", NULL))
 512                 return -ENODEV;
 513
 514         return pci_register_driver(&chipsfb_driver);
 515 }
 516
 517 module_init(chips_init);
 518
 519 static void __exit chipsfb_exit(void)
 520 {
 521         pci_unregister_driver(&chipsfb_driver);
 522 }
 523
 524 MODULE_LICENSE("GPL");