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[PATCH] w1: Make w1 connector notifications depend on connector.
[linux-2.6/verdex.git] / drivers / video / tgafb.c
blob7398bd48ba6c261c1a18079b1dda976446839570
1 /*
2 * linux/drivers/video/tgafb.c -- DEC 21030 TGA frame buffer device
3 *
4 * Copyright (C) 1995 Jay Estabrook
5 * Copyright (C) 1997 Geert Uytterhoeven
6 * Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha
7 * Copyright (C) 2002 Richard Henderson
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file COPYING in the main directory of this archive for
11 * more details.
12 */
13
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/sched.h>
17 #include <linux/errno.h>
18 #include <linux/string.h>
19 #include <linux/mm.h>
20 #include <linux/tty.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/init.h>
24 #include <linux/fb.h>
25 #include <linux/pci.h>
26 #include <linux/selection.h>
27 #include <asm/io.h>
28 #include <video/tgafb.h>
29 #include <linux/selection.h>
30
31 /*
32 * Local functions.
33 */
34
35 static int tgafb_check_var(struct fb_var_screeninfo *, struct fb_info *);
36 static int tgafb_set_par(struct fb_info *);
37 static void tgafb_set_pll(struct tga_par *, int);
38 static int tgafb_setcolreg(unsigned, unsigned, unsigned, unsigned,
39 unsigned, struct fb_info *);
40 static int tgafb_blank(int, struct fb_info *);
41 static void tgafb_init_fix(struct fb_info *);
42
43 static void tgafb_imageblit(struct fb_info *, const struct fb_image *);
44 static void tgafb_fillrect(struct fb_info *, const struct fb_fillrect *);
45 static void tgafb_copyarea(struct fb_info *, const struct fb_copyarea *);
46
47 static int tgafb_pci_register(struct pci_dev *, const struct pci_device_id *);
48 static void tgafb_pci_unregister(struct pci_dev *);
49
50 static const char *mode_option = "640x480@60";
51
52
53 /*
54 * Frame buffer operations
55 */
56
57 static struct fb_ops tgafb_ops = {
58 .owner = THIS_MODULE,
59 .fb_check_var = tgafb_check_var,
60 .fb_set_par = tgafb_set_par,
61 .fb_setcolreg = tgafb_setcolreg,
62 .fb_blank = tgafb_blank,
63 .fb_fillrect = tgafb_fillrect,
64 .fb_copyarea = tgafb_copyarea,
65 .fb_imageblit = tgafb_imageblit,
66 };
67
68
69 /*
70 * PCI registration operations
71 */
72
73 static struct pci_device_id const tgafb_pci_table[] = {
74 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TGA, PCI_ANY_ID, PCI_ANY_ID,
75 0, 0, 0 }
76 };
77
78 static struct pci_driver tgafb_driver = {
79 .name = "tgafb",
80 .id_table = tgafb_pci_table,
81 .probe = tgafb_pci_register,
82 .remove = __devexit_p(tgafb_pci_unregister),
83 };
84
85
86 /**
87 * tgafb_check_var - Optional function. Validates a var passed in.
88 * @var: frame buffer variable screen structure
89 * @info: frame buffer structure that represents a single frame buffer
90 */
91 static int
92 tgafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
93 {
94 struct tga_par *par = (struct tga_par *)info->par;
95
96 if (par->tga_type == TGA_TYPE_8PLANE) {
97 if (var->bits_per_pixel != 8)
98 return -EINVAL;
99 } else {
100 if (var->bits_per_pixel != 32)
101 return -EINVAL;
102 }
103
104 if (var->xres_virtual != var->xres || var->yres_virtual != var->yres)
105 return -EINVAL;
106 if (var->nonstd)
107 return -EINVAL;
108 if (1000000000 / var->pixclock > TGA_PLL_MAX_FREQ)
109 return -EINVAL;
110 if ((var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
111 return -EINVAL;
112
113 /* Some of the acceleration routines assume the line width is
114 a multiple of 64 bytes. */
115 if (var->xres * (par->tga_type == TGA_TYPE_8PLANE ? 1 : 4) % 64)
116 return -EINVAL;
117
118 return 0;
119 }
120
121 /**
122 * tgafb_set_par - Optional function. Alters the hardware state.
123 * @info: frame buffer structure that represents a single frame buffer
124 */
125 static int
126 tgafb_set_par(struct fb_info *info)
127 {
128 static unsigned int const deep_presets[4] = {
129 0x00014000,
130 0x0001440d,
131 0xffffffff,
132 0x0001441d
133 };
134 static unsigned int const rasterop_presets[4] = {
135 0x00000003,
136 0x00000303,
137 0xffffffff,
138 0x00000303
139 };
140 static unsigned int const mode_presets[4] = {
141 0x00002000,
142 0x00002300,
143 0xffffffff,
144 0x00002300
145 };
146 static unsigned int const base_addr_presets[4] = {
147 0x00000000,
148 0x00000001,
149 0xffffffff,
150 0x00000001
151 };
152
153 struct tga_par *par = (struct tga_par *) info->par;
154 u32 htimings, vtimings, pll_freq;
155 u8 tga_type;
156 int i, j;
157
158 /* Encode video timings. */
159 htimings = (((info->var.xres/4) & TGA_HORIZ_ACT_LSB)
160 | (((info->var.xres/4) & 0x600 << 19) & TGA_HORIZ_ACT_MSB));
161 vtimings = (info->var.yres & TGA_VERT_ACTIVE);
162 htimings |= ((info->var.right_margin/4) << 9) & TGA_HORIZ_FP;
163 vtimings |= (info->var.lower_margin << 11) & TGA_VERT_FP;
164 htimings |= ((info->var.hsync_len/4) << 14) & TGA_HORIZ_SYNC;
165 vtimings |= (info->var.vsync_len << 16) & TGA_VERT_SYNC;
166 htimings |= ((info->var.left_margin/4) << 21) & TGA_HORIZ_BP;
167 vtimings |= (info->var.upper_margin << 22) & TGA_VERT_BP;
168
169 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
170 htimings |= TGA_HORIZ_POLARITY;
171 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
172 vtimings |= TGA_VERT_POLARITY;
173
174 par->htimings = htimings;
175 par->vtimings = vtimings;
176
177 par->sync_on_green = !!(info->var.sync & FB_SYNC_ON_GREEN);
178
179 /* Store other useful values in par. */
180 par->xres = info->var.xres;
181 par->yres = info->var.yres;
182 par->pll_freq = pll_freq = 1000000000 / info->var.pixclock;
183 par->bits_per_pixel = info->var.bits_per_pixel;
184
185 tga_type = par->tga_type;
186
187 /* First, disable video. */
188 TGA_WRITE_REG(par, TGA_VALID_VIDEO | TGA_VALID_BLANK, TGA_VALID_REG);
189
190 /* Write the DEEP register. */
191 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
192 continue;
193 mb();
194 TGA_WRITE_REG(par, deep_presets[tga_type], TGA_DEEP_REG);
195 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
196 continue;
197 mb();
198
199 /* Write some more registers. */
200 TGA_WRITE_REG(par, rasterop_presets[tga_type], TGA_RASTEROP_REG);
201 TGA_WRITE_REG(par, mode_presets[tga_type], TGA_MODE_REG);
202 TGA_WRITE_REG(par, base_addr_presets[tga_type], TGA_BASE_ADDR_REG);
203
204 /* Calculate & write the PLL. */
205 tgafb_set_pll(par, pll_freq);
206
207 /* Write some more registers. */
208 TGA_WRITE_REG(par, 0xffffffff, TGA_PLANEMASK_REG);
209 TGA_WRITE_REG(par, 0xffffffff, TGA_PIXELMASK_REG);
210
211 /* Init video timing regs. */
212 TGA_WRITE_REG(par, htimings, TGA_HORIZ_REG);
213 TGA_WRITE_REG(par, vtimings, TGA_VERT_REG);
214
215 /* Initalise RAMDAC. */
216 if (tga_type == TGA_TYPE_8PLANE) {
217
218 /* Init BT485 RAMDAC registers. */
219 BT485_WRITE(par, 0xa2 | (par->sync_on_green ? 0x8 : 0x0),
220 BT485_CMD_0);
221 BT485_WRITE(par, 0x01, BT485_ADDR_PAL_WRITE);
222 BT485_WRITE(par, 0x14, BT485_CMD_3); /* cursor 64x64 */
223 BT485_WRITE(par, 0x40, BT485_CMD_1);
224 BT485_WRITE(par, 0x20, BT485_CMD_2); /* cursor off, for now */
225 BT485_WRITE(par, 0xff, BT485_PIXEL_MASK);
226
227 /* Fill palette registers. */
228 BT485_WRITE(par, 0x00, BT485_ADDR_PAL_WRITE);
229 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
230
231 for (i = 0; i < 16; i++) {
232 j = color_table[i];
233 TGA_WRITE_REG(par, default_red[j]|(BT485_DATA_PAL<<8),
234 TGA_RAMDAC_REG);
235 TGA_WRITE_REG(par, default_grn[j]|(BT485_DATA_PAL<<8),
236 TGA_RAMDAC_REG);
237 TGA_WRITE_REG(par, default_blu[j]|(BT485_DATA_PAL<<8),
238 TGA_RAMDAC_REG);
239 }
240 for (i = 0; i < 240*3; i += 4) {
241 TGA_WRITE_REG(par, 0x55|(BT485_DATA_PAL<<8),
242 TGA_RAMDAC_REG);
243 TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
244 TGA_RAMDAC_REG);
245 TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
246 TGA_RAMDAC_REG);
247 TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
248 TGA_RAMDAC_REG);
249 }
250
251 } else { /* 24-plane or 24plusZ */
252
253 /* Init BT463 registers. */
254 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_0, 0x40);
255 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_1, 0x08);
256 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_2,
257 (par->sync_on_green ? 0x80 : 0x40));
258
259 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_0, 0xff);
260 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_1, 0xff);
261 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_2, 0xff);
262 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_3, 0x0f);
263
264 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_0, 0x00);
265 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_1, 0x00);
266 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_2, 0x00);
267 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_3, 0x00);
268
269 /* Fill the palette. */
270 BT463_LOAD_ADDR(par, 0x0000);
271 TGA_WRITE_REG(par, BT463_PALETTE<<2, TGA_RAMDAC_REG);
272
273 for (i = 0; i < 16; i++) {
274 j = color_table[i];
275 TGA_WRITE_REG(par, default_red[j]|(BT463_PALETTE<<10),
276 TGA_RAMDAC_REG);
277 TGA_WRITE_REG(par, default_grn[j]|(BT463_PALETTE<<10),
278 TGA_RAMDAC_REG);
279 TGA_WRITE_REG(par, default_blu[j]|(BT463_PALETTE<<10),
280 TGA_RAMDAC_REG);
281 }
282 for (i = 0; i < 512*3; i += 4) {
283 TGA_WRITE_REG(par, 0x55|(BT463_PALETTE<<10),
284 TGA_RAMDAC_REG);
285 TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
286 TGA_RAMDAC_REG);
287 TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
288 TGA_RAMDAC_REG);
289 TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
290 TGA_RAMDAC_REG);
291 }
292
293 /* Fill window type table after start of vertical retrace. */
294 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
295 continue;
296 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
297 mb();
298 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
299 continue;
300 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
301
302 BT463_LOAD_ADDR(par, BT463_WINDOW_TYPE_BASE);
303 TGA_WRITE_REG(par, BT463_REG_ACC<<2, TGA_RAMDAC_SETUP_REG);
304
305 for (i = 0; i < 16; i++) {
306 TGA_WRITE_REG(par, 0x00|(BT463_REG_ACC<<10),
307 TGA_RAMDAC_REG);
308 TGA_WRITE_REG(par, 0x01|(BT463_REG_ACC<<10),
309 TGA_RAMDAC_REG);
310 TGA_WRITE_REG(par, 0x80|(BT463_REG_ACC<<10),
311 TGA_RAMDAC_REG);
312 }
313
314 }
315
316 /* Finally, enable video scan (and pray for the monitor... :-) */
317 TGA_WRITE_REG(par, TGA_VALID_VIDEO, TGA_VALID_REG);
318
319 return 0;
320 }
321
322 #define DIFFCHECK(X) \
323 do { \
324 if (m <= 0x3f) { \
325 int delta = f - (TGA_PLL_BASE_FREQ * (X)) / (r << shift); \
326 if (delta < 0) \
327 delta = -delta; \
328 if (delta < min_diff) \
329 min_diff = delta, vm = m, va = a, vr = r; \
330 } \
331 } while (0)
332
333 static void
334 tgafb_set_pll(struct tga_par *par, int f)
335 {
336 int n, shift, base, min_diff, target;
337 int r,a,m,vm = 34, va = 1, vr = 30;
338
339 for (r = 0 ; r < 12 ; r++)
340 TGA_WRITE_REG(par, !r, TGA_CLOCK_REG);
341
342 if (f > TGA_PLL_MAX_FREQ)
343 f = TGA_PLL_MAX_FREQ;
344
345 if (f >= TGA_PLL_MAX_FREQ / 2)
346 shift = 0;
347 else if (f >= TGA_PLL_MAX_FREQ / 4)
348 shift = 1;
349 else
350 shift = 2;
351
352 TGA_WRITE_REG(par, shift & 1, TGA_CLOCK_REG);
353 TGA_WRITE_REG(par, shift >> 1, TGA_CLOCK_REG);
354
355 for (r = 0 ; r < 10 ; r++)
356 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
357
358 if (f <= 120000) {
359 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
360 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
361 }
362 else if (f <= 200000) {
363 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
364 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
365 }
366 else {
367 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
368 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
369 }
370
371 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
372 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
373 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
374 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
375 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
376 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
377
378 target = (f << shift) / TGA_PLL_BASE_FREQ;
379 min_diff = TGA_PLL_MAX_FREQ;
380
381 r = 7 / target;
382 if (!r) r = 1;
383
384 base = target * r;
385 while (base < 449) {
386 for (n = base < 7 ? 7 : base; n < base + target && n < 449; n++) {
387 m = ((n + 3) / 7) - 1;
388 a = 0;
389 DIFFCHECK((m + 1) * 7);
390 m++;
391 DIFFCHECK((m + 1) * 7);
392 m = (n / 6) - 1;
393 if ((a = n % 6))
394 DIFFCHECK(n);
395 }
396 r++;
397 base += target;
398 }
399
400 vr--;
401
402 for (r = 0; r < 8; r++)
403 TGA_WRITE_REG(par, (vm >> r) & 1, TGA_CLOCK_REG);
404 for (r = 0; r < 8 ; r++)
405 TGA_WRITE_REG(par, (va >> r) & 1, TGA_CLOCK_REG);
406 for (r = 0; r < 7 ; r++)
407 TGA_WRITE_REG(par, (vr >> r) & 1, TGA_CLOCK_REG);
408 TGA_WRITE_REG(par, ((vr >> 7) & 1)|2, TGA_CLOCK_REG);
409 }
410
411
412 /**
413 * tgafb_setcolreg - Optional function. Sets a color register.
414 * @regno: boolean, 0 copy local, 1 get_user() function
415 * @red: frame buffer colormap structure
416 * @green: The green value which can be up to 16 bits wide
417 * @blue: The blue value which can be up to 16 bits wide.
418 * @transp: If supported the alpha value which can be up to 16 bits wide.
419 * @info: frame buffer info structure
420 */
421 static int
422 tgafb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
423 unsigned transp, struct fb_info *info)
424 {
425 struct tga_par *par = (struct tga_par *) info->par;
426
427 if (regno > 255)
428 return 1;
429 red >>= 8;
430 green >>= 8;
431 blue >>= 8;
432
433 if (par->tga_type == TGA_TYPE_8PLANE) {
434 BT485_WRITE(par, regno, BT485_ADDR_PAL_WRITE);
435 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
436 TGA_WRITE_REG(par, red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
437 TGA_WRITE_REG(par, green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
438 TGA_WRITE_REG(par, blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
439 } else if (regno < 16) {
440 u32 value = (red << 16) | (green << 8) | blue;
441 ((u32 *)info->pseudo_palette)[regno] = value;
442 }
443
444 return 0;
445 }
446
447
448 /**
449 * tgafb_blank - Optional function. Blanks the display.
450 * @blank_mode: the blank mode we want.
451 * @info: frame buffer structure that represents a single frame buffer
452 */
453 static int
454 tgafb_blank(int blank, struct fb_info *info)
455 {
456 struct tga_par *par = (struct tga_par *) info->par;
457 u32 vhcr, vvcr, vvvr;
458 unsigned long flags;
459
460 local_irq_save(flags);
461
462 vhcr = TGA_READ_REG(par, TGA_HORIZ_REG);
463 vvcr = TGA_READ_REG(par, TGA_VERT_REG);
464 vvvr = TGA_READ_REG(par, TGA_VALID_REG);
465 vvvr &= ~(TGA_VALID_VIDEO | TGA_VALID_BLANK);
466
467 switch (blank) {
468 case FB_BLANK_UNBLANK: /* Unblanking */
469 if (par->vesa_blanked) {
470 TGA_WRITE_REG(par, vhcr & 0xbfffffff, TGA_HORIZ_REG);
471 TGA_WRITE_REG(par, vvcr & 0xbfffffff, TGA_VERT_REG);
472 par->vesa_blanked = 0;
473 }
474 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO, TGA_VALID_REG);
475 break;
476
477 case FB_BLANK_NORMAL: /* Normal blanking */
478 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO | TGA_VALID_BLANK,
479 TGA_VALID_REG);
480 break;
481
482 case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
483 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
484 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
485 par->vesa_blanked = 1;
486 break;
487
488 case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
489 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
490 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
491 par->vesa_blanked = 1;
492 break;
493
494 case FB_BLANK_POWERDOWN: /* Poweroff */
495 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
496 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
497 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
498 par->vesa_blanked = 1;
499 break;
500 }
501
502 local_irq_restore(flags);
503 return 0;
504 }
505
506
507 /*
508 * Acceleration.
509 */
510
511 /**
512 * tgafb_imageblit - REQUIRED function. Can use generic routines if
513 * non acclerated hardware and packed pixel based.
514 * Copies a image from system memory to the screen.
515 *
516 * @info: frame buffer structure that represents a single frame buffer
517 * @image: structure defining the image.
518 */
519 static void
520 tgafb_imageblit(struct fb_info *info, const struct fb_image *image)
521 {
522 static unsigned char const bitrev[256] = {
523 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
524 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
525 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
526 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
527 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
528 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
529 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
530 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
531 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
532 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
533 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
534 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
535 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
536 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
537 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
538 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
539 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
540 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
541 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
542 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
543 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
544 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
545 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
546 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
547 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
548 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
549 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
550 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
551 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
552 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
553 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
554 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff
555 };
556
557 struct tga_par *par = (struct tga_par *) info->par;
558 u32 fgcolor, bgcolor, dx, dy, width, height, vxres, vyres, pixelmask;
559 unsigned long rincr, line_length, shift, pos, is8bpp;
560 unsigned long i, j;
561 const unsigned char *data;
562 void __iomem *regs_base;
563 void __iomem *fb_base;
564
565 dx = image->dx;
566 dy = image->dy;
567 width = image->width;
568 height = image->height;
569 vxres = info->var.xres_virtual;
570 vyres = info->var.yres_virtual;
571 line_length = info->fix.line_length;
572 rincr = (width + 7) / 8;
573
574 /* Crop the image to the screen. */
575 if (dx > vxres || dy > vyres)
576 return;
577 if (dx + width > vxres)
578 width = vxres - dx;
579 if (dy + height > vyres)
580 height = vyres - dy;
581
582 /* For copies that aren't pixel expansion, there's little we
583 can do better than the generic code. */
584 /* ??? There is a DMA write mode; I wonder if that could be
585 made to pull the data from the image buffer... */
586 if (image->depth > 1) {
587 cfb_imageblit(info, image);
588 return;
589 }
590
591 regs_base = par->tga_regs_base;
592 fb_base = par->tga_fb_base;
593 is8bpp = info->var.bits_per_pixel == 8;
594
595 /* Expand the color values to fill 32-bits. */
596 /* ??? Would be nice to notice colour changes elsewhere, so
597 that we can do this only when necessary. */
598 fgcolor = image->fg_color;
599 bgcolor = image->bg_color;
600 if (is8bpp) {
601 fgcolor |= fgcolor << 8;
602 fgcolor |= fgcolor << 16;
603 bgcolor |= bgcolor << 8;
604 bgcolor |= bgcolor << 16;
605 } else {
606 if (fgcolor < 16)
607 fgcolor = ((u32 *)info->pseudo_palette)[fgcolor];
608 if (bgcolor < 16)
609 bgcolor = ((u32 *)info->pseudo_palette)[bgcolor];
610 }
611 __raw_writel(fgcolor, regs_base + TGA_FOREGROUND_REG);
612 __raw_writel(bgcolor, regs_base + TGA_BACKGROUND_REG);
613
614 /* Acquire proper alignment; set up the PIXELMASK register
615 so that we only write the proper character cell. */
616 pos = dy * line_length;
617 if (is8bpp) {
618 pos += dx;
619 shift = pos & 3;
620 pos &= -4;
621 } else {
622 pos += dx * 4;
623 shift = (pos & 7) >> 2;
624 pos &= -8;
625 }
626
627 data = (const unsigned char *) image->data;
628
629 /* Enable opaque stipple mode. */
630 __raw_writel((is8bpp
631 ? TGA_MODE_SBM_8BPP | TGA_MODE_OPAQUE_STIPPLE
632 : TGA_MODE_SBM_24BPP | TGA_MODE_OPAQUE_STIPPLE),
633 regs_base + TGA_MODE_REG);
634
635 if (width + shift <= 32) {
636 unsigned long bwidth;
637
638 /* Handle common case of imaging a single character, in
639 a font less than 32 pixels wide. */
640
641 pixelmask = (1 << width) - 1;
642 pixelmask <<= shift;
643 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
644 wmb();
645
646 bwidth = (width + 7) / 8;
647
648 for (i = 0; i < height; ++i) {
649 u32 mask = 0;
650
651 /* The image data is bit big endian; we need
652 little endian. */
653 for (j = 0; j < bwidth; ++j)
654 mask |= bitrev[data[j]] << (j * 8);
655
656 __raw_writel(mask << shift, fb_base + pos);
657
658 pos += line_length;
659 data += rincr;
660 }
661 wmb();
662 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
663 } else if (shift == 0) {
664 unsigned long pos0 = pos;
665 const unsigned char *data0 = data;
666 unsigned long bincr = (is8bpp ? 8 : 8*4);
667 unsigned long bwidth;
668
669 /* Handle another common case in which accel_putcs
670 generates a large bitmap, which happens to be aligned.
671 Allow the tail to be misaligned. This case is
672 interesting because we've not got to hold partial
673 bytes across the words being written. */
674
675 wmb();
676
677 bwidth = (width / 8) & -4;
678 for (i = 0; i < height; ++i) {
679 for (j = 0; j < bwidth; j += 4) {
680 u32 mask = 0;
681 mask |= bitrev[data[j+0]] << (0 * 8);
682 mask |= bitrev[data[j+1]] << (1 * 8);
683 mask |= bitrev[data[j+2]] << (2 * 8);
684 mask |= bitrev[data[j+3]] << (3 * 8);
685 __raw_writel(mask, fb_base + pos + j*bincr);
686 }
687 pos += line_length;
688 data += rincr;
689 }
690 wmb();
691
692 pixelmask = (1ul << (width & 31)) - 1;
693 if (pixelmask) {
694 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
695 wmb();
696
697 pos = pos0 + bwidth*bincr;
698 data = data0 + bwidth;
699 bwidth = ((width & 31) + 7) / 8;
700
701 for (i = 0; i < height; ++i) {
702 u32 mask = 0;
703 for (j = 0; j < bwidth; ++j)
704 mask |= bitrev[data[j]] << (j * 8);
705 __raw_writel(mask, fb_base + pos);
706 pos += line_length;
707 data += rincr;
708 }
709 wmb();
710 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
711 }
712 } else {
713 unsigned long pos0 = pos;
714 const unsigned char *data0 = data;
715 unsigned long bincr = (is8bpp ? 8 : 8*4);
716 unsigned long bwidth;
717
718 /* Finally, handle the generic case of misaligned start.
719 Here we split the write into 16-bit spans. This allows
720 us to use only one pixel mask, instead of four as would
721 be required by writing 24-bit spans. */
722
723 pixelmask = 0xffff << shift;
724 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
725 wmb();
726
727 bwidth = (width / 8) & -2;
728 for (i = 0; i < height; ++i) {
729 for (j = 0; j < bwidth; j += 2) {
730 u32 mask = 0;
731 mask |= bitrev[data[j+0]] << (0 * 8);
732 mask |= bitrev[data[j+1]] << (1 * 8);
733 mask <<= shift;
734 __raw_writel(mask, fb_base + pos + j*bincr);
735 }
736 pos += line_length;
737 data += rincr;
738 }
739 wmb();
740
741 pixelmask = ((1ul << (width & 15)) - 1) << shift;
742 if (pixelmask) {
743 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
744 wmb();
745
746 pos = pos0 + bwidth*bincr;
747 data = data0 + bwidth;
748 bwidth = (width & 15) > 8;
749
750 for (i = 0; i < height; ++i) {
751 u32 mask = bitrev[data[0]];
752 if (bwidth)
753 mask |= bitrev[data[1]] << 8;
754 mask <<= shift;
755 __raw_writel(mask, fb_base + pos);
756 pos += line_length;
757 data += rincr;
758 }
759 wmb();
760 }
761 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
762 }
763
764 /* Disable opaque stipple mode. */
765 __raw_writel((is8bpp
766 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE
767 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE),
768 regs_base + TGA_MODE_REG);
769 }
770
771 /**
772 * tgafb_fillrect - REQUIRED function. Can use generic routines if
773 * non acclerated hardware and packed pixel based.
774 * Draws a rectangle on the screen.
775 *
776 * @info: frame buffer structure that represents a single frame buffer
777 * @rect: structure defining the rectagle and operation.
778 */
779 static void
780 tgafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
781 {
782 struct tga_par *par = (struct tga_par *) info->par;
783 int is8bpp = info->var.bits_per_pixel == 8;
784 u32 dx, dy, width, height, vxres, vyres, color;
785 unsigned long pos, align, line_length, i, j;
786 void __iomem *regs_base;
787 void __iomem *fb_base;
788
789 dx = rect->dx;
790 dy = rect->dy;
791 width = rect->width;
792 height = rect->height;
793 vxres = info->var.xres_virtual;
794 vyres = info->var.yres_virtual;
795 line_length = info->fix.line_length;
796 regs_base = par->tga_regs_base;
797 fb_base = par->tga_fb_base;
798
799 /* Crop the rectangle to the screen. */
800 if (dx > vxres || dy > vyres || !width || !height)
801 return;
802 if (dx + width > vxres)
803 width = vxres - dx;
804 if (dy + height > vyres)
805 height = vyres - dy;
806
807 pos = dy * line_length + dx * (is8bpp ? 1 : 4);
808
809 /* ??? We could implement ROP_XOR with opaque fill mode
810 and a RasterOp setting of GXxor, but as far as I can
811 tell, this mode is not actually used in the kernel.
812 Thus I am ignoring it for now. */
813 if (rect->rop != ROP_COPY) {
814 cfb_fillrect(info, rect);
815 return;
816 }
817
818 /* Expand the color value to fill 8 pixels. */
819 color = rect->color;
820 if (is8bpp) {
821 color |= color << 8;
822 color |= color << 16;
823 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
824 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
825 } else {
826 if (color < 16)
827 color = ((u32 *)info->pseudo_palette)[color];
828 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
829 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
830 __raw_writel(color, regs_base + TGA_BLOCK_COLOR2_REG);
831 __raw_writel(color, regs_base + TGA_BLOCK_COLOR3_REG);
832 __raw_writel(color, regs_base + TGA_BLOCK_COLOR4_REG);
833 __raw_writel(color, regs_base + TGA_BLOCK_COLOR5_REG);
834 __raw_writel(color, regs_base + TGA_BLOCK_COLOR6_REG);
835 __raw_writel(color, regs_base + TGA_BLOCK_COLOR7_REG);
836 }
837
838 /* The DATA register holds the fill mask for block fill mode.
839 Since we're not stippling, this is all ones. */
840 __raw_writel(0xffffffff, regs_base + TGA_DATA_REG);
841
842 /* Enable block fill mode. */
843 __raw_writel((is8bpp
844 ? TGA_MODE_SBM_8BPP | TGA_MODE_BLOCK_FILL
845 : TGA_MODE_SBM_24BPP | TGA_MODE_BLOCK_FILL),
846 regs_base + TGA_MODE_REG);
847 wmb();
848
849 /* We can fill 2k pixels per operation. Notice blocks that fit
850 the width of the screen so that we can take advantage of this
851 and fill more than one line per write. */
852 if (width == line_length)
853 width *= height, height = 1;
854
855 /* The write into the frame buffer must be aligned to 4 bytes,
856 but we are allowed to encode the offset within the word in
857 the data word written. */
858 align = (pos & 3) << 16;
859 pos &= -4;
860
861 if (width <= 2048) {
862 u32 data;
863
864 data = (width - 1) | align;
865
866 for (i = 0; i < height; ++i) {
867 __raw_writel(data, fb_base + pos);
868 pos += line_length;
869 }
870 } else {
871 unsigned long Bpp = (is8bpp ? 1 : 4);
872 unsigned long nwidth = width & -2048;
873 u32 fdata, ldata;
874
875 fdata = (2048 - 1) | align;
876 ldata = ((width & 2047) - 1) | align;
877
878 for (i = 0; i < height; ++i) {
879 for (j = 0; j < nwidth; j += 2048)
880 __raw_writel(fdata, fb_base + pos + j*Bpp);
881 if (j < width)
882 __raw_writel(ldata, fb_base + pos + j*Bpp);
883 pos += line_length;
884 }
885 }
886 wmb();
887
888 /* Disable block fill mode. */
889 __raw_writel((is8bpp
890 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE
891 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE),
892 regs_base + TGA_MODE_REG);
893 }
894
895 /**
896 * tgafb_copyarea - REQUIRED function. Can use generic routines if
897 * non acclerated hardware and packed pixel based.
898 * Copies on area of the screen to another area.
899 *
900 * @info: frame buffer structure that represents a single frame buffer
901 * @area: structure defining the source and destination.
902 */
903
904 /* Handle the special case of copying entire lines, e.g. during scrolling.
905 We can avoid a lot of needless computation in this case. In the 8bpp
906 case we need to use the COPY64 registers instead of mask writes into
907 the frame buffer to achieve maximum performance. */
908
909 static inline void
910 copyarea_line_8bpp(struct fb_info *info, u32 dy, u32 sy,
911 u32 height, u32 width)
912 {
913 struct tga_par *par = (struct tga_par *) info->par;
914 void __iomem *tga_regs = par->tga_regs_base;
915 unsigned long dpos, spos, i, n64;
916
917 /* Set up the MODE and PIXELSHIFT registers. */
918 __raw_writel(TGA_MODE_SBM_8BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
919 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
920 wmb();
921
922 n64 = (height * width) / 64;
923
924 if (dy < sy) {
925 spos = (sy + height) * width;
926 dpos = (dy + height) * width;
927
928 for (i = 0; i < n64; ++i) {
929 spos -= 64;
930 dpos -= 64;
931 __raw_writel(spos, tga_regs+TGA_COPY64_SRC);
932 wmb();
933 __raw_writel(dpos, tga_regs+TGA_COPY64_DST);
934 wmb();
935 }
936 } else {
937 spos = sy * width;
938 dpos = dy * width;
939
940 for (i = 0; i < n64; ++i) {
941 __raw_writel(spos, tga_regs+TGA_COPY64_SRC);
942 wmb();
943 __raw_writel(dpos, tga_regs+TGA_COPY64_DST);
944 wmb();
945 spos += 64;
946 dpos += 64;
947 }
948 }
949
950 /* Reset the MODE register to normal. */
951 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
952 }
953
954 static inline void
955 copyarea_line_32bpp(struct fb_info *info, u32 dy, u32 sy,
956 u32 height, u32 width)
957 {
958 struct tga_par *par = (struct tga_par *) info->par;
959 void __iomem *tga_regs = par->tga_regs_base;
960 void __iomem *tga_fb = par->tga_fb_base;
961 void __iomem *src;
962 void __iomem *dst;
963 unsigned long i, n16;
964
965 /* Set up the MODE and PIXELSHIFT registers. */
966 __raw_writel(TGA_MODE_SBM_24BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
967 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
968 wmb();
969
970 n16 = (height * width) / 16;
971
972 if (dy < sy) {
973 src = tga_fb + (sy + height) * width * 4;
974 dst = tga_fb + (dy + height) * width * 4;
975
976 for (i = 0; i < n16; ++i) {
977 src -= 64;
978 dst -= 64;
979 __raw_writel(0xffff, src);
980 wmb();
981 __raw_writel(0xffff, dst);
982 wmb();
983 }
984 } else {
985 src = tga_fb + sy * width * 4;
986 dst = tga_fb + dy * width * 4;
987
988 for (i = 0; i < n16; ++i) {
989 __raw_writel(0xffff, src);
990 wmb();
991 __raw_writel(0xffff, dst);
992 wmb();
993 src += 64;
994 dst += 64;
995 }
996 }
997
998 /* Reset the MODE register to normal. */
999 __raw_writel(TGA_MODE_SBM_24BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1000 }
1001
1002 /* The general case of forward copy in 8bpp mode. */
1003 static inline void
1004 copyarea_foreward_8bpp(struct fb_info *info, u32 dx, u32 dy, u32 sx, u32 sy,
1005 u32 height, u32 width, u32 line_length)
1006 {
1007 struct tga_par *par = (struct tga_par *) info->par;
1008 unsigned long i, copied, left;
1009 unsigned long dpos, spos, dalign, salign, yincr;
1010 u32 smask_first, dmask_first, dmask_last;
1011 int pixel_shift, need_prime, need_second;
1012 unsigned long n64, n32, xincr_first;
1013 void __iomem *tga_regs;
1014 void __iomem *tga_fb;
1015
1016 yincr = line_length;
1017 if (dy > sy) {
1018 dy += height - 1;
1019 sy += height - 1;
1020 yincr = -yincr;
1021 }
1022
1023 /* Compute the offsets and alignments in the frame buffer.
1024 More than anything else, these control how we do copies. */
1025 dpos = dy * line_length + dx;
1026 spos = sy * line_length + sx;
1027 dalign = dpos & 7;
1028 salign = spos & 7;
1029 dpos &= -8;
1030 spos &= -8;
1031
1032 /* Compute the value for the PIXELSHIFT register. This controls
1033 both non-co-aligned source and destination and copy direction. */
1034 if (dalign >= salign)
1035 pixel_shift = dalign - salign;
1036 else
1037 pixel_shift = 8 - (salign - dalign);
1038
1039 /* Figure out if we need an additional priming step for the
1040 residue register. */
1041 need_prime = (salign > dalign);
1042 if (need_prime)
1043 dpos -= 8;
1044
1045 /* Begin by copying the leading unaligned destination. Copy enough
1046 to make the next destination address 32-byte aligned. */
1047 copied = 32 - (dalign + (dpos & 31));
1048 if (copied == 32)
1049 copied = 0;
1050 xincr_first = (copied + 7) & -8;
1051 smask_first = dmask_first = (1ul << copied) - 1;
1052 smask_first <<= salign;
1053 dmask_first <<= dalign + need_prime*8;
1054 if (need_prime && copied > 24)
1055 copied -= 8;
1056 left = width - copied;
1057
1058 /* Care for small copies. */
1059 if (copied > width) {
1060 u32 t;
1061 t = (1ul << width) - 1;
1062 t <<= dalign + need_prime*8;
1063 dmask_first &= t;
1064 left = 0;
1065 }
1066
1067 /* Attempt to use 64-byte copies. This is only possible if the
1068 source and destination are co-aligned at 64 bytes. */
1069 n64 = need_second = 0;
1070 if ((dpos & 63) == (spos & 63)
1071 && (height == 1 || line_length % 64 == 0)) {
1072 /* We may need a 32-byte copy to ensure 64 byte alignment. */
1073 need_second = (dpos + xincr_first) & 63;
1074 if ((need_second & 32) != need_second)
1075 printk(KERN_ERR "tgafb: need_second wrong\n");
1076 if (left >= need_second + 64) {
1077 left -= need_second;
1078 n64 = left / 64;
1079 left %= 64;
1080 } else
1081 need_second = 0;
1082 }
1083
1084 /* Copy trailing full 32-byte sections. This will be the main
1085 loop if the 64 byte loop can't be used. */
1086 n32 = left / 32;
1087 left %= 32;
1088
1089 /* Copy the trailing unaligned destination. */
1090 dmask_last = (1ul << left) - 1;
1091
1092 tga_regs = par->tga_regs_base;
1093 tga_fb = par->tga_fb_base;
1094
1095 /* Set up the MODE and PIXELSHIFT registers. */
1096 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1097 __raw_writel(pixel_shift, tga_regs+TGA_PIXELSHIFT_REG);
1098 wmb();
1099
1100 for (i = 0; i < height; ++i) {
1101 unsigned long j;
1102 void __iomem *sfb;
1103 void __iomem *dfb;
1104
1105 sfb = tga_fb + spos;
1106 dfb = tga_fb + dpos;
1107 if (dmask_first) {
1108 __raw_writel(smask_first, sfb);
1109 wmb();
1110 __raw_writel(dmask_first, dfb);
1111 wmb();
1112 sfb += xincr_first;
1113 dfb += xincr_first;
1114 }
1115
1116 if (need_second) {
1117 __raw_writel(0xffffffff, sfb);
1118 wmb();
1119 __raw_writel(0xffffffff, dfb);
1120 wmb();
1121 sfb += 32;
1122 dfb += 32;
1123 }
1124
1125 if (n64 && (((unsigned long)sfb | (unsigned long)dfb) & 63))
1126 printk(KERN_ERR
1127 "tgafb: misaligned copy64 (s:%p, d:%p)\n",
1128 sfb, dfb);
1129
1130 for (j = 0; j < n64; ++j) {
1131 __raw_writel(sfb - tga_fb, tga_regs+TGA_COPY64_SRC);
1132 wmb();
1133 __raw_writel(dfb - tga_fb, tga_regs+TGA_COPY64_DST);
1134 wmb();
1135 sfb += 64;
1136 dfb += 64;
1137 }
1138
1139 for (j = 0; j < n32; ++j) {
1140 __raw_writel(0xffffffff, sfb);
1141 wmb();
1142 __raw_writel(0xffffffff, dfb);
1143 wmb();
1144 sfb += 32;
1145 dfb += 32;
1146 }
1147
1148 if (dmask_last) {
1149 __raw_writel(0xffffffff, sfb);
1150 wmb();
1151 __raw_writel(dmask_last, dfb);
1152 wmb();
1153 }
1154
1155 spos += yincr;
1156 dpos += yincr;
1157 }
1158
1159 /* Reset the MODE register to normal. */
1160 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1161 }
1162
1163 /* The (almost) general case of backward copy in 8bpp mode. */
1164 static inline void
1165 copyarea_backward_8bpp(struct fb_info *info, u32 dx, u32 dy, u32 sx, u32 sy,
1166 u32 height, u32 width, u32 line_length,
1167 const struct fb_copyarea *area)
1168 {
1169 struct tga_par *par = (struct tga_par *) info->par;
1170 unsigned long i, left, yincr;
1171 unsigned long depos, sepos, dealign, sealign;
1172 u32 mask_first, mask_last;
1173 unsigned long n32;
1174 void __iomem *tga_regs;
1175 void __iomem *tga_fb;
1176
1177 yincr = line_length;
1178 if (dy > sy) {
1179 dy += height - 1;
1180 sy += height - 1;
1181 yincr = -yincr;
1182 }
1183
1184 /* Compute the offsets and alignments in the frame buffer.
1185 More than anything else, these control how we do copies. */
1186 depos = dy * line_length + dx + width;
1187 sepos = sy * line_length + sx + width;
1188 dealign = depos & 7;
1189 sealign = sepos & 7;
1190
1191 /* ??? The documentation appears to be incorrect (or very
1192 misleading) wrt how pixel shifting works in backward copy
1193 mode, i.e. when PIXELSHIFT is negative. I give up for now.
1194 Do handle the common case of co-aligned backward copies,
1195 but frob everything else back on generic code. */
1196 if (dealign != sealign) {
1197 cfb_copyarea(info, area);
1198 return;
1199 }
1200
1201 /* We begin the copy with the trailing pixels of the
1202 unaligned destination. */
1203 mask_first = (1ul << dealign) - 1;
1204 left = width - dealign;
1205
1206 /* Care for small copies. */
1207 if (dealign > width) {
1208 mask_first ^= (1ul << (dealign - width)) - 1;
1209 left = 0;
1210 }
1211
1212 /* Next copy full words at a time. */
1213 n32 = left / 32;
1214 left %= 32;
1215
1216 /* Finally copy the unaligned head of the span. */
1217 mask_last = -1 << (32 - left);
1218
1219 tga_regs = par->tga_regs_base;
1220 tga_fb = par->tga_fb_base;
1221
1222 /* Set up the MODE and PIXELSHIFT registers. */
1223 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1224 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
1225 wmb();
1226
1227 for (i = 0; i < height; ++i) {
1228 unsigned long j;
1229 void __iomem *sfb;
1230 void __iomem *dfb;
1231
1232 sfb = tga_fb + sepos;
1233 dfb = tga_fb + depos;
1234 if (mask_first) {
1235 __raw_writel(mask_first, sfb);
1236 wmb();
1237 __raw_writel(mask_first, dfb);
1238 wmb();
1239 }
1240
1241 for (j = 0; j < n32; ++j) {
1242 sfb -= 32;
1243 dfb -= 32;
1244 __raw_writel(0xffffffff, sfb);
1245 wmb();
1246 __raw_writel(0xffffffff, dfb);
1247 wmb();
1248 }
1249
1250 if (mask_last) {
1251 sfb -= 32;
1252 dfb -= 32;
1253 __raw_writel(mask_last, sfb);
1254 wmb();
1255 __raw_writel(mask_last, dfb);
1256 wmb();
1257 }
1258
1259 sepos += yincr;
1260 depos += yincr;
1261 }
1262
1263 /* Reset the MODE register to normal. */
1264 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1265 }
1266
1267 static void
1268 tgafb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
1269 {
1270 unsigned long dx, dy, width, height, sx, sy, vxres, vyres;
1271 unsigned long line_length, bpp;
1272
1273 dx = area->dx;
1274 dy = area->dy;
1275 width = area->width;
1276 height = area->height;
1277 sx = area->sx;
1278 sy = area->sy;
1279 vxres = info->var.xres_virtual;
1280 vyres = info->var.yres_virtual;
1281 line_length = info->fix.line_length;
1282
1283 /* The top left corners must be in the virtual screen. */
1284 if (dx > vxres || sx > vxres || dy > vyres || sy > vyres)
1285 return;
1286
1287 /* Clip the destination. */
1288 if (dx + width > vxres)
1289 width = vxres - dx;
1290 if (dy + height > vyres)
1291 height = vyres - dy;
1292
1293 /* The source must be completely inside the virtual screen. */
1294 if (sx + width > vxres || sy + height > vyres)
1295 return;
1296
1297 bpp = info->var.bits_per_pixel;
1298
1299 /* Detect copies of the entire line. */
1300 if (width * (bpp >> 3) == line_length) {
1301 if (bpp == 8)
1302 copyarea_line_8bpp(info, dy, sy, height, width);
1303 else
1304 copyarea_line_32bpp(info, dy, sy, height, width);
1305 }
1306
1307 /* ??? The documentation is unclear to me exactly how the pixelshift
1308 register works in 32bpp mode. Since I don't have hardware to test,
1309 give up for now and fall back on the generic routines. */
1310 else if (bpp == 32)
1311 cfb_copyarea(info, area);
1312
1313 /* Detect overlapping source and destination that requires
1314 a backward copy. */
1315 else if (dy == sy && dx > sx && dx < sx + width)
1316 copyarea_backward_8bpp(info, dx, dy, sx, sy, height,
1317 width, line_length, area);
1318 else
1319 copyarea_foreward_8bpp(info, dx, dy, sx, sy, height,
1320 width, line_length);
1321 }
1322
1323
1324 /*
1325 * Initialisation
1326 */
1327
1328 static void
1329 tgafb_init_fix(struct fb_info *info)
1330 {
1331 struct tga_par *par = (struct tga_par *)info->par;
1332 u8 tga_type = par->tga_type;
1333 const char *tga_type_name;
1334
1335 switch (tga_type) {
1336 case TGA_TYPE_8PLANE:
1337 tga_type_name = "Digital ZLXp-E1";
1338 break;
1339 case TGA_TYPE_24PLANE:
1340 tga_type_name = "Digital ZLXp-E2";
1341 break;
1342 case TGA_TYPE_24PLUSZ:
1343 tga_type_name = "Digital ZLXp-E3";
1344 break;
1345 default:
1346 tga_type_name = "Unknown";
1347 break;
1348 }
1349
1350 strlcpy(info->fix.id, tga_type_name, sizeof(info->fix.id));
1351
1352 info->fix.type = FB_TYPE_PACKED_PIXELS;
1353 info->fix.type_aux = 0;
1354 info->fix.visual = (tga_type == TGA_TYPE_8PLANE
1355 ? FB_VISUAL_PSEUDOCOLOR
1356 : FB_VISUAL_TRUECOLOR);
1357
1358 info->fix.line_length = par->xres * (par->bits_per_pixel >> 3);
1359 info->fix.smem_start = (size_t) par->tga_fb_base;
1360 info->fix.smem_len = info->fix.line_length * par->yres;
1361 info->fix.mmio_start = (size_t) par->tga_regs_base;
1362 info->fix.mmio_len = 512;
1363
1364 info->fix.xpanstep = 0;
1365 info->fix.ypanstep = 0;
1366 info->fix.ywrapstep = 0;
1367
1368 info->fix.accel = FB_ACCEL_DEC_TGA;
1369 }
1370
1371 static __devinit int
1372 tgafb_pci_register(struct pci_dev *pdev, const struct pci_device_id *ent)
1373 {
1374 static unsigned int const fb_offset_presets[4] = {
1375 TGA_8PLANE_FB_OFFSET,
1376 TGA_24PLANE_FB_OFFSET,
1377 0xffffffff,
1378 TGA_24PLUSZ_FB_OFFSET
1379 };
1380
1381 struct all_info {
1382 struct fb_info info;
1383 struct tga_par par;
1384 u32 pseudo_palette[16];
1385 } *all;
1386
1387 void __iomem *mem_base;
1388 unsigned long bar0_start, bar0_len;
1389 u8 tga_type;
1390 int ret;
1391
1392 /* Enable device in PCI config. */
1393 if (pci_enable_device(pdev)) {
1394 printk(KERN_ERR "tgafb: Cannot enable PCI device\n");
1395 return -ENODEV;
1396 }
1397
1398 /* Allocate the fb and par structures. */
1399 all = kmalloc(sizeof(*all), GFP_KERNEL);
1400 if (!all) {
1401 printk(KERN_ERR "tgafb: Cannot allocate memory\n");
1402 return -ENOMEM;
1403 }
1404 memset(all, 0, sizeof(*all));
1405 pci_set_drvdata(pdev, all);
1406
1407 /* Request the mem regions. */
1408 bar0_start = pci_resource_start(pdev, 0);
1409 bar0_len = pci_resource_len(pdev, 0);
1410 ret = -ENODEV;
1411 if (!request_mem_region (bar0_start, bar0_len, "tgafb")) {
1412 printk(KERN_ERR "tgafb: cannot reserve FB region\n");
1413 goto err0;
1414 }
1415
1416 /* Map the framebuffer. */
1417 mem_base = ioremap(bar0_start, bar0_len);
1418 if (!mem_base) {
1419 printk(KERN_ERR "tgafb: Cannot map MMIO\n");
1420 goto err1;
1421 }
1422
1423 /* Grab info about the card. */
1424 tga_type = (readl(mem_base) >> 12) & 0x0f;
1425 all->par.pdev = pdev;
1426 all->par.tga_mem_base = mem_base;
1427 all->par.tga_fb_base = mem_base + fb_offset_presets[tga_type];
1428 all->par.tga_regs_base = mem_base + TGA_REGS_OFFSET;
1429 all->par.tga_type = tga_type;
1430 pci_read_config_byte(pdev, PCI_REVISION_ID, &all->par.tga_chip_rev);
1431
1432 /* Setup framebuffer. */
1433 all->info.flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA |
1434 FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_FILLRECT;
1435 all->info.fbops = &tgafb_ops;
1436 all->info.screen_base = all->par.tga_fb_base;
1437 all->info.par = &all->par;
1438 all->info.pseudo_palette = all->pseudo_palette;
1439
1440 /* This should give a reasonable default video mode. */
1441
1442 ret = fb_find_mode(&all->info.var, &all->info, mode_option,
1443 NULL, 0, NULL,
1444 tga_type == TGA_TYPE_8PLANE ? 8 : 32);
1445 if (ret == 0 || ret == 4) {
1446 printk(KERN_ERR "tgafb: Could not find valid video mode\n");
1447 ret = -EINVAL;
1448 goto err1;
1449 }
1450
1451 if (fb_alloc_cmap(&all->info.cmap, 256, 0)) {
1452 printk(KERN_ERR "tgafb: Could not allocate color map\n");
1453 ret = -ENOMEM;
1454 goto err1;
1455 }
1456
1457 tgafb_set_par(&all->info);
1458 tgafb_init_fix(&all->info);
1459
1460 all->info.device = &pdev->dev;
1461 if (register_framebuffer(&all->info) < 0) {
1462 printk(KERN_ERR "tgafb: Could not register framebuffer\n");
1463 ret = -EINVAL;
1464 goto err1;
1465 }
1466
1467 printk(KERN_INFO "tgafb: DC21030 [TGA] detected, rev=0x%02x\n",
1468 all->par.tga_chip_rev);
1469 printk(KERN_INFO "tgafb: at PCI bus %d, device %d, function %d\n",
1470 pdev->bus->number, PCI_SLOT(pdev->devfn),
1471 PCI_FUNC(pdev->devfn));
1472 printk(KERN_INFO "fb%d: %s frame buffer device at 0x%lx\n",
1473 all->info.node, all->info.fix.id, bar0_start);
1474
1475 return 0;
1476
1477 err1:
1478 release_mem_region(bar0_start, bar0_len);
1479 err0:
1480 kfree(all);
1481 return ret;
1482 }
1483
1484 static void __exit
1485 tgafb_pci_unregister(struct pci_dev *pdev)
1486 {
1487 struct fb_info *info = pci_get_drvdata(pdev);
1488 struct tga_par *par = info->par;
1489
1490 if (!info)
1491 return;
1492 unregister_framebuffer(info);
1493 iounmap(par->tga_mem_base);
1494 release_mem_region(pci_resource_start(pdev, 0),
1495 pci_resource_len(pdev, 0));
1496 kfree(info);
1497 }
1498
1499 #ifdef MODULE
1500 static void __exit
1501 tgafb_exit(void)
1502 {
1503 pci_unregister_driver(&tgafb_driver);
1504 }
1505 #endif /* MODULE */
1506
1507 #ifndef MODULE
1508 int __init
1509 tgafb_setup(char *arg)
1510 {
1511 char *this_opt;
1512
1513 if (arg && *arg) {
1514 while ((this_opt = strsep(&arg, ","))) {
1515 if (!*this_opt)
1516 continue;
1517 if (!strncmp(this_opt, "mode:", 5))
1518 mode_option = this_opt+5;
1519 else
1520 printk(KERN_ERR
1521 "tgafb: unknown parameter %s\n",
1522 this_opt);
1523 }
1524 }
1525
1526 return 0;
1527 }
1528 #endif /* !MODULE */
1529
1530 int __init
1531 tgafb_init(void)
1532 {
1533 #ifndef MODULE
1534 char *option = NULL;
1535
1536 if (fb_get_options("tgafb", &option))
1537 return -ENODEV;
1538 tgafb_setup(option);
1539 #endif
1540 return pci_register_driver(&tgafb_driver);
1541 }
1542
1543 /*
1544 * Modularisation
1545 */
1546
1547 module_init(tgafb_init);
1548
1549 #ifdef MODULE
1550 module_exit(tgafb_exit);
1551 #endif
1552
1553 MODULE_DESCRIPTION("framebuffer driver for TGA chipset");
1554 MODULE_LICENSE("GPL");
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