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[libata sata_mv] mv_hw_ops for hardware families; new errata
[linux-2.6/verdex.git] / drivers / scsi / sata_mv.c
blob4ca4b35d00225873a277acaf9ede03cc2cac5f28
1 /*
2 * sata_mv.c - Marvell SATA support
3 *
4 * Copyright 2005: EMC Corporation, all rights reserved.
5 *
6 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 */
22
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/init.h>
27 #include <linux/blkdev.h>
28 #include <linux/delay.h>
29 #include <linux/interrupt.h>
30 #include <linux/sched.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/device.h>
33 #include <scsi/scsi_host.h>
34 #include <scsi/scsi_cmnd.h>
35 #include <linux/libata.h>
36 #include <asm/io.h>
37
38 #define DRV_NAME "sata_mv"
39 #define DRV_VERSION "0.25"
40
41 enum {
42 /* BAR's are enumerated in terms of pci_resource_start() terms */
43 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
44 MV_IO_BAR = 2, /* offset 0x18: IO space */
45 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
46
47 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
48 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
49
50 MV_PCI_REG_BASE = 0,
51 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
52 MV_SATAHC0_REG_BASE = 0x20000,
53 MV_GPIO_PORT_CTL = 0x104f0,
54 MV_RESET_CFG = 0x180d8,
55
56 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
57 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
58 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
59 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
60
61 MV_USE_Q_DEPTH = ATA_DEF_QUEUE,
62
63 MV_MAX_Q_DEPTH = 32,
64 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
65
66 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
67 * CRPB needs alignment on a 256B boundary. Size == 256B
68 * SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB
69 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
70 */
71 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
72 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
73 MV_MAX_SG_CT = 176,
74 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
75 MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ),
76
77 MV_PORTS_PER_HC = 4,
78 /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */
79 MV_PORT_HC_SHIFT = 2,
80 /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */
81 MV_PORT_MASK = 3,
82
83 /* Host Flags */
84 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
85 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
86 MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
87 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO),
88 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
89
90 chip_504x = 0,
91 chip_508x = 1,
92 chip_5080 = 2,
93 chip_604x = 3,
94 chip_608x = 4,
95
96 CRQB_FLAG_READ = (1 << 0),
97 CRQB_TAG_SHIFT = 1,
98 CRQB_CMD_ADDR_SHIFT = 8,
99 CRQB_CMD_CS = (0x2 << 11),
100 CRQB_CMD_LAST = (1 << 15),
101
102 CRPB_FLAG_STATUS_SHIFT = 8,
103
104 EPRD_FLAG_END_OF_TBL = (1 << 31),
105
106 /* PCI interface registers */
107
108 PCI_COMMAND_OFS = 0xc00,
109
110 PCI_MAIN_CMD_STS_OFS = 0xd30,
111 STOP_PCI_MASTER = (1 << 2),
112 PCI_MASTER_EMPTY = (1 << 3),
113 GLOB_SFT_RST = (1 << 4),
114
115 PCI_IRQ_CAUSE_OFS = 0x1d58,
116 PCI_IRQ_MASK_OFS = 0x1d5c,
117 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
118
119 HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
120 HC_MAIN_IRQ_MASK_OFS = 0x1d64,
121 PORT0_ERR = (1 << 0), /* shift by port # */
122 PORT0_DONE = (1 << 1), /* shift by port # */
123 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
124 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
125 PCI_ERR = (1 << 18),
126 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
127 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
128 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
129 GPIO_INT = (1 << 22),
130 SELF_INT = (1 << 23),
131 TWSI_INT = (1 << 24),
132 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
133 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
134 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
135 HC_MAIN_RSVD),
136
137 /* SATAHC registers */
138 HC_CFG_OFS = 0,
139
140 HC_IRQ_CAUSE_OFS = 0x14,
141 CRPB_DMA_DONE = (1 << 0), /* shift by port # */
142 HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */
143 DEV_IRQ = (1 << 8), /* shift by port # */
144
145 /* Shadow block registers */
146 SHD_BLK_OFS = 0x100,
147 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
148
149 /* SATA registers */
150 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
151 SATA_ACTIVE_OFS = 0x350,
152 PHY_MODE3 = 0x310,
153 PHY_MODE4 = 0x314,
154 PHY_MODE2 = 0x330,
155 SATA_INTERFACE_CTL = 0x050,
156
157 MV_M2_PREAMP_MASK = 0x7e0,
158
159 /* Port registers */
160 EDMA_CFG_OFS = 0,
161 EDMA_CFG_Q_DEPTH = 0, /* queueing disabled */
162 EDMA_CFG_NCQ = (1 << 5),
163 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
164 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
165 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
166
167 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
168 EDMA_ERR_IRQ_MASK_OFS = 0xc,
169 EDMA_ERR_D_PAR = (1 << 0),
170 EDMA_ERR_PRD_PAR = (1 << 1),
171 EDMA_ERR_DEV = (1 << 2),
172 EDMA_ERR_DEV_DCON = (1 << 3),
173 EDMA_ERR_DEV_CON = (1 << 4),
174 EDMA_ERR_SERR = (1 << 5),
175 EDMA_ERR_SELF_DIS = (1 << 7),
176 EDMA_ERR_BIST_ASYNC = (1 << 8),
177 EDMA_ERR_CRBQ_PAR = (1 << 9),
178 EDMA_ERR_CRPB_PAR = (1 << 10),
179 EDMA_ERR_INTRL_PAR = (1 << 11),
180 EDMA_ERR_IORDY = (1 << 12),
181 EDMA_ERR_LNK_CTRL_RX = (0xf << 13),
182 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15),
183 EDMA_ERR_LNK_DATA_RX = (0xf << 17),
184 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21),
185 EDMA_ERR_LNK_DATA_TX = (0x1f << 26),
186 EDMA_ERR_TRANS_PROTO = (1 << 31),
187 EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
188 EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR |
189 EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR |
190 EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 |
191 EDMA_ERR_LNK_DATA_RX |
192 EDMA_ERR_LNK_DATA_TX |
193 EDMA_ERR_TRANS_PROTO),
194
195 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
196 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
197
198 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
199 EDMA_REQ_Q_PTR_SHIFT = 5,
200
201 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
202 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
203 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
204 EDMA_RSP_Q_PTR_SHIFT = 3,
205
206 EDMA_CMD_OFS = 0x28,
207 EDMA_EN = (1 << 0),
208 EDMA_DS = (1 << 1),
209 ATA_RST = (1 << 2),
210
211 EDMA_ARB_CFG = 0x38,
212
213 /* Host private flags (hp_flags) */
214 MV_HP_FLAG_MSI = (1 << 0),
215 MV_HP_ERRATA_50XXB0 = (1 << 1),
216 MV_HP_ERRATA_50XXB2 = (1 << 2),
217 MV_HP_ERRATA_60X1B2 = (1 << 3),
218 MV_HP_ERRATA_60X1C0 = (1 << 4),
219 MV_HP_50XX = (1 << 5),
220
221 /* Port private flags (pp_flags) */
222 MV_PP_FLAG_EDMA_EN = (1 << 0),
223 MV_PP_FLAG_EDMA_DS_ACT = (1 << 1),
224 };
225
226 #define IS_60XX(hpriv) (((hpriv)->hp_flags & MV_HP_50XX) == 0)
227
228 enum {
229 /* Our DMA boundary is determined by an ePRD being unable to handle
230 * anything larger than 64KB
231 */
232 MV_DMA_BOUNDARY = 0xffffU,
233
234 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
235
236 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
237 };
238
239 /* Command ReQuest Block: 32B */
240 struct mv_crqb {
241 u32 sg_addr;
242 u32 sg_addr_hi;
243 u16 ctrl_flags;
244 u16 ata_cmd[11];
245 };
246
247 /* Command ResPonse Block: 8B */
248 struct mv_crpb {
249 u16 id;
250 u16 flags;
251 u32 tmstmp;
252 };
253
254 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
255 struct mv_sg {
256 u32 addr;
257 u32 flags_size;
258 u32 addr_hi;
259 u32 reserved;
260 };
261
262 struct mv_port_priv {
263 struct mv_crqb *crqb;
264 dma_addr_t crqb_dma;
265 struct mv_crpb *crpb;
266 dma_addr_t crpb_dma;
267 struct mv_sg *sg_tbl;
268 dma_addr_t sg_tbl_dma;
269
270 unsigned req_producer; /* cp of req_in_ptr */
271 unsigned rsp_consumer; /* cp of rsp_out_ptr */
272 u32 pp_flags;
273 };
274
275 struct mv_port_signal {
276 u32 amps;
277 u32 pre;
278 };
279
280 struct mv_host_priv;
281 struct mv_hw_ops {
282 void (*phy_errata)(struct ata_port *ap);
283 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
284 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
285 void __iomem *mmio);
286 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio);
287 };
288
289 struct mv_host_priv {
290 u32 hp_flags;
291 struct mv_port_signal signal[8];
292 const struct mv_hw_ops *ops;
293 };
294
295 static void mv_irq_clear(struct ata_port *ap);
296 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
297 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
298 static void mv_phy_reset(struct ata_port *ap);
299 static void mv_host_stop(struct ata_host_set *host_set);
300 static int mv_port_start(struct ata_port *ap);
301 static void mv_port_stop(struct ata_port *ap);
302 static void mv_qc_prep(struct ata_queued_cmd *qc);
303 static int mv_qc_issue(struct ata_queued_cmd *qc);
304 static irqreturn_t mv_interrupt(int irq, void *dev_instance,
305 struct pt_regs *regs);
306 static void mv_eng_timeout(struct ata_port *ap);
307 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
308
309 static void mv5_phy_errata(struct ata_port *ap);
310 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
311 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
312 void __iomem *mmio);
313 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio);
314
315 static void mv6_phy_errata(struct ata_port *ap);
316 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
317 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
318 void __iomem *mmio);
319 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio);
320
321 static struct scsi_host_template mv_sht = {
322 .module = THIS_MODULE,
323 .name = DRV_NAME,
324 .ioctl = ata_scsi_ioctl,
325 .queuecommand = ata_scsi_queuecmd,
326 .eh_strategy_handler = ata_scsi_error,
327 .can_queue = MV_USE_Q_DEPTH,
328 .this_id = ATA_SHT_THIS_ID,
329 .sg_tablesize = MV_MAX_SG_CT,
330 .max_sectors = ATA_MAX_SECTORS,
331 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
332 .emulated = ATA_SHT_EMULATED,
333 .use_clustering = ATA_SHT_USE_CLUSTERING,
334 .proc_name = DRV_NAME,
335 .dma_boundary = MV_DMA_BOUNDARY,
336 .slave_configure = ata_scsi_slave_config,
337 .bios_param = ata_std_bios_param,
338 .ordered_flush = 1,
339 };
340
341 static const struct ata_port_operations mv_ops = {
342 .port_disable = ata_port_disable,
343
344 .tf_load = ata_tf_load,
345 .tf_read = ata_tf_read,
346 .check_status = ata_check_status,
347 .exec_command = ata_exec_command,
348 .dev_select = ata_std_dev_select,
349
350 .phy_reset = mv_phy_reset,
351
352 .qc_prep = mv_qc_prep,
353 .qc_issue = mv_qc_issue,
354
355 .eng_timeout = mv_eng_timeout,
356
357 .irq_handler = mv_interrupt,
358 .irq_clear = mv_irq_clear,
359
360 .scr_read = mv_scr_read,
361 .scr_write = mv_scr_write,
362
363 .port_start = mv_port_start,
364 .port_stop = mv_port_stop,
365 .host_stop = mv_host_stop,
366 };
367
368 static struct ata_port_info mv_port_info[] = {
369 { /* chip_504x */
370 .sht = &mv_sht,
371 .host_flags = MV_COMMON_FLAGS,
372 .pio_mask = 0x1f, /* pio0-4 */
373 .udma_mask = 0, /* 0x7f (udma0-6 disabled for now) */
374 .port_ops = &mv_ops,
375 },
376 { /* chip_508x */
377 .sht = &mv_sht,
378 .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
379 .pio_mask = 0x1f, /* pio0-4 */
380 .udma_mask = 0, /* 0x7f (udma0-6 disabled for now) */
381 .port_ops = &mv_ops,
382 },
383 { /* chip_5080 */
384 .sht = &mv_sht,
385 .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
386 .pio_mask = 0x1f, /* pio0-4 */
387 .udma_mask = 0, /* 0x7f (udma0-6 disabled for now) */
388 .port_ops = &mv_ops,
389 },
390 { /* chip_604x */
391 .sht = &mv_sht,
392 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
393 .pio_mask = 0x1f, /* pio0-4 */
394 .udma_mask = 0x7f, /* udma0-6 */
395 .port_ops = &mv_ops,
396 },
397 { /* chip_608x */
398 .sht = &mv_sht,
399 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
400 MV_FLAG_DUAL_HC),
401 .pio_mask = 0x1f, /* pio0-4 */
402 .udma_mask = 0x7f, /* udma0-6 */
403 .port_ops = &mv_ops,
404 },
405 };
406
407 static const struct pci_device_id mv_pci_tbl[] = {
408 #if 0 /* unusably broken right now */
409 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5040), 0, 0, chip_504x},
410 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5041), 0, 0, chip_504x},
411 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5080), 0, 0, chip_5080},
412 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5081), 0, 0, chip_508x},
413 #endif
414
415 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6040), 0, 0, chip_604x},
416 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6041), 0, 0, chip_604x},
417 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6080), 0, 0, chip_608x},
418 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6081), 0, 0, chip_608x},
419
420 {PCI_DEVICE(PCI_VENDOR_ID_ADAPTEC2, 0x0241), 0, 0, chip_604x},
421 {} /* terminate list */
422 };
423
424 static struct pci_driver mv_pci_driver = {
425 .name = DRV_NAME,
426 .id_table = mv_pci_tbl,
427 .probe = mv_init_one,
428 .remove = ata_pci_remove_one,
429 };
430
431 static const struct mv_hw_ops mv5xxx_ops = {
432 .phy_errata = mv5_phy_errata,
433 .enable_leds = mv5_enable_leds,
434 .read_preamp = mv5_read_preamp,
435 .reset_hc = mv5_reset_hc,
436 };
437
438 static const struct mv_hw_ops mv6xxx_ops = {
439 .phy_errata = mv6_phy_errata,
440 .enable_leds = mv6_enable_leds,
441 .read_preamp = mv6_read_preamp,
442 .reset_hc = mv6_reset_hc,
443 };
444
445 /*
446 * Functions
447 */
448
449 static inline void writelfl(unsigned long data, void __iomem *addr)
450 {
451 writel(data, addr);
452 (void) readl(addr); /* flush to avoid PCI posted write */
453 }
454
455 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
456 {
457 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
458 }
459
460 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
461 {
462 return (mv_hc_base(base, port >> MV_PORT_HC_SHIFT) +
463 MV_SATAHC_ARBTR_REG_SZ +
464 ((port & MV_PORT_MASK) * MV_PORT_REG_SZ));
465 }
466
467 static inline void __iomem *mv_ap_base(struct ata_port *ap)
468 {
469 return mv_port_base(ap->host_set->mmio_base, ap->port_no);
470 }
471
472 static inline int mv_get_hc_count(unsigned long host_flags)
473 {
474 return ((host_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
475 }
476
477 static void mv_irq_clear(struct ata_port *ap)
478 {
479 }
480
481 /**
482 * mv_start_dma - Enable eDMA engine
483 * @base: port base address
484 * @pp: port private data
485 *
486 * Verify the local cache of the eDMA state is accurate with an
487 * assert.
488 *
489 * LOCKING:
490 * Inherited from caller.
491 */
492 static void mv_start_dma(void __iomem *base, struct mv_port_priv *pp)
493 {
494 if (!(MV_PP_FLAG_EDMA_EN & pp->pp_flags)) {
495 writelfl(EDMA_EN, base + EDMA_CMD_OFS);
496 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
497 }
498 assert(EDMA_EN & readl(base + EDMA_CMD_OFS));
499 }
500
501 /**
502 * mv_stop_dma - Disable eDMA engine
503 * @ap: ATA channel to manipulate
504 *
505 * Verify the local cache of the eDMA state is accurate with an
506 * assert.
507 *
508 * LOCKING:
509 * Inherited from caller.
510 */
511 static void mv_stop_dma(struct ata_port *ap)
512 {
513 void __iomem *port_mmio = mv_ap_base(ap);
514 struct mv_port_priv *pp = ap->private_data;
515 u32 reg;
516 int i;
517
518 if (MV_PP_FLAG_EDMA_EN & pp->pp_flags) {
519 /* Disable EDMA if active. The disable bit auto clears.
520 */
521 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
522 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
523 } else {
524 assert(!(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS)));
525 }
526
527 /* now properly wait for the eDMA to stop */
528 for (i = 1000; i > 0; i--) {
529 reg = readl(port_mmio + EDMA_CMD_OFS);
530 if (!(EDMA_EN & reg)) {
531 break;
532 }
533 udelay(100);
534 }
535
536 if (EDMA_EN & reg) {
537 printk(KERN_ERR "ata%u: Unable to stop eDMA\n", ap->id);
538 /* FIXME: Consider doing a reset here to recover */
539 }
540 }
541
542 #ifdef ATA_DEBUG
543 static void mv_dump_mem(void __iomem *start, unsigned bytes)
544 {
545 int b, w;
546 for (b = 0; b < bytes; ) {
547 DPRINTK("%p: ", start + b);
548 for (w = 0; b < bytes && w < 4; w++) {
549 printk("%08x ",readl(start + b));
550 b += sizeof(u32);
551 }
552 printk("\n");
553 }
554 }
555 #endif
556
557 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
558 {
559 #ifdef ATA_DEBUG
560 int b, w;
561 u32 dw;
562 for (b = 0; b < bytes; ) {
563 DPRINTK("%02x: ", b);
564 for (w = 0; b < bytes && w < 4; w++) {
565 (void) pci_read_config_dword(pdev,b,&dw);
566 printk("%08x ",dw);
567 b += sizeof(u32);
568 }
569 printk("\n");
570 }
571 #endif
572 }
573 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
574 struct pci_dev *pdev)
575 {
576 #ifdef ATA_DEBUG
577 void __iomem *hc_base = mv_hc_base(mmio_base,
578 port >> MV_PORT_HC_SHIFT);
579 void __iomem *port_base;
580 int start_port, num_ports, p, start_hc, num_hcs, hc;
581
582 if (0 > port) {
583 start_hc = start_port = 0;
584 num_ports = 8; /* shld be benign for 4 port devs */
585 num_hcs = 2;
586 } else {
587 start_hc = port >> MV_PORT_HC_SHIFT;
588 start_port = port;
589 num_ports = num_hcs = 1;
590 }
591 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
592 num_ports > 1 ? num_ports - 1 : start_port);
593
594 if (NULL != pdev) {
595 DPRINTK("PCI config space regs:\n");
596 mv_dump_pci_cfg(pdev, 0x68);
597 }
598 DPRINTK("PCI regs:\n");
599 mv_dump_mem(mmio_base+0xc00, 0x3c);
600 mv_dump_mem(mmio_base+0xd00, 0x34);
601 mv_dump_mem(mmio_base+0xf00, 0x4);
602 mv_dump_mem(mmio_base+0x1d00, 0x6c);
603 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
604 hc_base = mv_hc_base(mmio_base, port >> MV_PORT_HC_SHIFT);
605 DPRINTK("HC regs (HC %i):\n", hc);
606 mv_dump_mem(hc_base, 0x1c);
607 }
608 for (p = start_port; p < start_port + num_ports; p++) {
609 port_base = mv_port_base(mmio_base, p);
610 DPRINTK("EDMA regs (port %i):\n",p);
611 mv_dump_mem(port_base, 0x54);
612 DPRINTK("SATA regs (port %i):\n",p);
613 mv_dump_mem(port_base+0x300, 0x60);
614 }
615 #endif
616 }
617
618 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
619 {
620 unsigned int ofs;
621
622 switch (sc_reg_in) {
623 case SCR_STATUS:
624 case SCR_CONTROL:
625 case SCR_ERROR:
626 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
627 break;
628 case SCR_ACTIVE:
629 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
630 break;
631 default:
632 ofs = 0xffffffffU;
633 break;
634 }
635 return ofs;
636 }
637
638 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
639 {
640 unsigned int ofs = mv_scr_offset(sc_reg_in);
641
642 if (0xffffffffU != ofs) {
643 return readl(mv_ap_base(ap) + ofs);
644 } else {
645 return (u32) ofs;
646 }
647 }
648
649 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
650 {
651 unsigned int ofs = mv_scr_offset(sc_reg_in);
652
653 if (0xffffffffU != ofs) {
654 writelfl(val, mv_ap_base(ap) + ofs);
655 }
656 }
657
658 /**
659 * mv_global_soft_reset - Perform the 6xxx global soft reset
660 * @mmio_base: base address of the HBA
661 *
662 * This routine only applies to 6xxx parts.
663 *
664 * LOCKING:
665 * Inherited from caller.
666 */
667 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio)
668 {
669 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
670 int i, rc = 0;
671 u32 t;
672
673 /* Following procedure defined in PCI "main command and status
674 * register" table.
675 */
676 t = readl(reg);
677 writel(t | STOP_PCI_MASTER, reg);
678
679 for (i = 0; i < 1000; i++) {
680 udelay(1);
681 t = readl(reg);
682 if (PCI_MASTER_EMPTY & t) {
683 break;
684 }
685 }
686 if (!(PCI_MASTER_EMPTY & t)) {
687 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
688 rc = 1;
689 goto done;
690 }
691
692 /* set reset */
693 i = 5;
694 do {
695 writel(t | GLOB_SFT_RST, reg);
696 t = readl(reg);
697 udelay(1);
698 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
699
700 if (!(GLOB_SFT_RST & t)) {
701 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
702 rc = 1;
703 goto done;
704 }
705
706 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
707 i = 5;
708 do {
709 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
710 t = readl(reg);
711 udelay(1);
712 } while ((GLOB_SFT_RST & t) && (i-- > 0));
713
714 if (GLOB_SFT_RST & t) {
715 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
716 rc = 1;
717 }
718 done:
719 return rc;
720 }
721
722 /**
723 * mv_host_stop - Host specific cleanup/stop routine.
724 * @host_set: host data structure
725 *
726 * Disable ints, cleanup host memory, call general purpose
727 * host_stop.
728 *
729 * LOCKING:
730 * Inherited from caller.
731 */
732 static void mv_host_stop(struct ata_host_set *host_set)
733 {
734 struct mv_host_priv *hpriv = host_set->private_data;
735 struct pci_dev *pdev = to_pci_dev(host_set->dev);
736
737 if (hpriv->hp_flags & MV_HP_FLAG_MSI) {
738 pci_disable_msi(pdev);
739 } else {
740 pci_intx(pdev, 0);
741 }
742 kfree(hpriv);
743 ata_host_stop(host_set);
744 }
745
746 static inline void mv_priv_free(struct mv_port_priv *pp, struct device *dev)
747 {
748 dma_free_coherent(dev, MV_PORT_PRIV_DMA_SZ, pp->crpb, pp->crpb_dma);
749 }
750
751 /**
752 * mv_port_start - Port specific init/start routine.
753 * @ap: ATA channel to manipulate
754 *
755 * Allocate and point to DMA memory, init port private memory,
756 * zero indices.
757 *
758 * LOCKING:
759 * Inherited from caller.
760 */
761 static int mv_port_start(struct ata_port *ap)
762 {
763 struct device *dev = ap->host_set->dev;
764 struct mv_port_priv *pp;
765 void __iomem *port_mmio = mv_ap_base(ap);
766 void *mem;
767 dma_addr_t mem_dma;
768 int rc = -ENOMEM;
769
770 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
771 if (!pp)
772 goto err_out;
773 memset(pp, 0, sizeof(*pp));
774
775 mem = dma_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma,
776 GFP_KERNEL);
777 if (!mem)
778 goto err_out_pp;
779 memset(mem, 0, MV_PORT_PRIV_DMA_SZ);
780
781 rc = ata_pad_alloc(ap, dev);
782 if (rc)
783 goto err_out_priv;
784
785 /* First item in chunk of DMA memory:
786 * 32-slot command request table (CRQB), 32 bytes each in size
787 */
788 pp->crqb = mem;
789 pp->crqb_dma = mem_dma;
790 mem += MV_CRQB_Q_SZ;
791 mem_dma += MV_CRQB_Q_SZ;
792
793 /* Second item:
794 * 32-slot command response table (CRPB), 8 bytes each in size
795 */
796 pp->crpb = mem;
797 pp->crpb_dma = mem_dma;
798 mem += MV_CRPB_Q_SZ;
799 mem_dma += MV_CRPB_Q_SZ;
800
801 /* Third item:
802 * Table of scatter-gather descriptors (ePRD), 16 bytes each
803 */
804 pp->sg_tbl = mem;
805 pp->sg_tbl_dma = mem_dma;
806
807 writelfl(EDMA_CFG_Q_DEPTH | EDMA_CFG_RD_BRST_EXT |
808 EDMA_CFG_WR_BUFF_LEN, port_mmio + EDMA_CFG_OFS);
809
810 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
811 writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK,
812 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
813
814 writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
815 writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
816
817 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
818 writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK,
819 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
820
821 pp->req_producer = pp->rsp_consumer = 0;
822
823 /* Don't turn on EDMA here...do it before DMA commands only. Else
824 * we'll be unable to send non-data, PIO, etc due to restricted access
825 * to shadow regs.
826 */
827 ap->private_data = pp;
828 return 0;
829
830 err_out_priv:
831 mv_priv_free(pp, dev);
832 err_out_pp:
833 kfree(pp);
834 err_out:
835 return rc;
836 }
837
838 /**
839 * mv_port_stop - Port specific cleanup/stop routine.
840 * @ap: ATA channel to manipulate
841 *
842 * Stop DMA, cleanup port memory.
843 *
844 * LOCKING:
845 * This routine uses the host_set lock to protect the DMA stop.
846 */
847 static void mv_port_stop(struct ata_port *ap)
848 {
849 struct device *dev = ap->host_set->dev;
850 struct mv_port_priv *pp = ap->private_data;
851 unsigned long flags;
852
853 spin_lock_irqsave(&ap->host_set->lock, flags);
854 mv_stop_dma(ap);
855 spin_unlock_irqrestore(&ap->host_set->lock, flags);
856
857 ap->private_data = NULL;
858 ata_pad_free(ap, dev);
859 mv_priv_free(pp, dev);
860 kfree(pp);
861 }
862
863 /**
864 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
865 * @qc: queued command whose SG list to source from
866 *
867 * Populate the SG list and mark the last entry.
868 *
869 * LOCKING:
870 * Inherited from caller.
871 */
872 static void mv_fill_sg(struct ata_queued_cmd *qc)
873 {
874 struct mv_port_priv *pp = qc->ap->private_data;
875 unsigned int i = 0;
876 struct scatterlist *sg;
877
878 ata_for_each_sg(sg, qc) {
879 u32 sg_len;
880 dma_addr_t addr;
881
882 addr = sg_dma_address(sg);
883 sg_len = sg_dma_len(sg);
884
885 pp->sg_tbl[i].addr = cpu_to_le32(addr & 0xffffffff);
886 pp->sg_tbl[i].addr_hi = cpu_to_le32((addr >> 16) >> 16);
887 assert(0 == (sg_len & ~MV_DMA_BOUNDARY));
888 pp->sg_tbl[i].flags_size = cpu_to_le32(sg_len);
889 if (ata_sg_is_last(sg, qc))
890 pp->sg_tbl[i].flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
891
892 i++;
893 }
894 }
895
896 static inline unsigned mv_inc_q_index(unsigned *index)
897 {
898 *index = (*index + 1) & MV_MAX_Q_DEPTH_MASK;
899 return *index;
900 }
901
902 static inline void mv_crqb_pack_cmd(u16 *cmdw, u8 data, u8 addr, unsigned last)
903 {
904 *cmdw = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
905 (last ? CRQB_CMD_LAST : 0);
906 }
907
908 /**
909 * mv_qc_prep - Host specific command preparation.
910 * @qc: queued command to prepare
911 *
912 * This routine simply redirects to the general purpose routine
913 * if command is not DMA. Else, it handles prep of the CRQB
914 * (command request block), does some sanity checking, and calls
915 * the SG load routine.
916 *
917 * LOCKING:
918 * Inherited from caller.
919 */
920 static void mv_qc_prep(struct ata_queued_cmd *qc)
921 {
922 struct ata_port *ap = qc->ap;
923 struct mv_port_priv *pp = ap->private_data;
924 u16 *cw;
925 struct ata_taskfile *tf;
926 u16 flags = 0;
927
928 if (ATA_PROT_DMA != qc->tf.protocol) {
929 return;
930 }
931
932 /* the req producer index should be the same as we remember it */
933 assert(((readl(mv_ap_base(qc->ap) + EDMA_REQ_Q_IN_PTR_OFS) >>
934 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
935 pp->req_producer);
936
937 /* Fill in command request block
938 */
939 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
940 flags |= CRQB_FLAG_READ;
941 }
942 assert(MV_MAX_Q_DEPTH > qc->tag);
943 flags |= qc->tag << CRQB_TAG_SHIFT;
944
945 pp->crqb[pp->req_producer].sg_addr =
946 cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
947 pp->crqb[pp->req_producer].sg_addr_hi =
948 cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
949 pp->crqb[pp->req_producer].ctrl_flags = cpu_to_le16(flags);
950
951 cw = &pp->crqb[pp->req_producer].ata_cmd[0];
952 tf = &qc->tf;
953
954 /* Sadly, the CRQB cannot accomodate all registers--there are
955 * only 11 bytes...so we must pick and choose required
956 * registers based on the command. So, we drop feature and
957 * hob_feature for [RW] DMA commands, but they are needed for
958 * NCQ. NCQ will drop hob_nsect.
959 */
960 switch (tf->command) {
961 case ATA_CMD_READ:
962 case ATA_CMD_READ_EXT:
963 case ATA_CMD_WRITE:
964 case ATA_CMD_WRITE_EXT:
965 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
966 break;
967 #ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */
968 case ATA_CMD_FPDMA_READ:
969 case ATA_CMD_FPDMA_WRITE:
970 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
971 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
972 break;
973 #endif /* FIXME: remove this line when NCQ added */
974 default:
975 /* The only other commands EDMA supports in non-queued and
976 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
977 * of which are defined/used by Linux. If we get here, this
978 * driver needs work.
979 *
980 * FIXME: modify libata to give qc_prep a return value and
981 * return error here.
982 */
983 BUG_ON(tf->command);
984 break;
985 }
986 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
987 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
988 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
989 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
990 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
991 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
992 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
993 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
994 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
995
996 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) {
997 return;
998 }
999 mv_fill_sg(qc);
1000 }
1001
1002 /**
1003 * mv_qc_issue - Initiate a command to the host
1004 * @qc: queued command to start
1005 *
1006 * This routine simply redirects to the general purpose routine
1007 * if command is not DMA. Else, it sanity checks our local
1008 * caches of the request producer/consumer indices then enables
1009 * DMA and bumps the request producer index.
1010 *
1011 * LOCKING:
1012 * Inherited from caller.
1013 */
1014 static int mv_qc_issue(struct ata_queued_cmd *qc)
1015 {
1016 void __iomem *port_mmio = mv_ap_base(qc->ap);
1017 struct mv_port_priv *pp = qc->ap->private_data;
1018 u32 in_ptr;
1019
1020 if (ATA_PROT_DMA != qc->tf.protocol) {
1021 /* We're about to send a non-EDMA capable command to the
1022 * port. Turn off EDMA so there won't be problems accessing
1023 * shadow block, etc registers.
1024 */
1025 mv_stop_dma(qc->ap);
1026 return ata_qc_issue_prot(qc);
1027 }
1028
1029 in_ptr = readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1030
1031 /* the req producer index should be the same as we remember it */
1032 assert(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
1033 pp->req_producer);
1034 /* until we do queuing, the queue should be empty at this point */
1035 assert(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
1036 ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS) >>
1037 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
1038
1039 mv_inc_q_index(&pp->req_producer); /* now incr producer index */
1040
1041 mv_start_dma(port_mmio, pp);
1042
1043 /* and write the request in pointer to kick the EDMA to life */
1044 in_ptr &= EDMA_REQ_Q_BASE_LO_MASK;
1045 in_ptr |= pp->req_producer << EDMA_REQ_Q_PTR_SHIFT;
1046 writelfl(in_ptr, port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1047
1048 return 0;
1049 }
1050
1051 /**
1052 * mv_get_crpb_status - get status from most recently completed cmd
1053 * @ap: ATA channel to manipulate
1054 *
1055 * This routine is for use when the port is in DMA mode, when it
1056 * will be using the CRPB (command response block) method of
1057 * returning command completion information. We assert indices
1058 * are good, grab status, and bump the response consumer index to
1059 * prove that we're up to date.
1060 *
1061 * LOCKING:
1062 * Inherited from caller.
1063 */
1064 static u8 mv_get_crpb_status(struct ata_port *ap)
1065 {
1066 void __iomem *port_mmio = mv_ap_base(ap);
1067 struct mv_port_priv *pp = ap->private_data;
1068 u32 out_ptr;
1069
1070 out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1071
1072 /* the response consumer index should be the same as we remember it */
1073 assert(((out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
1074 pp->rsp_consumer);
1075
1076 /* increment our consumer index... */
1077 pp->rsp_consumer = mv_inc_q_index(&pp->rsp_consumer);
1078
1079 /* and, until we do NCQ, there should only be 1 CRPB waiting */
1080 assert(((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) >>
1081 EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
1082 pp->rsp_consumer);
1083
1084 /* write out our inc'd consumer index so EDMA knows we're caught up */
1085 out_ptr &= EDMA_RSP_Q_BASE_LO_MASK;
1086 out_ptr |= pp->rsp_consumer << EDMA_RSP_Q_PTR_SHIFT;
1087 writelfl(out_ptr, port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1088
1089 /* Return ATA status register for completed CRPB */
1090 return (pp->crpb[pp->rsp_consumer].flags >> CRPB_FLAG_STATUS_SHIFT);
1091 }
1092
1093 /**
1094 * mv_err_intr - Handle error interrupts on the port
1095 * @ap: ATA channel to manipulate
1096 *
1097 * In most cases, just clear the interrupt and move on. However,
1098 * some cases require an eDMA reset, which is done right before
1099 * the COMRESET in mv_phy_reset(). The SERR case requires a
1100 * clear of pending errors in the SATA SERROR register. Finally,
1101 * if the port disabled DMA, update our cached copy to match.
1102 *
1103 * LOCKING:
1104 * Inherited from caller.
1105 */
1106 static void mv_err_intr(struct ata_port *ap)
1107 {
1108 void __iomem *port_mmio = mv_ap_base(ap);
1109 u32 edma_err_cause, serr = 0;
1110
1111 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1112
1113 if (EDMA_ERR_SERR & edma_err_cause) {
1114 serr = scr_read(ap, SCR_ERROR);
1115 scr_write_flush(ap, SCR_ERROR, serr);
1116 }
1117 if (EDMA_ERR_SELF_DIS & edma_err_cause) {
1118 struct mv_port_priv *pp = ap->private_data;
1119 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1120 }
1121 DPRINTK(KERN_ERR "ata%u: port error; EDMA err cause: 0x%08x "
1122 "SERR: 0x%08x\n", ap->id, edma_err_cause, serr);
1123
1124 /* Clear EDMA now that SERR cleanup done */
1125 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1126
1127 /* check for fatal here and recover if needed */
1128 if (EDMA_ERR_FATAL & edma_err_cause) {
1129 mv_phy_reset(ap);
1130 }
1131 }
1132
1133 /**
1134 * mv_host_intr - Handle all interrupts on the given host controller
1135 * @host_set: host specific structure
1136 * @relevant: port error bits relevant to this host controller
1137 * @hc: which host controller we're to look at
1138 *
1139 * Read then write clear the HC interrupt status then walk each
1140 * port connected to the HC and see if it needs servicing. Port
1141 * success ints are reported in the HC interrupt status reg, the
1142 * port error ints are reported in the higher level main
1143 * interrupt status register and thus are passed in via the
1144 * 'relevant' argument.
1145 *
1146 * LOCKING:
1147 * Inherited from caller.
1148 */
1149 static void mv_host_intr(struct ata_host_set *host_set, u32 relevant,
1150 unsigned int hc)
1151 {
1152 void __iomem *mmio = host_set->mmio_base;
1153 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1154 struct ata_port *ap;
1155 struct ata_queued_cmd *qc;
1156 u32 hc_irq_cause;
1157 int shift, port, port0, hard_port, handled;
1158 unsigned int err_mask;
1159 u8 ata_status = 0;
1160
1161 if (hc == 0) {
1162 port0 = 0;
1163 } else {
1164 port0 = MV_PORTS_PER_HC;
1165 }
1166
1167 /* we'll need the HC success int register in most cases */
1168 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1169 if (hc_irq_cause) {
1170 writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
1171 }
1172
1173 VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n",
1174 hc,relevant,hc_irq_cause);
1175
1176 for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) {
1177 ap = host_set->ports[port];
1178 hard_port = port & MV_PORT_MASK; /* range 0-3 */
1179 handled = 0; /* ensure ata_status is set if handled++ */
1180
1181 if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) {
1182 /* new CRPB on the queue; just one at a time until NCQ
1183 */
1184 ata_status = mv_get_crpb_status(ap);
1185 handled++;
1186 } else if ((DEV_IRQ << hard_port) & hc_irq_cause) {
1187 /* received ATA IRQ; read the status reg to clear INTRQ
1188 */
1189 ata_status = readb((void __iomem *)
1190 ap->ioaddr.status_addr);
1191 handled++;
1192 }
1193
1194 err_mask = ac_err_mask(ata_status);
1195
1196 shift = port << 1; /* (port * 2) */
1197 if (port >= MV_PORTS_PER_HC) {
1198 shift++; /* skip bit 8 in the HC Main IRQ reg */
1199 }
1200 if ((PORT0_ERR << shift) & relevant) {
1201 mv_err_intr(ap);
1202 err_mask |= AC_ERR_OTHER;
1203 handled++;
1204 }
1205
1206 if (handled && ap) {
1207 qc = ata_qc_from_tag(ap, ap->active_tag);
1208 if (NULL != qc) {
1209 VPRINTK("port %u IRQ found for qc, "
1210 "ata_status 0x%x\n", port,ata_status);
1211 /* mark qc status appropriately */
1212 ata_qc_complete(qc, err_mask);
1213 }
1214 }
1215 }
1216 VPRINTK("EXIT\n");
1217 }
1218
1219 /**
1220 * mv_interrupt -
1221 * @irq: unused
1222 * @dev_instance: private data; in this case the host structure
1223 * @regs: unused
1224 *
1225 * Read the read only register to determine if any host
1226 * controllers have pending interrupts. If so, call lower level
1227 * routine to handle. Also check for PCI errors which are only
1228 * reported here.
1229 *
1230 * LOCKING:
1231 * This routine holds the host_set lock while processing pending
1232 * interrupts.
1233 */
1234 static irqreturn_t mv_interrupt(int irq, void *dev_instance,
1235 struct pt_regs *regs)
1236 {
1237 struct ata_host_set *host_set = dev_instance;
1238 unsigned int hc, handled = 0, n_hcs;
1239 void __iomem *mmio = host_set->mmio_base;
1240 u32 irq_stat;
1241
1242 irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS);
1243
1244 /* check the cases where we either have nothing pending or have read
1245 * a bogus register value which can indicate HW removal or PCI fault
1246 */
1247 if (!irq_stat || (0xffffffffU == irq_stat)) {
1248 return IRQ_NONE;
1249 }
1250
1251 n_hcs = mv_get_hc_count(host_set->ports[0]->flags);
1252 spin_lock(&host_set->lock);
1253
1254 for (hc = 0; hc < n_hcs; hc++) {
1255 u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT));
1256 if (relevant) {
1257 mv_host_intr(host_set, relevant, hc);
1258 handled++;
1259 }
1260 }
1261 if (PCI_ERR & irq_stat) {
1262 printk(KERN_ERR DRV_NAME ": PCI ERROR; PCI IRQ cause=0x%08x\n",
1263 readl(mmio + PCI_IRQ_CAUSE_OFS));
1264
1265 DPRINTK("All regs @ PCI error\n");
1266 mv_dump_all_regs(mmio, -1, to_pci_dev(host_set->dev));
1267
1268 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
1269 handled++;
1270 }
1271 spin_unlock(&host_set->lock);
1272
1273 return IRQ_RETVAL(handled);
1274 }
1275
1276 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
1277 void __iomem *mmio)
1278 {
1279 /* FIXME */
1280 }
1281
1282 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1283 {
1284 /* FIXME */
1285 }
1286
1287 static void mv5_phy_errata(struct ata_port *ap)
1288 {
1289 /* FIXME */
1290 }
1291
1292 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio)
1293 {
1294 /* FIXME */
1295 return 1;
1296 }
1297
1298 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
1299 void __iomem *mmio)
1300 {
1301 void __iomem *port_mmio;
1302 u32 tmp;
1303
1304 tmp = readl(mmio + MV_RESET_CFG);
1305 if ((tmp & (1 << 0)) == 0) {
1306 hpriv->signal[idx].amps = 0x7 << 8;
1307 hpriv->signal[idx].pre = 0x1 << 5;
1308 return;
1309 }
1310
1311 port_mmio = mv_port_base(mmio, idx);
1312 tmp = readl(port_mmio + PHY_MODE2);
1313
1314 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
1315 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
1316 }
1317
1318 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1319 {
1320 writel(0x00000060, mmio + MV_GPIO_PORT_CTL);
1321 }
1322
1323 static void mv6_phy_errata(struct ata_port *ap)
1324 {
1325 struct mv_host_priv *hpriv = ap->host_set->private_data;
1326 u32 hp_flags = hpriv->hp_flags;
1327 void __iomem *port_mmio = mv_ap_base(ap);
1328 int fix_phy_mode2 =
1329 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1330 int fix_phy_mode4 =
1331 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1332 u32 m2, tmp;
1333
1334 if (fix_phy_mode2) {
1335 m2 = readl(port_mmio + PHY_MODE2);
1336 m2 &= ~(1 << 16);
1337 m2 |= (1 << 31);
1338 writel(m2, port_mmio + PHY_MODE2);
1339
1340 udelay(200);
1341
1342 m2 = readl(port_mmio + PHY_MODE2);
1343 m2 &= ~((1 << 16) | (1 << 31));
1344 writel(m2, port_mmio + PHY_MODE2);
1345
1346 udelay(200);
1347 }
1348
1349 /* who knows what this magic does */
1350 tmp = readl(port_mmio + PHY_MODE3);
1351 tmp &= ~0x7F800000;
1352 tmp |= 0x2A800000;
1353 writel(tmp, port_mmio + PHY_MODE3);
1354
1355 if (fix_phy_mode4) {
1356 u32 m4;
1357
1358 m4 = readl(port_mmio + PHY_MODE4);
1359
1360 if (hp_flags & MV_HP_ERRATA_60X1B2)
1361 tmp = readl(port_mmio + 0x310);
1362
1363 m4 = (m4 & ~(1 << 1)) | (1 << 0);
1364
1365 writel(m4, port_mmio + PHY_MODE4);
1366
1367 if (hp_flags & MV_HP_ERRATA_60X1B2)
1368 writel(tmp, port_mmio + 0x310);
1369 }
1370
1371 /* Revert values of pre-emphasis and signal amps to the saved ones */
1372 m2 = readl(port_mmio + PHY_MODE2);
1373
1374 m2 &= ~MV_M2_PREAMP_MASK;
1375 m2 |= hpriv->signal[ap->port_no].amps;
1376 m2 |= hpriv->signal[ap->port_no].pre;
1377 m2 &= ~(1 << 16);
1378
1379 writel(m2, port_mmio + PHY_MODE2);
1380 }
1381
1382 /**
1383 * mv_phy_reset - Perform eDMA reset followed by COMRESET
1384 * @ap: ATA channel to manipulate
1385 *
1386 * Part of this is taken from __sata_phy_reset and modified to
1387 * not sleep since this routine gets called from interrupt level.
1388 *
1389 * LOCKING:
1390 * Inherited from caller. This is coded to safe to call at
1391 * interrupt level, i.e. it does not sleep.
1392 */
1393 static void mv_phy_reset(struct ata_port *ap)
1394 {
1395 struct mv_port_priv *pp = ap->private_data;
1396 struct mv_host_priv *hpriv = ap->host_set->private_data;
1397 void __iomem *port_mmio = mv_ap_base(ap);
1398 struct ata_taskfile tf;
1399 struct ata_device *dev = &ap->device[0];
1400 unsigned long timeout;
1401
1402 VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio);
1403
1404 mv_stop_dma(ap);
1405
1406 writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
1407
1408 if (IS_60XX(hpriv)) {
1409 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
1410 ifctl |= (1 << 12) | (1 << 7);
1411 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
1412 }
1413
1414 udelay(25); /* allow reset propagation */
1415
1416 /* Spec never mentions clearing the bit. Marvell's driver does
1417 * clear the bit, however.
1418 */
1419 writelfl(0, port_mmio + EDMA_CMD_OFS);
1420
1421 hpriv->ops->phy_errata(ap);
1422
1423 DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
1424 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1425 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1426
1427 /* proceed to init communications via the scr_control reg */
1428 scr_write_flush(ap, SCR_CONTROL, 0x301);
1429 mdelay(1);
1430 scr_write_flush(ap, SCR_CONTROL, 0x300);
1431 timeout = jiffies + (HZ * 1);
1432 do {
1433 mdelay(10);
1434 if ((scr_read(ap, SCR_STATUS) & 0xf) != 1)
1435 break;
1436 } while (time_before(jiffies, timeout));
1437
1438 mv_scr_write(ap, SCR_ERROR, mv_scr_read(ap, SCR_ERROR));
1439
1440 DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x "
1441 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1442 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1443
1444 if (sata_dev_present(ap)) {
1445 ata_port_probe(ap);
1446 } else {
1447 printk(KERN_INFO "ata%u: no device found (phy stat %08x)\n",
1448 ap->id, scr_read(ap, SCR_STATUS));
1449 ata_port_disable(ap);
1450 return;
1451 }
1452 ap->cbl = ATA_CBL_SATA;
1453
1454 tf.lbah = readb((void __iomem *) ap->ioaddr.lbah_addr);
1455 tf.lbam = readb((void __iomem *) ap->ioaddr.lbam_addr);
1456 tf.lbal = readb((void __iomem *) ap->ioaddr.lbal_addr);
1457 tf.nsect = readb((void __iomem *) ap->ioaddr.nsect_addr);
1458
1459 dev->class = ata_dev_classify(&tf);
1460 if (!ata_dev_present(dev)) {
1461 VPRINTK("Port disabled post-sig: No device present.\n");
1462 ata_port_disable(ap);
1463 }
1464
1465 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1466
1467 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1468
1469 VPRINTK("EXIT\n");
1470 }
1471
1472 /**
1473 * mv_eng_timeout - Routine called by libata when SCSI times out I/O
1474 * @ap: ATA channel to manipulate
1475 *
1476 * Intent is to clear all pending error conditions, reset the
1477 * chip/bus, fail the command, and move on.
1478 *
1479 * LOCKING:
1480 * This routine holds the host_set lock while failing the command.
1481 */
1482 static void mv_eng_timeout(struct ata_port *ap)
1483 {
1484 struct ata_queued_cmd *qc;
1485 unsigned long flags;
1486
1487 printk(KERN_ERR "ata%u: Entering mv_eng_timeout\n",ap->id);
1488 DPRINTK("All regs @ start of eng_timeout\n");
1489 mv_dump_all_regs(ap->host_set->mmio_base, ap->port_no,
1490 to_pci_dev(ap->host_set->dev));
1491
1492 qc = ata_qc_from_tag(ap, ap->active_tag);
1493 printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n",
1494 ap->host_set->mmio_base, ap, qc, qc->scsicmd,
1495 &qc->scsicmd->cmnd);
1496
1497 mv_err_intr(ap);
1498 mv_phy_reset(ap);
1499
1500 if (!qc) {
1501 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
1502 ap->id);
1503 } else {
1504 /* hack alert! We cannot use the supplied completion
1505 * function from inside the ->eh_strategy_handler() thread.
1506 * libata is the only user of ->eh_strategy_handler() in
1507 * any kernel, so the default scsi_done() assumes it is
1508 * not being called from the SCSI EH.
1509 */
1510 spin_lock_irqsave(&ap->host_set->lock, flags);
1511 qc->scsidone = scsi_finish_command;
1512 ata_qc_complete(qc, AC_ERR_OTHER);
1513 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1514 }
1515 }
1516
1517 /**
1518 * mv_port_init - Perform some early initialization on a single port.
1519 * @port: libata data structure storing shadow register addresses
1520 * @port_mmio: base address of the port
1521 *
1522 * Initialize shadow register mmio addresses, clear outstanding
1523 * interrupts on the port, and unmask interrupts for the future
1524 * start of the port.
1525 *
1526 * LOCKING:
1527 * Inherited from caller.
1528 */
1529 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
1530 {
1531 unsigned long shd_base = (unsigned long) port_mmio + SHD_BLK_OFS;
1532 unsigned serr_ofs;
1533
1534 /* PIO related setup
1535 */
1536 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
1537 port->error_addr =
1538 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
1539 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
1540 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
1541 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
1542 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
1543 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
1544 port->status_addr =
1545 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
1546 /* special case: control/altstatus doesn't have ATA_REG_ address */
1547 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
1548
1549 /* unused: */
1550 port->cmd_addr = port->bmdma_addr = port->scr_addr = 0;
1551
1552 /* Clear any currently outstanding port interrupt conditions */
1553 serr_ofs = mv_scr_offset(SCR_ERROR);
1554 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
1555 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1556
1557 /* unmask all EDMA error interrupts */
1558 writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
1559
1560 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
1561 readl(port_mmio + EDMA_CFG_OFS),
1562 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
1563 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
1564 }
1565
1566 static int mv_chip_id(struct pci_dev *pdev, struct mv_host_priv *hpriv,
1567 unsigned int board_idx)
1568 {
1569 u8 rev_id;
1570 u32 hp_flags = hpriv->hp_flags;
1571
1572 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1573
1574 switch(board_idx) {
1575 case chip_5080:
1576 hpriv->ops = &mv5xxx_ops;
1577 hp_flags |= MV_HP_50XX;
1578
1579 switch (rev_id) {
1580 case 0x1:
1581 hp_flags |= MV_HP_ERRATA_50XXB0;
1582 break;
1583 case 0x3:
1584 hp_flags |= MV_HP_ERRATA_50XXB2;
1585 break;
1586 default:
1587 dev_printk(KERN_WARNING, &pdev->dev,
1588 "Applying 50XXB2 workarounds to unknown rev\n");
1589 hp_flags |= MV_HP_ERRATA_50XXB2;
1590 break;
1591 }
1592 break;
1593
1594 case chip_504x:
1595 case chip_508x:
1596 hpriv->ops = &mv5xxx_ops;
1597 hp_flags |= MV_HP_50XX;
1598
1599 switch (rev_id) {
1600 case 0x0:
1601 hp_flags |= MV_HP_ERRATA_50XXB0;
1602 break;
1603 case 0x3:
1604 hp_flags |= MV_HP_ERRATA_50XXB2;
1605 break;
1606 default:
1607 dev_printk(KERN_WARNING, &pdev->dev,
1608 "Applying B2 workarounds to unknown rev\n");
1609 hp_flags |= MV_HP_ERRATA_50XXB2;
1610 break;
1611 }
1612 break;
1613
1614 case chip_604x:
1615 case chip_608x:
1616 hpriv->ops = &mv6xxx_ops;
1617
1618 switch (rev_id) {
1619 case 0x7:
1620 hp_flags |= MV_HP_ERRATA_60X1B2;
1621 break;
1622 case 0x9:
1623 hp_flags |= MV_HP_ERRATA_60X1C0;
1624 break;
1625 default:
1626 dev_printk(KERN_WARNING, &pdev->dev,
1627 "Applying B2 workarounds to unknown rev\n");
1628 hp_flags |= MV_HP_ERRATA_60X1B2;
1629 break;
1630 }
1631 break;
1632
1633 default:
1634 printk(KERN_ERR DRV_NAME ": BUG: invalid board index %u\n", board_idx);
1635 return 1;
1636 }
1637
1638 hpriv->hp_flags = hp_flags;
1639
1640 return 0;
1641 }
1642
1643 /**
1644 * mv_init_host - Perform some early initialization of the host.
1645 * @pdev: host PCI device
1646 * @probe_ent: early data struct representing the host
1647 *
1648 * If possible, do an early global reset of the host. Then do
1649 * our port init and clear/unmask all/relevant host interrupts.
1650 *
1651 * LOCKING:
1652 * Inherited from caller.
1653 */
1654 static int mv_init_host(struct pci_dev *pdev, struct ata_probe_ent *probe_ent,
1655 unsigned int board_idx)
1656 {
1657 int rc = 0, n_hc, port, hc;
1658 void __iomem *mmio = probe_ent->mmio_base;
1659 void __iomem *port_mmio;
1660 struct mv_host_priv *hpriv = probe_ent->private_data;
1661
1662 /* global interrupt mask */
1663 writel(0, mmio + HC_MAIN_IRQ_MASK_OFS);
1664
1665 rc = mv_chip_id(pdev, hpriv, board_idx);
1666 if (rc)
1667 goto done;
1668
1669 n_hc = mv_get_hc_count(probe_ent->host_flags);
1670 probe_ent->n_ports = MV_PORTS_PER_HC * n_hc;
1671
1672 for (port = 0; port < probe_ent->n_ports; port++)
1673 hpriv->ops->read_preamp(hpriv, port, mmio);
1674
1675 rc = hpriv->ops->reset_hc(hpriv, mmio);
1676 if (rc)
1677 goto done;
1678
1679 hpriv->ops->enable_leds(hpriv, mmio);
1680
1681 for (port = 0; port < probe_ent->n_ports; port++) {
1682 port_mmio = mv_port_base(mmio, port);
1683 mv_port_init(&probe_ent->port[port], port_mmio);
1684 }
1685
1686 for (hc = 0; hc < n_hc; hc++) {
1687 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1688
1689 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
1690 "(before clear)=0x%08x\n", hc,
1691 readl(hc_mmio + HC_CFG_OFS),
1692 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
1693
1694 /* Clear any currently outstanding hc interrupt conditions */
1695 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
1696 }
1697
1698 /* Clear any currently outstanding host interrupt conditions */
1699 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
1700
1701 /* and unmask interrupt generation for host regs */
1702 writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS);
1703 writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS);
1704
1705 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
1706 "PCI int cause/mask=0x%08x/0x%08x\n",
1707 readl(mmio + HC_MAIN_IRQ_CAUSE_OFS),
1708 readl(mmio + HC_MAIN_IRQ_MASK_OFS),
1709 readl(mmio + PCI_IRQ_CAUSE_OFS),
1710 readl(mmio + PCI_IRQ_MASK_OFS));
1711
1712 done:
1713 return rc;
1714 }
1715
1716 /**
1717 * mv_print_info - Dump key info to kernel log for perusal.
1718 * @probe_ent: early data struct representing the host
1719 *
1720 * FIXME: complete this.
1721 *
1722 * LOCKING:
1723 * Inherited from caller.
1724 */
1725 static void mv_print_info(struct ata_probe_ent *probe_ent)
1726 {
1727 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1728 struct mv_host_priv *hpriv = probe_ent->private_data;
1729 u8 rev_id, scc;
1730 const char *scc_s;
1731
1732 /* Use this to determine the HW stepping of the chip so we know
1733 * what errata to workaround
1734 */
1735 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1736
1737 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
1738 if (scc == 0)
1739 scc_s = "SCSI";
1740 else if (scc == 0x01)
1741 scc_s = "RAID";
1742 else
1743 scc_s = "unknown";
1744
1745 dev_printk(KERN_INFO, &pdev->dev,
1746 "%u slots %u ports %s mode IRQ via %s\n",
1747 (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports,
1748 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
1749 }
1750
1751 /**
1752 * mv_init_one - handle a positive probe of a Marvell host
1753 * @pdev: PCI device found
1754 * @ent: PCI device ID entry for the matched host
1755 *
1756 * LOCKING:
1757 * Inherited from caller.
1758 */
1759 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1760 {
1761 static int printed_version = 0;
1762 struct ata_probe_ent *probe_ent = NULL;
1763 struct mv_host_priv *hpriv;
1764 unsigned int board_idx = (unsigned int)ent->driver_data;
1765 void __iomem *mmio_base;
1766 int pci_dev_busy = 0, rc;
1767
1768 if (!printed_version++)
1769 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
1770
1771 rc = pci_enable_device(pdev);
1772 if (rc) {
1773 return rc;
1774 }
1775
1776 rc = pci_request_regions(pdev, DRV_NAME);
1777 if (rc) {
1778 pci_dev_busy = 1;
1779 goto err_out;
1780 }
1781
1782 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1783 if (probe_ent == NULL) {
1784 rc = -ENOMEM;
1785 goto err_out_regions;
1786 }
1787
1788 memset(probe_ent, 0, sizeof(*probe_ent));
1789 probe_ent->dev = pci_dev_to_dev(pdev);
1790 INIT_LIST_HEAD(&probe_ent->node);
1791
1792 mmio_base = pci_iomap(pdev, MV_PRIMARY_BAR, 0);
1793 if (mmio_base == NULL) {
1794 rc = -ENOMEM;
1795 goto err_out_free_ent;
1796 }
1797
1798 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1799 if (!hpriv) {
1800 rc = -ENOMEM;
1801 goto err_out_iounmap;
1802 }
1803 memset(hpriv, 0, sizeof(*hpriv));
1804
1805 probe_ent->sht = mv_port_info[board_idx].sht;
1806 probe_ent->host_flags = mv_port_info[board_idx].host_flags;
1807 probe_ent->pio_mask = mv_port_info[board_idx].pio_mask;
1808 probe_ent->udma_mask = mv_port_info[board_idx].udma_mask;
1809 probe_ent->port_ops = mv_port_info[board_idx].port_ops;
1810
1811 probe_ent->irq = pdev->irq;
1812 probe_ent->irq_flags = SA_SHIRQ;
1813 probe_ent->mmio_base = mmio_base;
1814 probe_ent->private_data = hpriv;
1815
1816 /* initialize adapter */
1817 rc = mv_init_host(pdev, probe_ent, board_idx);
1818 if (rc) {
1819 goto err_out_hpriv;
1820 }
1821
1822 /* Enable interrupts */
1823 if (pci_enable_msi(pdev) == 0) {
1824 hpriv->hp_flags |= MV_HP_FLAG_MSI;
1825 } else {
1826 pci_intx(pdev, 1);
1827 }
1828
1829 mv_dump_pci_cfg(pdev, 0x68);
1830 mv_print_info(probe_ent);
1831
1832 if (ata_device_add(probe_ent) == 0) {
1833 rc = -ENODEV; /* No devices discovered */
1834 goto err_out_dev_add;
1835 }
1836
1837 kfree(probe_ent);
1838 return 0;
1839
1840 err_out_dev_add:
1841 if (MV_HP_FLAG_MSI & hpriv->hp_flags) {
1842 pci_disable_msi(pdev);
1843 } else {
1844 pci_intx(pdev, 0);
1845 }
1846 err_out_hpriv:
1847 kfree(hpriv);
1848 err_out_iounmap:
1849 pci_iounmap(pdev, mmio_base);
1850 err_out_free_ent:
1851 kfree(probe_ent);
1852 err_out_regions:
1853 pci_release_regions(pdev);
1854 err_out:
1855 if (!pci_dev_busy) {
1856 pci_disable_device(pdev);
1857 }
1858
1859 return rc;
1860 }
1861
1862 static int __init mv_init(void)
1863 {
1864 return pci_module_init(&mv_pci_driver);
1865 }
1866
1867 static void __exit mv_exit(void)
1868 {
1869 pci_unregister_driver(&mv_pci_driver);
1870 }
1871
1872 MODULE_AUTHOR("Brett Russ");
1873 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
1874 MODULE_LICENSE("GPL");
1875 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
1876 MODULE_VERSION(DRV_VERSION);
1877
1878 module_init(mv_init);
1879 module_exit(mv_exit);
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