2 * SPU core / file system interface and HW structures
4 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
6 * Author: Arnd Bergmann <arndb@de.ibm.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 #include <linux/workqueue.h>
28 #include <linux/sysdev.h>
30 #define LS_SIZE (256 * 1024)
31 #define LS_ADDR_MASK (LS_SIZE - 1)
33 #define MFC_PUT_CMD 0x20
34 #define MFC_PUTS_CMD 0x28
35 #define MFC_PUTR_CMD 0x30
36 #define MFC_PUTF_CMD 0x22
37 #define MFC_PUTB_CMD 0x21
38 #define MFC_PUTFS_CMD 0x2A
39 #define MFC_PUTBS_CMD 0x29
40 #define MFC_PUTRF_CMD 0x32
41 #define MFC_PUTRB_CMD 0x31
42 #define MFC_PUTL_CMD 0x24
43 #define MFC_PUTRL_CMD 0x34
44 #define MFC_PUTLF_CMD 0x26
45 #define MFC_PUTLB_CMD 0x25
46 #define MFC_PUTRLF_CMD 0x36
47 #define MFC_PUTRLB_CMD 0x35
49 #define MFC_GET_CMD 0x40
50 #define MFC_GETS_CMD 0x48
51 #define MFC_GETF_CMD 0x42
52 #define MFC_GETB_CMD 0x41
53 #define MFC_GETFS_CMD 0x4A
54 #define MFC_GETBS_CMD 0x49
55 #define MFC_GETL_CMD 0x44
56 #define MFC_GETLF_CMD 0x46
57 #define MFC_GETLB_CMD 0x45
59 #define MFC_SDCRT_CMD 0x80
60 #define MFC_SDCRTST_CMD 0x81
61 #define MFC_SDCRZ_CMD 0x89
62 #define MFC_SDCRS_CMD 0x8D
63 #define MFC_SDCRF_CMD 0x8F
65 #define MFC_GETLLAR_CMD 0xD0
66 #define MFC_PUTLLC_CMD 0xB4
67 #define MFC_PUTLLUC_CMD 0xB0
68 #define MFC_PUTQLLUC_CMD 0xB8
69 #define MFC_SNDSIG_CMD 0xA0
70 #define MFC_SNDSIGB_CMD 0xA1
71 #define MFC_SNDSIGF_CMD 0xA2
72 #define MFC_BARRIER_CMD 0xC0
73 #define MFC_EIEIO_CMD 0xC8
74 #define MFC_SYNC_CMD 0xCC
76 #define MFC_MIN_DMA_SIZE_SHIFT 4 /* 16 bytes */
77 #define MFC_MAX_DMA_SIZE_SHIFT 14 /* 16384 bytes */
78 #define MFC_MIN_DMA_SIZE (1 << MFC_MIN_DMA_SIZE_SHIFT)
79 #define MFC_MAX_DMA_SIZE (1 << MFC_MAX_DMA_SIZE_SHIFT)
80 #define MFC_MIN_DMA_SIZE_MASK (MFC_MIN_DMA_SIZE - 1)
81 #define MFC_MAX_DMA_SIZE_MASK (MFC_MAX_DMA_SIZE - 1)
82 #define MFC_MIN_DMA_LIST_SIZE 0x0008 /* 8 bytes */
83 #define MFC_MAX_DMA_LIST_SIZE 0x4000 /* 16K bytes */
85 #define MFC_TAGID_TO_TAGMASK(tag_id) (1 << (tag_id & 0x1F))
87 /* Events for Channels 0-2 */
88 #define MFC_DMA_TAG_STATUS_UPDATE_EVENT 0x00000001
89 #define MFC_DMA_TAG_CMD_STALL_NOTIFY_EVENT 0x00000002
90 #define MFC_DMA_QUEUE_AVAILABLE_EVENT 0x00000008
91 #define MFC_SPU_MAILBOX_WRITTEN_EVENT 0x00000010
92 #define MFC_DECREMENTER_EVENT 0x00000020
93 #define MFC_PU_INT_MAILBOX_AVAILABLE_EVENT 0x00000040
94 #define MFC_PU_MAILBOX_AVAILABLE_EVENT 0x00000080
95 #define MFC_SIGNAL_2_EVENT 0x00000100
96 #define MFC_SIGNAL_1_EVENT 0x00000200
97 #define MFC_LLR_LOST_EVENT 0x00000400
98 #define MFC_PRIV_ATTN_EVENT 0x00000800
99 #define MFC_MULTI_SRC_EVENT 0x00001000
101 /* Flags indicating progress during context switch. */
102 #define SPU_CONTEXT_SWITCH_PENDING 0UL
103 #define SPU_CONTEXT_SWITCH_ACTIVE 1UL
109 enum spu_utilization_state
{
113 SPU_UTIL_IDLE_LOADED
,
119 unsigned long local_store_phys
;
121 unsigned long problem_phys
;
122 struct spu_problem __iomem
*problem
;
123 struct spu_priv2 __iomem
*priv2
;
124 struct list_head cbe_list
;
125 struct list_head full_list
;
126 enum { SPU_FREE
, SPU_USED
} alloc_state
;
128 unsigned int irqs
[3];
134 unsigned int slb_replace
;
135 struct mm_struct
*mm
;
136 struct spu_context
*ctx
;
137 struct spu_runqueue
*rq
;
138 unsigned long long timestamp
;
142 spinlock_t register_lock
;
144 void (* wbox_callback
)(struct spu
*spu
);
145 void (* ibox_callback
)(struct spu
*spu
);
146 void (* stop_callback
)(struct spu
*spu
);
147 void (* mfc_callback
)(struct spu
*spu
);
148 void (* dma_callback
)(struct spu
*spu
, int type
);
156 void* pdata
; /* platform private data */
158 /* of based platforms only */
159 struct device_node
*devnode
;
162 struct spu_priv1 __iomem
*priv1
;
165 u64 shadow_int_mask_RW
[3];
167 struct sys_device sysdev
;
169 int has_mem_affinity
;
170 struct list_head aff_list
;
173 /* protected by interrupt reentrancy */
174 enum spu_utilization_state util_state
;
175 unsigned long long tstamp
;
176 unsigned long long times
[SPU_UTIL_MAX
];
177 unsigned long long vol_ctx_switch
;
178 unsigned long long invol_ctx_switch
;
179 unsigned long long min_flt
;
180 unsigned long long maj_flt
;
181 unsigned long long hash_flt
;
182 unsigned long long slb_flt
;
183 unsigned long long class2_intr
;
184 unsigned long long libassist
;
188 struct cbe_spu_info
{
189 struct mutex list_mutex
;
190 struct list_head spus
;
193 atomic_t reserved_spus
;
196 extern struct cbe_spu_info cbe_spu_info
[];
198 void spu_init_channels(struct spu
*spu
);
199 int spu_irq_class_0_bottom(struct spu
*spu
);
200 int spu_irq_class_1_bottom(struct spu
*spu
);
201 void spu_irq_setaffinity(struct spu
*spu
, int cpu
);
204 void crash_register_spus(struct list_head
*list
);
206 static inline void crash_register_spus(struct list_head
*list
)
211 extern void spu_invalidate_slbs(struct spu
*spu
);
212 extern void spu_associate_mm(struct spu
*spu
, struct mm_struct
*mm
);
214 /* Calls from the memory management to the SPU */
216 extern void spu_flush_all_slbs(struct mm_struct
*mm
);
218 /* This interface allows a profiler (e.g., OProfile) to store a ref
219 * to spu context information that it creates. This caching technique
220 * avoids the need to recreate this information after a save/restore operation.
222 * Assumes the caller has already incremented the ref count to
223 * profile_info; then spu_context_destroy must call kref_put
226 void spu_set_profile_private_kref(struct spu_context
*ctx
,
227 struct kref
*prof_info_kref
,
228 void ( * prof_info_release
) (struct kref
*kref
));
230 void *spu_get_profile_private_kref(struct spu_context
*ctx
);
232 /* system callbacks from the SPU */
233 struct spu_syscall_block
{
237 extern long spu_sys_callback(struct spu_syscall_block
*s
);
239 /* syscalls implemented in spufs */
241 extern struct spufs_calls
{
242 asmlinkage
long (*create_thread
)(const char __user
*name
,
243 unsigned int flags
, mode_t mode
,
244 struct file
*neighbor
);
245 asmlinkage
long (*spu_run
)(struct file
*filp
, __u32 __user
*unpc
,
246 __u32 __user
*ustatus
);
247 struct module
*owner
;
250 /* coredump calls implemented in spufs */
251 struct spu_coredump_calls
{
252 asmlinkage
int (*arch_notes_size
)(void);
253 asmlinkage
void (*arch_write_notes
)(struct file
*file
);
254 struct module
*owner
;
257 /* return status from spu_run, same as in libspe */
258 #define SPE_EVENT_DMA_ALIGNMENT 0x0008 /*A DMA alignment error */
259 #define SPE_EVENT_SPE_ERROR 0x0010 /*An illegal instruction error*/
260 #define SPE_EVENT_SPE_DATA_SEGMENT 0x0020 /*A DMA segmentation error */
261 #define SPE_EVENT_SPE_DATA_STORAGE 0x0040 /*A DMA storage error */
262 #define SPE_EVENT_INVALID_DMA 0x0800 /* Invalid MFC DMA */
265 * Flags for sys_spu_create.
267 #define SPU_CREATE_EVENTS_ENABLED 0x0001
268 #define SPU_CREATE_GANG 0x0002
269 #define SPU_CREATE_NOSCHED 0x0004
270 #define SPU_CREATE_ISOLATE 0x0008
271 #define SPU_CREATE_AFFINITY_SPU 0x0010
272 #define SPU_CREATE_AFFINITY_MEM 0x0020
274 #define SPU_CREATE_FLAG_ALL 0x003f /* mask of all valid flags */
277 #ifdef CONFIG_SPU_FS_MODULE
278 int register_spu_syscalls(struct spufs_calls
*calls
);
279 void unregister_spu_syscalls(struct spufs_calls
*calls
);
281 static inline int register_spu_syscalls(struct spufs_calls
*calls
)
285 static inline void unregister_spu_syscalls(struct spufs_calls
*calls
)
290 int register_arch_coredump_calls(struct spu_coredump_calls
*calls
);
291 void unregister_arch_coredump_calls(struct spu_coredump_calls
*calls
);
293 int spu_add_sysdev_attr(struct sysdev_attribute
*attr
);
294 void spu_remove_sysdev_attr(struct sysdev_attribute
*attr
);
296 int spu_add_sysdev_attr_group(struct attribute_group
*attrs
);
297 void spu_remove_sysdev_attr_group(struct attribute_group
*attrs
);
303 * oprofile can get notified when a context switch is performed
304 * on an spe. The notifer function that gets called is passed
305 * a pointer to the SPU structure as well as the object-id that
306 * identifies the binary running on that SPU now.
308 * For a context save, the object-id that is passed is zero,
309 * identifying that the kernel will run from that moment on.
311 * For a context restore, the object-id is the value written
312 * to object-id spufs file from user space and the notifer
313 * function can assume that spu->ctx is valid.
315 struct notifier_block
;
316 int spu_switch_event_register(struct notifier_block
* n
);
317 int spu_switch_event_unregister(struct notifier_block
* n
);
320 * This defines the Local Store, Problem Area and Privlege Area of an SPU.
323 union mfc_tag_size_class_cmd
{
346 #define MS_SYNC_PENDING 1L
347 u64 spc_mssync_RW
; /* 0x0000 */
348 u8 pad_0x0008_0x3000
[0x3000 - 0x0008];
351 u8 pad_0x3000_0x3004
[0x4]; /* 0x3000 */
352 u32 mfc_lsa_W
; /* 0x3004 */
353 u64 mfc_ea_W
; /* 0x3008 */
354 union mfc_tag_size_class_cmd mfc_union_W
; /* 0x3010 */
355 u8 pad_0x3018_0x3104
[0xec]; /* 0x3018 */
356 u32 dma_qstatus_R
; /* 0x3104 */
357 u8 pad_0x3108_0x3204
[0xfc]; /* 0x3108 */
358 u32 dma_querytype_RW
; /* 0x3204 */
359 u8 pad_0x3208_0x321c
[0x14]; /* 0x3208 */
360 u32 dma_querymask_RW
; /* 0x321c */
361 u8 pad_0x3220_0x322c
[0xc]; /* 0x3220 */
362 u32 dma_tagstatus_R
; /* 0x322c */
363 #define DMA_TAGSTATUS_INTR_ANY 1u
364 #define DMA_TAGSTATUS_INTR_ALL 2u
365 u8 pad_0x3230_0x4000
[0x4000 - 0x3230]; /* 0x3230 */
367 /* SPU Control Area */
368 u8 pad_0x4000_0x4004
[0x4]; /* 0x4000 */
369 u32 pu_mb_R
; /* 0x4004 */
370 u8 pad_0x4008_0x400c
[0x4]; /* 0x4008 */
371 u32 spu_mb_W
; /* 0x400c */
372 u8 pad_0x4010_0x4014
[0x4]; /* 0x4010 */
373 u32 mb_stat_R
; /* 0x4014 */
374 u8 pad_0x4018_0x401c
[0x4]; /* 0x4018 */
375 u32 spu_runcntl_RW
; /* 0x401c */
376 #define SPU_RUNCNTL_STOP 0L
377 #define SPU_RUNCNTL_RUNNABLE 1L
378 #define SPU_RUNCNTL_ISOLATE 2L
379 u8 pad_0x4020_0x4024
[0x4]; /* 0x4020 */
380 u32 spu_status_R
; /* 0x4024 */
381 #define SPU_STOP_STATUS_SHIFT 16
382 #define SPU_STATUS_STOPPED 0x0
383 #define SPU_STATUS_RUNNING 0x1
384 #define SPU_STATUS_STOPPED_BY_STOP 0x2
385 #define SPU_STATUS_STOPPED_BY_HALT 0x4
386 #define SPU_STATUS_WAITING_FOR_CHANNEL 0x8
387 #define SPU_STATUS_SINGLE_STEP 0x10
388 #define SPU_STATUS_INVALID_INSTR 0x20
389 #define SPU_STATUS_INVALID_CH 0x40
390 #define SPU_STATUS_ISOLATED_STATE 0x80
391 #define SPU_STATUS_ISOLATED_LOAD_STATUS 0x200
392 #define SPU_STATUS_ISOLATED_EXIT_STATUS 0x400
393 u8 pad_0x4028_0x402c
[0x4]; /* 0x4028 */
394 u32 spu_spe_R
; /* 0x402c */
395 u8 pad_0x4030_0x4034
[0x4]; /* 0x4030 */
396 u32 spu_npc_RW
; /* 0x4034 */
397 u8 pad_0x4038_0x14000
[0x14000 - 0x4038]; /* 0x4038 */
399 /* Signal Notification Area */
400 u8 pad_0x14000_0x1400c
[0xc]; /* 0x14000 */
401 u32 signal_notify1
; /* 0x1400c */
402 u8 pad_0x14010_0x1c00c
[0x7ffc]; /* 0x14010 */
403 u32 signal_notify2
; /* 0x1c00c */
404 } __attribute__ ((aligned(0x20000)));
406 /* SPU Privilege 2 State Area */
409 u8 pad_0x0000_0x1100
[0x1100 - 0x0000]; /* 0x0000 */
411 /* SLB Management Registers */
412 u8 pad_0x1100_0x1108
[0x8]; /* 0x1100 */
413 u64 slb_index_W
; /* 0x1108 */
414 #define SLB_INDEX_MASK 0x7L
415 u64 slb_esid_RW
; /* 0x1110 */
416 u64 slb_vsid_RW
; /* 0x1118 */
417 #define SLB_VSID_SUPERVISOR_STATE (0x1ull << 11)
418 #define SLB_VSID_SUPERVISOR_STATE_MASK (0x1ull << 11)
419 #define SLB_VSID_PROBLEM_STATE (0x1ull << 10)
420 #define SLB_VSID_PROBLEM_STATE_MASK (0x1ull << 10)
421 #define SLB_VSID_EXECUTE_SEGMENT (0x1ull << 9)
422 #define SLB_VSID_NO_EXECUTE_SEGMENT (0x1ull << 9)
423 #define SLB_VSID_EXECUTE_SEGMENT_MASK (0x1ull << 9)
424 #define SLB_VSID_4K_PAGE (0x0 << 8)
425 #define SLB_VSID_LARGE_PAGE (0x1ull << 8)
426 #define SLB_VSID_PAGE_SIZE_MASK (0x1ull << 8)
427 #define SLB_VSID_CLASS_MASK (0x1ull << 7)
428 #define SLB_VSID_VIRTUAL_PAGE_SIZE_MASK (0x1ull << 6)
429 u64 slb_invalidate_entry_W
; /* 0x1120 */
430 u64 slb_invalidate_all_W
; /* 0x1128 */
431 u8 pad_0x1130_0x2000
[0x2000 - 0x1130]; /* 0x1130 */
433 /* Context Save / Restore Area */
434 struct mfc_cq_sr spuq
[16]; /* 0x2000 */
435 struct mfc_cq_sr puq
[8]; /* 0x2200 */
436 u8 pad_0x2300_0x3000
[0x3000 - 0x2300]; /* 0x2300 */
439 u64 mfc_control_RW
; /* 0x3000 */
440 #define MFC_CNTL_RESUME_DMA_QUEUE (0ull << 0)
441 #define MFC_CNTL_SUSPEND_DMA_QUEUE (1ull << 0)
442 #define MFC_CNTL_SUSPEND_DMA_QUEUE_MASK (1ull << 0)
443 #define MFC_CNTL_SUSPEND_MASK (1ull << 4)
444 #define MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION (0ull << 8)
445 #define MFC_CNTL_SUSPEND_IN_PROGRESS (1ull << 8)
446 #define MFC_CNTL_SUSPEND_COMPLETE (3ull << 8)
447 #define MFC_CNTL_SUSPEND_DMA_STATUS_MASK (3ull << 8)
448 #define MFC_CNTL_DMA_QUEUES_EMPTY (1ull << 14)
449 #define MFC_CNTL_DMA_QUEUES_EMPTY_MASK (1ull << 14)
450 #define MFC_CNTL_PURGE_DMA_REQUEST (1ull << 15)
451 #define MFC_CNTL_PURGE_DMA_IN_PROGRESS (1ull << 24)
452 #define MFC_CNTL_PURGE_DMA_COMPLETE (3ull << 24)
453 #define MFC_CNTL_PURGE_DMA_STATUS_MASK (3ull << 24)
454 #define MFC_CNTL_RESTART_DMA_COMMAND (1ull << 32)
455 #define MFC_CNTL_DMA_COMMAND_REISSUE_PENDING (1ull << 32)
456 #define MFC_CNTL_DMA_COMMAND_REISSUE_STATUS_MASK (1ull << 32)
457 #define MFC_CNTL_MFC_PRIVILEGE_STATE (2ull << 33)
458 #define MFC_CNTL_MFC_PROBLEM_STATE (3ull << 33)
459 #define MFC_CNTL_MFC_KEY_PROTECTION_STATE_MASK (3ull << 33)
460 #define MFC_CNTL_DECREMENTER_HALTED (1ull << 35)
461 #define MFC_CNTL_DECREMENTER_RUNNING (1ull << 40)
462 #define MFC_CNTL_DECREMENTER_STATUS_MASK (1ull << 40)
463 u8 pad_0x3008_0x4000
[0x4000 - 0x3008]; /* 0x3008 */
465 /* Interrupt Mailbox */
466 u64 puint_mb_R
; /* 0x4000 */
467 u8 pad_0x4008_0x4040
[0x4040 - 0x4008]; /* 0x4008 */
470 u64 spu_privcntl_RW
; /* 0x4040 */
471 #define SPU_PRIVCNTL_MODE_NORMAL (0x0ull << 0)
472 #define SPU_PRIVCNTL_MODE_SINGLE_STEP (0x1ull << 0)
473 #define SPU_PRIVCNTL_MODE_MASK (0x1ull << 0)
474 #define SPU_PRIVCNTL_NO_ATTENTION_EVENT (0x0ull << 1)
475 #define SPU_PRIVCNTL_ATTENTION_EVENT (0x1ull << 1)
476 #define SPU_PRIVCNTL_ATTENTION_EVENT_MASK (0x1ull << 1)
477 #define SPU_PRIVCNT_LOAD_REQUEST_NORMAL (0x0ull << 2)
478 #define SPU_PRIVCNT_LOAD_REQUEST_ENABLE_MASK (0x1ull << 2)
479 u8 pad_0x4048_0x4058
[0x10]; /* 0x4048 */
480 u64 spu_lslr_RW
; /* 0x4058 */
481 u64 spu_chnlcntptr_RW
; /* 0x4060 */
482 u64 spu_chnlcnt_RW
; /* 0x4068 */
483 u64 spu_chnldata_RW
; /* 0x4070 */
484 u64 spu_cfg_RW
; /* 0x4078 */
485 u8 pad_0x4080_0x5000
[0x5000 - 0x4080]; /* 0x4080 */
487 /* PV2_ImplRegs: Implementation-specific privileged-state 2 regs */
488 u64 spu_pm_trace_tag_status_RW
; /* 0x5000 */
489 u64 spu_tag_status_query_RW
; /* 0x5008 */
490 #define TAG_STATUS_QUERY_CONDITION_BITS (0x3ull << 32)
491 #define TAG_STATUS_QUERY_MASK_BITS (0xffffffffull)
492 u64 spu_cmd_buf1_RW
; /* 0x5010 */
493 #define SPU_COMMAND_BUFFER_1_LSA_BITS (0x7ffffull << 32)
494 #define SPU_COMMAND_BUFFER_1_EAH_BITS (0xffffffffull)
495 u64 spu_cmd_buf2_RW
; /* 0x5018 */
496 #define SPU_COMMAND_BUFFER_2_EAL_BITS ((0xffffffffull) << 32)
497 #define SPU_COMMAND_BUFFER_2_TS_BITS (0xffffull << 16)
498 #define SPU_COMMAND_BUFFER_2_TAG_BITS (0x3full)
499 u64 spu_atomic_status_RW
; /* 0x5020 */
500 } __attribute__ ((aligned(0x20000)));
502 /* SPU Privilege 1 State Area */
504 /* Control and Configuration Area */
505 u64 mfc_sr1_RW
; /* 0x000 */
506 #define MFC_STATE1_LOCAL_STORAGE_DECODE_MASK 0x01ull
507 #define MFC_STATE1_BUS_TLBIE_MASK 0x02ull
508 #define MFC_STATE1_REAL_MODE_OFFSET_ENABLE_MASK 0x04ull
509 #define MFC_STATE1_PROBLEM_STATE_MASK 0x08ull
510 #define MFC_STATE1_RELOCATE_MASK 0x10ull
511 #define MFC_STATE1_MASTER_RUN_CONTROL_MASK 0x20ull
512 #define MFC_STATE1_TABLE_SEARCH_MASK 0x40ull
513 u64 mfc_lpid_RW
; /* 0x008 */
514 u64 spu_idr_RW
; /* 0x010 */
515 u64 mfc_vr_RO
; /* 0x018 */
516 #define MFC_VERSION_BITS (0xffff << 16)
517 #define MFC_REVISION_BITS (0xffff)
518 #define MFC_GET_VERSION_BITS(vr) (((vr) & MFC_VERSION_BITS) >> 16)
519 #define MFC_GET_REVISION_BITS(vr) ((vr) & MFC_REVISION_BITS)
520 u64 spu_vr_RO
; /* 0x020 */
521 #define SPU_VERSION_BITS (0xffff << 16)
522 #define SPU_REVISION_BITS (0xffff)
523 #define SPU_GET_VERSION_BITS(vr) (vr & SPU_VERSION_BITS) >> 16
524 #define SPU_GET_REVISION_BITS(vr) (vr & SPU_REVISION_BITS)
525 u8 pad_0x28_0x100
[0x100 - 0x28]; /* 0x28 */
528 u64 int_mask_RW
[3]; /* 0x100 */
529 #define CLASS0_ENABLE_DMA_ALIGNMENT_INTR 0x1L
530 #define CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR 0x2L
531 #define CLASS0_ENABLE_SPU_ERROR_INTR 0x4L
532 #define CLASS0_ENABLE_MFC_FIR_INTR 0x8L
533 #define CLASS1_ENABLE_SEGMENT_FAULT_INTR 0x1L
534 #define CLASS1_ENABLE_STORAGE_FAULT_INTR 0x2L
535 #define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_GET_INTR 0x4L
536 #define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_PUT_INTR 0x8L
537 #define CLASS2_ENABLE_MAILBOX_INTR 0x1L
538 #define CLASS2_ENABLE_SPU_STOP_INTR 0x2L
539 #define CLASS2_ENABLE_SPU_HALT_INTR 0x4L
540 #define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L
541 u8 pad_0x118_0x140
[0x28]; /* 0x118 */
542 u64 int_stat_RW
[3]; /* 0x140 */
543 u8 pad_0x158_0x180
[0x28]; /* 0x158 */
544 u64 int_route_RW
; /* 0x180 */
546 /* Interrupt Routing */
547 u8 pad_0x188_0x200
[0x200 - 0x188]; /* 0x188 */
549 /* Atomic Unit Control Area */
550 u64 mfc_atomic_flush_RW
; /* 0x200 */
551 #define mfc_atomic_flush_enable 0x1L
552 u8 pad_0x208_0x280
[0x78]; /* 0x208 */
553 u64 resource_allocation_groupID_RW
; /* 0x280 */
554 u64 resource_allocation_enable_RW
; /* 0x288 */
555 u8 pad_0x290_0x3c8
[0x3c8 - 0x290]; /* 0x290 */
557 /* SPU_Cache_ImplRegs: Implementation-dependent cache registers */
559 u64 smf_sbi_signal_sel
; /* 0x3c8 */
560 #define smf_sbi_mask_lsb 56
561 #define smf_sbi_shift (63 - smf_sbi_mask_lsb)
562 #define smf_sbi_mask (0x301LL << smf_sbi_shift)
563 #define smf_sbi_bus0_bits (0x001LL << smf_sbi_shift)
564 #define smf_sbi_bus2_bits (0x100LL << smf_sbi_shift)
565 #define smf_sbi2_bus0_bits (0x201LL << smf_sbi_shift)
566 #define smf_sbi2_bus2_bits (0x300LL << smf_sbi_shift)
567 u64 smf_ato_signal_sel
; /* 0x3d0 */
568 #define smf_ato_mask_lsb 35
569 #define smf_ato_shift (63 - smf_ato_mask_lsb)
570 #define smf_ato_mask (0x3LL << smf_ato_shift)
571 #define smf_ato_bus0_bits (0x2LL << smf_ato_shift)
572 #define smf_ato_bus2_bits (0x1LL << smf_ato_shift)
573 u8 pad_0x3d8_0x400
[0x400 - 0x3d8]; /* 0x3d8 */
575 /* TLB Management Registers */
576 u64 mfc_sdr_RW
; /* 0x400 */
577 u8 pad_0x408_0x500
[0xf8]; /* 0x408 */
578 u64 tlb_index_hint_RO
; /* 0x500 */
579 u64 tlb_index_W
; /* 0x508 */
580 u64 tlb_vpn_RW
; /* 0x510 */
581 u64 tlb_rpn_RW
; /* 0x518 */
582 u8 pad_0x520_0x540
[0x20]; /* 0x520 */
583 u64 tlb_invalidate_entry_W
; /* 0x540 */
584 u64 tlb_invalidate_all_W
; /* 0x548 */
585 u8 pad_0x550_0x580
[0x580 - 0x550]; /* 0x550 */
587 /* SPU_MMU_ImplRegs: Implementation-dependent MMU registers */
588 u64 smm_hid
; /* 0x580 */
589 #define PAGE_SIZE_MASK 0xf000000000000000ull
590 #define PAGE_SIZE_16MB_64KB 0x2000000000000000ull
591 u8 pad_0x588_0x600
[0x600 - 0x588]; /* 0x588 */
593 /* MFC Status/Control Area */
594 u64 mfc_accr_RW
; /* 0x600 */
595 #define MFC_ACCR_EA_ACCESS_GET (1 << 0)
596 #define MFC_ACCR_EA_ACCESS_PUT (1 << 1)
597 #define MFC_ACCR_LS_ACCESS_GET (1 << 3)
598 #define MFC_ACCR_LS_ACCESS_PUT (1 << 4)
599 u8 pad_0x608_0x610
[0x8]; /* 0x608 */
600 u64 mfc_dsisr_RW
; /* 0x610 */
601 #define MFC_DSISR_PTE_NOT_FOUND (1 << 30)
602 #define MFC_DSISR_ACCESS_DENIED (1 << 27)
603 #define MFC_DSISR_ATOMIC (1 << 26)
604 #define MFC_DSISR_ACCESS_PUT (1 << 25)
605 #define MFC_DSISR_ADDR_MATCH (1 << 22)
606 #define MFC_DSISR_LS (1 << 17)
607 #define MFC_DSISR_L (1 << 16)
608 #define MFC_DSISR_ADDRESS_OVERFLOW (1 << 0)
609 u8 pad_0x618_0x620
[0x8]; /* 0x618 */
610 u64 mfc_dar_RW
; /* 0x620 */
611 u8 pad_0x628_0x700
[0x700 - 0x628]; /* 0x628 */
613 /* Replacement Management Table (RMT) Area */
614 u64 rmt_index_RW
; /* 0x700 */
615 u8 pad_0x708_0x710
[0x8]; /* 0x708 */
616 u64 rmt_data1_RW
; /* 0x710 */
617 u8 pad_0x718_0x800
[0x800 - 0x718]; /* 0x718 */
619 /* Control/Configuration Registers */
620 u64 mfc_dsir_R
; /* 0x800 */
621 #define MFC_DSIR_Q (1 << 31)
622 #define MFC_DSIR_SPU_QUEUE MFC_DSIR_Q
623 u64 mfc_lsacr_RW
; /* 0x808 */
624 #define MFC_LSACR_COMPARE_MASK ((~0ull) << 32)
625 #define MFC_LSACR_COMPARE_ADDR ((~0ull) >> 32)
626 u64 mfc_lscrr_R
; /* 0x810 */
627 #define MFC_LSCRR_Q (1 << 31)
628 #define MFC_LSCRR_SPU_QUEUE MFC_LSCRR_Q
629 #define MFC_LSCRR_QI_SHIFT 32
630 #define MFC_LSCRR_QI_MASK ((~0ull) << MFC_LSCRR_QI_SHIFT)
631 u8 pad_0x818_0x820
[0x8]; /* 0x818 */
632 u64 mfc_tclass_id_RW
; /* 0x820 */
633 #define MFC_TCLASS_ID_ENABLE (1L << 0L)
634 #define MFC_TCLASS_SLOT2_ENABLE (1L << 5L)
635 #define MFC_TCLASS_SLOT1_ENABLE (1L << 6L)
636 #define MFC_TCLASS_SLOT0_ENABLE (1L << 7L)
637 #define MFC_TCLASS_QUOTA_2_SHIFT 8L
638 #define MFC_TCLASS_QUOTA_1_SHIFT 16L
639 #define MFC_TCLASS_QUOTA_0_SHIFT 24L
640 #define MFC_TCLASS_QUOTA_2_MASK (0x1FL << MFC_TCLASS_QUOTA_2_SHIFT)
641 #define MFC_TCLASS_QUOTA_1_MASK (0x1FL << MFC_TCLASS_QUOTA_1_SHIFT)
642 #define MFC_TCLASS_QUOTA_0_MASK (0x1FL << MFC_TCLASS_QUOTA_0_SHIFT)
643 u8 pad_0x828_0x900
[0x900 - 0x828]; /* 0x828 */
645 /* Real Mode Support Registers */
646 u64 mfc_rm_boundary
; /* 0x900 */
647 u8 pad_0x908_0x938
[0x30]; /* 0x908 */
648 u64 smf_dma_signal_sel
; /* 0x938 */
649 #define mfc_dma1_mask_lsb 41
650 #define mfc_dma1_shift (63 - mfc_dma1_mask_lsb)
651 #define mfc_dma1_mask (0x3LL << mfc_dma1_shift)
652 #define mfc_dma1_bits (0x1LL << mfc_dma1_shift)
653 #define mfc_dma2_mask_lsb 43
654 #define mfc_dma2_shift (63 - mfc_dma2_mask_lsb)
655 #define mfc_dma2_mask (0x3LL << mfc_dma2_shift)
656 #define mfc_dma2_bits (0x1LL << mfc_dma2_shift)
657 u8 pad_0x940_0xa38
[0xf8]; /* 0x940 */
658 u64 smm_signal_sel
; /* 0xa38 */
659 #define smm_sig_mask_lsb 12
660 #define smm_sig_shift (63 - smm_sig_mask_lsb)
661 #define smm_sig_mask (0x3LL << smm_sig_shift)
662 #define smm_sig_bus0_bits (0x2LL << smm_sig_shift)
663 #define smm_sig_bus2_bits (0x1LL << smm_sig_shift)
664 u8 pad_0xa40_0xc00
[0xc00 - 0xa40]; /* 0xa40 */
666 /* DMA Command Error Area */
667 u64 mfc_cer_R
; /* 0xc00 */
668 #define MFC_CER_Q (1 << 31)
669 #define MFC_CER_SPU_QUEUE MFC_CER_Q
670 u8 pad_0xc08_0x1000
[0x1000 - 0xc08]; /* 0xc08 */
672 /* PV1_ImplRegs: Implementation-dependent privileged-state 1 regs */
673 /* DMA Command Error Area */
674 u64 spu_ecc_cntl_RW
; /* 0x1000 */
675 #define SPU_ECC_CNTL_E (1ull << 0ull)
676 #define SPU_ECC_CNTL_ENABLE SPU_ECC_CNTL_E
677 #define SPU_ECC_CNTL_DISABLE (~SPU_ECC_CNTL_E & 1L)
678 #define SPU_ECC_CNTL_S (1ull << 1ull)
679 #define SPU_ECC_STOP_AFTER_ERROR SPU_ECC_CNTL_S
680 #define SPU_ECC_CONTINUE_AFTER_ERROR (~SPU_ECC_CNTL_S & 2L)
681 #define SPU_ECC_CNTL_B (1ull << 2ull)
682 #define SPU_ECC_BACKGROUND_ENABLE SPU_ECC_CNTL_B
683 #define SPU_ECC_BACKGROUND_DISABLE (~SPU_ECC_CNTL_B & 4L)
684 #define SPU_ECC_CNTL_I_SHIFT 3ull
685 #define SPU_ECC_CNTL_I_MASK (3ull << SPU_ECC_CNTL_I_SHIFT)
686 #define SPU_ECC_WRITE_ALWAYS (~SPU_ECC_CNTL_I & 12L)
687 #define SPU_ECC_WRITE_CORRECTABLE (1ull << SPU_ECC_CNTL_I_SHIFT)
688 #define SPU_ECC_WRITE_UNCORRECTABLE (3ull << SPU_ECC_CNTL_I_SHIFT)
689 #define SPU_ECC_CNTL_D (1ull << 5ull)
690 #define SPU_ECC_DETECTION_ENABLE SPU_ECC_CNTL_D
691 #define SPU_ECC_DETECTION_DISABLE (~SPU_ECC_CNTL_D & 32L)
692 u64 spu_ecc_stat_RW
; /* 0x1008 */
693 #define SPU_ECC_CORRECTED_ERROR (1ull << 0ul)
694 #define SPU_ECC_UNCORRECTED_ERROR (1ull << 1ul)
695 #define SPU_ECC_SCRUB_COMPLETE (1ull << 2ul)
696 #define SPU_ECC_SCRUB_IN_PROGRESS (1ull << 3ul)
697 #define SPU_ECC_INSTRUCTION_ERROR (1ull << 4ul)
698 #define SPU_ECC_DATA_ERROR (1ull << 5ul)
699 #define SPU_ECC_DMA_ERROR (1ull << 6ul)
700 #define SPU_ECC_STATUS_CNT_MASK (256ull << 8)
701 u64 spu_ecc_addr_RW
; /* 0x1010 */
702 u64 spu_err_mask_RW
; /* 0x1018 */
703 #define SPU_ERR_ILLEGAL_INSTR (1ull << 0ul)
704 #define SPU_ERR_ILLEGAL_CHANNEL (1ull << 1ul)
705 u8 pad_0x1020_0x1028
[0x1028 - 0x1020]; /* 0x1020 */
707 /* SPU Debug-Trace Bus (DTB) Selection Registers */
708 u64 spu_trig0_sel
; /* 0x1028 */
709 u64 spu_trig1_sel
; /* 0x1030 */
710 u64 spu_trig2_sel
; /* 0x1038 */
711 u64 spu_trig3_sel
; /* 0x1040 */
712 u64 spu_trace_sel
; /* 0x1048 */
713 #define spu_trace_sel_mask 0x1f1fLL
714 #define spu_trace_sel_bus0_bits 0x1000LL
715 #define spu_trace_sel_bus2_bits 0x0010LL
716 u64 spu_event0_sel
; /* 0x1050 */
717 u64 spu_event1_sel
; /* 0x1058 */
718 u64 spu_event2_sel
; /* 0x1060 */
719 u64 spu_event3_sel
; /* 0x1068 */
720 u64 spu_trace_cntl
; /* 0x1070 */
721 } __attribute__ ((aligned(0x2000)));
723 #endif /* __KERNEL__ */