arch/mips/ddb5xxx/ddb5477/irq.c

   1 /*
   2  * Copyright 2001 MontaVista Software Inc.
   3  * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
   4  *
   5  *  arch/mips/ddb5xxx/ddb5477/irq.c
   6  *     The irq setup and misc routines for DDB5476.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13 #include <linux/init.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/irq.h>
  16 #include <linux/types.h>
  17 #include <linux/ptrace.h>
  18
  19 #include <asm/i8259.h>
  20 #include <asm/system.h>
  21 #include <asm/mipsregs.h>
  22 #include <asm/debug.h>
  23 #include <asm/addrspace.h>
  24 #include <asm/bootinfo.h>
  25
  26 #include <asm/ddb5xxx/ddb5xxx.h>
  27
  28
  29 /*
  30  * IRQ mapping
  31  *
  32  *  0-7: 8 CPU interrupts
  33  *      0 -     software interrupt 0
  34  *      1 -     software interrupt 1
  35  *      2 -     most Vrc5477 interrupts are routed to this pin
  36  *      3 -     (optional) some other interrupts routed to this pin for debugg
  37  *      4 -     not used
  38  *      5 -     not used
  39  *      6 -     not used
  40  *      7 -     cpu timer (used by default)
  41  *
  42  *  8-39: 32 Vrc5477 interrupt sources
  43  *      (refer to the Vrc5477 manual)
  44  */
  45
  46 #define PCI0                    DDB_INTPPES0
  47 #define PCI1                    DDB_INTPPES1
  48
  49 #define ACTIVE_LOW              1
  50 #define ACTIVE_HIGH             0
  51
  52 #define LEVEL_SENSE             2
  53 #define EDGE_TRIGGER            0
  54
  55 #define INTA                    0
  56 #define INTB                    1
  57 #define INTC                    2
  58 #define INTD                    3
  59 #define INTE                    4
  60
  61 static inline void
  62 set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger)
  63 {
  64         u32 reg_value;
  65         u32 reg_bitmask;
  66
  67         reg_value = ddb_in32(pci);
  68         reg_bitmask = 0x3 << (intn * 2);
  69
  70         reg_value &= ~reg_bitmask;
  71         reg_value |= (active | trigger) << (intn * 2);
  72         ddb_out32(pci, reg_value);
  73 }
  74
  75 extern void vrc5477_irq_init(u32 base);
  76 extern void mips_cpu_irq_init(u32 base);
  77 static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
  78
  79 void __init arch_init_irq(void)
  80 {
  81         /* by default, we disable all interrupts and route all vrc5477
  82          * interrupts to pin 0 (irq 2) */
  83         ddb_out32(DDB_INTCTRL0, 0);
  84         ddb_out32(DDB_INTCTRL1, 0);
  85         ddb_out32(DDB_INTCTRL2, 0);
  86         ddb_out32(DDB_INTCTRL3, 0);
  87
  88         clear_c0_status(0xff00);
  89         set_c0_status(0x0400);
  90
  91         /* setup PCI interrupt attributes */
  92         set_pci_int_attr(PCI0, INTA, ACTIVE_LOW, LEVEL_SENSE);
  93         set_pci_int_attr(PCI0, INTB, ACTIVE_LOW, LEVEL_SENSE);
  94         if (mips_machtype == MACH_NEC_ROCKHOPPERII)
  95                 set_pci_int_attr(PCI0, INTC, ACTIVE_HIGH, LEVEL_SENSE);
  96         else
  97                 set_pci_int_attr(PCI0, INTC, ACTIVE_LOW, LEVEL_SENSE);
  98         set_pci_int_attr(PCI0, INTD, ACTIVE_LOW, LEVEL_SENSE);
  99         set_pci_int_attr(PCI0, INTE, ACTIVE_LOW, LEVEL_SENSE);
 100
 101         set_pci_int_attr(PCI1, INTA, ACTIVE_LOW, LEVEL_SENSE);
 102         set_pci_int_attr(PCI1, INTB, ACTIVE_LOW, LEVEL_SENSE);
 103         set_pci_int_attr(PCI1, INTC, ACTIVE_LOW, LEVEL_SENSE);
 104         set_pci_int_attr(PCI1, INTD, ACTIVE_LOW, LEVEL_SENSE);
 105         set_pci_int_attr(PCI1, INTE, ACTIVE_LOW, LEVEL_SENSE);
 106
 107         /*
 108          * for debugging purpose, we enable several error interrupts
 109          * and route them to pin 1. (IP3)
 110          */
 111         /* cpu parity check - 0 */
 112         ll_vrc5477_irq_route(0, 1); ll_vrc5477_irq_enable(0);
 113         /* cpu no-target decode - 1 */
 114         ll_vrc5477_irq_route(1, 1); ll_vrc5477_irq_enable(1);
 115         /* local bus read time-out - 7 */
 116         ll_vrc5477_irq_route(7, 1); ll_vrc5477_irq_enable(7);
 117         /* PCI SERR# - 14 */
 118         ll_vrc5477_irq_route(14, 1); ll_vrc5477_irq_enable(14);
 119         /* PCI internal error - 15 */
 120         ll_vrc5477_irq_route(15, 1); ll_vrc5477_irq_enable(15);
 121         /* IOPCI SERR# - 30 */
 122         ll_vrc5477_irq_route(30, 1); ll_vrc5477_irq_enable(30);
 123         /* IOPCI internal error - 31 */
 124         ll_vrc5477_irq_route(31, 1); ll_vrc5477_irq_enable(31);
 125
 126         /* init all controllers */
 127         init_i8259_irqs();
 128         mips_cpu_irq_init(CPU_IRQ_BASE);
 129         vrc5477_irq_init(VRC5477_IRQ_BASE);
 130
 131
 132         /* setup cascade interrupts */
 133         setup_irq(VRC5477_IRQ_BASE + VRC5477_I8259_CASCADE, &irq_cascade);
 134         setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade);
 135 }
 136
 137 u8 i8259_interrupt_ack(void)
 138 {
 139         u8 irq;
 140         u32 reg;
 141
 142         /* Set window 0 for interrupt acknowledge */
 143         reg = ddb_in32(DDB_PCIINIT10);
 144
 145         ddb_set_pmr(DDB_PCIINIT10, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32);
 146         irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE);
 147         ddb_out32(DDB_PCIINIT10, reg);
 148
 149         /* i8259.c set the base vector to be 0x0 */
 150         return irq + I8259_IRQ_BASE;
 151 }
 152 /*
 153  * the first level int-handler will jump here if it is a vrc5477 irq
 154  */
 155 #define NUM_5477_IRQS   32
 156 static void
 157 vrc5477_irq_dispatch(struct pt_regs *regs)
 158 {
 159         u32 intStatus;
 160         u32 bitmask;
 161         u32 i;
 162
 163         db_assert(ddb_in32(DDB_INT2STAT) == 0);
 164         db_assert(ddb_in32(DDB_INT3STAT) == 0);
 165         db_assert(ddb_in32(DDB_INT4STAT) == 0);
 166         db_assert(ddb_in32(DDB_NMISTAT) == 0);
 167
 168         if (ddb_in32(DDB_INT1STAT) != 0) {
 169 #if defined(CONFIG_RUNTIME_DEBUG)
 170                 vrc5477_show_int_regs();
 171 #endif
 172                 panic("error interrupt has happened.");
 173         }
 174
 175         intStatus = ddb_in32(DDB_INT0STAT);
 176
 177         if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
 178                 /* check for i8259 interrupts */
 179                 if (intStatus & (1 << VRC5477_I8259_CASCADE)) {
 180                         int i8259_irq = i8259_interrupt_ack();
 181                         do_IRQ(I8259_IRQ_BASE + i8259_irq, regs);
 182                         return;
 183                 }
 184         }
 185
 186         for (i=0, bitmask=1; i<= NUM_5477_IRQS; bitmask <<=1, i++) {
 187                 /* do we need to "and" with the int mask? */
 188                 if (intStatus & bitmask) {
 189                         do_IRQ(VRC5477_IRQ_BASE + i, regs);
 190                         return;
 191                 }
 192         }
 193 }
 194
 195 #define VR5477INTS (STATUSF_IP2|STATUSF_IP3|STATUSF_IP4|STATUSF_IP5|STATUSF_IP6)
 196
 197 asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
 198 {
 199         unsigned int pending = read_c0_cause() & read_c0_status();
 200
 201         if (pending & STATUSF_IP7)
 202                 do_IRQ(CPU_IRQ_BASE + 7, regs);
 203         else if (pending & VR5477INTS)
 204                 vrc5477_irq_dispatch(regs);
 205         else if (pending & STATUSF_IP0)
 206                 do_IRQ(CPU_IRQ_BASE, regs);
 207         else if (pending & STATUSF_IP1)
 208                 do_IRQ(CPU_IRQ_BASE + 1, regs);
 209         else
 210                 spurious_interrupt(regs);
 211 }