arch/mips/kernel/traps.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
   7  * Copyright (C) 1995, 1996 Paul M. Antoine
   8  * Copyright (C) 1998 Ulf Carlsson
   9  * Copyright (C) 1999 Silicon Graphics, Inc.
  10  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  11  * Copyright (C) 2000, 01 MIPS Technologies, Inc.
  12  * Copyright (C) 2002, 2003, 2004, 2005  Maciej W. Rozycki
  13  */
  14 #include <linux/init.h>
  15 #include <linux/mm.h>
  16 #include <linux/module.h>
  17 #include <linux/sched.h>
  18 #include <linux/smp.h>
  19 #include <linux/smp_lock.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/kallsyms.h>
  22 #include <linux/bootmem.h>
  23
  24 #include <asm/bootinfo.h>
  25 #include <asm/branch.h>
  26 #include <asm/break.h>
  27 #include <asm/cpu.h>
  28 #include <asm/dsp.h>
  29 #include <asm/fpu.h>
  30 #include <asm/mipsregs.h>
  31 #include <asm/mipsmtregs.h>
  32 #include <asm/module.h>
  33 #include <asm/pgtable.h>
  34 #include <asm/ptrace.h>
  35 #include <asm/sections.h>
  36 #include <asm/system.h>
  37 #include <asm/tlbdebug.h>
  38 #include <asm/traps.h>
  39 #include <asm/uaccess.h>
  40 #include <asm/mmu_context.h>
  41 #include <asm/watch.h>
  42 #include <asm/types.h>
  43
  44 extern asmlinkage void handle_int(void);
  45 extern asmlinkage void handle_tlbm(void);
  46 extern asmlinkage void handle_tlbl(void);
  47 extern asmlinkage void handle_tlbs(void);
  48 extern asmlinkage void handle_adel(void);
  49 extern asmlinkage void handle_ades(void);
  50 extern asmlinkage void handle_ibe(void);
  51 extern asmlinkage void handle_dbe(void);
  52 extern asmlinkage void handle_sys(void);
  53 extern asmlinkage void handle_bp(void);
  54 extern asmlinkage void handle_ri(void);
  55 extern asmlinkage void handle_cpu(void);
  56 extern asmlinkage void handle_ov(void);
  57 extern asmlinkage void handle_tr(void);
  58 extern asmlinkage void handle_fpe(void);
  59 extern asmlinkage void handle_mdmx(void);
  60 extern asmlinkage void handle_watch(void);
  61 extern asmlinkage void handle_mt(void);
  62 extern asmlinkage void handle_dsp(void);
  63 extern asmlinkage void handle_mcheck(void);
  64 extern asmlinkage void handle_reserved(void);
  65
  66 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
  67         struct mips_fpu_struct *ctx);
  68
  69 void (*board_be_init)(void);
  70 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
  71 void (*board_nmi_handler_setup)(void);
  72 void (*board_ejtag_handler_setup)(void);
  73 void (*board_bind_eic_interrupt)(int irq, int regset);
  74
  75 /*
  76  * These constant is for searching for possible module text segments.
  77  * MODULE_RANGE is a guess of how much space is likely to be vmalloced.
  78  */
  79 #define MODULE_RANGE (8*1024*1024)
  80
  81 /*
  82  * This routine abuses get_user()/put_user() to reference pointers
  83  * with at least a bit of error checking ...
  84  */
  85 void show_stack(struct task_struct *task, unsigned long *sp)
  86 {
  87         const int field = 2 * sizeof(unsigned long);
  88         long stackdata;
  89         int i;
  90
  91         if (!sp) {
  92                 if (task && task != current)
  93                         sp = (unsigned long *) task->thread.reg29;
  94                 else
  95                         sp = (unsigned long *) &sp;
  96         }
  97
  98         printk("Stack :");
  99         i = 0;
 100         while ((unsigned long) sp & (PAGE_SIZE - 1)) {
 101                 if (i && ((i % (64 / field)) == 0))
 102                         printk("\n       ");
 103                 if (i > 39) {
 104                         printk(" ...");
 105                         break;
 106                 }
 107
 108                 if (__get_user(stackdata, sp++)) {
 109                         printk(" (Bad stack address)");
 110                         break;
 111                 }
 112
 113                 printk(" %0*lx", field, stackdata);
 114                 i++;
 115         }
 116         printk("\n");
 117 }
 118
 119 void show_trace(struct task_struct *task, unsigned long *stack)
 120 {
 121         const int field = 2 * sizeof(unsigned long);
 122         unsigned long addr;
 123
 124         if (!stack) {
 125                 if (task && task != current)
 126                         stack = (unsigned long *) task->thread.reg29;
 127                 else
 128                         stack = (unsigned long *) &stack;
 129         }
 130
 131         printk("Call Trace:");
 132 #ifdef CONFIG_KALLSYMS
 133         printk("\n");
 134 #endif
 135         while (!kstack_end(stack)) {
 136                 addr = *stack++;
 137                 if (__kernel_text_address(addr)) {
 138                         printk(" [<%0*lx>] ", field, addr);
 139                         print_symbol("%s\n", addr);
 140                 }
 141         }
 142         printk("\n");
 143 }
 144
 145 /*
 146  * The architecture-independent dump_stack generator
 147  */
 148 void dump_stack(void)
 149 {
 150         unsigned long stack;
 151
 152         show_trace(current, &stack);
 153 }
 154
 155 EXPORT_SYMBOL(dump_stack);
 156
 157 void show_code(unsigned int *pc)
 158 {
 159         long i;
 160
 161         printk("\nCode:");
 162
 163         for(i = -3 ; i < 6 ; i++) {
 164                 unsigned int insn;
 165                 if (__get_user(insn, pc + i)) {
 166                         printk(" (Bad address in epc)\n");
 167                         break;
 168                 }
 169                 printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>'));
 170         }
 171 }
 172
 173 void show_regs(struct pt_regs *regs)
 174 {
 175         const int field = 2 * sizeof(unsigned long);
 176         unsigned int cause = regs->cp0_cause;
 177         int i;
 178
 179         printk("Cpu %d\n", smp_processor_id());
 180
 181         /*
 182          * Saved main processor registers
 183          */
 184         for (i = 0; i < 32; ) {
 185                 if ((i % 4) == 0)
 186                         printk("$%2d   :", i);
 187                 if (i == 0)
 188                         printk(" %0*lx", field, 0UL);
 189                 else if (i == 26 || i == 27)
 190                         printk(" %*s", field, "");
 191                 else
 192                         printk(" %0*lx", field, regs->regs[i]);
 193
 194                 i++;
 195                 if ((i % 4) == 0)
 196                         printk("\n");
 197         }
 198
 199         printk("Hi    : %0*lx\n", field, regs->hi);
 200         printk("Lo    : %0*lx\n", field, regs->lo);
 201
 202         /*
 203          * Saved cp0 registers
 204          */
 205         printk("epc   : %0*lx ", field, regs->cp0_epc);
 206         print_symbol("%s ", regs->cp0_epc);
 207         printk("    %s\n", print_tainted());
 208         printk("ra    : %0*lx ", field, regs->regs[31]);
 209         print_symbol("%s\n", regs->regs[31]);
 210
 211         printk("Status: %08x    ", (uint32_t) regs->cp0_status);
 212
 213         if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
 214                 if (regs->cp0_status & ST0_KUO)
 215                         printk("KUo ");
 216                 if (regs->cp0_status & ST0_IEO)
 217                         printk("IEo ");
 218                 if (regs->cp0_status & ST0_KUP)
 219                         printk("KUp ");
 220                 if (regs->cp0_status & ST0_IEP)
 221                         printk("IEp ");
 222                 if (regs->cp0_status & ST0_KUC)
 223                         printk("KUc ");
 224                 if (regs->cp0_status & ST0_IEC)
 225                         printk("IEc ");
 226         } else {
 227                 if (regs->cp0_status & ST0_KX)
 228                         printk("KX ");
 229                 if (regs->cp0_status & ST0_SX)
 230                         printk("SX ");
 231                 if (regs->cp0_status & ST0_UX)
 232                         printk("UX ");
 233                 switch (regs->cp0_status & ST0_KSU) {
 234                 case KSU_USER:
 235                         printk("USER ");
 236                         break;
 237                 case KSU_SUPERVISOR:
 238                         printk("SUPERVISOR ");
 239                         break;
 240                 case KSU_KERNEL:
 241                         printk("KERNEL ");
 242                         break;
 243                 default:
 244                         printk("BAD_MODE ");
 245                         break;
 246                 }
 247                 if (regs->cp0_status & ST0_ERL)
 248                         printk("ERL ");
 249                 if (regs->cp0_status & ST0_EXL)
 250                         printk("EXL ");
 251                 if (regs->cp0_status & ST0_IE)
 252                         printk("IE ");
 253         }
 254         printk("\n");
 255
 256         printk("Cause : %08x\n", cause);
 257
 258         cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
 259         if (1 <= cause && cause <= 5)
 260                 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
 261
 262         printk("PrId  : %08x\n", read_c0_prid());
 263 }
 264
 265 void show_registers(struct pt_regs *regs)
 266 {
 267         show_regs(regs);
 268         print_modules();
 269         printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
 270                 current->comm, current->pid, current_thread_info(), current);
 271         show_stack(current, (long *) regs->regs[29]);
 272         show_trace(current, (long *) regs->regs[29]);
 273         show_code((unsigned int *) regs->cp0_epc);
 274         printk("\n");
 275 }
 276
 277 static DEFINE_SPINLOCK(die_lock);
 278
 279 NORET_TYPE void ATTRIB_NORET die(const char * str, struct pt_regs * regs)
 280 {
 281         static int die_counter;
 282 #ifdef CONFIG_MIPS_MT_SMTC
 283         unsigned long dvpret = dvpe();
 284 #endif /* CONFIG_MIPS_MT_SMTC */
 285
 286         console_verbose();
 287         spin_lock_irq(&die_lock);
 288         bust_spinlocks(1);
 289 #ifdef CONFIG_MIPS_MT_SMTC
 290         mips_mt_regdump(dvpret);
 291 #endif /* CONFIG_MIPS_MT_SMTC */
 292         printk("%s[#%d]:\n", str, ++die_counter);
 293         show_registers(regs);
 294         spin_unlock_irq(&die_lock);
 295         do_exit(SIGSEGV);
 296 }
 297
 298 extern const struct exception_table_entry __start___dbe_table[];
 299 extern const struct exception_table_entry __stop___dbe_table[];
 300
 301 void __declare_dbe_table(void)
 302 {
 303         __asm__ __volatile__(
 304         ".section\t__dbe_table,\"a\"\n\t"
 305         ".previous"
 306         );
 307 }
 308
 309 /* Given an address, look for it in the exception tables. */
 310 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
 311 {
 312         const struct exception_table_entry *e;
 313
 314         e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
 315         if (!e)
 316                 e = search_module_dbetables(addr);
 317         return e;
 318 }
 319
 320 asmlinkage void do_be(struct pt_regs *regs)
 321 {
 322         const int field = 2 * sizeof(unsigned long);
 323         const struct exception_table_entry *fixup = NULL;
 324         int data = regs->cp0_cause & 4;
 325         int action = MIPS_BE_FATAL;
 326
 327         /* XXX For now.  Fixme, this searches the wrong table ...  */
 328         if (data && !user_mode(regs))
 329                 fixup = search_dbe_tables(exception_epc(regs));
 330
 331         if (fixup)
 332                 action = MIPS_BE_FIXUP;
 333
 334         if (board_be_handler)
 335                 action = board_be_handler(regs, fixup != 0);
 336
 337         switch (action) {
 338         case MIPS_BE_DISCARD:
 339                 return;
 340         case MIPS_BE_FIXUP:
 341                 if (fixup) {
 342                         regs->cp0_epc = fixup->nextinsn;
 343                         return;
 344                 }
 345                 break;
 346         default:
 347                 break;
 348         }
 349
 350         /*
 351          * Assume it would be too dangerous to continue ...
 352          */
 353         printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
 354                data ? "Data" : "Instruction",
 355                field, regs->cp0_epc, field, regs->regs[31]);
 356         die_if_kernel("Oops", regs);
 357         force_sig(SIGBUS, current);
 358 }
 359
 360 static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode)
 361 {
 362         unsigned int __user *epc;
 363
 364         epc = (unsigned int __user *) regs->cp0_epc +
 365               ((regs->cp0_cause & CAUSEF_BD) != 0);
 366         if (!get_user(*opcode, epc))
 367                 return 0;
 368
 369         force_sig(SIGSEGV, current);
 370         return 1;
 371 }
 372
 373 /*
 374  * ll/sc emulation
 375  */
 376
 377 #define OPCODE 0xfc000000
 378 #define BASE   0x03e00000
 379 #define RT     0x001f0000
 380 #define OFFSET 0x0000ffff
 381 #define LL     0xc0000000
 382 #define SC     0xe0000000
 383 #define SPEC3  0x7c000000
 384 #define RD     0x0000f800
 385 #define FUNC   0x0000003f
 386 #define RDHWR  0x0000003b
 387
 388 /*
 389  * The ll_bit is cleared by r*_switch.S
 390  */
 391
 392 unsigned long ll_bit;
 393
 394 static struct task_struct *ll_task = NULL;
 395
 396 static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode)
 397 {
 398         unsigned long value, __user *vaddr;
 399         long offset;
 400         int signal = 0;
 401
 402         /*
 403          * analyse the ll instruction that just caused a ri exception
 404          * and put the referenced address to addr.
 405          */
 406
 407         /* sign extend offset */
 408         offset = opcode & OFFSET;
 409         offset <<= 16;
 410         offset >>= 16;
 411
 412         vaddr = (unsigned long __user *)
 413                 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
 414
 415         if ((unsigned long)vaddr & 3) {
 416                 signal = SIGBUS;
 417                 goto sig;
 418         }
 419         if (get_user(value, vaddr)) {
 420                 signal = SIGSEGV;
 421                 goto sig;
 422         }
 423
 424         preempt_disable();
 425
 426         if (ll_task == NULL || ll_task == current) {
 427                 ll_bit = 1;
 428         } else {
 429                 ll_bit = 0;
 430         }
 431         ll_task = current;
 432
 433         preempt_enable();
 434
 435         compute_return_epc(regs);
 436
 437         regs->regs[(opcode & RT) >> 16] = value;
 438
 439         return;
 440
 441 sig:
 442         force_sig(signal, current);
 443 }
 444
 445 static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode)
 446 {
 447         unsigned long __user *vaddr;
 448         unsigned long reg;
 449         long offset;
 450         int signal = 0;
 451
 452         /*
 453          * analyse the sc instruction that just caused a ri exception
 454          * and put the referenced address to addr.
 455          */
 456
 457         /* sign extend offset */
 458         offset = opcode & OFFSET;
 459         offset <<= 16;
 460         offset >>= 16;
 461
 462         vaddr = (unsigned long __user *)
 463                 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
 464         reg = (opcode & RT) >> 16;
 465
 466         if ((unsigned long)vaddr & 3) {
 467                 signal = SIGBUS;
 468                 goto sig;
 469         }
 470
 471         preempt_disable();
 472
 473         if (ll_bit == 0 || ll_task != current) {
 474                 compute_return_epc(regs);
 475                 regs->regs[reg] = 0;
 476                 preempt_enable();
 477                 return;
 478         }
 479
 480         preempt_enable();
 481
 482         if (put_user(regs->regs[reg], vaddr)) {
 483                 signal = SIGSEGV;
 484                 goto sig;
 485         }
 486
 487         compute_return_epc(regs);
 488         regs->regs[reg] = 1;
 489
 490         return;
 491
 492 sig:
 493         force_sig(signal, current);
 494 }
 495
 496 /*
 497  * ll uses the opcode of lwc0 and sc uses the opcode of swc0.  That is both
 498  * opcodes are supposed to result in coprocessor unusable exceptions if
 499  * executed on ll/sc-less processors.  That's the theory.  In practice a
 500  * few processors such as NEC's VR4100 throw reserved instruction exceptions
 501  * instead, so we're doing the emulation thing in both exception handlers.
 502  */
 503 static inline int simulate_llsc(struct pt_regs *regs)
 504 {
 505         unsigned int opcode;
 506
 507         if (unlikely(get_insn_opcode(regs, &opcode)))
 508                 return -EFAULT;
 509
 510         if ((opcode & OPCODE) == LL) {
 511                 simulate_ll(regs, opcode);
 512                 return 0;
 513         }
 514         if ((opcode & OPCODE) == SC) {
 515                 simulate_sc(regs, opcode);
 516                 return 0;
 517         }
 518
 519         return -EFAULT;                 /* Strange things going on ... */
 520 }
 521
 522 /*
 523  * Simulate trapping 'rdhwr' instructions to provide user accessible
 524  * registers not implemented in hardware.  The only current use of this
 525  * is the thread area pointer.
 526  */
 527 static inline int simulate_rdhwr(struct pt_regs *regs)
 528 {
 529         struct thread_info *ti = task_thread_info(current);
 530         unsigned int opcode;
 531
 532         if (unlikely(get_insn_opcode(regs, &opcode)))
 533                 return -EFAULT;
 534
 535         if (unlikely(compute_return_epc(regs)))
 536                 return -EFAULT;
 537
 538         if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
 539                 int rd = (opcode & RD) >> 11;
 540                 int rt = (opcode & RT) >> 16;
 541                 switch (rd) {
 542                         case 29:
 543                                 regs->regs[rt] = ti->tp_value;
 544                                 return 0;
 545                         default:
 546                                 return -EFAULT;
 547                 }
 548         }
 549
 550         /* Not ours.  */
 551         return -EFAULT;
 552 }
 553
 554 asmlinkage void do_ov(struct pt_regs *regs)
 555 {
 556         siginfo_t info;
 557
 558         die_if_kernel("Integer overflow", regs);
 559
 560         info.si_code = FPE_INTOVF;
 561         info.si_signo = SIGFPE;
 562         info.si_errno = 0;
 563         info.si_addr = (void __user *) regs->cp0_epc;
 564         force_sig_info(SIGFPE, &info, current);
 565 }
 566
 567 /*
 568  * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
 569  */
 570 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
 571 {
 572         die_if_kernel("FP exception in kernel code", regs);
 573
 574         if (fcr31 & FPU_CSR_UNI_X) {
 575                 int sig;
 576
 577                 preempt_disable();
 578
 579 #ifdef CONFIG_PREEMPT
 580                 if (!is_fpu_owner()) {
 581                         /* We might lose fpu before disabling preempt... */
 582                         own_fpu();
 583                         BUG_ON(!used_math());
 584                         restore_fp(current);
 585                 }
 586 #endif
 587                 /*
 588                  * Unimplemented operation exception.  If we've got the full
 589                  * software emulator on-board, let's use it...
 590                  *
 591                  * Force FPU to dump state into task/thread context.  We're
 592                  * moving a lot of data here for what is probably a single
 593                  * instruction, but the alternative is to pre-decode the FP
 594                  * register operands before invoking the emulator, which seems
 595                  * a bit extreme for what should be an infrequent event.
 596                  */
 597                 save_fp(current);
 598                 /* Ensure 'resume' not overwrite saved fp context again. */
 599                 lose_fpu();
 600
 601                 preempt_enable();
 602
 603                 /* Run the emulator */
 604                 sig = fpu_emulator_cop1Handler (regs, &current->thread.fpu);
 605
 606                 preempt_disable();
 607
 608                 own_fpu();      /* Using the FPU again.  */
 609                 /*
 610                  * We can't allow the emulated instruction to leave any of
 611                  * the cause bit set in $fcr31.
 612                  */
 613                 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
 614
 615                 /* Restore the hardware register state */
 616                 restore_fp(current);
 617
 618                 preempt_enable();
 619
 620                 /* If something went wrong, signal */
 621                 if (sig)
 622                         force_sig(sig, current);
 623
 624                 return;
 625         }
 626
 627         force_sig(SIGFPE, current);
 628 }
 629
 630 asmlinkage void do_bp(struct pt_regs *regs)
 631 {
 632         unsigned int opcode, bcode;
 633         siginfo_t info;
 634
 635         die_if_kernel("Break instruction in kernel code", regs);
 636
 637         if (get_insn_opcode(regs, &opcode))
 638                 return;
 639
 640         /*
 641          * There is the ancient bug in the MIPS assemblers that the break
 642          * code starts left to bit 16 instead to bit 6 in the opcode.
 643          * Gas is bug-compatible, but not always, grrr...
 644          * We handle both cases with a simple heuristics.  --macro
 645          */
 646         bcode = ((opcode >> 6) & ((1 << 20) - 1));
 647         if (bcode < (1 << 10))
 648                 bcode <<= 10;
 649
 650         /*
 651          * (A short test says that IRIX 5.3 sends SIGTRAP for all break
 652          * insns, even for break codes that indicate arithmetic failures.
 653          * Weird ...)
 654          * But should we continue the brokenness???  --macro
 655          */
 656         switch (bcode) {
 657         case BRK_OVERFLOW << 10:
 658         case BRK_DIVZERO << 10:
 659                 if (bcode == (BRK_DIVZERO << 10))
 660                         info.si_code = FPE_INTDIV;
 661                 else
 662                         info.si_code = FPE_INTOVF;
 663                 info.si_signo = SIGFPE;
 664                 info.si_errno = 0;
 665                 info.si_addr = (void __user *) regs->cp0_epc;
 666                 force_sig_info(SIGFPE, &info, current);
 667                 break;
 668         default:
 669                 force_sig(SIGTRAP, current);
 670         }
 671 }
 672
 673 asmlinkage void do_tr(struct pt_regs *regs)
 674 {
 675         unsigned int opcode, tcode = 0;
 676         siginfo_t info;
 677
 678         die_if_kernel("Trap instruction in kernel code", regs);
 679
 680         if (get_insn_opcode(regs, &opcode))
 681                 return;
 682
 683         /* Immediate versions don't provide a code.  */
 684         if (!(opcode & OPCODE))
 685                 tcode = ((opcode >> 6) & ((1 << 10) - 1));
 686
 687         /*
 688          * (A short test says that IRIX 5.3 sends SIGTRAP for all trap
 689          * insns, even for trap codes that indicate arithmetic failures.
 690          * Weird ...)
 691          * But should we continue the brokenness???  --macro
 692          */
 693         switch (tcode) {
 694         case BRK_OVERFLOW:
 695         case BRK_DIVZERO:
 696                 if (tcode == BRK_DIVZERO)
 697                         info.si_code = FPE_INTDIV;
 698                 else
 699                         info.si_code = FPE_INTOVF;
 700                 info.si_signo = SIGFPE;
 701                 info.si_errno = 0;
 702                 info.si_addr = (void __user *) regs->cp0_epc;
 703                 force_sig_info(SIGFPE, &info, current);
 704                 break;
 705         default:
 706                 force_sig(SIGTRAP, current);
 707         }
 708 }
 709
 710 asmlinkage void do_ri(struct pt_regs *regs)
 711 {
 712         die_if_kernel("Reserved instruction in kernel code", regs);
 713
 714         if (!cpu_has_llsc)
 715                 if (!simulate_llsc(regs))
 716                         return;
 717
 718         if (!simulate_rdhwr(regs))
 719                 return;
 720
 721         force_sig(SIGILL, current);
 722 }
 723
 724 asmlinkage void do_cpu(struct pt_regs *regs)
 725 {
 726         unsigned int cpid;
 727
 728         die_if_kernel("do_cpu invoked from kernel context!", regs);
 729
 730         cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
 731
 732         switch (cpid) {
 733         case 0:
 734                 if (!cpu_has_llsc)
 735                         if (!simulate_llsc(regs))
 736                                 return;
 737
 738                 if (!simulate_rdhwr(regs))
 739                         return;
 740
 741                 break;
 742
 743         case 1:
 744                 preempt_disable();
 745
 746                 own_fpu();
 747                 if (used_math()) {      /* Using the FPU again.  */
 748                         restore_fp(current);
 749                 } else {                        /* First time FPU user.  */
 750                         init_fpu();
 751                         set_used_math();
 752                 }
 753
 754                 preempt_enable();
 755
 756                 if (!cpu_has_fpu) {
 757                         int sig = fpu_emulator_cop1Handler(regs,
 758                                                 &current->thread.fpu);
 759                         if (sig)
 760                                 force_sig(sig, current);
 761 #ifdef CONFIG_MIPS_MT_FPAFF
 762                         else {
 763                         /*
 764                          * MIPS MT processors may have fewer FPU contexts
 765                          * than CPU threads. If we've emulated more than
 766                          * some threshold number of instructions, force
 767                          * migration to a "CPU" that has FP support.
 768                          */
 769                          if(mt_fpemul_threshold > 0
 770                          && ((current->thread.emulated_fp++
 771                             > mt_fpemul_threshold))) {
 772                           /*
 773                            * If there's no FPU present, or if the
 774                            * application has already restricted
 775                            * the allowed set to exclude any CPUs
 776                            * with FPUs, we'll skip the procedure.
 777                            */
 778                           if (cpus_intersects(current->cpus_allowed,
 779                                                 mt_fpu_cpumask)) {
 780                             cpumask_t tmask;
 781
 782                             cpus_and(tmask,
 783                                         current->thread.user_cpus_allowed,
 784                                         mt_fpu_cpumask);
 785                             set_cpus_allowed(current, tmask);
 786                             current->thread.mflags |= MF_FPUBOUND;
 787                           }
 788                          }
 789                         }
 790 #endif /* CONFIG_MIPS_MT_FPAFF */
 791                 }
 792
 793                 return;
 794
 795         case 2:
 796         case 3:
 797                 die_if_kernel("do_cpu invoked from kernel context!", regs);
 798                 break;
 799         }
 800
 801         force_sig(SIGILL, current);
 802 }
 803
 804 asmlinkage void do_mdmx(struct pt_regs *regs)
 805 {
 806         force_sig(SIGILL, current);
 807 }
 808
 809 asmlinkage void do_watch(struct pt_regs *regs)
 810 {
 811         /*
 812          * We use the watch exception where available to detect stack
 813          * overflows.
 814          */
 815         dump_tlb_all();
 816         show_regs(regs);
 817         panic("Caught WATCH exception - probably caused by stack overflow.");
 818 }
 819
 820 asmlinkage void do_mcheck(struct pt_regs *regs)
 821 {
 822         const int field = 2 * sizeof(unsigned long);
 823         int multi_match = regs->cp0_status & ST0_TS;
 824
 825         show_regs(regs);
 826
 827         if (multi_match) {
 828                 printk("Index   : %0x\n", read_c0_index());
 829                 printk("Pagemask: %0x\n", read_c0_pagemask());
 830                 printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
 831                 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
 832                 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
 833                 printk("\n");
 834                 dump_tlb_all();
 835         }
 836
 837         show_code((unsigned int *) regs->cp0_epc);
 838
 839         /*
 840          * Some chips may have other causes of machine check (e.g. SB1
 841          * graduation timer)
 842          */
 843         panic("Caught Machine Check exception - %scaused by multiple "
 844               "matching entries in the TLB.",
 845               (multi_match) ? "" : "not ");
 846 }
 847
 848 asmlinkage void do_mt(struct pt_regs *regs)
 849 {
 850         int subcode;
 851
 852         subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
 853                         >> VPECONTROL_EXCPT_SHIFT;
 854         switch (subcode) {
 855         case 0:
 856                 printk(KERN_DEBUG "Thread Underflow\n");
 857                 break;
 858         case 1:
 859                 printk(KERN_DEBUG "Thread Overflow\n");
 860                 break;
 861         case 2:
 862                 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
 863                 break;
 864         case 3:
 865                 printk(KERN_DEBUG "Gating Storage Exception\n");
 866                 break;
 867         case 4:
 868                 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
 869                 break;
 870         case 5:
 871                 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n");
 872                 break;
 873         default:
 874                 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
 875                         subcode);
 876                 break;
 877         }
 878         die_if_kernel("MIPS MT Thread exception in kernel", regs);
 879
 880         force_sig(SIGILL, current);
 881 }
 882
 883
 884 asmlinkage void do_dsp(struct pt_regs *regs)
 885 {
 886         if (cpu_has_dsp)
 887                 panic("Unexpected DSP exception\n");
 888
 889         force_sig(SIGILL, current);
 890 }
 891
 892 asmlinkage void do_reserved(struct pt_regs *regs)
 893 {
 894         /*
 895          * Game over - no way to handle this if it ever occurs.  Most probably
 896          * caused by a new unknown cpu type or after another deadly
 897          * hard/software error.
 898          */
 899         show_regs(regs);
 900         panic("Caught reserved exception %ld - should not happen.",
 901               (regs->cp0_cause & 0x7f) >> 2);
 902 }
 903
 904 asmlinkage void do_default_vi(struct pt_regs *regs)
 905 {
 906         show_regs(regs);
 907         panic("Caught unexpected vectored interrupt.");
 908 }
 909
 910 /*
 911  * Some MIPS CPUs can enable/disable for cache parity detection, but do
 912  * it different ways.
 913  */
 914 static inline void parity_protection_init(void)
 915 {
 916         switch (current_cpu_data.cputype) {
 917         case CPU_24K:
 918         case CPU_34K:
 919         case CPU_5KC:
 920                 write_c0_ecc(0x80000000);
 921                 back_to_back_c0_hazard();
 922                 /* Set the PE bit (bit 31) in the c0_errctl register. */
 923                 printk(KERN_INFO "Cache parity protection %sabled\n",
 924                        (read_c0_ecc() & 0x80000000) ? "en" : "dis");
 925                 break;
 926         case CPU_20KC:
 927         case CPU_25KF:
 928                 /* Clear the DE bit (bit 16) in the c0_status register. */
 929                 printk(KERN_INFO "Enable cache parity protection for "
 930                        "MIPS 20KC/25KF CPUs.\n");
 931                 clear_c0_status(ST0_DE);
 932                 break;
 933         default:
 934                 break;
 935         }
 936 }
 937
 938 asmlinkage void cache_parity_error(void)
 939 {
 940         const int field = 2 * sizeof(unsigned long);
 941         unsigned int reg_val;
 942
 943         /* For the moment, report the problem and hang. */
 944         printk("Cache error exception:\n");
 945         printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
 946         reg_val = read_c0_cacheerr();
 947         printk("c0_cacheerr == %08x\n", reg_val);
 948
 949         printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
 950                reg_val & (1<<30) ? "secondary" : "primary",
 951                reg_val & (1<<31) ? "data" : "insn");
 952         printk("Error bits: %s%s%s%s%s%s%s\n",
 953                reg_val & (1<<29) ? "ED " : "",
 954                reg_val & (1<<28) ? "ET " : "",
 955                reg_val & (1<<26) ? "EE " : "",
 956                reg_val & (1<<25) ? "EB " : "",
 957                reg_val & (1<<24) ? "EI " : "",
 958                reg_val & (1<<23) ? "E1 " : "",
 959                reg_val & (1<<22) ? "E0 " : "");
 960         printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
 961
 962 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
 963         if (reg_val & (1<<22))
 964                 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
 965
 966         if (reg_val & (1<<23))
 967                 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
 968 #endif
 969
 970         panic("Can't handle the cache error!");
 971 }
 972
 973 /*
 974  * SDBBP EJTAG debug exception handler.
 975  * We skip the instruction and return to the next instruction.
 976  */
 977 void ejtag_exception_handler(struct pt_regs *regs)
 978 {
 979         const int field = 2 * sizeof(unsigned long);
 980         unsigned long depc, old_epc;
 981         unsigned int debug;
 982
 983         printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
 984         depc = read_c0_depc();
 985         debug = read_c0_debug();
 986         printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
 987         if (debug & 0x80000000) {
 988                 /*
 989                  * In branch delay slot.
 990                  * We cheat a little bit here and use EPC to calculate the
 991                  * debug return address (DEPC). EPC is restored after the
 992                  * calculation.
 993                  */
 994                 old_epc = regs->cp0_epc;
 995                 regs->cp0_epc = depc;
 996                 __compute_return_epc(regs);
 997                 depc = regs->cp0_epc;
 998                 regs->cp0_epc = old_epc;
 999         } else
1000                 depc += 4;
1001         write_c0_depc(depc);
1002
1003 #if 0
1004         printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1005         write_c0_debug(debug | 0x100);
1006 #endif
1007 }
1008
1009 /*
1010  * NMI exception handler.
1011  */
1012 void nmi_exception_handler(struct pt_regs *regs)
1013 {
1014 #ifdef CONFIG_MIPS_MT_SMTC
1015         unsigned long dvpret = dvpe();
1016         bust_spinlocks(1);
1017         printk("NMI taken!!!!\n");
1018         mips_mt_regdump(dvpret);
1019 #else
1020         bust_spinlocks(1);
1021         printk("NMI taken!!!!\n");
1022 #endif /* CONFIG_MIPS_MT_SMTC */
1023         die("NMI", regs);
1024         while(1) ;
1025 }
1026
1027 #define VECTORSPACING 0x100     /* for EI/VI mode */
1028
1029 unsigned long ebase;
1030 unsigned long exception_handlers[32];
1031 unsigned long vi_handlers[64];
1032
1033 /*
1034  * As a side effect of the way this is implemented we're limited
1035  * to interrupt handlers in the address range from
1036  * KSEG0 <= x < KSEG0 + 256mb on the Nevada.  Oh well ...
1037  */
1038 void *set_except_vector(int n, void *addr)
1039 {
1040         unsigned long handler = (unsigned long) addr;
1041         unsigned long old_handler = exception_handlers[n];
1042
1043         exception_handlers[n] = handler;
1044         if (n == 0 && cpu_has_divec) {
1045                 *(volatile u32 *)(ebase + 0x200) = 0x08000000 |
1046                                                  (0x03ffffff & (handler >> 2));
1047                 flush_icache_range(ebase + 0x200, ebase + 0x204);
1048         }
1049         return (void *)old_handler;
1050 }
1051
1052 #ifdef CONFIG_CPU_MIPSR2_SRS
1053 /*
1054  * MIPSR2 shadow register set allocation
1055  * FIXME: SMP...
1056  */
1057
1058 static struct shadow_registers {
1059         /*
1060          * Number of shadow register sets supported
1061          */
1062         unsigned long sr_supported;
1063         /*
1064          * Bitmap of allocated shadow registers
1065          */
1066         unsigned long sr_allocated;
1067 } shadow_registers;
1068
1069 static void mips_srs_init(void)
1070 {
1071         shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1072         printk(KERN_INFO "%d MIPSR2 register sets available\n",
1073                shadow_registers.sr_supported);
1074         shadow_registers.sr_allocated = 1;      /* Set 0 used by kernel */
1075 }
1076
1077 int mips_srs_max(void)
1078 {
1079         return shadow_registers.sr_supported;
1080 }
1081
1082 int mips_srs_alloc(void)
1083 {
1084         struct shadow_registers *sr = &shadow_registers;
1085         int set;
1086
1087 again:
1088         set = find_first_zero_bit(&sr->sr_allocated, sr->sr_supported);
1089         if (set >= sr->sr_supported)
1090                 return -1;
1091
1092         if (test_and_set_bit(set, &sr->sr_allocated))
1093                 goto again;
1094
1095         return set;
1096 }
1097
1098 void mips_srs_free(int set)
1099 {
1100         struct shadow_registers *sr = &shadow_registers;
1101
1102         clear_bit(set, &sr->sr_allocated);
1103 }
1104
1105 static void *set_vi_srs_handler(int n, void *addr, int srs)
1106 {
1107         unsigned long handler;
1108         unsigned long old_handler = vi_handlers[n];
1109         u32 *w;
1110         unsigned char *b;
1111
1112         if (!cpu_has_veic && !cpu_has_vint)
1113                 BUG();
1114
1115         if (addr == NULL) {
1116                 handler = (unsigned long) do_default_vi;
1117                 srs = 0;
1118         } else
1119                 handler = (unsigned long) addr;
1120         vi_handlers[n] = (unsigned long) addr;
1121
1122         b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1123
1124         if (srs >= mips_srs_max())
1125                 panic("Shadow register set %d not supported", srs);
1126
1127         if (cpu_has_veic) {
1128                 if (board_bind_eic_interrupt)
1129                         board_bind_eic_interrupt (n, srs);
1130         } else if (cpu_has_vint) {
1131                 /* SRSMap is only defined if shadow sets are implemented */
1132                 if (mips_srs_max() > 1)
1133                         change_c0_srsmap (0xf << n*4, srs << n*4);
1134         }
1135
1136         if (srs == 0) {
1137                 /*
1138                  * If no shadow set is selected then use the default handler
1139                  * that does normal register saving and a standard interrupt exit
1140                  */
1141
1142                 extern char except_vec_vi, except_vec_vi_lui;
1143                 extern char except_vec_vi_ori, except_vec_vi_end;
1144 #ifdef CONFIG_MIPS_MT_SMTC
1145                 /*
1146                  * We need to provide the SMTC vectored interrupt handler
1147                  * not only with the address of the handler, but with the
1148                  * Status.IM bit to be masked before going there.
1149                  */
1150                 extern char except_vec_vi_mori;
1151                 const int mori_offset = &except_vec_vi_mori - &except_vec_vi;
1152 #endif /* CONFIG_MIPS_MT_SMTC */
1153                 const int handler_len = &except_vec_vi_end - &except_vec_vi;
1154                 const int lui_offset = &except_vec_vi_lui - &except_vec_vi;
1155                 const int ori_offset = &except_vec_vi_ori - &except_vec_vi;
1156
1157                 if (handler_len > VECTORSPACING) {
1158                         /*
1159                          * Sigh... panicing won't help as the console
1160                          * is probably not configured :(
1161                          */
1162                         panic ("VECTORSPACING too small");
1163                 }
1164
1165                 memcpy (b, &except_vec_vi, handler_len);
1166 #ifdef CONFIG_MIPS_MT_SMTC
1167                 if (n > 7)
1168                         printk("Vector index %d exceeds SMTC maximum\n", n);
1169                 w = (u32 *)(b + mori_offset);
1170                 *w = (*w & 0xffff0000) | (0x100 << n);
1171 #endif /* CONFIG_MIPS_MT_SMTC */
1172                 w = (u32 *)(b + lui_offset);
1173                 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
1174                 w = (u32 *)(b + ori_offset);
1175                 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
1176                 flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len));
1177         }
1178         else {
1179                 /*
1180                  * In other cases jump directly to the interrupt handler
1181                  *
1182                  * It is the handlers responsibility to save registers if required
1183                  * (eg hi/lo) and return from the exception using "eret"
1184                  */
1185                 w = (u32 *)b;
1186                 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */
1187                 *w = 0;
1188                 flush_icache_range((unsigned long)b, (unsigned long)(b+8));
1189         }
1190
1191         return (void *)old_handler;
1192 }
1193
1194 void *set_vi_handler(int n, void *addr)
1195 {
1196         return set_vi_srs_handler(n, addr, 0);
1197 }
1198
1199 #else
1200
1201 static inline void mips_srs_init(void)
1202 {
1203 }
1204
1205 #endif /* CONFIG_CPU_MIPSR2_SRS */
1206
1207 /*
1208  * This is used by native signal handling
1209  */
1210 asmlinkage int (*save_fp_context)(struct sigcontext *sc);
1211 asmlinkage int (*restore_fp_context)(struct sigcontext *sc);
1212
1213 extern asmlinkage int _save_fp_context(struct sigcontext *sc);
1214 extern asmlinkage int _restore_fp_context(struct sigcontext *sc);
1215
1216 extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc);
1217 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc);
1218
1219 #ifdef CONFIG_SMP
1220 static int smp_save_fp_context(struct sigcontext *sc)
1221 {
1222         return cpu_has_fpu
1223                ? _save_fp_context(sc)
1224                : fpu_emulator_save_context(sc);
1225 }
1226
1227 static int smp_restore_fp_context(struct sigcontext *sc)
1228 {
1229         return cpu_has_fpu
1230                ? _restore_fp_context(sc)
1231                : fpu_emulator_restore_context(sc);
1232 }
1233 #endif
1234
1235 static inline void signal_init(void)
1236 {
1237 #ifdef CONFIG_SMP
1238         /* For now just do the cpu_has_fpu check when the functions are invoked */
1239         save_fp_context = smp_save_fp_context;
1240         restore_fp_context = smp_restore_fp_context;
1241 #else
1242         if (cpu_has_fpu) {
1243                 save_fp_context = _save_fp_context;
1244                 restore_fp_context = _restore_fp_context;
1245         } else {
1246                 save_fp_context = fpu_emulator_save_context;
1247                 restore_fp_context = fpu_emulator_restore_context;
1248         }
1249 #endif
1250 }
1251
1252 #ifdef CONFIG_MIPS32_COMPAT
1253
1254 /*
1255  * This is used by 32-bit signal stuff on the 64-bit kernel
1256  */
1257 asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc);
1258 asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc);
1259
1260 extern asmlinkage int _save_fp_context32(struct sigcontext32 *sc);
1261 extern asmlinkage int _restore_fp_context32(struct sigcontext32 *sc);
1262
1263 extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 *sc);
1264 extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 *sc);
1265
1266 static inline void signal32_init(void)
1267 {
1268         if (cpu_has_fpu) {
1269                 save_fp_context32 = _save_fp_context32;
1270                 restore_fp_context32 = _restore_fp_context32;
1271         } else {
1272                 save_fp_context32 = fpu_emulator_save_context32;
1273                 restore_fp_context32 = fpu_emulator_restore_context32;
1274         }
1275 }
1276 #endif
1277
1278 extern void cpu_cache_init(void);
1279 extern void tlb_init(void);
1280 extern void flush_tlb_handlers(void);
1281
1282 void __init per_cpu_trap_init(void)
1283 {
1284         unsigned int cpu = smp_processor_id();
1285         unsigned int status_set = ST0_CU0;
1286 #ifdef CONFIG_MIPS_MT_SMTC
1287         int secondaryTC = 0;
1288         int bootTC = (cpu == 0);
1289
1290         /*
1291          * Only do per_cpu_trap_init() for first TC of Each VPE.
1292          * Note that this hack assumes that the SMTC init code
1293          * assigns TCs consecutively and in ascending order.
1294          */
1295
1296         if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
1297             ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
1298                 secondaryTC = 1;
1299 #endif /* CONFIG_MIPS_MT_SMTC */
1300
1301         /*
1302          * Disable coprocessors and select 32-bit or 64-bit addressing
1303          * and the 16/32 or 32/32 FPR register model.  Reset the BEV
1304          * flag that some firmware may have left set and the TS bit (for
1305          * IP27).  Set XX for ISA IV code to work.
1306          */
1307 #ifdef CONFIG_64BIT
1308         status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1309 #endif
1310         if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
1311                 status_set |= ST0_XX;
1312         change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1313                          status_set);
1314
1315         if (cpu_has_dsp)
1316                 set_c0_status(ST0_MX);
1317
1318 #ifdef CONFIG_CPU_MIPSR2
1319         write_c0_hwrena (0x0000000f); /* Allow rdhwr to all registers */
1320 #endif
1321
1322 #ifdef CONFIG_MIPS_MT_SMTC
1323         if (!secondaryTC) {
1324 #endif /* CONFIG_MIPS_MT_SMTC */
1325
1326         /*
1327          * Interrupt handling.
1328          */
1329         if (cpu_has_veic || cpu_has_vint) {
1330                 write_c0_ebase (ebase);
1331                 /* Setting vector spacing enables EI/VI mode  */
1332                 change_c0_intctl (0x3e0, VECTORSPACING);
1333         }
1334         if (cpu_has_divec) {
1335                 if (cpu_has_mipsmt) {
1336                         unsigned int vpflags = dvpe();
1337                         set_c0_cause(CAUSEF_IV);
1338                         evpe(vpflags);
1339                 } else
1340                         set_c0_cause(CAUSEF_IV);
1341         }
1342 #ifdef CONFIG_MIPS_MT_SMTC
1343         }
1344 #endif /* CONFIG_MIPS_MT_SMTC */
1345
1346         cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1347         TLBMISS_HANDLER_SETUP();
1348
1349         atomic_inc(&init_mm.mm_count);
1350         current->active_mm = &init_mm;
1351         BUG_ON(current->mm);
1352         enter_lazy_tlb(&init_mm, current);
1353
1354 #ifdef CONFIG_MIPS_MT_SMTC
1355         if (bootTC) {
1356 #endif /* CONFIG_MIPS_MT_SMTC */
1357                 cpu_cache_init();
1358                 tlb_init();
1359 #ifdef CONFIG_MIPS_MT_SMTC
1360         }
1361 #endif /* CONFIG_MIPS_MT_SMTC */
1362 }
1363
1364 /* Install CPU exception handler */
1365 void __init set_handler (unsigned long offset, void *addr, unsigned long size)
1366 {
1367         memcpy((void *)(ebase + offset), addr, size);
1368         flush_icache_range(ebase + offset, ebase + offset + size);
1369 }
1370
1371 /* Install uncached CPU exception handler */
1372 void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size)
1373 {
1374 #ifdef CONFIG_32BIT
1375         unsigned long uncached_ebase = KSEG1ADDR(ebase);
1376 #endif
1377 #ifdef CONFIG_64BIT
1378         unsigned long uncached_ebase = TO_UNCAC(ebase);
1379 #endif
1380
1381         memcpy((void *)(uncached_ebase + offset), addr, size);
1382 }
1383
1384 void __init trap_init(void)
1385 {
1386         extern char except_vec3_generic, except_vec3_r4000;
1387         extern char except_vec4;
1388         unsigned long i;
1389
1390         if (cpu_has_veic || cpu_has_vint)
1391                 ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64);
1392         else
1393                 ebase = CAC_BASE;
1394
1395         mips_srs_init();
1396
1397         per_cpu_trap_init();
1398
1399         /*
1400          * Copy the generic exception handlers to their final destination.
1401          * This will be overriden later as suitable for a particular
1402          * configuration.
1403          */
1404         set_handler(0x180, &except_vec3_generic, 0x80);
1405
1406         /*
1407          * Setup default vectors
1408          */
1409         for (i = 0; i <= 31; i++)
1410                 set_except_vector(i, handle_reserved);
1411
1412         /*
1413          * Copy the EJTAG debug exception vector handler code to it's final
1414          * destination.
1415          */
1416         if (cpu_has_ejtag && board_ejtag_handler_setup)
1417                 board_ejtag_handler_setup ();
1418
1419         /*
1420          * Only some CPUs have the watch exceptions.
1421          */
1422         if (cpu_has_watch)
1423                 set_except_vector(23, handle_watch);
1424
1425         /*
1426          * Initialise interrupt handlers
1427          */
1428         if (cpu_has_veic || cpu_has_vint) {
1429                 int nvec = cpu_has_veic ? 64 : 8;
1430                 for (i = 0; i < nvec; i++)
1431                         set_vi_handler(i, NULL);
1432         }
1433         else if (cpu_has_divec)
1434                 set_handler(0x200, &except_vec4, 0x8);
1435
1436         /*
1437          * Some CPUs can enable/disable for cache parity detection, but does
1438          * it different ways.
1439          */
1440         parity_protection_init();
1441
1442         /*
1443          * The Data Bus Errors / Instruction Bus Errors are signaled
1444          * by external hardware.  Therefore these two exceptions
1445          * may have board specific handlers.
1446          */
1447         if (board_be_init)
1448                 board_be_init();
1449
1450         set_except_vector(0, handle_int);
1451         set_except_vector(1, handle_tlbm);
1452         set_except_vector(2, handle_tlbl);
1453         set_except_vector(3, handle_tlbs);
1454
1455         set_except_vector(4, handle_adel);
1456         set_except_vector(5, handle_ades);
1457
1458         set_except_vector(6, handle_ibe);
1459         set_except_vector(7, handle_dbe);
1460
1461         set_except_vector(8, handle_sys);
1462         set_except_vector(9, handle_bp);
1463         set_except_vector(10, handle_ri);
1464         set_except_vector(11, handle_cpu);
1465         set_except_vector(12, handle_ov);
1466         set_except_vector(13, handle_tr);
1467
1468         if (current_cpu_data.cputype == CPU_R6000 ||
1469             current_cpu_data.cputype == CPU_R6000A) {
1470                 /*
1471                  * The R6000 is the only R-series CPU that features a machine
1472                  * check exception (similar to the R4000 cache error) and
1473                  * unaligned ldc1/sdc1 exception.  The handlers have not been
1474                  * written yet.  Well, anyway there is no R6000 machine on the
1475                  * current list of targets for Linux/MIPS.
1476                  * (Duh, crap, there is someone with a triple R6k machine)
1477                  */
1478                 //set_except_vector(14, handle_mc);
1479                 //set_except_vector(15, handle_ndc);
1480         }
1481
1482
1483         if (board_nmi_handler_setup)
1484                 board_nmi_handler_setup();
1485
1486         if (cpu_has_fpu && !cpu_has_nofpuex)
1487                 set_except_vector(15, handle_fpe);
1488
1489         set_except_vector(22, handle_mdmx);
1490
1491         if (cpu_has_mcheck)
1492                 set_except_vector(24, handle_mcheck);
1493
1494         if (cpu_has_mipsmt)
1495                 set_except_vector(25, handle_mt);
1496
1497         if (cpu_has_dsp)
1498                 set_except_vector(26, handle_dsp);
1499
1500         if (cpu_has_vce)
1501                 /* Special exception: R4[04]00 uses also the divec space. */
1502                 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
1503         else if (cpu_has_4kex)
1504                 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
1505         else
1506                 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
1507
1508         signal_init();
1509 #ifdef CONFIG_MIPS32_COMPAT
1510         signal32_init();
1511 #endif
1512
1513         flush_icache_range(ebase, ebase + 0x400);
1514         flush_tlb_handlers();
1515 }