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[PATCH] briq_panel: read() and write() get __user pointers, damnit
[linux-2.6/verdex.git] / arch / mips / momentum / jaguar_atx / setup.c
blobe6fe2992227d7b728fc7fcbaad2734444ad18dc9
1 /*
2 * BRIEF MODULE DESCRIPTION
3 * Momentum Computer Jaguar-ATX board dependent boot routines
4 *
5 * Copyright (C) 1996, 1997, 2001, 04, 06 Ralf Baechle (ralf@linux-mips.org)
6 * Copyright (C) 2000 RidgeRun, Inc.
7 * Copyright (C) 2001 Red Hat, Inc.
8 * Copyright (C) 2002 Momentum Computer
9 *
10 * Author: Matthew Dharm, Momentum Computer
11 * mdharm@momenco.com
12 *
13 * Louis Hamilton, Red Hat, Inc.
14 * hamilton@redhat.com [MIPS64 modifications]
15 *
16 * Author: RidgeRun, Inc.
17 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
18 *
19 * Copyright 2001 MontaVista Software Inc.
20 * Author: jsun@mvista.com or jsun@junsun.net
21 *
22 * This program is free software; you can redistribute it and/or modify it
23 * under the terms of the GNU General Public License as published by the
24 * Free Software Foundation; either version 2 of the License, or (at your
25 * option) any later version.
26 *
27 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
28 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
29 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
30 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
31 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
32 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
33 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
34 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
36 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 *
38 * You should have received a copy of the GNU General Public License along
39 * with this program; if not, write to the Free Software Foundation, Inc.,
40 * 675 Mass Ave, Cambridge, MA 02139, USA.
41 */
42 #include <linux/bcd.h>
43 #include <linux/init.h>
44 #include <linux/kernel.h>
45 #include <linux/types.h>
46 #include <linux/mm.h>
47 #include <linux/bootmem.h>
48 #include <linux/module.h>
49 #include <linux/pci.h>
50 #include <linux/swap.h>
51 #include <linux/ioport.h>
52 #include <linux/pm.h>
53 #include <linux/sched.h>
54 #include <linux/interrupt.h>
55 #include <linux/timex.h>
56 #include <linux/vmalloc.h>
57 #include <linux/mv643xx.h>
58
59 #include <asm/time.h>
60 #include <asm/bootinfo.h>
61 #include <asm/page.h>
62 #include <asm/io.h>
63 #include <asm/irq.h>
64 #include <asm/processor.h>
65 #include <asm/ptrace.h>
66 #include <asm/reboot.h>
67 #include <asm/tlbflush.h>
68
69 #include "jaguar_atx_fpga.h"
70
71 extern unsigned long mv64340_sram_base;
72 unsigned long cpu_clock;
73
74 /* These functions are used for rebooting or halting the machine*/
75 extern void momenco_jaguar_restart(char *command);
76 extern void momenco_jaguar_halt(void);
77 extern void momenco_jaguar_power_off(void);
78
79 void momenco_time_init(void);
80
81 static char reset_reason;
82
83 static inline unsigned long ENTRYLO(unsigned long paddr)
84 {
85 return ((paddr & PAGE_MASK) |
86 (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL |
87 _CACHE_UNCACHED)) >> 6;
88 }
89
90 void __init bus_error_init(void) { /* nothing */ }
91
92 /*
93 * Load a few TLB entries for the MV64340 and perhiperals. The MV64340 is going
94 * to be hit on every IRQ anyway - there's absolutely no point in letting it be
95 * a random TLB entry, as it'll just cause needless churning of the TLB. And we
96 * use the other half for the serial port, which is just a PITA otherwise :)
97 *
98 * Device Physical Virtual
99 * MV64340 Internal Regs 0xf4000000 0xf4000000
100 * Ocelot-C[S] PLD (CS0) 0xfc000000 0xfc000000
101 * NVRAM (CS1) 0xfc800000 0xfc800000
102 * UARTs (CS2) 0xfd000000 0xfd000000
103 * Internal SRAM 0xfe000000 0xfe000000
104 * M-Systems DOC (CS3) 0xff000000 0xff000000
105 */
106
107 static __init void wire_stupidity_into_tlb(void)
108 {
109 #ifdef CONFIG_32BIT
110 write_c0_wired(0);
111 local_flush_tlb_all();
112
113 /* marvell and extra space */
114 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000),
115 0xf4000000UL, PM_64K);
116 /* fpga, rtc, and uart */
117 add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000),
118 0xfc000000UL, PM_16M);
119 // /* m-sys and internal SRAM */
120 // add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000),
121 // 0xfe000000UL, PM_16M);
122
123 marvell_base = 0xf4000000;
124 //mv64340_sram_base = 0xfe000000; /* Currently unused */
125 #endif
126 }
127
128 unsigned long marvell_base = 0xf4000000L;
129 unsigned long ja_fpga_base = JAGUAR_ATX_CS0_ADDR;
130 unsigned long uart_base = 0xfd000000L;
131 static unsigned char *rtc_base = (unsigned char*) 0xfc800000L;
132
133 EXPORT_SYMBOL(marvell_base);
134
135 static __init int per_cpu_mappings(void)
136 {
137 marvell_base = (unsigned long) ioremap(0xf4000000, 0x10000);
138 ja_fpga_base = (unsigned long) ioremap(JAGUAR_ATX_CS0_ADDR, 0x1000);
139 uart_base = (unsigned long) ioremap(0xfd000000UL, 0x1000);
140 rtc_base = ioremap(0xfc000000UL, 0x8000);
141 // ioremap(0xfe000000, 32 << 20);
142 write_c0_wired(0);
143 local_flush_tlb_all();
144 ja_setup_console();
145
146 return 0;
147 }
148 arch_initcall(per_cpu_mappings);
149
150 unsigned long m48t37y_get_time(void)
151 {
152 unsigned int year, month, day, hour, min, sec;
153 unsigned long flags;
154
155 spin_lock_irqsave(&rtc_lock, flags);
156 /* stop the update */
157 rtc_base[0x7ff8] = 0x40;
158
159 year = BCD2BIN(rtc_base[0x7fff]);
160 year += BCD2BIN(rtc_base[0x7ff1]) * 100;
161
162 month = BCD2BIN(rtc_base[0x7ffe]);
163
164 day = BCD2BIN(rtc_base[0x7ffd]);
165
166 hour = BCD2BIN(rtc_base[0x7ffb]);
167 min = BCD2BIN(rtc_base[0x7ffa]);
168 sec = BCD2BIN(rtc_base[0x7ff9]);
169
170 /* start the update */
171 rtc_base[0x7ff8] = 0x00;
172 spin_unlock_irqrestore(&rtc_lock, flags);
173
174 return mktime(year, month, day, hour, min, sec);
175 }
176
177 int m48t37y_set_time(unsigned long sec)
178 {
179 struct rtc_time tm;
180 unsigned long flags;
181
182 /* convert to a more useful format -- note months count from 0 */
183 to_tm(sec, &tm);
184 tm.tm_mon += 1;
185
186 spin_lock_irqsave(&rtc_lock, flags);
187 /* enable writing */
188 rtc_base[0x7ff8] = 0x80;
189
190 /* year */
191 rtc_base[0x7fff] = BIN2BCD(tm.tm_year % 100);
192 rtc_base[0x7ff1] = BIN2BCD(tm.tm_year / 100);
193
194 /* month */
195 rtc_base[0x7ffe] = BIN2BCD(tm.tm_mon);
196
197 /* day */
198 rtc_base[0x7ffd] = BIN2BCD(tm.tm_mday);
199
200 /* hour/min/sec */
201 rtc_base[0x7ffb] = BIN2BCD(tm.tm_hour);
202 rtc_base[0x7ffa] = BIN2BCD(tm.tm_min);
203 rtc_base[0x7ff9] = BIN2BCD(tm.tm_sec);
204
205 /* day of week -- not really used, but let's keep it up-to-date */
206 rtc_base[0x7ffc] = BIN2BCD(tm.tm_wday + 1);
207
208 /* disable writing */
209 rtc_base[0x7ff8] = 0x00;
210 spin_unlock_irqrestore(&rtc_lock, flags);
211
212 return 0;
213 }
214
215 void __init plat_timer_setup(struct irqaction *irq)
216 {
217 setup_irq(8, irq);
218 }
219
220 /*
221 * Ugly but the least of all evils. TLB initialization did flush the TLB so
222 * We need to setup mappings again before we can touch the RTC.
223 */
224 void momenco_time_init(void)
225 {
226 wire_stupidity_into_tlb();
227
228 mips_hpt_frequency = cpu_clock / 2;
229
230 rtc_mips_get_time = m48t37y_get_time;
231 rtc_mips_set_time = m48t37y_set_time;
232 }
233
234 static struct resource mv_pci_io_mem0_resource = {
235 .name = "MV64340 PCI0 IO MEM",
236 .flags = IORESOURCE_IO
237 };
238
239 static struct resource mv_pci_mem0_resource = {
240 .name = "MV64340 PCI0 MEM",
241 .flags = IORESOURCE_MEM
242 };
243
244 static struct mv_pci_controller mv_bus0_controller = {
245 .pcic = {
246 .pci_ops = &mv_pci_ops,
247 .mem_resource = &mv_pci_mem0_resource,
248 .io_resource = &mv_pci_io_mem0_resource,
249 },
250 .config_addr = MV64340_PCI_0_CONFIG_ADDR,
251 .config_vreg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG,
252 };
253
254 static uint32_t mv_io_base, mv_io_size;
255
256 static void ja_pci0_init(void)
257 {
258 uint32_t mem0_base, mem0_size;
259 uint32_t io_base, io_size;
260
261 io_base = MV_READ(MV64340_PCI_0_IO_BASE_ADDR) << 16;
262 io_size = (MV_READ(MV64340_PCI_0_IO_SIZE) + 1) << 16;
263 mem0_base = MV_READ(MV64340_PCI_0_MEMORY0_BASE_ADDR) << 16;
264 mem0_size = (MV_READ(MV64340_PCI_0_MEMORY0_SIZE) + 1) << 16;
265
266 mv_pci_io_mem0_resource.start = 0;
267 mv_pci_io_mem0_resource.end = io_size - 1;
268 mv_pci_mem0_resource.start = mem0_base;
269 mv_pci_mem0_resource.end = mem0_base + mem0_size - 1;
270 mv_bus0_controller.pcic.mem_offset = mem0_base;
271 mv_bus0_controller.pcic.io_offset = 0;
272
273 ioport_resource.end = io_size - 1;
274
275 register_pci_controller(&mv_bus0_controller.pcic);
276
277 mv_io_base = io_base;
278 mv_io_size = io_size;
279 }
280
281 static struct resource mv_pci_io_mem1_resource = {
282 .name = "MV64340 PCI1 IO MEM",
283 .flags = IORESOURCE_IO
284 };
285
286 static struct resource mv_pci_mem1_resource = {
287 .name = "MV64340 PCI1 MEM",
288 .flags = IORESOURCE_MEM
289 };
290
291 static struct mv_pci_controller mv_bus1_controller = {
292 .pcic = {
293 .pci_ops = &mv_pci_ops,
294 .mem_resource = &mv_pci_mem1_resource,
295 .io_resource = &mv_pci_io_mem1_resource,
296 },
297 .config_addr = MV64340_PCI_1_CONFIG_ADDR,
298 .config_vreg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG,
299 };
300
301 static __init void ja_pci1_init(void)
302 {
303 uint32_t mem0_base, mem0_size;
304 uint32_t io_base, io_size;
305
306 io_base = MV_READ(MV64340_PCI_1_IO_BASE_ADDR) << 16;
307 io_size = (MV_READ(MV64340_PCI_1_IO_SIZE) + 1) << 16;
308 mem0_base = MV_READ(MV64340_PCI_1_MEMORY0_BASE_ADDR) << 16;
309 mem0_size = (MV_READ(MV64340_PCI_1_MEMORY0_SIZE) + 1) << 16;
310
311 /*
312 * Here we assume the I/O window of second bus to be contiguous with
313 * the first. A gap is no problem but would waste address space for
314 * remapping the port space.
315 */
316 mv_pci_io_mem1_resource.start = mv_io_size;
317 mv_pci_io_mem1_resource.end = mv_io_size + io_size - 1;
318 mv_pci_mem1_resource.start = mem0_base;
319 mv_pci_mem1_resource.end = mem0_base + mem0_size - 1;
320 mv_bus1_controller.pcic.mem_offset = mem0_base;
321 mv_bus1_controller.pcic.io_offset = 0;
322
323 ioport_resource.end = io_base + io_size -mv_io_base - 1;
324
325 register_pci_controller(&mv_bus1_controller.pcic);
326
327 mv_io_size = io_base + io_size - mv_io_base;
328 }
329
330 static __init int __init ja_pci_init(void)
331 {
332 unsigned long io_v_base;
333 uint32_t enable;
334
335 enable = ~MV_READ(MV64340_BASE_ADDR_ENABLE);
336
337 /*
338 * We require at least one enabled I/O or PCI memory window or we
339 * will ignore this PCI bus. We ignore PCI windows 1, 2 and 3.
340 */
341 if (enable & (0x01 << 9) || enable & (0x01 << 10))
342 ja_pci0_init();
343
344 if (enable & (0x01 << 14) || enable & (0x01 << 15))
345 ja_pci1_init();
346
347 if (mv_io_size) {
348 io_v_base = (unsigned long) ioremap(mv_io_base, mv_io_size);
349 if (!io_v_base)
350 panic("Could not ioremap I/O port range");
351
352 set_io_port_base(io_v_base);
353 }
354
355 return 0;
356 }
357
358 arch_initcall(ja_pci_init);
359
360 void __init plat_mem_setup(void)
361 {
362 unsigned int tmpword;
363
364 board_time_init = momenco_time_init;
365
366 _machine_restart = momenco_jaguar_restart;
367 _machine_halt = momenco_jaguar_halt;
368 pm_power_off = momenco_jaguar_power_off;
369
370 /*
371 * initrd_start = (unsigned long)jaguar_initrd_start;
372 * initrd_end = (unsigned long)jaguar_initrd_start + (ulong)jaguar_initrd_size;
373 * initrd_below_start_ok = 1;
374 */
375
376 wire_stupidity_into_tlb();
377
378 /*
379 * shut down ethernet ports, just to be sure our memory doesn't get
380 * corrupted by random ethernet traffic.
381 */
382 MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
383 MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
384 MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(2), 0xff << 8);
385 MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
386 MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
387 MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0xff << 8);
388 while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
389 while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
390 while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(2)) & 0xff);
391 while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
392 while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
393 while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(2)) & 0xff);
394 MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0),
395 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
396 MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1),
397 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
398 MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(2),
399 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(2)) & ~1);
400
401 /* Turn off the Bit-Error LED */
402 JAGUAR_FPGA_WRITE(0x80, CLR);
403
404 tmpword = JAGUAR_FPGA_READ(BOARDREV);
405 if (tmpword < 26)
406 printk("Momentum Jaguar-ATX: Board Assembly Rev. %c\n",
407 'A'+tmpword);
408 else
409 printk("Momentum Jaguar-ATX: Board Assembly Revision #0x%x\n",
410 tmpword);
411
412 tmpword = JAGUAR_FPGA_READ(FPGA_REV);
413 printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15);
414 tmpword = JAGUAR_FPGA_READ(RESET_STATUS);
415 printk("Reset reason: 0x%x\n", tmpword);
416 switch (tmpword) {
417 case 0x1:
418 printk(" - Power-up reset\n");
419 break;
420 case 0x2:
421 printk(" - Push-button reset\n");
422 break;
423 case 0x8:
424 printk(" - Watchdog reset\n");
425 break;
426 case 0x10:
427 printk(" - JTAG reset\n");
428 break;
429 default:
430 printk(" - Unknown reset cause\n");
431 }
432 reset_reason = tmpword;
433 JAGUAR_FPGA_WRITE(0xff, RESET_STATUS);
434
435 tmpword = JAGUAR_FPGA_READ(BOARD_STATUS);
436 printk("Board Status register: 0x%02x\n", tmpword);
437 printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
438 printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
439
440 /* 256MiB of RM9000x2 DDR */
441 // add_memory_region(0x0, 0x100<<20, BOOT_MEM_RAM);
442
443 /* 128MiB of MV-64340 DDR */
444 // add_memory_region(0x100<<20, 0x80<<20, BOOT_MEM_RAM);
445
446 /* XXX Memory configuration should be picked up from PMON2k */
447 #ifdef CONFIG_JAGUAR_DMALOW
448 printk("Jaguar ATX DMA-low mode set\n");
449 add_memory_region(0x00000000, 0x08000000, BOOT_MEM_RAM);
450 add_memory_region(0x08000000, 0x10000000, BOOT_MEM_RAM);
451 #else
452 /* 128MiB of MV-64340 DDR RAM */
453 printk("Jaguar ATX DMA-low mode is not set\n");
454 add_memory_region(0x100<<20, 0x80<<20, BOOT_MEM_RAM);
455 #endif
456
457 #ifdef GEMDEBUG_TRACEBUFFER
458 {
459 unsigned int tbControl;
460 tbControl =
461 0 << 26 | /* post trigger delay 0 */
462 0x2 << 16 | /* sequential trace mode */
463 // 0x0 << 16 | /* non-sequential trace mode */
464 // 0xf << 4 | /* watchpoints disabled */
465 2 << 2 | /* armed */
466 2 ; /* interrupt disabled */
467 printk ("setting tbControl = %08lx\n", tbControl);
468 write_32bit_cp0_set1_register($22, tbControl);
469 __asm__ __volatile__(".set noreorder\n\t" \
470 "nop; nop; nop; nop; nop; nop;\n\t" \
471 "nop; nop; nop; nop; nop; nop;\n\t" \
472 ".set reorder\n\t");
473
474 }
475 #endif
476 }
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