| blob | d88e182e40b3849ba085ec3f83265adac690e538 |
1 /*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
11 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk).
13 *
14 * This file contains the low-level support and setup for the
15 * PowerPC platform, including trap and interrupt dispatch.
16 * (The PPC 8xx embedded CPUs use head_8xx.S instead.)
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License
20 * as published by the Free Software Foundation; either version
21 * 2 of the License, or (at your option) any later version.
22 *
23 */
25 #include <asm/reg.h>
26 #include <asm/page.h>
27 #include <asm/mmu.h>
28 #include <asm/pgtable.h>
29 #include <asm/cputable.h>
30 #include <asm/cache.h>
31 #include <asm/thread_info.h>
32 #include <asm/ppc_asm.h>
33 #include <asm/asm-offsets.h>
35 #ifdef CONFIG_APUS
36 #include <asm/amigappc.h>
37 #endif
39 /* 601 only have IBAT; cr0.eq is set on 601 when using this macro */
40 #define LOAD_BAT(n, reg, RA, RB) \
41 /* see the comment for clear_bats() -- Cort */ \
42 li RA,0; \
43 mtspr SPRN_IBAT##n##U,RA; \
44 mtspr SPRN_DBAT##n##U,RA; \
45 lwz RA,(n*16)+0(reg); \
46 lwz RB,(n*16)+4(reg); \
47 mtspr SPRN_IBAT##n##U,RA; \
48 mtspr SPRN_IBAT##n##L,RB; \
49 beq 1f; \
50 lwz RA,(n*16)+8(reg); \
51 lwz RB,(n*16)+12(reg); \
52 mtspr SPRN_DBAT##n##U,RA; \
53 mtspr SPRN_DBAT##n##L,RB; \
54 1:
56 .text
57 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
58 .stabs "head_32.S",N_SO,0,0,0f
59 0:
60 .globl _stext
61 _stext:
63 /*
64 * _start is defined this way because the XCOFF loader in the OpenFirmware
65 * on the powermac expects the entry point to be a procedure descriptor.
66 */
67 .text
68 .globl _start
69 _start:
70 /*
71 * These are here for legacy reasons, the kernel used to
72 * need to look like a coff function entry for the pmac
73 * but we're always started by some kind of bootloader now.
74 * -- Cort
75 */
76 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
77 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
78 nop
80 /* PMAC
81 * Enter here with the kernel text, data and bss loaded starting at
82 * 0, running with virtual == physical mapping.
83 * r5 points to the prom entry point (the client interface handler
84 * address). Address translation is turned on, with the prom
85 * managing the hash table. Interrupts are disabled. The stack
86 * pointer (r1) points to just below the end of the half-meg region
87 * from 0x380000 - 0x400000, which is mapped in already.
88 *
89 * If we are booted from MacOS via BootX, we enter with the kernel
90 * image loaded somewhere, and the following values in registers:
91 * r3: 'BooX' (0x426f6f58)
92 * r4: virtual address of boot_infos_t
93 * r5: 0
94 *
95 * APUS
96 * r3: 'APUS'
97 * r4: physical address of memory base
98 * Linux/m68k style BootInfo structure at &_end.
99 *
100 * PREP
101 * This is jumped to on prep systems right after the kernel is relocated
102 * to its proper place in memory by the boot loader. The expected layout
103 * of the regs is:
104 * r3: ptr to residual data
105 * r4: initrd_start or if no initrd then 0
106 * r5: initrd_end - unused if r4 is 0
107 * r6: Start of command line string
108 * r7: End of command line string
109 *
110 * This just gets a minimal mmu environment setup so we can call
111 * start_here() to do the real work.
112 * -- Cort
113 */
115 .globl __start
116 __start:
117 /*
118 * We have to do any OF calls before we map ourselves to KERNELBASE,
119 * because OF may have I/O devices mapped into that area
120 * (particularly on CHRP).
121 */
122 #ifdef CONFIG_PPC_MULTIPLATFORM
123 cmpwi 0,r5,0
124 beq 1f
125 bl prom_init
126 trap
127 #endif
129 /*
130 * Check for BootX signature when supporting PowerMac and branch to
131 * appropriate trampoline if it's present
132 */
133 #ifdef CONFIG_PPC_PMAC
134 1: lis r31,0x426f
135 ori r31,r31,0x6f58
136 cmpw 0,r3,r31
137 bne 1f
138 bl bootx_init
139 trap
140 #endif /* CONFIG_PPC_PMAC */
142 1: mr r31,r3 /* save parameters */
143 mr r30,r4
144 li r24,0 /* cpu # */
146 /*
147 * early_init() does the early machine identification and does
148 * the necessary low-level setup and clears the BSS
149 * -- Cort <cort@fsmlabs.com>
150 */
151 bl early_init
153 #ifdef CONFIG_APUS
154 /* On APUS the __va/__pa constants need to be set to the correct
155 * values before continuing.
156 */
157 mr r4,r30
158 bl fix_mem_constants
159 #endif /* CONFIG_APUS */
161 /* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains
162 * the physical address we are running at, returned by early_init()
163 */
164 bl mmu_off
165 __after_mmu_off:
166 bl clear_bats
167 bl flush_tlbs
169 bl initial_bats
170 #if !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT)
171 bl setup_disp_bat
172 #endif
174 /*
175 * Call setup_cpu for CPU 0 and initialize 6xx Idle
176 */
177 bl reloc_offset
178 li r24,0 /* cpu# */
179 bl call_setup_cpu /* Call setup_cpu for this CPU */
180 #ifdef CONFIG_6xx
181 bl reloc_offset
182 bl init_idle_6xx
183 #endif /* CONFIG_6xx */
186 #ifndef CONFIG_APUS
187 /*
188 * We need to run with _start at physical address 0.
189 * On CHRP, we are loaded at 0x10000 since OF on CHRP uses
190 * the exception vectors at 0 (and therefore this copy
191 * overwrites OF's exception vectors with our own).
192 * The MMU is off at this point.
193 */
194 bl reloc_offset
195 mr r26,r3
196 addis r4,r3,KERNELBASE@h /* current address of _start */
197 cmpwi 0,r4,0 /* are we already running at 0? */
198 bne relocate_kernel
199 #endif /* CONFIG_APUS */
200 /*
201 * we now have the 1st 16M of ram mapped with the bats.
202 * prep needs the mmu to be turned on here, but pmac already has it on.
203 * this shouldn't bother the pmac since it just gets turned on again
204 * as we jump to our code at KERNELBASE. -- Cort
205 * Actually no, pmac doesn't have it on any more. BootX enters with MMU
206 * off, and in other cases, we now turn it off before changing BATs above.
207 */
208 turn_on_mmu:
209 mfmsr r0
210 ori r0,r0,MSR_DR|MSR_IR
211 mtspr SPRN_SRR1,r0
212 lis r0,start_here@h
213 ori r0,r0,start_here@l
214 mtspr SPRN_SRR0,r0
215 SYNC
216 RFI /* enables MMU */
218 /*
219 * We need __secondary_hold as a place to hold the other cpus on
220 * an SMP machine, even when we are running a UP kernel.
221 */
222 . = 0xc0 /* for prep bootloader */
223 li r3,1 /* MTX only has 1 cpu */
224 .globl __secondary_hold
225 __secondary_hold:
226 /* tell the master we're here */
227 stw r3,__secondary_hold_acknowledge@l(0)
228 #ifdef CONFIG_SMP
229 100: lwz r4,0(0)
230 /* wait until we're told to start */
231 cmpw 0,r4,r3
232 bne 100b
233 /* our cpu # was at addr 0 - go */
234 mr r24,r3 /* cpu # */
235 b __secondary_start
236 #else
237 b .
238 #endif /* CONFIG_SMP */
240 .globl __secondary_hold_spinloop
241 __secondary_hold_spinloop:
242 .long 0
243 .globl __secondary_hold_acknowledge
244 __secondary_hold_acknowledge:
245 .long -1
247 /*
248 * Exception entry code. This code runs with address translation
249 * turned off, i.e. using physical addresses.
250 * We assume sprg3 has the physical address of the current
251 * task's thread_struct.
252 */
253 #define EXCEPTION_PROLOG \
254 mtspr SPRN_SPRG0,r10; \
255 mtspr SPRN_SPRG1,r11; \
256 mfcr r10; \
257 EXCEPTION_PROLOG_1; \
258 EXCEPTION_PROLOG_2
260 #define EXCEPTION_PROLOG_1 \
261 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
262 andi. r11,r11,MSR_PR; \
263 tophys(r11,r1); /* use tophys(r1) if kernel */ \
264 beq 1f; \
265 mfspr r11,SPRN_SPRG3; \
266 lwz r11,THREAD_INFO-THREAD(r11); \
267 addi r11,r11,THREAD_SIZE; \
268 tophys(r11,r11); \
269 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
272 #define EXCEPTION_PROLOG_2 \
273 CLR_TOP32(r11); \
274 stw r10,_CCR(r11); /* save registers */ \
275 stw r12,GPR12(r11); \
276 stw r9,GPR9(r11); \
277 mfspr r10,SPRN_SPRG0; \
278 stw r10,GPR10(r11); \
279 mfspr r12,SPRN_SPRG1; \
280 stw r12,GPR11(r11); \
281 mflr r10; \
282 stw r10,_LINK(r11); \
283 mfspr r12,SPRN_SRR0; \
284 mfspr r9,SPRN_SRR1; \
285 stw r1,GPR1(r11); \
286 stw r1,0(r11); \
287 tovirt(r1,r11); /* set new kernel sp */ \
288 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
289 MTMSRD(r10); /* (except for mach check in rtas) */ \
290 stw r0,GPR0(r11); \
291 lis r10,0x7265; /* put exception frame marker */ \
292 addi r10,r10,0x6773; \
293 stw r10,8(r11); \
294 SAVE_4GPRS(3, r11); \
295 SAVE_2GPRS(7, r11)
297 /*
298 * Note: code which follows this uses cr0.eq (set if from kernel),
299 * r11, r12 (SRR0), and r9 (SRR1).
300 *
301 * Note2: once we have set r1 we are in a position to take exceptions
302 * again, and we could thus set MSR:RI at that point.
303 */
305 /*
306 * Exception vectors.
307 */
308 #define EXCEPTION(n, label, hdlr, xfer) \
309 . = n; \
310 label: \
311 EXCEPTION_PROLOG; \
312 addi r3,r1,STACK_FRAME_OVERHEAD; \
313 xfer(n, hdlr)
315 #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
316 li r10,trap; \
317 stw r10,_TRAP(r11); \
318 li r10,MSR_KERNEL; \
319 copyee(r10, r9); \
320 bl tfer; \
321 i##n: \
322 .long hdlr; \
323 .long ret
325 #define COPY_EE(d, s) rlwimi d,s,0,16,16
326 #define NOCOPY(d, s)
328 #define EXC_XFER_STD(n, hdlr) \
329 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
330 ret_from_except_full)
332 #define EXC_XFER_LITE(n, hdlr) \
333 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
334 ret_from_except)
336 #define EXC_XFER_EE(n, hdlr) \
337 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
338 ret_from_except_full)
340 #define EXC_XFER_EE_LITE(n, hdlr) \
341 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
342 ret_from_except)
344 /* System reset */
345 /* core99 pmac starts the seconary here by changing the vector, and
346 putting it back to what it was (unknown_exception) when done. */
347 #if defined(CONFIG_GEMINI) && defined(CONFIG_SMP)
348 . = 0x100
349 b __secondary_start_gemini
350 #else
351 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
352 #endif
354 /* Machine check */
355 /*
356 * On CHRP, this is complicated by the fact that we could get a
357 * machine check inside RTAS, and we have no guarantee that certain
358 * critical registers will have the values we expect. The set of
359 * registers that might have bad values includes all the GPRs
360 * and all the BATs. We indicate that we are in RTAS by putting
361 * a non-zero value, the address of the exception frame to use,
362 * in SPRG2. The machine check handler checks SPRG2 and uses its
363 * value if it is non-zero. If we ever needed to free up SPRG2,
364 * we could use a field in the thread_info or thread_struct instead.
365 * (Other exception handlers assume that r1 is a valid kernel stack
366 * pointer when we take an exception from supervisor mode.)
367 * -- paulus.
368 */
369 . = 0x200
370 mtspr SPRN_SPRG0,r10
371 mtspr SPRN_SPRG1,r11
372 mfcr r10
373 #ifdef CONFIG_PPC_CHRP
374 mfspr r11,SPRN_SPRG2
375 cmpwi 0,r11,0
376 bne 7f
377 #endif /* CONFIG_PPC_CHRP */
378 EXCEPTION_PROLOG_1
379 7: EXCEPTION_PROLOG_2
380 addi r3,r1,STACK_FRAME_OVERHEAD
381 #ifdef CONFIG_PPC_CHRP
382 mfspr r4,SPRN_SPRG2
383 cmpwi cr1,r4,0
384 bne cr1,1f
385 #endif
386 EXC_XFER_STD(0x200, machine_check_exception)
387 #ifdef CONFIG_PPC_CHRP
388 1: b machine_check_in_rtas
389 #endif
391 /* Data access exception. */
392 . = 0x300
393 DataAccess:
394 EXCEPTION_PROLOG
395 mfspr r10,SPRN_DSISR
396 andis. r0,r10,0xa470 /* weird error? */
397 bne 1f /* if not, try to put a PTE */
398 mfspr r4,SPRN_DAR /* into the hash table */
399 rlwinm r3,r10,32-15,21,21 /* DSISR_STORE -> _PAGE_RW */
400 bl hash_page
401 1: stw r10,_DSISR(r11)
402 mr r5,r10
403 mfspr r4,SPRN_DAR
404 EXC_XFER_EE_LITE(0x300, handle_page_fault)
407 /* Instruction access exception. */
408 . = 0x400
409 InstructionAccess:
410 EXCEPTION_PROLOG
411 andis. r0,r9,0x4000 /* no pte found? */
412 beq 1f /* if so, try to put a PTE */
413 li r3,0 /* into the hash table */
414 mr r4,r12 /* SRR0 is fault address */
415 bl hash_page
416 1: mr r4,r12
417 mr r5,r9
418 EXC_XFER_EE_LITE(0x400, handle_page_fault)
420 /* External interrupt */
421 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
423 /* Alignment exception */
424 . = 0x600
425 Alignment:
426 EXCEPTION_PROLOG
427 mfspr r4,SPRN_DAR
428 stw r4,_DAR(r11)
429 mfspr r5,SPRN_DSISR
430 stw r5,_DSISR(r11)
431 addi r3,r1,STACK_FRAME_OVERHEAD
432 EXC_XFER_EE(0x600, alignment_exception)
434 /* Program check exception */
435 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
437 /* Floating-point unavailable */
438 . = 0x800
439 FPUnavailable:
440 EXCEPTION_PROLOG
441 bne load_up_fpu /* if from user, just load it up */
442 addi r3,r1,STACK_FRAME_OVERHEAD
443 EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception)
445 /* Decrementer */
446 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
448 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
449 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
451 /* System call */
452 . = 0xc00
453 SystemCall:
454 EXCEPTION_PROLOG
455 EXC_XFER_EE_LITE(0xc00, DoSyscall)
457 /* Single step - not used on 601 */
458 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
459 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
461 /*
462 * The Altivec unavailable trap is at 0x0f20. Foo.
463 * We effectively remap it to 0x3000.
464 * We include an altivec unavailable exception vector even if
465 * not configured for Altivec, so that you can't panic a
466 * non-altivec kernel running on a machine with altivec just
467 * by executing an altivec instruction.
468 */
469 . = 0xf00
470 b PerformanceMonitor
472 . = 0xf20
473 b AltiVecUnavailable
475 /*
476 * Handle TLB miss for instruction on 603/603e.
477 * Note: we get an alternate set of r0 - r3 to use automatically.
478 */
479 . = 0x1000
480 InstructionTLBMiss:
481 /*
482 * r0: stored ctr
483 * r1: linux style pte ( later becomes ppc hardware pte )
484 * r2: ptr to linux-style pte
485 * r3: scratch
486 */
487 mfctr r0
488 /* Get PTE (linux-style) and check access */
489 mfspr r3,SPRN_IMISS
490 lis r1,KERNELBASE@h /* check if kernel address */
491 cmplw 0,r3,r1
492 mfspr r2,SPRN_SPRG3
493 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
494 lwz r2,PGDIR(r2)
495 blt+ 112f
496 lis r2,swapper_pg_dir@ha /* if kernel address, use */
497 addi r2,r2,swapper_pg_dir@l /* kernel page table */
498 mfspr r1,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
499 rlwinm r1,r1,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
500 112: tophys(r2,r2)
501 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
502 lwz r2,0(r2) /* get pmd entry */
503 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
504 beq- InstructionAddressInvalid /* return if no mapping */
505 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
506 lwz r3,0(r2) /* get linux-style pte */
507 andc. r1,r1,r3 /* check access & ~permission */
508 bne- InstructionAddressInvalid /* return if access not permitted */
509 ori r3,r3,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
510 /*
511 * NOTE! We are assuming this is not an SMP system, otherwise
512 * we would need to update the pte atomically with lwarx/stwcx.
513 */
514 stw r3,0(r2) /* update PTE (accessed bit) */
515 /* Convert linux-style PTE to low word of PPC-style PTE */
516 rlwinm r1,r3,32-10,31,31 /* _PAGE_RW -> PP lsb */
517 rlwinm r2,r3,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
518 and r1,r1,r2 /* writable if _RW and _DIRTY */
519 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
520 rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */
521 ori r1,r1,0xe14 /* clear out reserved bits and M */
522 andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
523 mtspr SPRN_RPA,r1
524 mfspr r3,SPRN_IMISS
525 tlbli r3
526 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
527 mtcrf 0x80,r3
528 rfi
529 InstructionAddressInvalid:
530 mfspr r3,SPRN_SRR1
531 rlwinm r1,r3,9,6,6 /* Get load/store bit */
533 addis r1,r1,0x2000
534 mtspr SPRN_DSISR,r1 /* (shouldn't be needed) */
535 mtctr r0 /* Restore CTR */
536 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
537 or r2,r2,r1
538 mtspr SPRN_SRR1,r2
539 mfspr r1,SPRN_IMISS /* Get failing address */
540 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
541 rlwimi r2,r2,1,30,30 /* change 1 -> 3 */
542 xor r1,r1,r2
543 mtspr SPRN_DAR,r1 /* Set fault address */
544 mfmsr r0 /* Restore "normal" registers */
545 xoris r0,r0,MSR_TGPR>>16
546 mtcrf 0x80,r3 /* Restore CR0 */
547 mtmsr r0
548 b InstructionAccess
550 /*
551 * Handle TLB miss for DATA Load operation on 603/603e
552 */
553 . = 0x1100
554 DataLoadTLBMiss:
555 /*
556 * r0: stored ctr
557 * r1: linux style pte ( later becomes ppc hardware pte )
558 * r2: ptr to linux-style pte
559 * r3: scratch
560 */
561 mfctr r0
562 /* Get PTE (linux-style) and check access */
563 mfspr r3,SPRN_DMISS
564 lis r1,KERNELBASE@h /* check if kernel address */
565 cmplw 0,r3,r1
566 mfspr r2,SPRN_SPRG3
567 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
568 lwz r2,PGDIR(r2)
569 blt+ 112f
570 lis r2,swapper_pg_dir@ha /* if kernel address, use */
571 addi r2,r2,swapper_pg_dir@l /* kernel page table */
572 mfspr r1,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
573 rlwinm r1,r1,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
574 112: tophys(r2,r2)
575 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
576 lwz r2,0(r2) /* get pmd entry */
577 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
578 beq- DataAddressInvalid /* return if no mapping */
579 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
580 lwz r3,0(r2) /* get linux-style pte */
581 andc. r1,r1,r3 /* check access & ~permission */
582 bne- DataAddressInvalid /* return if access not permitted */
583 ori r3,r3,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
584 /*
585 * NOTE! We are assuming this is not an SMP system, otherwise
586 * we would need to update the pte atomically with lwarx/stwcx.
587 */
588 stw r3,0(r2) /* update PTE (accessed bit) */
589 /* Convert linux-style PTE to low word of PPC-style PTE */
590 rlwinm r1,r3,32-10,31,31 /* _PAGE_RW -> PP lsb */
591 rlwinm r2,r3,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
592 and r1,r1,r2 /* writable if _RW and _DIRTY */
593 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
594 rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */
595 ori r1,r1,0xe14 /* clear out reserved bits and M */
596 andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
597 mtspr SPRN_RPA,r1
598 mfspr r3,SPRN_DMISS
599 tlbld r3
600 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
601 mtcrf 0x80,r3
602 rfi
603 DataAddressInvalid:
604 mfspr r3,SPRN_SRR1
605 rlwinm r1,r3,9,6,6 /* Get load/store bit */
606 addis r1,r1,0x2000
607 mtspr SPRN_DSISR,r1
608 mtctr r0 /* Restore CTR */
609 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
610 mtspr SPRN_SRR1,r2
611 mfspr r1,SPRN_DMISS /* Get failing address */
612 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
613 beq 20f /* Jump if big endian */
614 xori r1,r1,3
615 20: mtspr SPRN_DAR,r1 /* Set fault address */
616 mfmsr r0 /* Restore "normal" registers */
617 xoris r0,r0,MSR_TGPR>>16
618 mtcrf 0x80,r3 /* Restore CR0 */
619 mtmsr r0
620 b DataAccess
622 /*
623 * Handle TLB miss for DATA Store on 603/603e
624 */
625 . = 0x1200
626 DataStoreTLBMiss:
627 /*
628 * r0: stored ctr
629 * r1: linux style pte ( later becomes ppc hardware pte )
630 * r2: ptr to linux-style pte
631 * r3: scratch
632 */
633 mfctr r0
634 /* Get PTE (linux-style) and check access */
635 mfspr r3,SPRN_DMISS
636 lis r1,KERNELBASE@h /* check if kernel address */
637 cmplw 0,r3,r1
638 mfspr r2,SPRN_SPRG3
639 li r1,_PAGE_RW|_PAGE_USER|_PAGE_PRESENT /* access flags */
640 lwz r2,PGDIR(r2)
641 blt+ 112f
642 lis r2,swapper_pg_dir@ha /* if kernel address, use */
643 addi r2,r2,swapper_pg_dir@l /* kernel page table */
644 mfspr r1,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
645 rlwinm r1,r1,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
646 112: tophys(r2,r2)
647 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
648 lwz r2,0(r2) /* get pmd entry */
649 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
650 beq- DataAddressInvalid /* return if no mapping */
651 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
652 lwz r3,0(r2) /* get linux-style pte */
653 andc. r1,r1,r3 /* check access & ~permission */
654 bne- DataAddressInvalid /* return if access not permitted */
655 ori r3,r3,_PAGE_ACCESSED|_PAGE_DIRTY
656 /*
657 * NOTE! We are assuming this is not an SMP system, otherwise
658 * we would need to update the pte atomically with lwarx/stwcx.
659 */
660 stw r3,0(r2) /* update PTE (accessed/dirty bits) */
661 /* Convert linux-style PTE to low word of PPC-style PTE */
662 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
663 li r1,0xe15 /* clear out reserved bits and M */
664 andc r1,r3,r1 /* PP = user? 2: 0 */
665 mtspr SPRN_RPA,r1
666 mfspr r3,SPRN_DMISS
667 tlbld r3
668 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
669 mtcrf 0x80,r3
670 rfi
672 #ifndef CONFIG_ALTIVEC
673 #define altivec_assist_exception unknown_exception
674 #endif
676 EXCEPTION(0x1300, Trap_13, instruction_breakpoint_exception, EXC_XFER_EE)
677 EXCEPTION(0x1400, SMI, SMIException, EXC_XFER_EE)
678 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
679 EXCEPTION(0x1600, Trap_16, altivec_assist_exception, EXC_XFER_EE)
680 EXCEPTION(0x1700, Trap_17, TAUException, EXC_XFER_STD)
681 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
682 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
683 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
684 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
685 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE)
686 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
687 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
688 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
689 EXCEPTION(0x2000, RunMode, RunModeException, EXC_XFER_EE)
690 EXCEPTION(0x2100, Trap_21, unknown_exception, EXC_XFER_EE)
691 EXCEPTION(0x2200, Trap_22, unknown_exception, EXC_XFER_EE)
692 EXCEPTION(0x2300, Trap_23, unknown_exception, EXC_XFER_EE)
693 EXCEPTION(0x2400, Trap_24, unknown_exception, EXC_XFER_EE)
694 EXCEPTION(0x2500, Trap_25, unknown_exception, EXC_XFER_EE)
695 EXCEPTION(0x2600, Trap_26, unknown_exception, EXC_XFER_EE)
696 EXCEPTION(0x2700, Trap_27, unknown_exception, EXC_XFER_EE)
697 EXCEPTION(0x2800, Trap_28, unknown_exception, EXC_XFER_EE)
698 EXCEPTION(0x2900, Trap_29, unknown_exception, EXC_XFER_EE)
699 EXCEPTION(0x2a00, Trap_2a, unknown_exception, EXC_XFER_EE)
700 EXCEPTION(0x2b00, Trap_2b, unknown_exception, EXC_XFER_EE)
701 EXCEPTION(0x2c00, Trap_2c, unknown_exception, EXC_XFER_EE)
702 EXCEPTION(0x2d00, Trap_2d, unknown_exception, EXC_XFER_EE)
703 EXCEPTION(0x2e00, Trap_2e, unknown_exception, EXC_XFER_EE)
704 EXCEPTION(0x2f00, MOLTrampoline, unknown_exception, EXC_XFER_EE_LITE)
706 .globl mol_trampoline
707 .set mol_trampoline, i0x2f00
709 . = 0x3000
711 AltiVecUnavailable:
712 EXCEPTION_PROLOG
713 #ifdef CONFIG_ALTIVEC
714 bne load_up_altivec /* if from user, just load it up */
715 #endif /* CONFIG_ALTIVEC */
716 addi r3,r1,STACK_FRAME_OVERHEAD
717 EXC_XFER_EE_LITE(0xf20, altivec_unavailable_exception)
719 PerformanceMonitor:
720 EXCEPTION_PROLOG
721 addi r3,r1,STACK_FRAME_OVERHEAD
722 EXC_XFER_STD(0xf00, performance_monitor_exception)
724 #ifdef CONFIG_ALTIVEC
725 /* Note that the AltiVec support is closely modeled after the FP
726 * support. Changes to one are likely to be applicable to the
727 * other! */
728 load_up_altivec:
729 /*
730 * Disable AltiVec for the task which had AltiVec previously,
731 * and save its AltiVec registers in its thread_struct.
732 * Enables AltiVec for use in the kernel on return.
733 * On SMP we know the AltiVec units are free, since we give it up every
734 * switch. -- Kumar
735 */
736 mfmsr r5
737 oris r5,r5,MSR_VEC@h
738 MTMSRD(r5) /* enable use of AltiVec now */
739 isync
740 /*
741 * For SMP, we don't do lazy AltiVec switching because it just gets too
742 * horrendously complex, especially when a task switches from one CPU
743 * to another. Instead we call giveup_altivec in switch_to.
744 */
745 #ifndef CONFIG_SMP
746 tophys(r6,0)
747 addis r3,r6,last_task_used_altivec@ha
748 lwz r4,last_task_used_altivec@l(r3)
749 cmpwi 0,r4,0
750 beq 1f
751 add r4,r4,r6
752 addi r4,r4,THREAD /* want THREAD of last_task_used_altivec */
753 SAVE_32VRS(0,r10,r4)
754 mfvscr vr0
755 li r10,THREAD_VSCR
756 stvx vr0,r10,r4
757 lwz r5,PT_REGS(r4)
758 add r5,r5,r6
759 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
760 lis r10,MSR_VEC@h
761 andc r4,r4,r10 /* disable altivec for previous task */
762 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
763 1:
764 #endif /* CONFIG_SMP */
765 /* enable use of AltiVec after return */
766 oris r9,r9,MSR_VEC@h
767 mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */
768 li r4,1
769 li r10,THREAD_VSCR
770 stw r4,THREAD_USED_VR(r5)
771 lvx vr0,r10,r5
772 mtvscr vr0
773 REST_32VRS(0,r10,r5)
774 #ifndef CONFIG_SMP
775 subi r4,r5,THREAD
776 sub r4,r4,r6
777 stw r4,last_task_used_altivec@l(r3)
778 #endif /* CONFIG_SMP */
779 /* restore registers and return */
780 /* we haven't used ctr or xer or lr */
781 b fast_exception_return
783 /*
784 * AltiVec unavailable trap from kernel - print a message, but let
785 * the task use AltiVec in the kernel until it returns to user mode.
786 */
787 KernelAltiVec:
788 lwz r3,_MSR(r1)
789 oris r3,r3,MSR_VEC@h
790 stw r3,_MSR(r1) /* enable use of AltiVec after return */
791 lis r3,87f@h
792 ori r3,r3,87f@l
793 mr r4,r2 /* current */
794 lwz r5,_NIP(r1)
795 bl printk
796 b ret_from_except
797 87: .string "AltiVec used in kernel (task=%p, pc=%x) \n"
798 .align 4,0
800 /*
801 * giveup_altivec(tsk)
802 * Disable AltiVec for the task given as the argument,
803 * and save the AltiVec registers in its thread_struct.
804 * Enables AltiVec for use in the kernel on return.
805 */
807 .globl giveup_altivec
808 giveup_altivec:
809 mfmsr r5
810 oris r5,r5,MSR_VEC@h
811 SYNC
812 MTMSRD(r5) /* enable use of AltiVec now */
813 isync
814 cmpwi 0,r3,0
815 beqlr- /* if no previous owner, done */
816 addi r3,r3,THREAD /* want THREAD of task */
817 lwz r5,PT_REGS(r3)
818 cmpwi 0,r5,0
819 SAVE_32VRS(0, r4, r3)
820 mfvscr vr0
821 li r4,THREAD_VSCR
822 stvx vr0,r4,r3
823 beq 1f
824 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
825 lis r3,MSR_VEC@h
826 andc r4,r4,r3 /* disable AltiVec for previous task */
827 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
828 1:
829 #ifndef CONFIG_SMP
830 li r5,0
831 lis r4,last_task_used_altivec@ha
832 stw r5,last_task_used_altivec@l(r4)
833 #endif /* CONFIG_SMP */
834 blr
835 #endif /* CONFIG_ALTIVEC */
837 /*
838 * This code is jumped to from the startup code to copy
839 * the kernel image to physical address 0.
840 */
841 relocate_kernel:
842 addis r9,r26,klimit@ha /* fetch klimit */
843 lwz r25,klimit@l(r9)
844 addis r25,r25,-KERNELBASE@h
845 li r3,0 /* Destination base address */
846 li r6,0 /* Destination offset */
847 li r5,0x4000 /* # bytes of memory to copy */
848 bl copy_and_flush /* copy the first 0x4000 bytes */
849 addi r0,r3,4f@l /* jump to the address of 4f */
850 mtctr r0 /* in copy and do the rest. */
851 bctr /* jump to the copy */
852 4: mr r5,r25
853 bl copy_and_flush /* copy the rest */
854 b turn_on_mmu
856 /*
857 * Copy routine used to copy the kernel to start at physical address 0
858 * and flush and invalidate the caches as needed.
859 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
860 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
861 */
862 _GLOBAL(copy_and_flush)
863 addi r5,r5,-4
864 addi r6,r6,-4
865 4: li r0,L1_CACHE_BYTES/4
866 mtctr r0
867 3: addi r6,r6,4 /* copy a cache line */
868 lwzx r0,r6,r4
869 stwx r0,r6,r3
870 bdnz 3b
871 dcbst r6,r3 /* write it to memory */
872 sync
873 icbi r6,r3 /* flush the icache line */
874 cmplw 0,r6,r5
875 blt 4b
876 sync /* additional sync needed on g4 */
877 isync
878 addi r5,r5,4
879 addi r6,r6,4
880 blr
882 #ifdef CONFIG_APUS
883 /*
884 * On APUS the physical base address of the kernel is not known at compile
885 * time, which means the __pa/__va constants used are incorrect. In the
886 * __init section is recorded the virtual addresses of instructions using
887 * these constants, so all that has to be done is fix these before
888 * continuing the kernel boot.
889 *
890 * r4 = The physical address of the kernel base.
891 */
892 fix_mem_constants:
893 mr r10,r4
894 addis r10,r10,-KERNELBASE@h /* virt_to_phys constant */
895 neg r11,r10 /* phys_to_virt constant */
897 lis r12,__vtop_table_begin@h
898 ori r12,r12,__vtop_table_begin@l
899 add r12,r12,r10 /* table begin phys address */
900 lis r13,__vtop_table_end@h
901 ori r13,r13,__vtop_table_end@l
902 add r13,r13,r10 /* table end phys address */
903 subi r12,r12,4
904 subi r13,r13,4
905 1: lwzu r14,4(r12) /* virt address of instruction */
906 add r14,r14,r10 /* phys address of instruction */
907 lwz r15,0(r14) /* instruction, now insert top */
908 rlwimi r15,r10,16,16,31 /* half of vp const in low half */
909 stw r15,0(r14) /* of instruction and restore. */
910 dcbst r0,r14 /* write it to memory */
911 sync
912 icbi r0,r14 /* flush the icache line */
913 cmpw r12,r13
914 bne 1b
915 sync /* additional sync needed on g4 */
916 isync
918 /*
919 * Map the memory where the exception handlers will
920 * be copied to when hash constants have been patched.
921 */
922 #ifdef CONFIG_APUS_FAST_EXCEPT
923 lis r8,0xfff0
924 #else
925 lis r8,0
926 #endif
927 ori r8,r8,0x2 /* 128KB, supervisor */
928 mtspr SPRN_DBAT3U,r8
929 mtspr SPRN_DBAT3L,r8
931 lis r12,__ptov_table_begin@h
932 ori r12,r12,__ptov_table_begin@l
933 add r12,r12,r10 /* table begin phys address */
934 lis r13,__ptov_table_end@h
935 ori r13,r13,__ptov_table_end@l
936 add r13,r13,r10 /* table end phys address */
937 subi r12,r12,4
938 subi r13,r13,4
939 1: lwzu r14,4(r12) /* virt address of instruction */
940 add r14,r14,r10 /* phys address of instruction */
941 lwz r15,0(r14) /* instruction, now insert top */
942 rlwimi r15,r11,16,16,31 /* half of pv const in low half*/
943 stw r15,0(r14) /* of instruction and restore. */
944 dcbst r0,r14 /* write it to memory */
945 sync
946 icbi r0,r14 /* flush the icache line */
947 cmpw r12,r13
948 bne 1b
950 sync /* additional sync needed on g4 */
951 isync /* No speculative loading until now */
952 blr
954 /***********************************************************************
955 * Please note that on APUS the exception handlers are located at the
956 * physical address 0xfff0000. For this reason, the exception handlers
957 * cannot use relative branches to access the code below.
958 ***********************************************************************/
959 #endif /* CONFIG_APUS */
961 #ifdef CONFIG_SMP
962 #ifdef CONFIG_GEMINI
963 .globl __secondary_start_gemini
964 __secondary_start_gemini:
965 mfspr r4,SPRN_HID0
966 ori r4,r4,HID0_ICFI
967 li r3,0
968 ori r3,r3,HID0_ICE
969 andc r4,r4,r3
970 mtspr SPRN_HID0,r4
971 sync
972 b __secondary_start
973 #endif /* CONFIG_GEMINI */
975 .globl __secondary_start_mpc86xx
976 __secondary_start_mpc86xx:
977 mfspr r3, SPRN_PIR
978 stw r3, __secondary_hold_acknowledge@l(0)
979 mr r24, r3 /* cpu # */
980 b __secondary_start
982 .globl __secondary_start_pmac_0
983 __secondary_start_pmac_0:
984 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
985 li r24,0
986 b 1f
987 li r24,1
988 b 1f
989 li r24,2
990 b 1f
991 li r24,3
992 1:
993 /* on powersurge, we come in here with IR=0 and DR=1, and DBAT 0
994 set to map the 0xf0000000 - 0xffffffff region */
995 mfmsr r0
996 rlwinm r0,r0,0,28,26 /* clear DR (0x10) */
997 SYNC
998 mtmsr r0
999 isync
1001 .globl __secondary_start
1002 __secondary_start:
1003 /* Copy some CPU settings from CPU 0 */
1004 bl __restore_cpu_setup
1006 lis r3,-KERNELBASE@h
1007 mr r4,r24
1008 bl call_setup_cpu /* Call setup_cpu for this CPU */
1009 #ifdef CONFIG_6xx
1010 lis r3,-KERNELBASE@h
1011 bl init_idle_6xx
1012 #endif /* CONFIG_6xx */
1014 /* get current_thread_info and current */
1015 lis r1,secondary_ti@ha
1016 tophys(r1,r1)
1017 lwz r1,secondary_ti@l(r1)
1018 tophys(r2,r1)
1019 lwz r2,TI_TASK(r2)
1021 /* stack */
1022 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1023 li r0,0
1024 tophys(r3,r1)
1025 stw r0,0(r3)
1027 /* load up the MMU */
1028 bl load_up_mmu
1030 /* ptr to phys current thread */
1031 tophys(r4,r2)
1032 addi r4,r4,THREAD /* phys address of our thread_struct */
1033 CLR_TOP32(r4)
1034 mtspr SPRN_SPRG3,r4
1035 li r3,0
1036 mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */
1038 /* enable MMU and jump to start_secondary */
1039 li r4,MSR_KERNEL
1040 FIX_SRR1(r4,r5)
1041 lis r3,start_secondary@h
1042 ori r3,r3,start_secondary@l
1043 mtspr SPRN_SRR0,r3
1044 mtspr SPRN_SRR1,r4
1045 SYNC
1046 RFI
1047 #endif /* CONFIG_SMP */
1049 /*
1050 * Those generic dummy functions are kept for CPUs not
1051 * included in CONFIG_6xx
1052 */
1053 #if !defined(CONFIG_6xx)
1054 _GLOBAL(__save_cpu_setup)
1055 blr
1056 _GLOBAL(__restore_cpu_setup)
1057 blr
1058 #endif /* !defined(CONFIG_6xx) */
1061 /*
1062 * Load stuff into the MMU. Intended to be called with
1063 * IR=0 and DR=0.
1064 */
1065 load_up_mmu:
1066 sync /* Force all PTE updates to finish */
1067 isync
1068 tlbia /* Clear all TLB entries */
1069 sync /* wait for tlbia/tlbie to finish */
1070 TLBSYNC /* ... on all CPUs */
1071 /* Load the SDR1 register (hash table base & size) */
1072 lis r6,_SDR1@ha
1073 tophys(r6,r6)
1074 lwz r6,_SDR1@l(r6)
1075 mtspr SPRN_SDR1,r6
1076 li r0,16 /* load up segment register values */
1077 mtctr r0 /* for context 0 */
1078 lis r3,0x2000 /* Ku = 1, VSID = 0 */
1079 li r4,0
1080 3: mtsrin r3,r4
1081 addi r3,r3,0x111 /* increment VSID */
1082 addis r4,r4,0x1000 /* address of next segment */
1083 bdnz 3b
1085 /* Load the BAT registers with the values set up by MMU_init.
1086 MMU_init takes care of whether we're on a 601 or not. */
1087 mfpvr r3
1088 srwi r3,r3,16
1089 cmpwi r3,1
1090 lis r3,BATS@ha
1091 addi r3,r3,BATS@l
1092 tophys(r3,r3)
1093 LOAD_BAT(0,r3,r4,r5)
1094 LOAD_BAT(1,r3,r4,r5)
1095 LOAD_BAT(2,r3,r4,r5)
1096 LOAD_BAT(3,r3,r4,r5)
1097 BEGIN_FTR_SECTION
1098 LOAD_BAT(4,r3,r4,r5)
1099 LOAD_BAT(5,r3,r4,r5)
1100 LOAD_BAT(6,r3,r4,r5)
1101 LOAD_BAT(7,r3,r4,r5)
1102 END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS)
1103 blr
1105 /*
1106 * This is where the main kernel code starts.
1107 */
1108 start_here:
1109 /* ptr to current */
1110 lis r2,init_task@h
1111 ori r2,r2,init_task@l
1112 /* Set up for using our exception vectors */
1113 /* ptr to phys current thread */
1114 tophys(r4,r2)
1115 addi r4,r4,THREAD /* init task's THREAD */
1116 CLR_TOP32(r4)
1117 mtspr SPRN_SPRG3,r4
1118 li r3,0
1119 mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */
1121 /* stack */
1122 lis r1,init_thread_union@ha
1123 addi r1,r1,init_thread_union@l
1124 li r0,0
1125 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
1126 /*
1127 * Do early platform-specific initialization,
1128 * and set up the MMU.
1129 */
1130 mr r3,r31
1131 mr r4,r30
1132 bl machine_init
1133 bl __save_cpu_setup
1134 bl MMU_init
1136 #ifdef CONFIG_APUS
1137 /* Copy exception code to exception vector base on APUS. */
1138 lis r4,KERNELBASE@h
1139 #ifdef CONFIG_APUS_FAST_EXCEPT
1140 lis r3,0xfff0 /* Copy to 0xfff00000 */
1141 #else
1142 lis r3,0 /* Copy to 0x00000000 */
1143 #endif
1144 li r5,0x4000 /* # bytes of memory to copy */
1145 li r6,0
1146 bl copy_and_flush /* copy the first 0x4000 bytes */
1147 #endif /* CONFIG_APUS */
1149 /*
1150 * Go back to running unmapped so we can load up new values
1151 * for SDR1 (hash table pointer) and the segment registers
1152 * and change to using our exception vectors.
1153 */
1154 lis r4,2f@h
1155 ori r4,r4,2f@l
1156 tophys(r4,r4)
1157 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
1158 FIX_SRR1(r3,r5)
1159 mtspr SPRN_SRR0,r4
1160 mtspr SPRN_SRR1,r3
1161 SYNC
1162 RFI
1163 /* Load up the kernel context */
1164 2: bl load_up_mmu
1166 #ifdef CONFIG_BDI_SWITCH
1167 /* Add helper information for the Abatron bdiGDB debugger.
1168 * We do this here because we know the mmu is disabled, and
1169 * will be enabled for real in just a few instructions.
1170 */
1171 lis r5, abatron_pteptrs@h
1172 ori r5, r5, abatron_pteptrs@l
1173 stw r5, 0xf0(r0) /* This much match your Abatron config */
1174 lis r6, swapper_pg_dir@h
1175 ori r6, r6, swapper_pg_dir@l
1176 tophys(r5, r5)
1177 stw r6, 0(r5)
1178 #endif /* CONFIG_BDI_SWITCH */
1180 /* Now turn on the MMU for real! */
1181 li r4,MSR_KERNEL
1182 FIX_SRR1(r4,r5)
1183 lis r3,start_kernel@h
1184 ori r3,r3,start_kernel@l
1185 mtspr SPRN_SRR0,r3
1186 mtspr SPRN_SRR1,r4
1187 SYNC
1188 RFI
1190 /*
1191 * Set up the segment registers for a new context.
1192 */
1193 _GLOBAL(set_context)
1194 mulli r3,r3,897 /* multiply context by skew factor */
1195 rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */
1196 addis r3,r3,0x6000 /* Set Ks, Ku bits */
1197 li r0,NUM_USER_SEGMENTS
1198 mtctr r0
1200 #ifdef CONFIG_BDI_SWITCH
1201 /* Context switch the PTE pointer for the Abatron BDI2000.
1202 * The PGDIR is passed as second argument.
1203 */
1204 lis r5, KERNELBASE@h
1205 lwz r5, 0xf0(r5)
1206 stw r4, 0x4(r5)
1207 #endif
1208 li r4,0
1209 isync
1210 3:
1211 mtsrin r3,r4
1212 addi r3,r3,0x111 /* next VSID */
1213 rlwinm r3,r3,0,8,3 /* clear out any overflow from VSID field */
1214 addis r4,r4,0x1000 /* address of next segment */
1215 bdnz 3b
1216 sync
1217 isync
1218 blr
1220 /*
1221 * An undocumented "feature" of 604e requires that the v bit
1222 * be cleared before changing BAT values.
1223 *
1224 * Also, newer IBM firmware does not clear bat3 and 4 so
1225 * this makes sure it's done.
1226 * -- Cort
1227 */
1228 clear_bats:
1229 li r10,0
1230 mfspr r9,SPRN_PVR
1231 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1232 cmpwi r9, 1
1233 beq 1f
1235 mtspr SPRN_DBAT0U,r10
1236 mtspr SPRN_DBAT0L,r10
1237 mtspr SPRN_DBAT1U,r10
1238 mtspr SPRN_DBAT1L,r10
1239 mtspr SPRN_DBAT2U,r10
1240 mtspr SPRN_DBAT2L,r10
1241 mtspr SPRN_DBAT3U,r10
1242 mtspr SPRN_DBAT3L,r10
1243 1:
1244 mtspr SPRN_IBAT0U,r10
1245 mtspr SPRN_IBAT0L,r10
1246 mtspr SPRN_IBAT1U,r10
1247 mtspr SPRN_IBAT1L,r10
1248 mtspr SPRN_IBAT2U,r10
1249 mtspr SPRN_IBAT2L,r10
1250 mtspr SPRN_IBAT3U,r10
1251 mtspr SPRN_IBAT3L,r10
1252 BEGIN_FTR_SECTION
1253 /* Here's a tweak: at this point, CPU setup have
1254 * not been called yet, so HIGH_BAT_EN may not be
1255 * set in HID0 for the 745x processors. However, it
1256 * seems that doesn't affect our ability to actually
1257 * write to these SPRs.
1258 */
1259 mtspr SPRN_DBAT4U,r10
1260 mtspr SPRN_DBAT4L,r10
1261 mtspr SPRN_DBAT5U,r10
1262 mtspr SPRN_DBAT5L,r10
1263 mtspr SPRN_DBAT6U,r10
1264 mtspr SPRN_DBAT6L,r10
1265 mtspr SPRN_DBAT7U,r10
1266 mtspr SPRN_DBAT7L,r10
1267 mtspr SPRN_IBAT4U,r10
1268 mtspr SPRN_IBAT4L,r10
1269 mtspr SPRN_IBAT5U,r10
1270 mtspr SPRN_IBAT5L,r10
1271 mtspr SPRN_IBAT6U,r10
1272 mtspr SPRN_IBAT6L,r10
1273 mtspr SPRN_IBAT7U,r10
1274 mtspr SPRN_IBAT7L,r10
1275 END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS)
1276 blr
1278 flush_tlbs:
1279 lis r10, 0x40
1280 1: addic. r10, r10, -0x1000
1281 tlbie r10
1282 blt 1b
1283 sync
1284 blr
1286 mmu_off:
1287 addi r4, r3, __after_mmu_off - _start
1288 mfmsr r3
1289 andi. r0,r3,MSR_DR|MSR_IR /* MMU enabled? */
1290 beqlr
1291 andc r3,r3,r0
1292 mtspr SPRN_SRR0,r4
1293 mtspr SPRN_SRR1,r3
1294 sync
1295 RFI
1297 /*
1298 * Use the first pair of BAT registers to map the 1st 16MB
1299 * of RAM to KERNELBASE. From this point on we can't safely
1300 * call OF any more.
1301 */
1302 initial_bats:
1303 lis r11,KERNELBASE@h
1304 mfspr r9,SPRN_PVR
1305 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1306 cmpwi 0,r9,1
1307 bne 4f
1308 ori r11,r11,4 /* set up BAT registers for 601 */
1309 li r8,0x7f /* valid, block length = 8MB */
1310 oris r9,r11,0x800000@h /* set up BAT reg for 2nd 8M */
1311 oris r10,r8,0x800000@h /* set up BAT reg for 2nd 8M */
1312 mtspr SPRN_IBAT0U,r11 /* N.B. 601 has valid bit in */
1313 mtspr SPRN_IBAT0L,r8 /* lower BAT register */
1314 mtspr SPRN_IBAT1U,r9
1315 mtspr SPRN_IBAT1L,r10
1316 isync
1317 blr
1319 4: tophys(r8,r11)
1320 #ifdef CONFIG_SMP
1321 ori r8,r8,0x12 /* R/W access, M=1 */
1322 #else
1323 ori r8,r8,2 /* R/W access */
1324 #endif /* CONFIG_SMP */
1325 #ifdef CONFIG_APUS
1326 ori r11,r11,BL_8M<<2|0x2 /* set up 8MB BAT registers for 604 */
1327 #else
1328 ori r11,r11,BL_256M<<2|0x2 /* set up BAT registers for 604 */
1329 #endif /* CONFIG_APUS */
1331 mtspr SPRN_DBAT0L,r8 /* N.B. 6xx (not 601) have valid */
1332 mtspr SPRN_DBAT0U,r11 /* bit in upper BAT register */
1333 mtspr SPRN_IBAT0L,r8
1334 mtspr SPRN_IBAT0U,r11
1335 isync
1336 blr
1339 #if !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT)
1340 setup_disp_bat:
1341 /*
1342 * setup the display bat prepared for us in prom.c
1343 */
1344 mflr r8
1345 bl reloc_offset
1346 mtlr r8
1347 addis r8,r3,disp_BAT@ha
1348 addi r8,r8,disp_BAT@l
1349 cmpwi cr0,r8,0
1350 beqlr
1351 lwz r11,0(r8)
1352 lwz r8,4(r8)
1353 mfspr r9,SPRN_PVR
1354 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1355 cmpwi 0,r9,1
1356 beq 1f
1357 mtspr SPRN_DBAT3L,r8
1358 mtspr SPRN_DBAT3U,r11
1359 blr
1360 1: mtspr SPRN_IBAT3L,r8
1361 mtspr SPRN_IBAT3U,r11
1362 blr
1363 #endif /* !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT) */
1365 #ifdef CONFIG_8260
1366 /* Jump into the system reset for the rom.
1367 * We first disable the MMU, and then jump to the ROM reset address.
1368 *
1369 * r3 is the board info structure, r4 is the location for starting.
1370 * I use this for building a small kernel that can load other kernels,
1371 * rather than trying to write or rely on a rom monitor that can tftp load.
1372 */
1373 .globl m8260_gorom
1374 m8260_gorom:
1375 mfmsr r0
1376 rlwinm r0,r0,0,17,15 /* clear MSR_EE in r0 */
1377 sync
1378 mtmsr r0
1379 sync
1380 mfspr r11, SPRN_HID0
1381 lis r10, 0
1382 ori r10,r10,HID0_ICE|HID0_DCE
1383 andc r11, r11, r10
1384 mtspr SPRN_HID0, r11
1385 isync
1386 li r5, MSR_ME|MSR_RI
1387 lis r6,2f@h
1388 addis r6,r6,-KERNELBASE@h
1389 ori r6,r6,2f@l
1390 mtspr SPRN_SRR0,r6
1391 mtspr SPRN_SRR1,r5
1392 isync
1393 sync
1394 rfi
1395 2:
1396 mtlr r4
1397 blr
1398 #endif
1401 /*
1402 * We put a few things here that have to be page-aligned.
1403 * This stuff goes at the beginning of the data segment,
1404 * which is page-aligned.
1405 */
1406 .data
1407 .globl sdata
1408 sdata:
1409 .globl empty_zero_page
1410 empty_zero_page:
1411 .space 4096
1413 .globl swapper_pg_dir
1414 swapper_pg_dir:
1415 .space 4096
1417 /*
1418 * This space gets a copy of optional info passed to us by the bootstrap
1419 * Used to pass parameters into the kernel like root=/dev/sda1, etc.
1420 */
1421 .globl cmd_line
1422 cmd_line:
1423 .space 512
1425 .globl intercept_table
1426 intercept_table:
1427 .long 0, 0, i0x200, i0x300, i0x400, 0, i0x600, i0x700
1428 .long i0x800, 0, 0, 0, 0, i0xd00, 0, 0
1429 .long 0, 0, 0, i0x1300, 0, 0, 0, 0
1430 .long 0, 0, 0, 0, 0, 0, 0, 0
1431 .long 0, 0, 0, 0, 0, 0, 0, 0
1432 .long 0, 0, 0, 0, 0, 0, 0, 0
1434 /* Room for two PTE pointers, usually the kernel and current user pointers
1435 * to their respective root page table.
1436 */
1437 abatron_pteptrs:
1438 .space 8