include/asm-arm/arch-s3c2410/bast-map.h

   1 /* linux/include/asm-arm/arch-s3c2410/bast-map.h
   2  *
   3  * (c) 2003,2004 Simtec Electronics
   4  *  Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * Machine BAST - Memory map definitions
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 /* needs arch/map.h including with this */
  14
  15 /* ok, we've used up to 0x13000000, now we need to find space for the
  16  * peripherals that live in the nGCS[x] areas, which are quite numerous
  17  * in their space. We also have the board's CPLD to find register space
  18  * for.
  19  */
  20
  21 #ifndef __ASM_ARCH_BASTMAP_H
  22 #define __ASM_ARCH_BASTMAP_H
  23
  24 #define BAST_IOADDR(x)     (S3C2410_ADDR((x) + 0x01300000))
  25
  26 /* we put the CPLD registers next, to get them out of the way */
  27
  28 #define BAST_VA_CTRL1       BAST_IOADDR(0x00000000)      /* 0x01300000 */
  29 #define BAST_PA_CTRL1       (S3C2410_CS5 | 0x7800000)
  30
  31 #define BAST_VA_CTRL2       BAST_IOADDR(0x00100000)      /* 0x01400000 */
  32 #define BAST_PA_CTRL2       (S3C2410_CS1 | 0x6000000)
  33
  34 #define BAST_VA_CTRL3       BAST_IOADDR(0x00200000)      /* 0x01500000 */
  35 #define BAST_PA_CTRL3       (S3C2410_CS1 | 0x6800000)
  36
  37 #define BAST_VA_CTRL4       BAST_IOADDR(0x00300000)      /* 0x01600000 */
  38 #define BAST_PA_CTRL4       (S3C2410_CS1 | 0x7000000)
  39
  40 /* next, we have the PC104 ISA interrupt registers */
  41
  42 #define BAST_PA_PC104_IRQREQ  (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
  43 #define BAST_VA_PC104_IRQREQ  BAST_IOADDR(0x00400000)
  44
  45 #define BAST_PA_PC104_IRQRAW  (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
  46 #define BAST_VA_PC104_IRQRAW  BAST_IOADDR(0x00500000)
  47
  48 #define BAST_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
  49 #define BAST_VA_PC104_IRQMASK BAST_IOADDR(0x00600000)
  50
  51 #define BAST_PA_LCD_RCMD1     (0x8800000)
  52 #define BAST_VA_LCD_RCMD1     BAST_IOADDR(0x00700000)
  53
  54 #define BAST_PA_LCD_WCMD1     (0x8000000)
  55 #define BAST_VA_LCD_WCMD1     BAST_IOADDR(0x00800000)
  56
  57 #define BAST_PA_LCD_RDATA1    (0x9800000)
  58 #define BAST_VA_LCD_RDATA1    BAST_IOADDR(0x00900000)
  59
  60 #define BAST_PA_LCD_WDATA1    (0x9000000)
  61 #define BAST_VA_LCD_WDATA1    BAST_IOADDR(0x00A00000)
  62
  63 #define BAST_PA_LCD_RCMD2     (0xA800000)
  64 #define BAST_VA_LCD_RCMD2     BAST_IOADDR(0x00B00000)
  65
  66 #define BAST_PA_LCD_WCMD2     (0xA000000)
  67 #define BAST_VA_LCD_WCMD2     BAST_IOADDR(0x00C00000)
  68
  69 #define BAST_PA_LCD_RDATA2    (0xB800000)
  70 #define BAST_VA_LCD_RDATA2    BAST_IOADDR(0x00D00000)
  71
  72 #define BAST_PA_LCD_WDATA2    (0xB000000)
  73 #define BAST_VA_LCD_WDATA2    BAST_IOADDR(0x00E00000)
  74
  75
  76 /* 0xE0000000 contains the IO space that is split by speed and
  77  * wether the access is for 8 or 16bit IO... this ensures that
  78  * the correct access is made
  79  *
  80  * 0x10000000 of space, partitioned as so:
  81  *
  82  * 0x00000000 to 0x04000000  8bit,  slow
  83  * 0x04000000 to 0x08000000  16bit, slow
  84  * 0x08000000 to 0x0C000000  16bit, net
  85  * 0x0C000000 to 0x10000000  16bit, fast
  86  *
  87  * each of these spaces has the following in:
  88  *
  89  * 0x00000000 to 0x01000000 16MB ISA IO space
  90  * 0x01000000 to 0x02000000 16MB ISA memory space
  91  * 0x02000000 to 0x02100000 1MB  IDE primary channel
  92  * 0x02100000 to 0x02200000 1MB  IDE primary channel aux
  93  * 0x02200000 to 0x02400000 1MB  IDE secondary channel
  94  * 0x02300000 to 0x02400000 1MB  IDE secondary channel aux
  95  * 0x02400000 to 0x02500000 1MB  ASIX ethernet controller
  96  * 0x02500000 to 0x02600000 1MB  Davicom DM9000 ethernet controller
  97  * 0x02600000 to 0x02700000 1MB  PC SuperIO controller
  98  *
  99  * the phyiscal layout of the zones are:
 100  *  nGCS2 - 8bit, slow
 101  *  nGCS3 - 16bit, slow
 102  *  nGCS4 - 16bit, net
 103  *  nGCS5 - 16bit, fast
 104  */
 105
 106 #define BAST_VA_MULTISPACE (0xE0000000)
 107
 108 #define BAST_VA_ISAIO      (BAST_VA_MULTISPACE + 0x00000000)
 109 #define BAST_VA_ISAMEM     (BAST_VA_MULTISPACE + 0x01000000)
 110 #define BAST_VA_IDEPRI     (BAST_VA_MULTISPACE + 0x02000000)
 111 #define BAST_VA_IDEPRIAUX  (BAST_VA_MULTISPACE + 0x02100000)
 112 #define BAST_VA_IDESEC     (BAST_VA_MULTISPACE + 0x02200000)
 113 #define BAST_VA_IDESECAUX  (BAST_VA_MULTISPACE + 0x02300000)
 114 #define BAST_VA_ASIXNET    (BAST_VA_MULTISPACE + 0x02400000)
 115 #define BAST_VA_DM9000     (BAST_VA_MULTISPACE + 0x02500000)
 116 #define BAST_VA_SUPERIO    (BAST_VA_MULTISPACE + 0x02600000)
 117
 118 #define BAST_VA_MULTISPACE (0xE0000000)
 119
 120 #define BAST_VAM_CS2 (0x00000000)
 121 #define BAST_VAM_CS3 (0x04000000)
 122 #define BAST_VAM_CS4 (0x08000000)
 123 #define BAST_VAM_CS5 (0x0C000000)
 124
 125 /* physical offset addresses for the peripherals */
 126
 127 #define BAST_PA_ISAIO     (0x00000000)
 128 #define BAST_PA_ASIXNET   (0x01000000)
 129 #define BAST_PA_SUPERIO   (0x01800000)
 130 #define BAST_PA_IDEPRI    (0x02000000)
 131 #define BAST_PA_IDEPRIAUX (0x02800000)
 132 #define BAST_PA_IDESEC    (0x03000000)
 133 #define BAST_PA_IDESECAUX (0x03800000)
 134 #define BAST_PA_ISAMEM    (0x04000000)
 135 #define BAST_PA_DM9000    (0x05000000)
 136
 137 /* some configurations for the peripherals */
 138
 139 #define BAST_PCSIO (BAST_VA_SUPERIO + BAST_VAM_CS2)
 140 /*  */
 141
 142 #define BAST_ASIXNET_CS  BAST_VAM_CS5
 143 #define BAST_IDE_CS      BAST_VAM_CS5
 144 #define BAST_DM9000_CS   BAST_VAM_CS4
 145
 146 #endif /* __ASM_ARCH_BASTMAP_H */