include/asm-arm/arch-s3c2410/map.h

   1 /* linux/include/asm-arm/arch-s3c2410/map.h
   2  *
   3  * (c) 2003 Simtec Electronics
   4  *  Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C2410 - Memory map definitions
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #ifndef __ASM_ARCH_MAP_H
  14 #define __ASM_ARCH_MAP_H
  15
  16 /* we have a bit of a tight squeeze to fit all our registers from
  17  * 0xF00000000 upwards, since we use all of the nGCS space in some
  18  * capacity, and also need to fit the S3C2410 registers in as well...
  19  *
  20  * we try to ensure stuff like the IRQ registers are available for
  21  * an single MOVS instruction (ie, only 8 bits of set data)
  22  *
  23  * Note, we are trying to remove some of these from the implementation
  24  * as they are only useful to certain drivers...
  25  */
  26
  27 #ifndef __ASSEMBLY__
  28 #define S3C2410_ADDR(x)   ((void __iomem *)0xF0000000 + (x))
  29 #else
  30 #define S3C2410_ADDR(x)   (0xF0000000 + (x))
  31 #endif
  32
  33 #define S3C2400_ADDR(x)   S3C2410_ADDR(x)
  34
  35 /* interrupt controller is the first thing we put in, to make
  36  * the assembly code for the irq detection easier
  37  */
  38 #define S3C24XX_VA_IRQ     S3C2410_ADDR(0x00000000)
  39 #define S3C2400_PA_IRQ     (0x14400000)
  40 #define S3C2410_PA_IRQ     (0x4A000000)
  41 #define S3C24XX_SZ_IRQ     SZ_1M
  42
  43 /* memory controller registers */
  44 #define S3C24XX_VA_MEMCTRL S3C2410_ADDR(0x00100000)
  45 #define S3C2400_PA_MEMCTRL (0x14000000)
  46 #define S3C2410_PA_MEMCTRL (0x48000000)
  47 #define S3C24XX_SZ_MEMCTRL SZ_1M
  48
  49 /* USB host controller */
  50 #define S3C24XX_VA_USBHOST S3C2410_ADDR(0x00200000)
  51 #define S3C2400_PA_USBHOST (0x14200000)
  52 #define S3C2410_PA_USBHOST (0x49000000)
  53 #define S3C24XX_SZ_USBHOST SZ_1M
  54
  55 /* DMA controller */
  56 #define S3C24XX_VA_DMA     S3C2410_ADDR(0x00300000)
  57 #define S3C2400_PA_DMA     (0x14600000)
  58 #define S3C2410_PA_DMA     (0x4B000000)
  59 #define S3C24XX_SZ_DMA     SZ_1M
  60
  61 /* Clock and Power management */
  62 #define S3C24XX_VA_CLKPWR  S3C2410_ADDR(0x00400000)
  63 #define S3C2400_PA_CLKPWR  (0x14800000)
  64 #define S3C2410_PA_CLKPWR  (0x4C000000)
  65 #define S3C24XX_SZ_CLKPWR  SZ_1M
  66
  67 /* LCD controller */
  68 #define S3C24XX_VA_LCD     S3C2410_ADDR(0x00600000)
  69 #define S3C2400_PA_LCD     (0x14A00000)
  70 #define S3C2410_PA_LCD     (0x4D000000)
  71 #define S3C24XX_SZ_LCD     SZ_1M
  72
  73 /* NAND flash controller */
  74 #define S3C24XX_VA_NAND    S3C2410_ADDR(0x00700000)
  75 #define S3C2410_PA_NAND    (0x4E000000)
  76 #define S3C24XX_SZ_NAND    SZ_1M
  77
  78 /* MMC controller - available on the S3C2400 */
  79 #define S3C2400_VA_MMC     S3C2400_ADDR(0x00700000)
  80 #define S3C2400_PA_MMC     (0x15A00000)
  81 #define S3C2400_SZ_MMC     SZ_1M
  82
  83 /* UARTs */
  84 #define S3C24XX_VA_UART    S3C2410_ADDR(0x00800000)
  85 #define S3C2400_PA_UART    (0x15000000)
  86 #define S3C2410_PA_UART    (0x50000000)
  87 #define S3C24XX_SZ_UART    SZ_1M
  88
  89 /* Timers */
  90 #define S3C24XX_VA_TIMER   S3C2410_ADDR(0x00900000)
  91 #define S3C2400_PA_TIMER   (0x15100000)
  92 #define S3C2410_PA_TIMER   (0x51000000)
  93 #define S3C24XX_SZ_TIMER   SZ_1M
  94
  95 /* USB Device port */
  96 #define S3C24XX_VA_USBDEV  S3C2410_ADDR(0x00A00000)
  97 #define S3C2400_PA_USBDEV  (0x15200140)
  98 #define S3C2410_PA_USBDEV  (0x52000000)
  99 #define S3C24XX_SZ_USBDEV  SZ_1M
 100
 101 /* Watchdog */
 102 #define S3C24XX_VA_WATCHDOG S3C2410_ADDR(0x00B00000)
 103 #define S3C2400_PA_WATCHDOG (0x15300000)
 104 #define S3C2410_PA_WATCHDOG (0x53000000)
 105 #define S3C24XX_SZ_WATCHDOG SZ_1M
 106
 107 /* IIC hardware controller */
 108 #define S3C24XX_VA_IIC     S3C2410_ADDR(0x00C00000)
 109 #define S3C2400_PA_IIC     (0x15400000)
 110 #define S3C2410_PA_IIC     (0x54000000)
 111 #define S3C24XX_SZ_IIC     SZ_1M
 112
 113 #define VA_IIC_BASE        (S3C24XX_VA_IIC)
 114
 115 /* IIS controller */
 116 #define S3C24XX_VA_IIS     S3C2410_ADDR(0x00D00000)
 117 #define S3C2400_PA_IIS     (0x15508000)
 118 #define S3C2410_PA_IIS     (0x55000000)
 119 #define S3C24XX_SZ_IIS     SZ_1M
 120
 121 /* GPIO ports */
 122
 123 /* the calculation for the VA of this must ensure that
 124  * it is the same distance apart from the UART in the
 125  * phsyical address space, as the initial mapping for the IO
 126  * is done as a 1:1 maping. This puts it (currently) at
 127  * 0xF6800000, which is not in the way of any current mapping
 128  * by the base system.
 129 */
 130
 131 #define S3C2400_PA_GPIO    (0x15600000)
 132 #define S3C2410_PA_GPIO    (0x56000000)
 133 #define S3C24XX_VA_GPIO    ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
 134 #define S3C24XX_SZ_GPIO    SZ_1M
 135
 136 /* RTC */
 137 #define S3C24XX_VA_RTC     S3C2410_ADDR(0x00F00000)
 138 #define S3C2400_PA_RTC     (0x15700040)
 139 #define S3C2410_PA_RTC     (0x57000000)
 140 #define S3C24XX_SZ_RTC     SZ_1M
 141
 142 /* ADC */
 143 #define S3C24XX_VA_ADC     S3C2410_ADDR(0x01000000)
 144 #define S3C2400_PA_ADC     (0x15800000)
 145 #define S3C2410_PA_ADC     (0x58000000)
 146 #define S3C24XX_SZ_ADC     SZ_1M
 147
 148 /* SPI */
 149 #define S3C24XX_VA_SPI     S3C2410_ADDR(0x01100000)
 150 #define S3C2400_PA_SPI     (0x15900000)
 151 #define S3C2410_PA_SPI     (0x59000000)
 152 #define S3C24XX_SZ_SPI     SZ_1M
 153
 154 /* SDI */
 155 #define S3C24XX_VA_SDI     S3C2410_ADDR(0x01200000)
 156 #define S3C2410_PA_SDI     (0x5A000000)
 157 #define S3C24XX_SZ_SDI     SZ_1M
 158
 159 /* CAMIF */
 160 #define S3C2440_PA_CAMIF   (0x4F000000)
 161 #define S3C2440_SZ_CAMIF   SZ_1M
 162
 163 /* ISA style IO, for each machine to sort out mappings for, if it
 164  * implements it. We reserve two 16M regions for ISA.
 165  */
 166
 167 #define S3C24XX_VA_ISA_WORD  S3C2410_ADDR(0x02000000)
 168 #define S3C24XX_VA_ISA_BYTE  S3C2410_ADDR(0x03000000)
 169
 170 /* physical addresses of all the chip-select areas */
 171
 172 #define S3C2410_CS0 (0x00000000)
 173 #define S3C2410_CS1 (0x08000000)
 174 #define S3C2410_CS2 (0x10000000)
 175 #define S3C2410_CS3 (0x18000000)
 176 #define S3C2410_CS4 (0x20000000)
 177 #define S3C2410_CS5 (0x28000000)
 178 #define S3C2410_CS6 (0x30000000)
 179 #define S3C2410_CS7 (0x38000000)
 180
 181 #define S3C2410_SDRAM_PA    (S3C2410_CS6)
 182
 183 #define S3C2400_CS0 (0x00000000)
 184 #define S3C2400_CS1 (0x02000000)
 185 #define S3C2400_CS2 (0x04000000)
 186 #define S3C2400_CS3 (0x06000000)
 187 #define S3C2400_CS4 (0x08000000)
 188 #define S3C2400_CS5 (0x0A000000)
 189 #define S3C2400_CS6 (0x0C000000)
 190 #define S3C2400_CS7 (0x0E000000)
 191
 192 #define S3C2400_SDRAM_PA    (S3C2400_CS6)
 193
 194 /* Use a single interface for common resources between S3C24XX cpus */
 195
 196 #ifdef CONFIG_CPU_S3C2400
 197 #define S3C24XX_PA_IRQ      S3C2400_PA_IRQ
 198 #define S3C24XX_PA_MEMCTRL  S3C2400_PA_MEMCTRL
 199 #define S3C24XX_PA_USBHOST  S3C2400_PA_USBHOST
 200 #define S3C24XX_PA_DMA      S3C2400_PA_DMA
 201 #define S3C24XX_PA_CLKPWR   S3C2400_PA_CLKPWR
 202 #define S3C24XX_PA_LCD      S3C2400_PA_LCD
 203 #define S3C24XX_PA_UART     S3C2400_PA_UART
 204 #define S3C24XX_PA_TIMER    S3C2400_PA_TIMER
 205 #define S3C24XX_PA_USBDEV   S3C2400_PA_USBDEV
 206 #define S3C24XX_PA_WATCHDOG S3C2400_PA_WATCHDOG
 207 #define S3C24XX_PA_IIC      S3C2400_PA_IIC
 208 #define S3C24XX_PA_IIS      S3C2400_PA_IIS
 209 #define S3C24XX_PA_GPIO     S3C2400_PA_GPIO
 210 #define S3C24XX_PA_RTC      S3C2400_PA_RTC
 211 #define S3C24XX_PA_ADC      S3C2400_PA_ADC
 212 #define S3C24XX_PA_SPI      S3C2400_PA_SPI
 213 #else
 214 #define S3C24XX_PA_IRQ      S3C2410_PA_IRQ
 215 #define S3C24XX_PA_MEMCTRL  S3C2410_PA_MEMCTRL
 216 #define S3C24XX_PA_USBHOST  S3C2410_PA_USBHOST
 217 #define S3C24XX_PA_DMA      S3C2410_PA_DMA
 218 #define S3C24XX_PA_CLKPWR   S3C2410_PA_CLKPWR
 219 #define S3C24XX_PA_LCD      S3C2410_PA_LCD
 220 #define S3C24XX_PA_UART     S3C2410_PA_UART
 221 #define S3C24XX_PA_TIMER    S3C2410_PA_TIMER
 222 #define S3C24XX_PA_USBDEV   S3C2410_PA_USBDEV
 223 #define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
 224 #define S3C24XX_PA_IIC      S3C2410_PA_IIC
 225 #define S3C24XX_PA_IIS      S3C2410_PA_IIS
 226 #define S3C24XX_PA_GPIO     S3C2410_PA_GPIO
 227 #define S3C24XX_PA_RTC      S3C2410_PA_RTC
 228 #define S3C24XX_PA_ADC      S3C2410_PA_ADC
 229 #define S3C24XX_PA_SPI      S3C2410_PA_SPI
 230 #endif
 231
 232 /* deal with the registers that move under the 2412/2413 */
 233
 234 #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
 235 #ifndef __ASSEMBLY__
 236 extern void __iomem *s3c24xx_va_gpio2;
 237 #endif
 238 #ifdef CONFIG_CPU_S3C2412_ONLY
 239 #define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)
 240 #else
 241 #define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
 242 #endif
 243 #else
 244 #define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
 245 #define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
 246 #endif
 247
 248 #endif /* __ASM_ARCH_MAP_H */