1 #ifndef __ASM_SH_SYSTEM_H
2 #define __ASM_SH_SYSTEM_H
5 * Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima
6 * Copyright (C) 2002 Paul Mundt
11 * switch_to() should switch tasks to task nr n, first
14 #define switch_to(prev, next, last) do { \
15 struct task_struct *__last; \
16 register unsigned long *__ts1 __asm__ ("r1") = &prev->thread.sp; \
17 register unsigned long *__ts2 __asm__ ("r2") = &prev->thread.pc; \
18 register unsigned long *__ts4 __asm__ ("r4") = (unsigned long *)prev; \
19 register unsigned long *__ts5 __asm__ ("r5") = (unsigned long *)next; \
20 register unsigned long *__ts6 __asm__ ("r6") = &next->thread.sp; \
21 register unsigned long __ts7 __asm__ ("r7") = next->thread.pc; \
22 __asm__ __volatile__ (".balign 4\n\t" \
23 "stc.l gbr, @-r15\n\t" \
24 "sts.l pr, @-r15\n\t" \
25 "mov.l r8, @-r15\n\t" \
26 "mov.l r9, @-r15\n\t" \
27 "mov.l r10, @-r15\n\t" \
28 "mov.l r11, @-r15\n\t" \
29 "mov.l r12, @-r15\n\t" \
30 "mov.l r13, @-r15\n\t" \
31 "mov.l r14, @-r15\n\t" \
32 "mov.l r15, @r1 ! save SP\n\t" \
33 "mov.l @r6, r15 ! change to new stack\n\t" \
35 "mov.l %0, @r2 ! save PC\n\t" \
37 "jmp @%0 ! call __switch_to\n\t" \
38 " lds r7, pr ! with return to new PC\n\t" \
41 ".long __switch_to\n" \
43 "mov.l @r15+, r14\n\t" \
44 "mov.l @r15+, r13\n\t" \
45 "mov.l @r15+, r12\n\t" \
46 "mov.l @r15+, r11\n\t" \
47 "mov.l @r15+, r10\n\t" \
48 "mov.l @r15+, r9\n\t" \
49 "mov.l @r15+, r8\n\t" \
50 "lds.l @r15+, pr\n\t" \
51 "ldc.l @r15+, gbr\n\t" \
53 : "r" (__ts1), "r" (__ts2), "r" (__ts4), \
54 "r" (__ts5), "r" (__ts6), "r" (__ts7) \
60 * On SMP systems, when the scheduler does migration-cost autodetection,
61 * it needs a way to flush as much of the CPU's caches as possible.
65 static inline void sched_cacheflush(void)
69 #define nop() __asm__ __volatile__ ("nop")
72 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
74 static __inline__
unsigned long tas(volatile int *m
)
75 { /* #define tas(ptr) (xchg((ptr),1)) */
78 __asm__
__volatile__ ("tas.b @%1\n\t"
80 : "=r" (retval
): "r" (m
): "t", "memory");
84 extern void __xchg_called_with_bad_pointer(void);
86 #define mb() __asm__ __volatile__ ("": : :"memory")
88 #define wmb() __asm__ __volatile__ ("": : :"memory")
89 #define read_barrier_depends() do { } while(0)
93 #define smp_rmb() rmb()
94 #define smp_wmb() wmb()
95 #define smp_read_barrier_depends() read_barrier_depends()
97 #define smp_mb() barrier()
98 #define smp_rmb() barrier()
99 #define smp_wmb() barrier()
100 #define smp_read_barrier_depends() do { } while(0)
103 #define set_mb(var, value) do { xchg(&var, value); } while (0)
105 /* Interrupt Control */
106 static __inline__
void local_irq_enable(void)
108 unsigned long __dummy0
, __dummy1
;
110 __asm__
__volatile__("stc sr, %0\n\t"
112 "stc r6_bank, %1\n\t"
115 : "=&r" (__dummy0
), "=r" (__dummy1
)
120 static __inline__
void local_irq_disable(void)
122 unsigned long __dummy
;
123 __asm__
__volatile__("stc sr, %0\n\t"
131 #define local_save_flags(x) \
132 __asm__("stc sr, %0; and #0xf0, %0" : "=&z" (x) :/**/: "memory" )
134 #define irqs_disabled() \
136 unsigned long flags; \
137 local_save_flags(flags); \
141 static __inline__
unsigned long local_irq_save(void)
143 unsigned long flags
, __dummy
;
145 __asm__
__volatile__("stc sr, %1\n\t"
151 : "=&z" (flags
), "=&r" (__dummy
)
158 static __inline__
void local_irq_restore(unsigned long x
)
160 if ((x
& 0x000000f0) != 0x000000f0)
164 local_save_flags(flags
);
167 extern void dump_stack(void);
168 printk(KERN_ERR
"BUG!\n");
175 #define local_irq_restore(x) do { \
176 if ((x & 0x000000f0) != 0x000000f0) \
177 local_irq_enable(); \
181 #define really_restore_flags(x) do { \
182 if ((x & 0x000000f0) != 0x000000f0) \
183 local_irq_enable(); \
185 local_irq_disable(); \
190 * When handling TLB or caches, we need to do it from P2 area.
192 #define jump_to_P2() \
194 unsigned long __dummy; \
195 __asm__ __volatile__( \
204 : "r" (0x20000000)); \
210 #define back_to_P1() \
212 unsigned long __dummy; \
213 __asm__ __volatile__( \
214 "nop;nop;nop;nop;nop;nop;nop\n\t" \
221 : "=&r" (__dummy)); \
224 /* For spinlocks etc */
225 #define local_irq_save(x) x = local_irq_save()
227 static __inline__
unsigned long xchg_u32(volatile int * m
, unsigned long val
)
229 unsigned long flags
, retval
;
231 local_irq_save(flags
);
234 local_irq_restore(flags
);
238 static __inline__
unsigned long xchg_u8(volatile unsigned char * m
, unsigned long val
)
240 unsigned long flags
, retval
;
242 local_irq_save(flags
);
245 local_irq_restore(flags
);
249 static __inline__
unsigned long __xchg(unsigned long x
, volatile void * ptr
, int size
)
253 return xchg_u32(ptr
, x
);
256 return xchg_u8(ptr
, x
);
259 __xchg_called_with_bad_pointer();
264 * disable hlt during certain critical i/o operations
266 #define HAVE_DISABLE_HLT
267 void disable_hlt(void);
268 void enable_hlt(void);
270 #define arch_align_stack(x) (x)