include/asm-arm/arch-s3c2410/dma.h

   1 /* linux/include/asm-arm/arch-bast/dma.h
   2  *
   3  * Copyright (C) 2003,2004 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * Samsung S3C2410X DMA support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Changelog:
  13  *  ??-May-2003 BJD   Created file
  14  *  ??-Jun-2003 BJD   Added more dma functionality to go with arch
  15  *  10-Nov-2004 BJD   Added sys_device support
  16 */
  17
  18 #ifndef __ASM_ARCH_DMA_H
  19 #define __ASM_ARCH_DMA_H __FILE__
  20
  21 #include <linux/config.h>
  22 #include <linux/sysdev.h>
  23 #include "hardware.h"
  24
  25
  26 /*
  27  * This is the maximum DMA address(physical address) that can be DMAd to.
  28  *
  29  */
  30 #define MAX_DMA_ADDRESS         0x20000000
  31 #define MAX_DMA_TRANSFER_SIZE   0x100000 /* Data Unit is half word  */
  32
  33
  34 /* we have 4 dma channels */
  35 #define S3C2410_DMA_CHANNELS        (4)
  36
  37 /* types */
  38
  39 typedef enum {
  40         S3C2410_DMA_IDLE,
  41         S3C2410_DMA_RUNNING,
  42         S3C2410_DMA_PAUSED
  43 } s3c2410_dma_state_t;
  44
  45
  46 /* s3c2410_dma_loadst_t
  47  *
  48  * This represents the state of the DMA engine, wrt to the loaded / running
  49  * transfers. Since we don't have any way of knowing exactly the state of
  50  * the DMA transfers, we need to know the state to make decisions on wether
  51  * we can
  52  *
  53  * S3C2410_DMA_NONE
  54  *
  55  * There are no buffers loaded (the channel should be inactive)
  56  *
  57  * S3C2410_DMA_1LOADED
  58  *
  59  * There is one buffer loaded, however it has not been confirmed to be
  60  * loaded by the DMA engine. This may be because the channel is not
  61  * yet running, or the DMA driver decided that it was too costly to
  62  * sit and wait for it to happen.
  63  *
  64  * S3C2410_DMA_1RUNNING
  65  *
  66  * The buffer has been confirmed running, and not finisged
  67  *
  68  * S3C2410_DMA_1LOADED_1RUNNING
  69  *
  70  * There is a buffer waiting to be loaded by the DMA engine, and one
  71  * currently running.
  72 */
  73
  74 typedef enum {
  75         S3C2410_DMALOAD_NONE,
  76         S3C2410_DMALOAD_1LOADED,
  77         S3C2410_DMALOAD_1RUNNING,
  78         S3C2410_DMALOAD_1LOADED_1RUNNING,
  79 } s3c2410_dma_loadst_t;
  80
  81 typedef enum {
  82         S3C2410_RES_OK,
  83         S3C2410_RES_ERR,
  84         S3C2410_RES_ABORT
  85 } s3c2410_dma_buffresult_t;
  86
  87
  88 typedef enum s3c2410_dmasrc_e s3c2410_dmasrc_t;
  89
  90 enum s3c2410_dmasrc_e {
  91         S3C2410_DMASRC_HW,      /* source is memory */
  92         S3C2410_DMASRC_MEM      /* source is hardware */
  93 };
  94
  95 /* enum s3c2410_chan_op_e
  96  *
  97  * operation codes passed to the DMA code by the user, and also used
  98  * to inform the current channel owner of any changes to the system state
  99 */
 100
 101 enum s3c2410_chan_op_e {
 102         S3C2410_DMAOP_START,
 103         S3C2410_DMAOP_STOP,
 104         S3C2410_DMAOP_PAUSE,
 105         S3C2410_DMAOP_RESUME,
 106         S3C2410_DMAOP_FLUSH,
 107         S3C2410_DMAOP_TIMEOUT,           /* internal signal to handler */
 108 };
 109
 110 typedef enum s3c2410_chan_op_e s3c2410_chan_op_t;
 111
 112 /* flags */
 113
 114 #define S3C2410_DMAF_SLOW         (1<<0)   /* slow, so don't worry about
 115                                             * waiting for reloads */
 116 #define S3C2410_DMAF_AUTOSTART    (1<<1)   /* auto-start if buffer queued */
 117
 118 /* dma buffer */
 119
 120 typedef struct s3c2410_dma_buf_s s3c2410_dma_buf_t;
 121
 122 struct s3c2410_dma_client {
 123         char                *name;
 124 };
 125
 126 typedef struct s3c2410_dma_client s3c2410_dma_client_t;
 127
 128 /* s3c2410_dma_buf_s
 129  *
 130  * internally used buffer structure to describe a queued or running
 131  * buffer.
 132 */
 133
 134 struct s3c2410_dma_buf_s {
 135         s3c2410_dma_buf_t   *next;
 136         int                  magic;        /* magic */
 137         int                  size;         /* buffer size in bytes */
 138         dma_addr_t           data;         /* start of DMA data */
 139         dma_addr_t           ptr;          /* where the DMA got to [1] */
 140         void                *id;           /* client's id */
 141 };
 142
 143 /* [1] is this updated for both recv/send modes? */
 144
 145 typedef struct s3c2410_dma_chan_s s3c2410_dma_chan_t;
 146
 147 /* s3c2410_dma_cbfn_t
 148  *
 149  * buffer callback routine type
 150 */
 151
 152 typedef void (*s3c2410_dma_cbfn_t)(s3c2410_dma_chan_t *, void *buf, int size,
 153                                    s3c2410_dma_buffresult_t result);
 154
 155 typedef int  (*s3c2410_dma_opfn_t)(s3c2410_dma_chan_t *,
 156                                    s3c2410_chan_op_t );
 157
 158 struct s3c2410_dma_stats_s {
 159         unsigned long          loads;
 160         unsigned long          timeout_longest;
 161         unsigned long          timeout_shortest;
 162         unsigned long          timeout_avg;
 163         unsigned long          timeout_failed;
 164 };
 165
 166 typedef struct s3c2410_dma_stats_s s3c2410_dma_stats_t;
 167
 168 /* struct s3c2410_dma_chan_s
 169  *
 170  * full state information for each DMA channel
 171 */
 172
 173 struct s3c2410_dma_chan_s {
 174         /* channel state flags and information */
 175         unsigned char          number;      /* number of this dma channel */
 176         unsigned char          in_use;      /* channel allocated */
 177         unsigned char          irq_claimed; /* irq claimed for channel */
 178         unsigned char          irq_enabled; /* irq enabled for channel */
 179         unsigned char          xfer_unit;   /* size of an transfer */
 180
 181         /* channel state */
 182
 183         s3c2410_dma_state_t    state;
 184         s3c2410_dma_loadst_t   load_state;
 185         s3c2410_dma_client_t  *client;
 186
 187         /* channel configuration */
 188         s3c2410_dmasrc_t       source;
 189         unsigned long          dev_addr;
 190         unsigned long          load_timeout;
 191         unsigned int           flags;        /* channel flags */
 192
 193         /* channel's hardware position and configuration */
 194         void __iomem           *regs;        /* channels registers */
 195         void __iomem           *addr_reg;    /* data address register */
 196         unsigned int           irq;          /* channel irq */
 197         unsigned long          dcon;         /* default value of DCON */
 198
 199         /* driver handles */
 200         s3c2410_dma_cbfn_t     callback_fn;  /* buffer done callback */
 201         s3c2410_dma_opfn_t     op_fn;        /* channel operation callback */
 202
 203         /* stats gathering */
 204         s3c2410_dma_stats_t   *stats;
 205         s3c2410_dma_stats_t    stats_store;
 206
 207         /* buffer list and information */
 208         s3c2410_dma_buf_t      *curr;        /* current dma buffer */
 209         s3c2410_dma_buf_t      *next;        /* next buffer to load */
 210         s3c2410_dma_buf_t      *end;         /* end of queue */
 211
 212         /* system device */
 213         struct sys_device       dev;
 214 };
 215
 216 /* the currently allocated channel information */
 217 extern s3c2410_dma_chan_t s3c2410_chans[];
 218
 219 /* note, we don't really use dma_device_t at the moment */
 220 typedef unsigned long dma_device_t;
 221
 222 /* functions --------------------------------------------------------------- */
 223
 224 /* s3c2410_dma_request
 225  *
 226  * request a dma channel exclusivley
 227 */
 228
 229 extern int s3c2410_dma_request(dmach_t channel,
 230                                s3c2410_dma_client_t *, void *dev);
 231
 232
 233 /* s3c2410_dma_ctrl
 234  *
 235  * change the state of the dma channel
 236 */
 237
 238 extern int s3c2410_dma_ctrl(dmach_t channel, s3c2410_chan_op_t op);
 239
 240 /* s3c2410_dma_setflags
 241  *
 242  * set the channel's flags to a given state
 243 */
 244
 245 extern int s3c2410_dma_setflags(dmach_t channel,
 246                                 unsigned int flags);
 247
 248 /* s3c2410_dma_free
 249  *
 250  * free the dma channel (will also abort any outstanding operations)
 251 */
 252
 253 extern int s3c2410_dma_free(dmach_t channel, s3c2410_dma_client_t *);
 254
 255 /* s3c2410_dma_enqueue
 256  *
 257  * place the given buffer onto the queue of operations for the channel.
 258  * The buffer must be allocated from dma coherent memory, or the Dcache/WB
 259  * drained before the buffer is given to the DMA system.
 260 */
 261
 262 extern int s3c2410_dma_enqueue(dmach_t channel, void *id,
 263                                dma_addr_t data, int size);
 264
 265 /* s3c2410_dma_config
 266  *
 267  * configure the dma channel
 268 */
 269
 270 extern int s3c2410_dma_config(dmach_t channel, int xferunit, int dcon);
 271
 272 /* s3c2410_dma_devconfig
 273  *
 274  * configure the device we're talking to
 275 */
 276
 277 extern int s3c2410_dma_devconfig(int channel, s3c2410_dmasrc_t source,
 278                                  int hwcfg, unsigned long devaddr);
 279
 280 /* s3c2410_dma_getposition
 281  *
 282  * get the position that the dma transfer is currently at
 283 */
 284
 285 extern int s3c2410_dma_getposition(dmach_t channel,
 286                                    dma_addr_t *src, dma_addr_t *dest);
 287
 288 extern int s3c2410_dma_set_opfn(dmach_t, s3c2410_dma_opfn_t rtn);
 289 extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn);
 290
 291 /* DMA Register definitions */
 292
 293 #define S3C2410_DMA_DISRC       (0x00)
 294 #define S3C2410_DMA_DISRCC      (0x04)
 295 #define S3C2410_DMA_DIDST       (0x08)
 296 #define S3C2410_DMA_DIDSTC      (0x0C)
 297 #define S3C2410_DMA_DCON        (0x10)
 298 #define S3C2410_DMA_DSTAT       (0x14)
 299 #define S3C2410_DMA_DCSRC       (0x18)
 300 #define S3C2410_DMA_DCDST       (0x1C)
 301 #define S3C2410_DMA_DMASKTRIG   (0x20)
 302
 303 #define S3C2410_DISRCC_INC      (1<<0)
 304 #define S3C2410_DISRCC_APB      (1<<1)
 305
 306 #define S3C2410_DMASKTRIG_STOP   (1<<2)
 307 #define S3C2410_DMASKTRIG_ON     (1<<1)
 308 #define S3C2410_DMASKTRIG_SWTRIG (1<<0)
 309
 310 #define S3C2410_DCON_DEMAND     (0<<31)
 311 #define S3C2410_DCON_HANDSHAKE  (1<<31)
 312 #define S3C2410_DCON_SYNC_PCLK  (0<<30)
 313 #define S3C2410_DCON_SYNC_HCLK  (1<<30)
 314
 315 #define S3C2410_DCON_INTREQ     (1<<29)
 316
 317 #define S3C2410_DCON_CH0_XDREQ0 (0<<24)
 318 #define S3C2410_DCON_CH0_UART0  (1<<24)
 319 #define S3C2410_DCON_CH0_SDI    (2<<24)
 320 #define S3C2410_DCON_CH0_TIMER  (3<<24)
 321 #define S3C2410_DCON_CH0_USBEP1 (4<<24)
 322
 323 #define S3C2410_DCON_CH1_XDREQ1 (0<<24)
 324 #define S3C2410_DCON_CH1_UART1  (1<<24)
 325 #define S3C2410_DCON_CH1_I2SSDI (2<<24)
 326 #define S3C2410_DCON_CH1_SPI    (3<<24)
 327 #define S3C2410_DCON_CH1_USBEP2 (4<<24)
 328
 329 #define S3C2410_DCON_CH2_I2SSDO (0<<24)
 330 #define S3C2410_DCON_CH2_I2SSDI (1<<24)
 331 #define S3C2410_DCON_CH2_SDI    (2<<24)
 332 #define S3C2410_DCON_CH2_TIMER  (3<<24)
 333 #define S3C2410_DCON_CH2_USBEP3 (4<<24)
 334
 335 #define S3C2410_DCON_CH3_UART2  (0<<24)
 336 #define S3C2410_DCON_CH3_SDI    (1<<24)
 337 #define S3C2410_DCON_CH3_SPI    (2<<24)
 338 #define S3C2410_DCON_CH3_TIMER  (3<<24)
 339 #define S3C2410_DCON_CH3_USBEP4 (4<<24)
 340
 341 #define S3C2410_DCON_SRCSHIFT   (24)
 342 #define S3C2410_DCON_SRCMASK    (7<<24)
 343
 344 #define S3C2410_DCON_BYTE       (0<<20)
 345 #define S3C2410_DCON_HALFWORD   (1<<20)
 346 #define S3C2410_DCON_WORD       (2<<20)
 347
 348 #define S3C2410_DCON_AUTORELOAD (0<<22)
 349 #define S3C2410_DCON_NORELOAD   (1<<22)
 350 #define S3C2410_DCON_HWTRIG     (1<<23)
 351
 352 #ifdef CONFIG_CPU_S3C2440
 353 #define S3C2440_DIDSTC_CHKINT   (1<<2)
 354
 355 #define S3C2440_DCON_CH0_I2SSDO (5<<24)
 356 #define S3C2440_DCON_CH0_PCMIN  (6<<24)
 357
 358 #define S3C2440_DCON_CH1_PCMOUT (5<<24)
 359 #define S3C2440_DCON_CH1_SDI    (6<<24)
 360
 361 #define S3C2440_DCON_CH2_PCMIN  (5<<24)
 362 #define S3C2440_DCON_CH2_MICIN  (6<<24)
 363
 364 #define S3C2440_DCON_CH3_MICIN  (5<<24)
 365 #define S3C2440_DCON_CH3_PCMOUT (6<<24)
 366 #endif
 367
 368 #endif /* __ASM_ARCH_DMA_H */