include/asm-arm/arch-epxa10db/mode_ctrl00.h

   1 #ifndef __MODE_CTRL00_H
   2 #define __MODE_CTRL00_H
   3
   4 /*
   5  * Register definitions for the reset and mode control
   6  */
   7
   8 /*
   9  *  Copyright (C) 2001 Altera Corporation
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  24  */
  25
  26
  27
  28 #define BOOT_CR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR  ))
  29 #define BOOT_CR_BF_MSK (0x1)
  30 #define BOOT_CR_BF_OFST (0)
  31 #define BOOT_CR_HM_MSK (0x2)
  32 #define BOOT_CR_HM_OFST (1)
  33 #define BOOT_CR_RE_MSK (0x4)
  34 #define BOOT_CR_RE_OFST (2)
  35
  36 #define RESET_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR  + 0x4 ))
  37 #define RESET_SR_WR_MSK (0x1)
  38 #define RESET_SR_WR_OFST (0)
  39 #define RESET_SR_CR_MSK (0x2)
  40 #define RESET_SR_CR_OFST (1)
  41 #define RESET_SR_JT_MSK (0x4)
  42 #define RESET_SR_JT_OFST (2)
  43 #define RESET_SR_ER_MSK (0x8)
  44 #define RESET_SR_ER_OFST (3)
  45
  46 #define ID_CODE(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR  + 0x08 ))
  47
  48 #define SRAM0_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR  + 0x20 ))
  49 #define SRAM0_SR_SIZE_MSK (0xFFFFF000)
  50 #define SRAM0_SR_SIZE_OFST (12)
  51
  52 #define SRAM1_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR  + 0x24 ))
  53 #define SRAM1_SR_SIZE_MSK (0xFFFFF000)
  54 #define SRAM1_SR_SIZE_OFST (12)
  55
  56 #define DPSRAM0_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR  + 0x30 ))
  57
  58 #define DPSRAM0_SR_MODE_MSK (0xF)
  59 #define DPSRAM0_SR_MODE_OFST (0)
  60 #define DPSRAM0_SR_GLBL_MSK (0x30)
  61 #define DPSRAM0_SR_SIZE_MSK (0xFFFFF000)
  62 #define DPSRAM0_SR_SIZE_OFST (12)
  63
  64 #define DPSRAM0_LCR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR  + 0x34 ))
  65 #define DPSRAM0_LCR_LCKADDR_MSK (0x1FFE0)
  66 #define DPSRAM0_LCR_LCKADDR_OFST (4)
  67
  68 #define DPSRAM1_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR  + 0x38 ))
  69 #define DPSRAM1_SR_MODE_MSK (0xF)
  70 #define DPSRAM1_SR_MODE_OFST (0)
  71 #define DPSRAM1_SR_GLBL_MSK (0x30)
  72 #define DPSRAM1_SR_GLBL_OFST (4)
  73 #define DPSRAM1_SR_SIZE_MSK (0xFFFFF000)
  74 #define DPSRAM1_SR_SIZE_OFST (12)
  75
  76 #define DPSRAM1_LCR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR  + 0x3C ))
  77 #define DPSRAM1_LCR_LCKADDR_MSK (0x1FFE0)
  78 #define DPSRAM1_LCR_LCKADDR_OFST (4)
  79
  80 #endif /* __MODE_CTRL00_H */