arch/arm/mach-omap1/time.c

   1 /*
   2  * linux/arch/arm/mach-omap1/time.c
   3  *
   4  * OMAP Timers
   5  *
   6  * Copyright (C) 2004 Nokia Corporation
   7  * Partial timer rewrite and additional dynamic tick timer support by
   8  * Tony Lindgen <tony@atomide.com> and
   9  * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  10  *
  11  * MPU timer code based on the older MPU timer code for OMAP
  12  * Copyright (C) 2000 RidgeRun, Inc.
  13  * Author: Greg Lonnon <glonnon@ridgerun.com>
  14  *
  15  * This program is free software; you can redistribute it and/or modify it
  16  * under the terms of the GNU General Public License as published by the
  17  * Free Software Foundation; either version 2 of the License, or (at your
  18  * option) any later version.
  19  *
  20  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  21  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  22  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  23  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  26  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  27  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  30  *
  31  * You should have received a copy of the  GNU General Public License along
  32  * with this program; if not, write  to the Free Software Foundation, Inc.,
  33  * 675 Mass Ave, Cambridge, MA 02139, USA.
  34  */
  35
  36 #include <linux/config.h>
  37 #include <linux/kernel.h>
  38 #include <linux/init.h>
  39 #include <linux/delay.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/sched.h>
  42 #include <linux/spinlock.h>
  43
  44 #include <asm/system.h>
  45 #include <asm/hardware.h>
  46 #include <asm/io.h>
  47 #include <asm/leds.h>
  48 #include <asm/irq.h>
  49 #include <asm/mach/irq.h>
  50 #include <asm/mach/time.h>
  51
  52 struct sys_timer omap_timer;
  53
  54 #ifdef CONFIG_OMAP_MPU_TIMER
  55
  56 /*
  57  * ---------------------------------------------------------------------------
  58  * MPU timer
  59  * ---------------------------------------------------------------------------
  60  */
  61 #define OMAP_MPU_TIMER_BASE             OMAP_MPU_TIMER1_BASE
  62 #define OMAP_MPU_TIMER_OFFSET           0x100
  63
  64 /* cycles to nsec conversions taken from arch/i386/kernel/timers/timer_tsc.c,
  65  * converted to use kHz by Kevin Hilman */
  66 /* convert from cycles(64bits) => nanoseconds (64bits)
  67  *  basic equation:
  68  *              ns = cycles / (freq / ns_per_sec)
  69  *              ns = cycles * (ns_per_sec / freq)
  70  *              ns = cycles * (10^9 / (cpu_khz * 10^3))
  71  *              ns = cycles * (10^6 / cpu_khz)
  72  *
  73  *      Then we use scaling math (suggested by george at mvista.com) to get:
  74  *              ns = cycles * (10^6 * SC / cpu_khz / SC
  75  *              ns = cycles * cyc2ns_scale / SC
  76  *
  77  *      And since SC is a constant power of two, we can convert the div
  78  *  into a shift.
  79  *                      -johnstul at us.ibm.com "math is hard, lets go shopping!"
  80  */
  81 static unsigned long cyc2ns_scale;
  82 #define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
  83
  84 static inline void set_cyc2ns_scale(unsigned long cpu_khz)
  85 {
  86         cyc2ns_scale = (1000000 << CYC2NS_SCALE_FACTOR)/cpu_khz;
  87 }
  88
  89 static inline unsigned long long cycles_2_ns(unsigned long long cyc)
  90 {
  91         return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR;
  92 }
  93
  94 /*
  95  * MPU_TICKS_PER_SEC must be an even number, otherwise machinecycles_to_usecs
  96  * will break. On P2, the timer count rate is 6.5 MHz after programming PTV
  97  * with 0. This divides the 13MHz input by 2, and is undocumented.
  98  */
  99 #ifdef CONFIG_MACH_OMAP_PERSEUS2
 100 /* REVISIT: This ifdef construct should be replaced by a query to clock
 101  * framework to see if timer base frequency is 12.0, 13.0 or 19.2 MHz.
 102  */
 103 #define MPU_TICKS_PER_SEC               (13000000 / 2)
 104 #else
 105 #define MPU_TICKS_PER_SEC               (12000000 / 2)
 106 #endif
 107
 108 #define MPU_TIMER_TICK_PERIOD           ((MPU_TICKS_PER_SEC / HZ) - 1)
 109
 110 typedef struct {
 111         u32 cntl;                       /* CNTL_TIMER, R/W */
 112         u32 load_tim;                   /* LOAD_TIM,   W */
 113         u32 read_tim;                   /* READ_TIM,   R */
 114 } omap_mpu_timer_regs_t;
 115
 116 #define omap_mpu_timer_base(n)                                          \
 117 ((volatile omap_mpu_timer_regs_t*)IO_ADDRESS(OMAP_MPU_TIMER_BASE +      \
 118                                  (n)*OMAP_MPU_TIMER_OFFSET))
 119
 120 static inline unsigned long omap_mpu_timer_read(int nr)
 121 {
 122         volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
 123         return timer->read_tim;
 124 }
 125
 126 static inline void omap_mpu_timer_start(int nr, unsigned long load_val)
 127 {
 128         volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
 129
 130         timer->cntl = MPU_TIMER_CLOCK_ENABLE;
 131         udelay(1);
 132         timer->load_tim = load_val;
 133         udelay(1);
 134         timer->cntl = (MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_AR | MPU_TIMER_ST);
 135 }
 136
 137 unsigned long omap_mpu_timer_ticks_to_usecs(unsigned long nr_ticks)
 138 {
 139         unsigned long long nsec;
 140
 141         nsec = cycles_2_ns((unsigned long long)nr_ticks);
 142         return (unsigned long)nsec / 1000;
 143 }
 144
 145 /*
 146  * Last processed system timer interrupt
 147  */
 148 static unsigned long omap_mpu_timer_last = 0;
 149
 150 /*
 151  * Returns elapsed usecs since last system timer interrupt
 152  */
 153 static unsigned long omap_mpu_timer_gettimeoffset(void)
 154 {
 155         unsigned long now = 0 - omap_mpu_timer_read(0);
 156         unsigned long elapsed = now - omap_mpu_timer_last;
 157
 158         return omap_mpu_timer_ticks_to_usecs(elapsed);
 159 }
 160
 161 /*
 162  * Elapsed time between interrupts is calculated using timer0.
 163  * Latency during the interrupt is calculated using timer1.
 164  * Both timer0 and timer1 are counting at 6MHz (P2 6.5MHz).
 165  */
 166 static irqreturn_t omap_mpu_timer_interrupt(int irq, void *dev_id,
 167                                         struct pt_regs *regs)
 168 {
 169         unsigned long now, latency;
 170
 171         write_seqlock(&xtime_lock);
 172         now = 0 - omap_mpu_timer_read(0);
 173         latency = MPU_TICKS_PER_SEC / HZ - omap_mpu_timer_read(1);
 174         omap_mpu_timer_last = now - latency;
 175         timer_tick(regs);
 176         write_sequnlock(&xtime_lock);
 177
 178         return IRQ_HANDLED;
 179 }
 180
 181 static struct irqaction omap_mpu_timer_irq = {
 182         .name           = "mpu timer",
 183         .flags          = SA_INTERRUPT | SA_TIMER,
 184         .handler        = omap_mpu_timer_interrupt,
 185 };
 186
 187 static unsigned long omap_mpu_timer1_overflows;
 188 static irqreturn_t omap_mpu_timer1_interrupt(int irq, void *dev_id,
 189                                              struct pt_regs *regs)
 190 {
 191         omap_mpu_timer1_overflows++;
 192         return IRQ_HANDLED;
 193 }
 194
 195 static struct irqaction omap_mpu_timer1_irq = {
 196         .name           = "mpu timer1 overflow",
 197         .flags          = SA_INTERRUPT,
 198         .handler        = omap_mpu_timer1_interrupt,
 199 };
 200
 201 static __init void omap_init_mpu_timer(void)
 202 {
 203         set_cyc2ns_scale(MPU_TICKS_PER_SEC / 1000);
 204         omap_timer.offset = omap_mpu_timer_gettimeoffset;
 205         setup_irq(INT_TIMER1, &omap_mpu_timer1_irq);
 206         setup_irq(INT_TIMER2, &omap_mpu_timer_irq);
 207         omap_mpu_timer_start(0, 0xffffffff);
 208         omap_mpu_timer_start(1, MPU_TIMER_TICK_PERIOD);
 209 }
 210
 211 /*
 212  * Scheduler clock - returns current time in nanosec units.
 213  */
 214 unsigned long long sched_clock(void)
 215 {
 216         unsigned long ticks = 0 - omap_mpu_timer_read(0);
 217         unsigned long long ticks64;
 218
 219         ticks64 = omap_mpu_timer1_overflows;
 220         ticks64 <<= 32;
 221         ticks64 |= ticks;
 222
 223         return cycles_2_ns(ticks64);
 224 }
 225 #endif  /* CONFIG_OMAP_MPU_TIMER */
 226
 227 #ifdef CONFIG_OMAP_32K_TIMER
 228
 229 #ifdef CONFIG_ARCH_OMAP1510
 230 #error OMAP 32KHz timer does not currently work on 1510!
 231 #endif
 232
 233 /*
 234  * ---------------------------------------------------------------------------
 235  * 32KHz OS timer
 236  *
 237  * This currently works only on 16xx, as 1510 does not have the continuous
 238  * 32KHz synchronous timer. The 32KHz synchronous timer is used to keep track
 239  * of time in addition to the 32KHz OS timer. Using only the 32KHz OS timer
 240  * on 1510 would be possible, but the timer would not be as accurate as
 241  * with the 32KHz synchronized timer.
 242  * ---------------------------------------------------------------------------
 243  */
 244 #define OMAP_32K_TIMER_BASE             0xfffb9000
 245 #define OMAP_32K_TIMER_CR               0x08
 246 #define OMAP_32K_TIMER_TVR              0x00
 247 #define OMAP_32K_TIMER_TCR              0x04
 248
 249 #define OMAP_32K_TICKS_PER_HZ           (32768 / HZ)
 250
 251 /*
 252  * TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1
 253  * so with HZ = 100, TVR = 327.68.
 254  */
 255 #define OMAP_32K_TIMER_TICK_PERIOD      ((32768 / HZ) - 1)
 256 #define TIMER_32K_SYNCHRONIZED          0xfffbc410
 257
 258 #define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate)                     \
 259                                 (((nr_jiffies) * (clock_rate)) / HZ)
 260
 261 static inline void omap_32k_timer_write(int val, int reg)
 262 {
 263         omap_writew(val, reg + OMAP_32K_TIMER_BASE);
 264 }
 265
 266 static inline unsigned long omap_32k_timer_read(int reg)
 267 {
 268         return omap_readl(reg + OMAP_32K_TIMER_BASE) & 0xffffff;
 269 }
 270
 271 /*
 272  * The 32KHz synchronized timer is an additional timer on 16xx.
 273  * It is always running.
 274  */
 275 static inline unsigned long omap_32k_sync_timer_read(void)
 276 {
 277         return omap_readl(TIMER_32K_SYNCHRONIZED);
 278 }
 279
 280 static inline void omap_32k_timer_start(unsigned long load_val)
 281 {
 282         omap_32k_timer_write(load_val, OMAP_32K_TIMER_TVR);
 283         omap_32k_timer_write(0x0f, OMAP_32K_TIMER_CR);
 284 }
 285
 286 static inline void omap_32k_timer_stop(void)
 287 {
 288         omap_32k_timer_write(0x0, OMAP_32K_TIMER_CR);
 289 }
 290
 291 /*
 292  * Rounds down to nearest usec. Note that this will overflow for larger values.
 293  */
 294 static inline unsigned long omap_32k_ticks_to_usecs(unsigned long ticks_32k)
 295 {
 296         return (ticks_32k * 5*5*5*5*5*5) >> 9;
 297 }
 298
 299 /*
 300  * Rounds down to nearest nsec.
 301  */
 302 static inline unsigned long long
 303 omap_32k_ticks_to_nsecs(unsigned long ticks_32k)
 304 {
 305         return (unsigned long long) ticks_32k * 1000 * 5*5*5*5*5*5 >> 9;
 306 }
 307
 308 static unsigned long omap_32k_last_tick = 0;
 309
 310 /*
 311  * Returns elapsed usecs since last 32k timer interrupt
 312  */
 313 static unsigned long omap_32k_timer_gettimeoffset(void)
 314 {
 315         unsigned long now = omap_32k_sync_timer_read();
 316         return omap_32k_ticks_to_usecs(now - omap_32k_last_tick);
 317 }
 318
 319 /*
 320  * Returns current time from boot in nsecs. It's OK for this to wrap
 321  * around for now, as it's just a relative time stamp.
 322  */
 323 unsigned long long sched_clock(void)
 324 {
 325         return omap_32k_ticks_to_nsecs(omap_32k_sync_timer_read());
 326 }
 327
 328 /*
 329  * Timer interrupt for 32KHz timer. When dynamic tick is enabled, this
 330  * function is also called from other interrupts to remove latency
 331  * issues with dynamic tick. In the dynamic tick case, we need to lock
 332  * with irqsave.
 333  */
 334 static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id,
 335                                             struct pt_regs *regs)
 336 {
 337         unsigned long flags;
 338         unsigned long now;
 339
 340         write_seqlock_irqsave(&xtime_lock, flags);
 341         now = omap_32k_sync_timer_read();
 342
 343         while (now - omap_32k_last_tick >= OMAP_32K_TICKS_PER_HZ) {
 344                 omap_32k_last_tick += OMAP_32K_TICKS_PER_HZ;
 345                 timer_tick(regs);
 346         }
 347
 348         /* Restart timer so we don't drift off due to modulo or dynamic tick.
 349          * By default we program the next timer to be continuous to avoid
 350          * latencies during high system load. During dynamic tick operation the
 351          * continuous timer can be overridden from pm_idle to be longer.
 352          */
 353         omap_32k_timer_start(omap_32k_last_tick + OMAP_32K_TICKS_PER_HZ - now);
 354         write_sequnlock_irqrestore(&xtime_lock, flags);
 355
 356         return IRQ_HANDLED;
 357 }
 358
 359 #ifdef CONFIG_NO_IDLE_HZ
 360 /*
 361  * Programs the next timer interrupt needed. Called when dynamic tick is
 362  * enabled, and to reprogram the ticks to skip from pm_idle. Note that
 363  * we can keep the timer continuous, and don't need to set it to run in
 364  * one-shot mode. This is because the timer will get reprogrammed again
 365  * after next interrupt.
 366  */
 367 void omap_32k_timer_reprogram(unsigned long next_tick)
 368 {
 369         omap_32k_timer_start(JIFFIES_TO_HW_TICKS(next_tick, 32768) + 1);
 370 }
 371
 372 static struct irqaction omap_32k_timer_irq;
 373 extern struct timer_update_handler timer_update;
 374
 375 static int omap_32k_timer_enable_dyn_tick(void)
 376 {
 377         /* No need to reprogram timer, just use the next interrupt */
 378         return 0;
 379 }
 380
 381 static int omap_32k_timer_disable_dyn_tick(void)
 382 {
 383         omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
 384         return 0;
 385 }
 386
 387 static struct dyn_tick_timer omap_dyn_tick_timer = {
 388         .enable         = omap_32k_timer_enable_dyn_tick,
 389         .disable        = omap_32k_timer_disable_dyn_tick,
 390         .reprogram      = omap_32k_timer_reprogram,
 391         .handler        = omap_32k_timer_interrupt,
 392 };
 393 #endif  /* CONFIG_NO_IDLE_HZ */
 394
 395 static struct irqaction omap_32k_timer_irq = {
 396         .name           = "32KHz timer",
 397         .flags          = SA_INTERRUPT | SA_TIMER,
 398         .handler        = omap_32k_timer_interrupt,
 399 };
 400
 401 static __init void omap_init_32k_timer(void)
 402 {
 403
 404 #ifdef CONFIG_NO_IDLE_HZ
 405         omap_timer.dyn_tick = &omap_dyn_tick_timer;
 406 #endif
 407
 408         setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
 409         omap_timer.offset  = omap_32k_timer_gettimeoffset;
 410         omap_32k_last_tick = omap_32k_sync_timer_read();
 411         omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
 412 }
 413 #endif  /* CONFIG_OMAP_32K_TIMER */
 414
 415 /*
 416  * ---------------------------------------------------------------------------
 417  * Timer initialization
 418  * ---------------------------------------------------------------------------
 419  */
 420 static void __init omap_timer_init(void)
 421 {
 422 #if defined(CONFIG_OMAP_MPU_TIMER)
 423         omap_init_mpu_timer();
 424 #elif defined(CONFIG_OMAP_32K_TIMER)
 425         omap_init_32k_timer();
 426 #else
 427 #error No system timer selected in Kconfig!
 428 #endif
 429 }
 430
 431 struct sys_timer omap_timer = {
 432         .init           = omap_timer_init,
 433         .offset         = NULL,         /* Initialized later */
 434 };