arch/ia64/pci/pci.c

   1 /*
   2  * pci.c - Low-Level PCI Access in IA-64
   3  *
   4  * Derived from bios32.c of i386 tree.
   5  *
   6  * (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P.
   7  *      David Mosberger-Tang <davidm@hpl.hp.com>
   8  *      Bjorn Helgaas <bjorn.helgaas@hp.com>
   9  * Copyright (C) 2004 Silicon Graphics, Inc.
  10  *
  11  * Note: Above list of copyright holders is incomplete...
  12  */
  13 #include <linux/config.h>
  14
  15 #include <linux/acpi.h>
  16 #include <linux/types.h>
  17 #include <linux/kernel.h>
  18 #include <linux/pci.h>
  19 #include <linux/init.h>
  20 #include <linux/ioport.h>
  21 #include <linux/slab.h>
  22 #include <linux/smp_lock.h>
  23 #include <linux/spinlock.h>
  24
  25 #include <asm/machvec.h>
  26 #include <asm/page.h>
  27 #include <asm/system.h>
  28 #include <asm/io.h>
  29 #include <asm/sal.h>
  30 #include <asm/smp.h>
  31 #include <asm/irq.h>
  32 #include <asm/hw_irq.h>
  33
  34
  35 /*
  36  * Low-level SAL-based PCI configuration access functions. Note that SAL
  37  * calls are already serialized (via sal_lock), so we don't need another
  38  * synchronization mechanism here.
  39  */
  40
  41 #define PCI_SAL_ADDRESS(seg, bus, devfn, reg)           \
  42         (((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg))
  43
  44 /* SAL 3.2 adds support for extended config space. */
  45
  46 #define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg)       \
  47         (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg))
  48
  49 static int
  50 pci_sal_read (unsigned int seg, unsigned int bus, unsigned int devfn,
  51               int reg, int len, u32 *value)
  52 {
  53         u64 addr, data = 0;
  54         int mode, result;
  55
  56         if (!value || (seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
  57                 return -EINVAL;
  58
  59         if ((seg | reg) <= 255) {
  60                 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
  61                 mode = 0;
  62         } else {
  63                 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
  64                 mode = 1;
  65         }
  66         result = ia64_sal_pci_config_read(addr, mode, len, &data);
  67         if (result != 0)
  68                 return -EINVAL;
  69
  70         *value = (u32) data;
  71         return 0;
  72 }
  73
  74 static int
  75 pci_sal_write (unsigned int seg, unsigned int bus, unsigned int devfn,
  76                int reg, int len, u32 value)
  77 {
  78         u64 addr;
  79         int mode, result;
  80
  81         if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
  82                 return -EINVAL;
  83
  84         if ((seg | reg) <= 255) {
  85                 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
  86                 mode = 0;
  87         } else {
  88                 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
  89                 mode = 1;
  90         }
  91         result = ia64_sal_pci_config_write(addr, mode, len, value);
  92         if (result != 0)
  93                 return -EINVAL;
  94         return 0;
  95 }
  96
  97 static struct pci_raw_ops pci_sal_ops = {
  98         .read =         pci_sal_read,
  99         .write =        pci_sal_write
 100 };
 101
 102 struct pci_raw_ops *raw_pci_ops = &pci_sal_ops;
 103
 104 static int
 105 pci_read (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
 106 {
 107         return raw_pci_ops->read(pci_domain_nr(bus), bus->number,
 108                                  devfn, where, size, value);
 109 }
 110
 111 static int
 112 pci_write (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
 113 {
 114         return raw_pci_ops->write(pci_domain_nr(bus), bus->number,
 115                                   devfn, where, size, value);
 116 }
 117
 118 struct pci_ops pci_root_ops = {
 119         .read = pci_read,
 120         .write = pci_write,
 121 };
 122
 123 #ifdef CONFIG_NUMA
 124 extern acpi_status acpi_map_iosapic(acpi_handle, u32, void *, void **);
 125 static void acpi_map_iosapics(void)
 126 {
 127         acpi_get_devices(NULL, acpi_map_iosapic, NULL, NULL);
 128 }
 129 #else
 130 static void acpi_map_iosapics(void)
 131 {
 132         return;
 133 }
 134 #endif /* CONFIG_NUMA */
 135
 136 static int __init
 137 pci_acpi_init (void)
 138 {
 139         acpi_map_iosapics();
 140
 141         return 0;
 142 }
 143
 144 subsys_initcall(pci_acpi_init);
 145
 146 /* Called by ACPI when it finds a new root bus.  */
 147
 148 static struct pci_controller * __devinit
 149 alloc_pci_controller (int seg)
 150 {
 151         struct pci_controller *controller;
 152
 153         controller = kmalloc(sizeof(*controller), GFP_KERNEL);
 154         if (!controller)
 155                 return NULL;
 156
 157         memset(controller, 0, sizeof(*controller));
 158         controller->segment = seg;
 159         controller->node = -1;
 160         return controller;
 161 }
 162
 163 static u64 __devinit
 164 add_io_space (struct acpi_resource_address64 *addr)
 165 {
 166         u64 offset;
 167         int sparse = 0;
 168         int i;
 169
 170         if (addr->address_translation_offset == 0)
 171                 return IO_SPACE_BASE(0);        /* part of legacy IO space */
 172
 173         if (addr->attribute.io.translation_attribute == ACPI_SPARSE_TRANSLATION)
 174                 sparse = 1;
 175
 176         offset = (u64) ioremap(addr->address_translation_offset, 0);
 177         for (i = 0; i < num_io_spaces; i++)
 178                 if (io_space[i].mmio_base == offset &&
 179                     io_space[i].sparse == sparse)
 180                         return IO_SPACE_BASE(i);
 181
 182         if (num_io_spaces == MAX_IO_SPACES) {
 183                 printk("Too many IO port spaces\n");
 184                 return ~0;
 185         }
 186
 187         i = num_io_spaces++;
 188         io_space[i].mmio_base = offset;
 189         io_space[i].sparse = sparse;
 190
 191         return IO_SPACE_BASE(i);
 192 }
 193
 194 static acpi_status __devinit
 195 count_window (struct acpi_resource *resource, void *data)
 196 {
 197         unsigned int *windows = (unsigned int *) data;
 198         struct acpi_resource_address64 addr;
 199         acpi_status status;
 200
 201         status = acpi_resource_to_address64(resource, &addr);
 202         if (ACPI_SUCCESS(status))
 203                 if (addr.resource_type == ACPI_MEMORY_RANGE ||
 204                     addr.resource_type == ACPI_IO_RANGE)
 205                         (*windows)++;
 206
 207         return AE_OK;
 208 }
 209
 210 struct pci_root_info {
 211         struct pci_controller *controller;
 212         char *name;
 213 };
 214
 215 static __devinit acpi_status add_window(struct acpi_resource *res, void *data)
 216 {
 217         struct pci_root_info *info = data;
 218         struct pci_window *window;
 219         struct acpi_resource_address64 addr;
 220         acpi_status status;
 221         unsigned long flags, offset = 0;
 222         struct resource *root;
 223
 224         status = acpi_resource_to_address64(res, &addr);
 225         if (!ACPI_SUCCESS(status))
 226                 return AE_OK;
 227
 228         if (!addr.address_length)
 229                 return AE_OK;
 230
 231         if (addr.resource_type == ACPI_MEMORY_RANGE) {
 232                 flags = IORESOURCE_MEM;
 233                 root = &iomem_resource;
 234                 offset = addr.address_translation_offset;
 235         } else if (addr.resource_type == ACPI_IO_RANGE) {
 236                 flags = IORESOURCE_IO;
 237                 root = &ioport_resource;
 238                 offset = add_io_space(&addr);
 239                 if (offset == ~0)
 240                         return AE_OK;
 241         } else
 242                 return AE_OK;
 243
 244         window = &info->controller->window[info->controller->windows++];
 245         window->resource.name = info->name;
 246         window->resource.flags = flags;
 247         window->resource.start = addr.min_address_range + offset;
 248         window->resource.end = addr.max_address_range + offset;
 249         window->resource.child = NULL;
 250         window->offset = offset;
 251
 252         if (insert_resource(root, &window->resource)) {
 253                 printk(KERN_ERR "alloc 0x%lx-0x%lx from %s for %s failed\n",
 254                         window->resource.start, window->resource.end,
 255                         root->name, info->name);
 256         }
 257
 258         return AE_OK;
 259 }
 260
 261 static void __devinit
 262 pcibios_setup_root_windows(struct pci_bus *bus, struct pci_controller *ctrl)
 263 {
 264         int i, j;
 265
 266         j = 0;
 267         for (i = 0; i < ctrl->windows; i++) {
 268                 struct resource *res = &ctrl->window[i].resource;
 269                 /* HP's firmware has a hack to work around a Windows bug.
 270                  * Ignore these tiny memory ranges */
 271                 if ((res->flags & IORESOURCE_MEM) &&
 272                     (res->end - res->start < 16))
 273                         continue;
 274                 if (j >= PCI_BUS_NUM_RESOURCES) {
 275                         printk("Ignoring range [%lx-%lx] (%lx)\n", res->start,
 276                                         res->end, res->flags);
 277                         continue;
 278                 }
 279                 bus->resource[j++] = res;
 280         }
 281 }
 282
 283 struct pci_bus * __devinit
 284 pci_acpi_scan_root(struct acpi_device *device, int domain, int bus)
 285 {
 286         struct pci_root_info info;
 287         struct pci_controller *controller;
 288         unsigned int windows = 0;
 289         struct pci_bus *pbus;
 290         char *name;
 291         int pxm;
 292
 293         controller = alloc_pci_controller(domain);
 294         if (!controller)
 295                 goto out1;
 296
 297         controller->acpi_handle = device->handle;
 298
 299         pxm = acpi_get_pxm(controller->acpi_handle);
 300 #ifdef CONFIG_NUMA
 301         if (pxm >= 0)
 302                 controller->node = pxm_to_nid_map[pxm];
 303 #endif
 304
 305         acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window,
 306                         &windows);
 307         controller->window = kmalloc_node(sizeof(*controller->window) * windows,
 308                         GFP_KERNEL, controller->node);
 309         if (!controller->window)
 310                 goto out2;
 311
 312         name = kmalloc(16, GFP_KERNEL);
 313         if (!name)
 314                 goto out3;
 315
 316         sprintf(name, "PCI Bus %04x:%02x", domain, bus);
 317         info.controller = controller;
 318         info.name = name;
 319         acpi_walk_resources(device->handle, METHOD_NAME__CRS, add_window,
 320                         &info);
 321
 322         pbus = pci_scan_bus_parented(NULL, bus, &pci_root_ops, controller);
 323         if (pbus)
 324                 pcibios_setup_root_windows(pbus, controller);
 325
 326         return pbus;
 327
 328 out3:
 329         kfree(controller->window);
 330 out2:
 331         kfree(controller);
 332 out1:
 333         return NULL;
 334 }
 335
 336 void pcibios_resource_to_bus(struct pci_dev *dev,
 337                 struct pci_bus_region *region, struct resource *res)
 338 {
 339         struct pci_controller *controller = PCI_CONTROLLER(dev);
 340         unsigned long offset = 0;
 341         int i;
 342
 343         for (i = 0; i < controller->windows; i++) {
 344                 struct pci_window *window = &controller->window[i];
 345                 if (!(window->resource.flags & res->flags))
 346                         continue;
 347                 if (window->resource.start > res->start)
 348                         continue;
 349                 if (window->resource.end < res->end)
 350                         continue;
 351                 offset = window->offset;
 352                 break;
 353         }
 354
 355         region->start = res->start - offset;
 356         region->end = res->end - offset;
 357 }
 358 EXPORT_SYMBOL(pcibios_resource_to_bus);
 359
 360 void pcibios_bus_to_resource(struct pci_dev *dev,
 361                 struct resource *res, struct pci_bus_region *region)
 362 {
 363         struct pci_controller *controller = PCI_CONTROLLER(dev);
 364         unsigned long offset = 0;
 365         int i;
 366
 367         for (i = 0; i < controller->windows; i++) {
 368                 struct pci_window *window = &controller->window[i];
 369                 if (!(window->resource.flags & res->flags))
 370                         continue;
 371                 if (window->resource.start - window->offset > region->start)
 372                         continue;
 373                 if (window->resource.end - window->offset < region->end)
 374                         continue;
 375                 offset = window->offset;
 376                 break;
 377         }
 378
 379         res->start = region->start + offset;
 380         res->end = region->end + offset;
 381 }
 382 EXPORT_SYMBOL(pcibios_bus_to_resource);
 383
 384 static int __devinit is_valid_resource(struct pci_dev *dev, int idx)
 385 {
 386         unsigned int i, type_mask = IORESOURCE_IO | IORESOURCE_MEM;
 387         struct resource *devr = &dev->resource[idx];
 388
 389         if (!dev->bus)
 390                 return 0;
 391         for (i=0; i<PCI_BUS_NUM_RESOURCES; i++) {
 392                 struct resource *busr = dev->bus->resource[i];
 393
 394                 if (!busr || ((busr->flags ^ devr->flags) & type_mask))
 395                         continue;
 396                 if ((devr->start) && (devr->start >= busr->start) &&
 397                                 (devr->end <= busr->end))
 398                         return 1;
 399         }
 400         return 0;
 401 }
 402
 403 static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev)
 404 {
 405         struct pci_bus_region region;
 406         int i;
 407         int limit = (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) ? \
 408                 PCI_BRIDGE_RESOURCES : PCI_NUM_RESOURCES;
 409
 410         for (i = 0; i < limit; i++) {
 411                 if (!dev->resource[i].flags)
 412                         continue;
 413                 region.start = dev->resource[i].start;
 414                 region.end = dev->resource[i].end;
 415                 pcibios_bus_to_resource(dev, &dev->resource[i], &region);
 416                 if ((is_valid_resource(dev, i)))
 417                         pci_claim_resource(dev, i);
 418         }
 419 }
 420
 421 /*
 422  *  Called after each bus is probed, but before its children are examined.
 423  */
 424 void __devinit
 425 pcibios_fixup_bus (struct pci_bus *b)
 426 {
 427         struct pci_dev *dev;
 428
 429         if (b->self) {
 430                 pci_read_bridge_bases(b);
 431                 pcibios_fixup_device_resources(b->self);
 432         }
 433         list_for_each_entry(dev, &b->devices, bus_list)
 434                 pcibios_fixup_device_resources(dev);
 435
 436         return;
 437 }
 438
 439 void __devinit
 440 pcibios_update_irq (struct pci_dev *dev, int irq)
 441 {
 442         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 443
 444         /* ??? FIXME -- record old value for shutdown.  */
 445 }
 446
 447 static inline int
 448 pcibios_enable_resources (struct pci_dev *dev, int mask)
 449 {
 450         u16 cmd, old_cmd;
 451         int idx;
 452         struct resource *r;
 453         unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM;
 454
 455         if (!dev)
 456                 return -EINVAL;
 457
 458         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 459         old_cmd = cmd;
 460         for (idx=0; idx<PCI_NUM_RESOURCES; idx++) {
 461                 /* Only set up the desired resources.  */
 462                 if (!(mask & (1 << idx)))
 463                         continue;
 464
 465                 r = &dev->resource[idx];
 466                 if (!(r->flags & type_mask))
 467                         continue;
 468                 if ((idx == PCI_ROM_RESOURCE) &&
 469                                 (!(r->flags & IORESOURCE_ROM_ENABLE)))
 470                         continue;
 471                 if (!r->start && r->end) {
 472                         printk(KERN_ERR
 473                                "PCI: Device %s not available because of resource collisions\n",
 474                                pci_name(dev));
 475                         return -EINVAL;
 476                 }
 477                 if (r->flags & IORESOURCE_IO)
 478                         cmd |= PCI_COMMAND_IO;
 479                 if (r->flags & IORESOURCE_MEM)
 480                         cmd |= PCI_COMMAND_MEMORY;
 481         }
 482         if (cmd != old_cmd) {
 483                 printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
 484                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 485         }
 486         return 0;
 487 }
 488
 489 int
 490 pcibios_enable_device (struct pci_dev *dev, int mask)
 491 {
 492         int ret;
 493
 494         ret = pcibios_enable_resources(dev, mask);
 495         if (ret < 0)
 496                 return ret;
 497
 498         return acpi_pci_irq_enable(dev);
 499 }
 500
 501 void
 502 pcibios_disable_device (struct pci_dev *dev)
 503 {
 504         acpi_pci_irq_disable(dev);
 505 }
 506
 507 void
 508 pcibios_align_resource (void *data, struct resource *res,
 509                         unsigned long size, unsigned long align)
 510 {
 511 }
 512
 513 /*
 514  * PCI BIOS setup, always defaults to SAL interface
 515  */
 516 char * __init
 517 pcibios_setup (char *str)
 518 {
 519         return NULL;
 520 }
 521
 522 int
 523 pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
 524                      enum pci_mmap_state mmap_state, int write_combine)
 525 {
 526         /*
 527          * I/O space cannot be accessed via normal processor loads and
 528          * stores on this platform.
 529          */
 530         if (mmap_state == pci_mmap_io)
 531                 /*
 532                  * XXX we could relax this for I/O spaces for which ACPI
 533                  * indicates that the space is 1-to-1 mapped.  But at the
 534                  * moment, we don't support multiple PCI address spaces and
 535                  * the legacy I/O space is not 1-to-1 mapped, so this is moot.
 536                  */
 537                 return -EINVAL;
 538
 539         /*
 540          * Leave vm_pgoff as-is, the PCI space address is the physical
 541          * address on this platform.
 542          */
 543         vma->vm_flags |= (VM_SHM | VM_RESERVED | VM_IO);
 544
 545         if (write_combine && efi_range_is_wc(vma->vm_start,
 546                                              vma->vm_end - vma->vm_start))
 547                 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
 548         else
 549                 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
 550
 551         if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
 552                              vma->vm_end - vma->vm_start, vma->vm_page_prot))
 553                 return -EAGAIN;
 554
 555         return 0;
 556 }
 557
 558 /**
 559  * ia64_pci_get_legacy_mem - generic legacy mem routine
 560  * @bus: bus to get legacy memory base address for
 561  *
 562  * Find the base of legacy memory for @bus.  This is typically the first
 563  * megabyte of bus address space for @bus or is simply 0 on platforms whose
 564  * chipsets support legacy I/O and memory routing.  Returns the base address
 565  * or an error pointer if an error occurred.
 566  *
 567  * This is the ia64 generic version of this routine.  Other platforms
 568  * are free to override it with a machine vector.
 569  */
 570 char *ia64_pci_get_legacy_mem(struct pci_bus *bus)
 571 {
 572         return (char *)__IA64_UNCACHED_OFFSET;
 573 }
 574
 575 /**
 576  * pci_mmap_legacy_page_range - map legacy memory space to userland
 577  * @bus: bus whose legacy space we're mapping
 578  * @vma: vma passed in by mmap
 579  *
 580  * Map legacy memory space for this device back to userspace using a machine
 581  * vector to get the base address.
 582  */
 583 int
 584 pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma)
 585 {
 586         char *addr;
 587
 588         addr = pci_get_legacy_mem(bus);
 589         if (IS_ERR(addr))
 590                 return PTR_ERR(addr);
 591
 592         vma->vm_pgoff += (unsigned long)addr >> PAGE_SHIFT;
 593         vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
 594         vma->vm_flags |= (VM_SHM | VM_RESERVED | VM_IO);
 595
 596         if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
 597                             vma->vm_end - vma->vm_start, vma->vm_page_prot))
 598                 return -EAGAIN;
 599
 600         return 0;
 601 }
 602
 603 /**
 604  * ia64_pci_legacy_read - read from legacy I/O space
 605  * @bus: bus to read
 606  * @port: legacy port value
 607  * @val: caller allocated storage for returned value
 608  * @size: number of bytes to read
 609  *
 610  * Simply reads @size bytes from @port and puts the result in @val.
 611  *
 612  * Again, this (and the write routine) are generic versions that can be
 613  * overridden by the platform.  This is necessary on platforms that don't
 614  * support legacy I/O routing or that hard fail on legacy I/O timeouts.
 615  */
 616 int ia64_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size)
 617 {
 618         int ret = size;
 619
 620         switch (size) {
 621         case 1:
 622                 *val = inb(port);
 623                 break;
 624         case 2:
 625                 *val = inw(port);
 626                 break;
 627         case 4:
 628                 *val = inl(port);
 629                 break;
 630         default:
 631                 ret = -EINVAL;
 632                 break;
 633         }
 634
 635         return ret;
 636 }
 637
 638 /**
 639  * ia64_pci_legacy_write - perform a legacy I/O write
 640  * @bus: bus pointer
 641  * @port: port to write
 642  * @val: value to write
 643  * @size: number of bytes to write from @val
 644  *
 645  * Simply writes @size bytes of @val to @port.
 646  */
 647 int ia64_pci_legacy_write(struct pci_dev *bus, u16 port, u32 val, u8 size)
 648 {
 649         int ret = 0;
 650
 651         switch (size) {
 652         case 1:
 653                 outb(val, port);
 654                 break;
 655         case 2:
 656                 outw(val, port);
 657                 break;
 658         case 4:
 659                 outl(val, port);
 660                 break;
 661         default:
 662                 ret = -EINVAL;
 663                 break;
 664         }
 665
 666         return ret;
 667 }
 668
 669 /**
 670  * pci_cacheline_size - determine cacheline size for PCI devices
 671  * @dev: void
 672  *
 673  * We want to use the line-size of the outer-most cache.  We assume
 674  * that this line-size is the same for all CPUs.
 675  *
 676  * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
 677  *
 678  * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
 679  */
 680 static unsigned long
 681 pci_cacheline_size (void)
 682 {
 683         u64 levels, unique_caches;
 684         s64 status;
 685         pal_cache_config_info_t cci;
 686         static u8 cacheline_size;
 687
 688         if (cacheline_size)
 689                 return cacheline_size;
 690
 691         status = ia64_pal_cache_summary(&levels, &unique_caches);
 692         if (status != 0) {
 693                 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
 694                        __FUNCTION__, status);
 695                 return SMP_CACHE_BYTES;
 696         }
 697
 698         status = ia64_pal_cache_config_info(levels - 1, /* cache_type (data_or_unified)= */ 2,
 699                                             &cci);
 700         if (status != 0) {
 701                 printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed (status=%ld)\n",
 702                        __FUNCTION__, status);
 703                 return SMP_CACHE_BYTES;
 704         }
 705         cacheline_size = 1 << cci.pcci_line_size;
 706         return cacheline_size;
 707 }
 708
 709 /**
 710  * pcibios_prep_mwi - helper function for drivers/pci/pci.c:pci_set_mwi()
 711  * @dev: the PCI device for which MWI is enabled
 712  *
 713  * For ia64, we can get the cacheline sizes from PAL.
 714  *
 715  * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
 716  */
 717 int
 718 pcibios_prep_mwi (struct pci_dev *dev)
 719 {
 720         unsigned long desired_linesize, current_linesize;
 721         int rc = 0;
 722         u8 pci_linesize;
 723
 724         desired_linesize = pci_cacheline_size();
 725
 726         pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &pci_linesize);
 727         current_linesize = 4 * pci_linesize;
 728         if (desired_linesize != current_linesize) {
 729                 printk(KERN_WARNING "PCI: slot %s has incorrect PCI cache line size of %lu bytes,",
 730                        pci_name(dev), current_linesize);
 731                 if (current_linesize > desired_linesize) {
 732                         printk(" expected %lu bytes instead\n", desired_linesize);
 733                         rc = -EINVAL;
 734                 } else {
 735                         printk(" correcting to %lu\n", desired_linesize);
 736                         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, desired_linesize / 4);
 737                 }
 738         }
 739         return rc;
 740 }
 741
 742 int pci_vector_resources(int last, int nr_released)
 743 {
 744         int count = nr_released;
 745
 746         count += (IA64_LAST_DEVICE_VECTOR - last);
 747
 748         return count;
 749 }