arch/ppc/syslib/ppc83xx_setup.c

   1 /*
   2  * arch/ppc/syslib/ppc83xx_setup.c
   3  *
   4  * MPC83XX common board code
   5  *
   6  * Maintainer: Kumar Gala <kumar.gala@freescale.com>
   7  *
   8  * Copyright 2005 Freescale Semiconductor Inc.
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful, but
  16  * WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18  * General Public License for more details.
  19  *
  20  * You should have received a copy of the  GNU General Public License along
  21  * with this program; if not, write  to the Free Software Foundation, Inc.,
  22  * 675 Mass Ave, Cambridge, MA 02139, USA.
  23  *
  24  * Added PCI support -- Tony Li <tony.li@freescale.com>
  25  */
  26
  27 #include <linux/config.h>
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/init.h>
  31 #include <linux/pci.h>
  32 #include <linux/serial.h>
  33 #include <linux/tty.h>  /* for linux/serial_core.h */
  34 #include <linux/serial_core.h>
  35 #include <linux/serial_8250.h>
  36
  37 #include <asm/time.h>
  38 #include <asm/mpc83xx.h>
  39 #include <asm/mmu.h>
  40 #include <asm/ppc_sys.h>
  41 #include <asm/kgdb.h>
  42 #include <asm/delay.h>
  43
  44 #include <syslib/ppc83xx_setup.h>
  45 #if defined(CONFIG_PCI)
  46 #include <asm/delay.h>
  47 #include <syslib/ppc83xx_pci.h>
  48 #endif
  49
  50 phys_addr_t immrbar;
  51
  52 /* Return the amount of memory */
  53 unsigned long __init
  54 mpc83xx_find_end_of_memory(void)
  55 {
  56         bd_t *binfo;
  57
  58         binfo = (bd_t *) __res;
  59
  60         return binfo->bi_memsize;
  61 }
  62
  63 long __init
  64 mpc83xx_time_init(void)
  65 {
  66 #define SPCR_OFFS   0x00000110
  67 #define SPCR_TBEN   0x00400000
  68
  69         bd_t *binfo = (bd_t *)__res;
  70         u32 *spcr = ioremap(binfo->bi_immr_base + SPCR_OFFS, 4);
  71
  72         *spcr |= SPCR_TBEN;
  73
  74         iounmap(spcr);
  75
  76         return 0;
  77 }
  78
  79 /* The decrementer counts at the system (internal) clock freq divided by 4 */
  80 void __init
  81 mpc83xx_calibrate_decr(void)
  82 {
  83         bd_t *binfo = (bd_t *) __res;
  84         unsigned int freq, divisor;
  85
  86         freq = binfo->bi_busfreq;
  87         divisor = 4;
  88         tb_ticks_per_jiffy = freq / HZ / divisor;
  89         tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000);
  90 }
  91
  92 #ifdef CONFIG_SERIAL_8250
  93 void __init
  94 mpc83xx_early_serial_map(void)
  95 {
  96 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
  97         struct uart_port serial_req;
  98 #endif
  99         struct plat_serial8250_port *pdata;
 100         bd_t *binfo = (bd_t *) __res;
 101         pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC83xx_DUART);
 102
 103         /* Setup serial port access */
 104         pdata[0].uartclk = binfo->bi_busfreq;
 105         pdata[0].mapbase += binfo->bi_immr_base;
 106         pdata[0].membase = ioremap(pdata[0].mapbase, 0x100);
 107
 108 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 109         memset(&serial_req, 0, sizeof (serial_req));
 110         serial_req.iotype = SERIAL_IO_MEM;
 111         serial_req.mapbase = pdata[0].mapbase;
 112         serial_req.membase = pdata[0].membase;
 113         serial_req.regshift = 0;
 114
 115         gen550_init(0, &serial_req);
 116 #endif
 117
 118         pdata[1].uartclk = binfo->bi_busfreq;
 119         pdata[1].mapbase += binfo->bi_immr_base;
 120         pdata[1].membase = ioremap(pdata[1].mapbase, 0x100);
 121
 122 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 123         /* Assume gen550_init() doesn't modify serial_req */
 124         serial_req.mapbase = pdata[1].mapbase;
 125         serial_req.membase = pdata[1].membase;
 126
 127         gen550_init(1, &serial_req);
 128 #endif
 129 }
 130 #endif
 131
 132 void
 133 mpc83xx_restart(char *cmd)
 134 {
 135         volatile unsigned char __iomem *reg;
 136         unsigned char tmp;
 137
 138         reg = ioremap(BCSR_PHYS_ADDR, BCSR_SIZE);
 139
 140         local_irq_disable();
 141
 142         /*
 143          * Unlock the BCSR bits so a PRST will update the contents.
 144          * Otherwise the reset asserts but doesn't clear.
 145          */
 146         tmp = in_8(reg + BCSR_MISC_REG3_OFF);
 147         tmp |= BCSR_MISC_REG3_CNFLOCK; /* low true, high false */
 148         out_8(reg + BCSR_MISC_REG3_OFF, tmp);
 149
 150         /*
 151          * Trigger a reset via a low->high transition of the
 152          * PORESET bit.
 153          */
 154         tmp = in_8(reg + BCSR_MISC_REG2_OFF);
 155         tmp &= ~BCSR_MISC_REG2_PORESET;
 156         out_8(reg + BCSR_MISC_REG2_OFF, tmp);
 157
 158         udelay(1);
 159
 160         tmp |= BCSR_MISC_REG2_PORESET;
 161         out_8(reg + BCSR_MISC_REG2_OFF, tmp);
 162
 163         for(;;);
 164 }
 165
 166 void
 167 mpc83xx_power_off(void)
 168 {
 169         local_irq_disable();
 170         for(;;);
 171 }
 172
 173 void
 174 mpc83xx_halt(void)
 175 {
 176         local_irq_disable();
 177         for(;;);
 178 }
 179
 180 #if defined(CONFIG_PCI)
 181 void __init
 182 mpc83xx_setup_pci1(struct pci_controller *hose)
 183 {
 184         u16 reg16;
 185         volatile immr_pcictrl_t * pci_ctrl;
 186         volatile immr_ios_t * ios;
 187         bd_t *binfo = (bd_t *) __res;
 188
 189         pci_ctrl = ioremap(binfo->bi_immr_base + 0x8500, sizeof(immr_pcictrl_t));
 190         ios = ioremap(binfo->bi_immr_base + 0x8400, sizeof(immr_ios_t));
 191
 192         /*
 193          * Configure PCI Outbound Translation Windows
 194          */
 195         ios->potar0 = (MPC83xx_PCI1_LOWER_MEM >> 12) & POTAR_TA_MASK;
 196         ios->pobar0 = (MPC83xx_PCI1_LOWER_MEM >> 12) & POBAR_BA_MASK;
 197         ios->pocmr0 = POCMR_EN |
 198                 (((0xffffffff - (MPC83xx_PCI1_UPPER_MEM -
 199                                 MPC83xx_PCI1_LOWER_MEM)) >> 12) & POCMR_CM_MASK);
 200
 201         /* mapped to PCI1 IO space */
 202         ios->potar1 = (MPC83xx_PCI1_LOWER_IO >> 12) & POTAR_TA_MASK;
 203         ios->pobar1 = (MPC83xx_PCI1_IO_BASE >> 12) & POBAR_BA_MASK;
 204         ios->pocmr1 = POCMR_EN | POCMR_IO |
 205                 (((0xffffffff - (MPC83xx_PCI1_UPPER_IO -
 206                                 MPC83xx_PCI1_LOWER_IO)) >> 12) & POCMR_CM_MASK);
 207
 208         /*
 209          * Configure PCI Inbound Translation Windows
 210          */
 211         pci_ctrl->pitar1 = 0x0;
 212         pci_ctrl->pibar1 = 0x0;
 213         pci_ctrl->piebar1 = 0x0;
 214         pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;
 215
 216         /*
 217          * Release PCI RST signal
 218          */
 219         pci_ctrl->gcr = 0;
 220         udelay(2000);
 221         pci_ctrl->gcr = 1;
 222         udelay(2000);
 223
 224         reg16 = 0xff;
 225         early_read_config_word(hose, hose->first_busno, 0, PCI_COMMAND, &reg16);
 226         reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 227         early_write_config_word(hose, hose->first_busno, 0, PCI_COMMAND, reg16);
 228
 229         /*
 230          * Clear non-reserved bits in status register.
 231          */
 232         early_write_config_word(hose, hose->first_busno, 0, PCI_STATUS, 0xffff);
 233         early_write_config_byte(hose, hose->first_busno, 0, PCI_LATENCY_TIMER, 0x80);
 234
 235         iounmap(pci_ctrl);
 236         iounmap(ios);
 237 }
 238
 239 void __init
 240 mpc83xx_setup_pci2(struct pci_controller *hose)
 241 {
 242         u16 reg16;
 243         volatile immr_pcictrl_t * pci_ctrl;
 244         volatile immr_ios_t * ios;
 245         bd_t *binfo = (bd_t *) __res;
 246
 247         pci_ctrl = ioremap(binfo->bi_immr_base + 0x8600, sizeof(immr_pcictrl_t));
 248         ios = ioremap(binfo->bi_immr_base + 0x8400, sizeof(immr_ios_t));
 249
 250         /*
 251          * Configure PCI Outbound Translation Windows
 252          */
 253         ios->potar3 = (MPC83xx_PCI2_LOWER_MEM >> 12) & POTAR_TA_MASK;
 254         ios->pobar3 = (MPC83xx_PCI2_LOWER_MEM >> 12) & POBAR_BA_MASK;
 255         ios->pocmr3 = POCMR_EN | POCMR_DST |
 256                 (((0xffffffff - (MPC83xx_PCI2_UPPER_MEM -
 257                                 MPC83xx_PCI2_LOWER_MEM)) >> 12) & POCMR_CM_MASK);
 258
 259         /* mapped to PCI2 IO space */
 260         ios->potar4 = (MPC83xx_PCI2_LOWER_IO >> 12) & POTAR_TA_MASK;
 261         ios->pobar4 = (MPC83xx_PCI2_IO_BASE >> 12) & POBAR_BA_MASK;
 262         ios->pocmr4 = POCMR_EN | POCMR_DST | POCMR_IO |
 263                 (((0xffffffff - (MPC83xx_PCI2_UPPER_IO -
 264                                 MPC83xx_PCI2_LOWER_IO)) >> 12) & POCMR_CM_MASK);
 265
 266         /*
 267          * Configure PCI Inbound Translation Windows
 268          */
 269         pci_ctrl->pitar1 = 0x0;
 270         pci_ctrl->pibar1 = 0x0;
 271         pci_ctrl->piebar1 = 0x0;
 272         pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;
 273
 274         /*
 275          * Release PCI RST signal
 276          */
 277         pci_ctrl->gcr = 0;
 278         udelay(2000);
 279         pci_ctrl->gcr = 1;
 280         udelay(2000);
 281
 282         reg16 = 0xff;
 283         early_read_config_word(hose, hose->first_busno, 0, PCI_COMMAND, &reg16);
 284         reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 285         early_write_config_word(hose, hose->first_busno, 0, PCI_COMMAND, reg16);
 286
 287         /*
 288          * Clear non-reserved bits in status register.
 289          */
 290         early_write_config_word(hose, hose->first_busno, 0, PCI_STATUS, 0xffff);
 291         early_write_config_byte(hose, hose->first_busno, 0, PCI_LATENCY_TIMER, 0x80);
 292
 293         iounmap(pci_ctrl);
 294         iounmap(ios);
 295 }
 296
 297 /*
 298  * PCI buses can be enabled only if SYS board combinates with PIB
 299  * (Platform IO Board) board which provide 3 PCI slots. There is 2 PCI buses
 300  * and 3 PCI slots, so people must configure the routes between them before
 301  * enable PCI bus. This routes are under the control of PCA9555PW device which
 302  * can be accessed via I2C bus 2 and are configured by firmware. Refer to
 303  * Freescale to get more information about firmware configuration.
 304  */
 305
 306 extern int mpc83xx_exclude_device(u_char bus, u_char devfn);
 307 extern int mpc83xx_map_irq(struct pci_dev *dev, unsigned char idsel,
 308                 unsigned char pin);
 309 void __init
 310 mpc83xx_setup_hose(void)
 311 {
 312         u32 val32;
 313         volatile immr_clk_t * clk;
 314         struct pci_controller * hose1;
 315 #ifdef CONFIG_MPC83xx_PCI2
 316         struct pci_controller * hose2;
 317 #endif
 318         bd_t * binfo = (bd_t *)__res;
 319
 320         clk = ioremap(binfo->bi_immr_base + 0xA00,
 321                         sizeof(immr_clk_t));
 322
 323         /*
 324          * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
 325          */
 326         val32 = clk->occr;
 327         udelay(2000);
 328         clk->occr = 0xff000000;
 329         udelay(2000);
 330
 331         iounmap(clk);
 332
 333         hose1 = pcibios_alloc_controller();
 334         if(!hose1)
 335                 return;
 336
 337         ppc_md.pci_swizzle = common_swizzle;
 338         ppc_md.pci_map_irq = mpc83xx_map_irq;
 339
 340         hose1->bus_offset = 0;
 341         hose1->first_busno = 0;
 342         hose1->last_busno = 0xff;
 343
 344         setup_indirect_pci(hose1, binfo->bi_immr_base + PCI1_CFG_ADDR_OFFSET,
 345                         binfo->bi_immr_base + PCI1_CFG_DATA_OFFSET);
 346         hose1->set_cfg_type = 1;
 347
 348         mpc83xx_setup_pci1(hose1);
 349
 350         hose1->pci_mem_offset = MPC83xx_PCI1_MEM_OFFSET;
 351         hose1->mem_space.start = MPC83xx_PCI1_LOWER_MEM;
 352         hose1->mem_space.end = MPC83xx_PCI1_UPPER_MEM;
 353
 354         hose1->io_base_phys = MPC83xx_PCI1_IO_BASE;
 355         hose1->io_space.start = MPC83xx_PCI1_LOWER_IO;
 356         hose1->io_space.end = MPC83xx_PCI1_UPPER_IO;
 357 #ifdef CONFIG_MPC83xx_PCI2
 358         isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE,
 359                         MPC83xx_PCI1_IO_SIZE + MPC83xx_PCI2_IO_SIZE);
 360 #else
 361         isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE,
 362                         MPC83xx_PCI1_IO_SIZE);
 363 #endif /* CONFIG_MPC83xx_PCI2 */
 364         hose1->io_base_virt = (void *)isa_io_base;
 365         /* setup resources */
 366         pci_init_resource(&hose1->io_resource,
 367                         MPC83xx_PCI1_LOWER_IO,
 368                         MPC83xx_PCI1_UPPER_IO,
 369                         IORESOURCE_IO, "PCI host bridge 1");
 370         pci_init_resource(&hose1->mem_resources[0],
 371                         MPC83xx_PCI1_LOWER_MEM,
 372                         MPC83xx_PCI1_UPPER_MEM,
 373                         IORESOURCE_MEM, "PCI host bridge 1");
 374
 375         ppc_md.pci_exclude_device = mpc83xx_exclude_device;
 376         hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno);
 377
 378 #ifdef CONFIG_MPC83xx_PCI2
 379         hose2 = pcibios_alloc_controller();
 380         if(!hose2)
 381                 return;
 382
 383         hose2->bus_offset = hose1->last_busno + 1;
 384         hose2->first_busno = hose1->last_busno + 1;
 385         hose2->last_busno = 0xff;
 386         setup_indirect_pci(hose2, binfo->bi_immr_base + PCI2_CFG_ADDR_OFFSET,
 387                         binfo->bi_immr_base + PCI2_CFG_DATA_OFFSET);
 388         hose2->set_cfg_type = 1;
 389
 390         mpc83xx_setup_pci2(hose2);
 391
 392         hose2->pci_mem_offset = MPC83xx_PCI2_MEM_OFFSET;
 393         hose2->mem_space.start = MPC83xx_PCI2_LOWER_MEM;
 394         hose2->mem_space.end = MPC83xx_PCI2_UPPER_MEM;
 395
 396         hose2->io_base_phys = MPC83xx_PCI2_IO_BASE;
 397         hose2->io_space.start = MPC83xx_PCI2_LOWER_IO;
 398         hose2->io_space.end = MPC83xx_PCI2_UPPER_IO;
 399         hose2->io_base_virt = (void *)(isa_io_base + MPC83xx_PCI1_IO_SIZE);
 400         /* setup resources */
 401         pci_init_resource(&hose2->io_resource,
 402                         MPC83xx_PCI2_LOWER_IO,
 403                         MPC83xx_PCI2_UPPER_IO,
 404                         IORESOURCE_IO, "PCI host bridge 2");
 405         pci_init_resource(&hose2->mem_resources[0],
 406                         MPC83xx_PCI2_LOWER_MEM,
 407                         MPC83xx_PCI2_UPPER_MEM,
 408                         IORESOURCE_MEM, "PCI host bridge 2");
 409
 410         hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno);
 411 #endif /* CONFIG_MPC83xx_PCI2 */
 412 }
 413 #endif /*CONFIG_PCI*/