drivers/media/dvb/frontends/stv0297.c

   1 /*
   2     Driver for STV0297 demodulator
   3
   4     Copyright (C) 2004 Andrew de Quincey <adq_dvb@lidskialf.net>
   5     Copyright (C) 2003-2004 Dennis Noermann <dennis.noermann@noernet.de>
   6
   7     This program is free software; you can redistribute it and/or modify
   8     it under the terms of the GNU General Public License as published by
   9     the Free Software Foundation; either version 2 of the License, or
  10     (at your option) any later version.
  11
  12     This program is distributed in the hope that it will be useful,
  13     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15     GNU General Public License for more details.
  16
  17     You should have received a copy of the GNU General Public License
  18     along with this program; if not, write to the Free Software
  19     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20 */
  21
  22 #include <linux/init.h>
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/string.h>
  26 #include <linux/delay.h>
  27
  28 #include "dvb_frontend.h"
  29 #include "stv0297.h"
  30
  31 struct stv0297_state {
  32         struct i2c_adapter *i2c;
  33         struct dvb_frontend_ops ops;
  34         const struct stv0297_config *config;
  35         struct dvb_frontend frontend;
  36
  37         unsigned long base_freq;
  38 };
  39
  40 #if 1
  41 #define dprintk(x...) printk(x)
  42 #else
  43 #define dprintk(x...)
  44 #endif
  45
  46 #define STV0297_CLOCK_KHZ   28900
  47
  48
  49 static int stv0297_writereg(struct stv0297_state *state, u8 reg, u8 data)
  50 {
  51         int ret;
  52         u8 buf[] = { reg, data };
  53         struct i2c_msg msg = {.addr = state->config->demod_address,.flags = 0,.buf = buf,.len = 2 };
  54
  55         ret = i2c_transfer(state->i2c, &msg, 1);
  56
  57         if (ret != 1)
  58                 dprintk("%s: writereg error (reg == 0x%02x, val == 0x%02x, "
  59                         "ret == %i)\n", __FUNCTION__, reg, data, ret);
  60
  61         return (ret != 1) ? -1 : 0;
  62 }
  63
  64 static int stv0297_readreg(struct stv0297_state *state, u8 reg)
  65 {
  66         int ret;
  67         u8 b0[] = { reg };
  68         u8 b1[] = { 0 };
  69         struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf = b0,.len =
  70                                   1},
  71         {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b1,.len = 1}
  72         };
  73
  74         // this device needs a STOP between the register and data
  75         if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) {
  76                 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg, ret);
  77                 return -1;
  78         }
  79         if ((ret = i2c_transfer(state->i2c, &msg[1], 1)) != 1) {
  80                 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg, ret);
  81                 return -1;
  82         }
  83
  84         return b1[0];
  85 }
  86
  87 static int stv0297_writereg_mask(struct stv0297_state *state, u8 reg, u8 mask, u8 data)
  88 {
  89         int val;
  90
  91         val = stv0297_readreg(state, reg);
  92         val &= ~mask;
  93         val |= (data & mask);
  94         stv0297_writereg(state, reg, val);
  95
  96         return 0;
  97 }
  98
  99 static int stv0297_readregs(struct stv0297_state *state, u8 reg1, u8 * b, u8 len)
 100 {
 101         int ret;
 102         struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf =
 103                                   &reg1,.len = 1},
 104         {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b,.len = len}
 105         };
 106
 107         // this device needs a STOP between the register and data
 108         if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) {
 109                 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg1, ret);
 110                 return -1;
 111         }
 112         if ((ret = i2c_transfer(state->i2c, &msg[1], 1)) != 1) {
 113                 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg1, ret);
 114                 return -1;
 115         }
 116
 117         return 0;
 118 }
 119
 120 static u32 stv0297_get_symbolrate(struct stv0297_state *state)
 121 {
 122         u64 tmp;
 123
 124         tmp = stv0297_readreg(state, 0x55);
 125         tmp |= stv0297_readreg(state, 0x56) << 8;
 126         tmp |= stv0297_readreg(state, 0x57) << 16;
 127         tmp |= stv0297_readreg(state, 0x58) << 24;
 128
 129         tmp *= STV0297_CLOCK_KHZ;
 130         tmp >>= 32;
 131
 132         return (u32) tmp;
 133 }
 134
 135 static void stv0297_set_symbolrate(struct stv0297_state *state, u32 srate)
 136 {
 137         long tmp;
 138
 139         tmp = 131072L * srate;  /* 131072 = 2^17  */
 140         tmp = tmp / (STV0297_CLOCK_KHZ / 4);    /* 1/4 = 2^-2 */
 141         tmp = tmp * 8192L;      /* 8192 = 2^13 */
 142
 143         stv0297_writereg(state, 0x55, (unsigned char) (tmp & 0xFF));
 144         stv0297_writereg(state, 0x56, (unsigned char) (tmp >> 8));
 145         stv0297_writereg(state, 0x57, (unsigned char) (tmp >> 16));
 146         stv0297_writereg(state, 0x58, (unsigned char) (tmp >> 24));
 147 }
 148
 149 static void stv0297_set_sweeprate(struct stv0297_state *state, short fshift, long symrate)
 150 {
 151         long tmp;
 152
 153         tmp = (long) fshift *262144L;   /* 262144 = 2*18 */
 154         tmp /= symrate;
 155         tmp *= 1024;            /* 1024 = 2*10   */
 156
 157         // adjust
 158         if (tmp >= 0) {
 159                 tmp += 500000;
 160         } else {
 161                 tmp -= 500000;
 162         }
 163         tmp /= 1000000;
 164
 165         stv0297_writereg(state, 0x60, tmp & 0xFF);
 166         stv0297_writereg_mask(state, 0x69, 0xF0, (tmp >> 4) & 0xf0);
 167 }
 168
 169 static void stv0297_set_carrieroffset(struct stv0297_state *state, long offset)
 170 {
 171         long tmp;
 172
 173         /* symrate is hardcoded to 10000 */
 174         tmp = offset * 26844L;  /* (2**28)/10000 */
 175         if (tmp < 0)
 176                 tmp += 0x10000000;
 177         tmp &= 0x0FFFFFFF;
 178
 179         stv0297_writereg(state, 0x66, (unsigned char) (tmp & 0xFF));
 180         stv0297_writereg(state, 0x67, (unsigned char) (tmp >> 8));
 181         stv0297_writereg(state, 0x68, (unsigned char) (tmp >> 16));
 182         stv0297_writereg_mask(state, 0x69, 0x0F, (tmp >> 24) & 0x0f);
 183 }
 184
 185 /*
 186 static long stv0297_get_carrieroffset(struct stv0297_state *state)
 187 {
 188         s64 tmp;
 189
 190         stv0297_writereg(state, 0x6B, 0x00);
 191
 192         tmp = stv0297_readreg(state, 0x66);
 193         tmp |= (stv0297_readreg(state, 0x67) << 8);
 194         tmp |= (stv0297_readreg(state, 0x68) << 16);
 195         tmp |= (stv0297_readreg(state, 0x69) & 0x0F) << 24;
 196
 197         tmp *= stv0297_get_symbolrate(state);
 198         tmp >>= 28;
 199
 200         return (s32) tmp;
 201 }
 202 */
 203
 204 static void stv0297_set_initialdemodfreq(struct stv0297_state *state, long freq)
 205 {
 206         s32 tmp;
 207
 208         if (freq > 10000)
 209                 freq -= STV0297_CLOCK_KHZ;
 210
 211         tmp = (STV0297_CLOCK_KHZ * 1000) / (1 << 16);
 212         tmp = (freq * 1000) / tmp;
 213         if (tmp > 0xffff)
 214                 tmp = 0xffff;
 215
 216         stv0297_writereg_mask(state, 0x25, 0x80, 0x80);
 217         stv0297_writereg(state, 0x21, tmp >> 8);
 218         stv0297_writereg(state, 0x20, tmp);
 219 }
 220
 221 static int stv0297_set_qam(struct stv0297_state *state, fe_modulation_t modulation)
 222 {
 223         int val = 0;
 224
 225         switch (modulation) {
 226         case QAM_16:
 227                 val = 0;
 228                 break;
 229
 230         case QAM_32:
 231                 val = 1;
 232                 break;
 233
 234         case QAM_64:
 235                 val = 4;
 236                 break;
 237
 238         case QAM_128:
 239                 val = 2;
 240                 break;
 241
 242         case QAM_256:
 243                 val = 3;
 244                 break;
 245
 246         default:
 247                 return -EINVAL;
 248         }
 249
 250         stv0297_writereg_mask(state, 0x00, 0x70, val << 4);
 251
 252         return 0;
 253 }
 254
 255 static int stv0297_set_inversion(struct stv0297_state *state, fe_spectral_inversion_t inversion)
 256 {
 257         int val = 0;
 258
 259         switch (inversion) {
 260         case INVERSION_OFF:
 261                 val = 0;
 262                 break;
 263
 264         case INVERSION_ON:
 265                 val = 1;
 266                 break;
 267
 268         default:
 269                 return -EINVAL;
 270         }
 271
 272         stv0297_writereg_mask(state, 0x83, 0x08, val << 3);
 273
 274         return 0;
 275 }
 276
 277 int stv0297_enable_plli2c(struct dvb_frontend *fe)
 278 {
 279         struct stv0297_state *state = fe->demodulator_priv;
 280
 281         stv0297_writereg(state, 0x87, 0x78);
 282         stv0297_writereg(state, 0x86, 0xc8);
 283
 284         return 0;
 285 }
 286
 287 static int stv0297_init(struct dvb_frontend *fe)
 288 {
 289         struct stv0297_state *state = fe->demodulator_priv;
 290         int i;
 291
 292         /* load init table */
 293         for (i=0; !(state->config->inittab[i] == 0xff && state->config->inittab[i+1] == 0xff); i+=2)
 294                 stv0297_writereg(state, state->config->inittab[i], state->config->inittab[i+1]);
 295         msleep(200);
 296
 297         if (state->config->pll_init)
 298                 state->config->pll_init(fe);
 299
 300         return 0;
 301 }
 302
 303 static int stv0297_sleep(struct dvb_frontend *fe)
 304 {
 305         struct stv0297_state *state = fe->demodulator_priv;
 306
 307         stv0297_writereg_mask(state, 0x80, 1, 1);
 308
 309         return 0;
 310 }
 311
 312 static int stv0297_read_status(struct dvb_frontend *fe, fe_status_t * status)
 313 {
 314         struct stv0297_state *state = fe->demodulator_priv;
 315
 316         u8 sync = stv0297_readreg(state, 0xDF);
 317
 318         *status = 0;
 319         if (sync & 0x80)
 320                 *status |=
 321                         FE_HAS_SYNC | FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_LOCK;
 322         return 0;
 323 }
 324
 325 static int stv0297_read_ber(struct dvb_frontend *fe, u32 * ber)
 326 {
 327         struct stv0297_state *state = fe->demodulator_priv;
 328         u8 BER[3];
 329
 330         stv0297_writereg(state, 0xA0, 0x80);    // Start Counting bit errors for 4096 Bytes
 331         mdelay(25);             // Hopefully got 4096 Bytes
 332         stv0297_readregs(state, 0xA0, BER, 3);
 333         mdelay(25);
 334         *ber = (BER[2] << 8 | BER[1]) / (8 * 4096);
 335
 336         return 0;
 337 }
 338
 339
 340 static int stv0297_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
 341 {
 342         struct stv0297_state *state = fe->demodulator_priv;
 343         u8 STRENGTH[2];
 344
 345         stv0297_readregs(state, 0x41, STRENGTH, 2);
 346         *strength = (STRENGTH[1] & 0x03) << 8 | STRENGTH[0];
 347
 348         return 0;
 349 }
 350
 351 static int stv0297_read_snr(struct dvb_frontend *fe, u16 * snr)
 352 {
 353         struct stv0297_state *state = fe->demodulator_priv;
 354         u8 SNR[2];
 355
 356         stv0297_readregs(state, 0x07, SNR, 2);
 357         *snr = SNR[1] << 8 | SNR[0];
 358
 359         return 0;
 360 }
 361
 362 static int stv0297_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
 363 {
 364         struct stv0297_state *state = fe->demodulator_priv;
 365
 366         *ucblocks = (stv0297_readreg(state, 0xD5) << 8)
 367                 | stv0297_readreg(state, 0xD4);
 368
 369         return 0;
 370 }
 371
 372 static int stv0297_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
 373 {
 374         struct stv0297_state *state = fe->demodulator_priv;
 375         int u_threshold;
 376         int initial_u;
 377         int blind_u;
 378         int delay;
 379         int sweeprate;
 380         int carrieroffset;
 381         unsigned long starttime;
 382         unsigned long timeout;
 383         fe_spectral_inversion_t inversion;
 384
 385         switch (p->u.qam.modulation) {
 386         case QAM_16:
 387         case QAM_32:
 388         case QAM_64:
 389                 delay = 100;
 390                 sweeprate = 1500;
 391                 break;
 392
 393         case QAM_128:
 394                 delay = 150;
 395                 sweeprate = 1000;
 396                 break;
 397
 398         case QAM_256:
 399                 delay = 200;
 400                 sweeprate = 500;
 401                 break;
 402
 403         default:
 404                 return -EINVAL;
 405         }
 406
 407         // determine inversion dependant parameters
 408         inversion = p->inversion;
 409         if (state->config->invert)
 410                 inversion = (inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON;
 411         carrieroffset = -330;
 412         switch (inversion) {
 413         case INVERSION_OFF:
 414                 break;
 415
 416         case INVERSION_ON:
 417                 sweeprate = -sweeprate;
 418                 carrieroffset = -carrieroffset;
 419                 break;
 420
 421         default:
 422                 return -EINVAL;
 423         }
 424
 425         stv0297_init(fe);
 426         state->config->pll_set(fe, p);
 427
 428         /* clear software interrupts */
 429         stv0297_writereg(state, 0x82, 0x0);
 430
 431         /* set initial demodulation frequency */
 432         stv0297_set_initialdemodfreq(state, 7250);
 433
 434         /* setup AGC */
 435         stv0297_writereg_mask(state, 0x43, 0x10, 0x00);
 436         stv0297_writereg(state, 0x41, 0x00);
 437         stv0297_writereg_mask(state, 0x42, 0x03, 0x01);
 438         stv0297_writereg_mask(state, 0x36, 0x60, 0x00);
 439         stv0297_writereg_mask(state, 0x36, 0x18, 0x00);
 440         stv0297_writereg_mask(state, 0x71, 0x80, 0x80);
 441         stv0297_writereg(state, 0x72, 0x00);
 442         stv0297_writereg(state, 0x73, 0x00);
 443         stv0297_writereg_mask(state, 0x74, 0x0F, 0x00);
 444         stv0297_writereg_mask(state, 0x43, 0x08, 0x00);
 445         stv0297_writereg_mask(state, 0x71, 0x80, 0x00);
 446
 447         /* setup STL */
 448         stv0297_writereg_mask(state, 0x5a, 0x20, 0x20);
 449         stv0297_writereg_mask(state, 0x5b, 0x02, 0x02);
 450         stv0297_writereg_mask(state, 0x5b, 0x02, 0x00);
 451         stv0297_writereg_mask(state, 0x5b, 0x01, 0x00);
 452         stv0297_writereg_mask(state, 0x5a, 0x40, 0x40);
 453
 454         /* disable frequency sweep */
 455         stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);
 456
 457         /* reset deinterleaver */
 458         stv0297_writereg_mask(state, 0x81, 0x01, 0x01);
 459         stv0297_writereg_mask(state, 0x81, 0x01, 0x00);
 460
 461         /* ??? */
 462         stv0297_writereg_mask(state, 0x83, 0x20, 0x20);
 463         stv0297_writereg_mask(state, 0x83, 0x20, 0x00);
 464
 465         /* reset equaliser */
 466         u_threshold = stv0297_readreg(state, 0x00) & 0xf;
 467         initial_u = stv0297_readreg(state, 0x01) >> 4;
 468         blind_u = stv0297_readreg(state, 0x01) & 0xf;
 469         stv0297_writereg_mask(state, 0x84, 0x01, 0x01);
 470         stv0297_writereg_mask(state, 0x84, 0x01, 0x00);
 471         stv0297_writereg_mask(state, 0x00, 0x0f, u_threshold);
 472         stv0297_writereg_mask(state, 0x01, 0xf0, initial_u << 4);
 473         stv0297_writereg_mask(state, 0x01, 0x0f, blind_u);
 474
 475         /* data comes from internal A/D */
 476         stv0297_writereg_mask(state, 0x87, 0x80, 0x00);
 477
 478         /* clear phase registers */
 479         stv0297_writereg(state, 0x63, 0x00);
 480         stv0297_writereg(state, 0x64, 0x00);
 481         stv0297_writereg(state, 0x65, 0x00);
 482         stv0297_writereg(state, 0x66, 0x00);
 483         stv0297_writereg(state, 0x67, 0x00);
 484         stv0297_writereg(state, 0x68, 0x00);
 485         stv0297_writereg_mask(state, 0x69, 0x0f, 0x00);
 486
 487         /* set parameters */
 488         stv0297_set_qam(state, p->u.qam.modulation);
 489         stv0297_set_symbolrate(state, p->u.qam.symbol_rate / 1000);
 490         stv0297_set_sweeprate(state, sweeprate, p->u.qam.symbol_rate / 1000);
 491         stv0297_set_carrieroffset(state, carrieroffset);
 492         stv0297_set_inversion(state, inversion);
 493
 494         /* kick off lock */
 495         /* Disable corner detection for higher QAMs */
 496         if (p->u.qam.modulation == QAM_128 ||
 497                 p->u.qam.modulation == QAM_256)
 498                 stv0297_writereg_mask(state, 0x88, 0x08, 0x00);
 499         else
 500                 stv0297_writereg_mask(state, 0x88, 0x08, 0x08);
 501
 502         stv0297_writereg_mask(state, 0x5a, 0x20, 0x00);
 503         stv0297_writereg_mask(state, 0x6a, 0x01, 0x01);
 504         stv0297_writereg_mask(state, 0x43, 0x40, 0x40);
 505         stv0297_writereg_mask(state, 0x5b, 0x30, 0x00);
 506         stv0297_writereg_mask(state, 0x03, 0x0c, 0x0c);
 507         stv0297_writereg_mask(state, 0x03, 0x03, 0x03);
 508         stv0297_writereg_mask(state, 0x43, 0x10, 0x10);
 509
 510         /* wait for WGAGC lock */
 511         starttime = jiffies;
 512         timeout = jiffies + msecs_to_jiffies(2000);
 513         while (time_before(jiffies, timeout)) {
 514                 msleep(10);
 515                 if (stv0297_readreg(state, 0x43) & 0x08)
 516                         break;
 517         }
 518         if (time_after(jiffies, timeout)) {
 519                 goto timeout;
 520         }
 521         msleep(20);
 522
 523         /* wait for equaliser partial convergence */
 524         timeout = jiffies + msecs_to_jiffies(500);
 525         while (time_before(jiffies, timeout)) {
 526                 msleep(10);
 527
 528                 if (stv0297_readreg(state, 0x82) & 0x04) {
 529                         break;
 530                 }
 531         }
 532         if (time_after(jiffies, timeout)) {
 533                 goto timeout;
 534         }
 535
 536         /* wait for equaliser full convergence */
 537         timeout = jiffies + msecs_to_jiffies(delay);
 538         while (time_before(jiffies, timeout)) {
 539                 msleep(10);
 540
 541                 if (stv0297_readreg(state, 0x82) & 0x08) {
 542                         break;
 543                 }
 544         }
 545         if (time_after(jiffies, timeout)) {
 546                 goto timeout;
 547         }
 548
 549         /* disable sweep */
 550         stv0297_writereg_mask(state, 0x6a, 1, 0);
 551         stv0297_writereg_mask(state, 0x88, 8, 0);
 552
 553         /* wait for main lock */
 554         timeout = jiffies + msecs_to_jiffies(20);
 555         while (time_before(jiffies, timeout)) {
 556                 msleep(10);
 557
 558                 if (stv0297_readreg(state, 0xDF) & 0x80) {
 559                         break;
 560                 }
 561         }
 562         if (time_after(jiffies, timeout)) {
 563                 goto timeout;
 564         }
 565         msleep(100);
 566
 567         /* is it still locked after that delay? */
 568         if (!(stv0297_readreg(state, 0xDF) & 0x80)) {
 569                 goto timeout;
 570         }
 571
 572         /* success!! */
 573         stv0297_writereg_mask(state, 0x5a, 0x40, 0x00);
 574         state->base_freq = p->frequency;
 575         return 0;
 576
 577 timeout:
 578         stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);
 579         return 0;
 580 }
 581
 582 static int stv0297_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
 583 {
 584         struct stv0297_state *state = fe->demodulator_priv;
 585         int reg_00, reg_83;
 586
 587         reg_00 = stv0297_readreg(state, 0x00);
 588         reg_83 = stv0297_readreg(state, 0x83);
 589
 590         p->frequency = state->base_freq;
 591         p->inversion = (reg_83 & 0x08) ? INVERSION_ON : INVERSION_OFF;
 592         if (state->config->invert)
 593                 p->inversion = (p->inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON;
 594         p->u.qam.symbol_rate = stv0297_get_symbolrate(state) * 1000;
 595         p->u.qam.fec_inner = FEC_NONE;
 596
 597         switch ((reg_00 >> 4) & 0x7) {
 598         case 0:
 599                 p->u.qam.modulation = QAM_16;
 600                 break;
 601         case 1:
 602                 p->u.qam.modulation = QAM_32;
 603                 break;
 604         case 2:
 605                 p->u.qam.modulation = QAM_128;
 606                 break;
 607         case 3:
 608                 p->u.qam.modulation = QAM_256;
 609                 break;
 610         case 4:
 611                 p->u.qam.modulation = QAM_64;
 612                 break;
 613         }
 614
 615         return 0;
 616 }
 617
 618 static void stv0297_release(struct dvb_frontend *fe)
 619 {
 620         struct stv0297_state *state = fe->demodulator_priv;
 621         kfree(state);
 622 }
 623
 624 static struct dvb_frontend_ops stv0297_ops;
 625
 626 struct dvb_frontend *stv0297_attach(const struct stv0297_config *config,
 627                                     struct i2c_adapter *i2c)
 628 {
 629         struct stv0297_state *state = NULL;
 630
 631         /* allocate memory for the internal state */
 632         state = kmalloc(sizeof(struct stv0297_state), GFP_KERNEL);
 633         if (state == NULL)
 634                 goto error;
 635
 636         /* setup the state */
 637         state->config = config;
 638         state->i2c = i2c;
 639         memcpy(&state->ops, &stv0297_ops, sizeof(struct dvb_frontend_ops));
 640         state->base_freq = 0;
 641
 642         /* check if the demod is there */
 643         if ((stv0297_readreg(state, 0x80) & 0x70) != 0x20)
 644                 goto error;
 645
 646         /* create dvb_frontend */
 647         state->frontend.ops = &state->ops;
 648         state->frontend.demodulator_priv = state;
 649         return &state->frontend;
 650
 651 error:
 652         kfree(state);
 653         return NULL;
 654 }
 655
 656 static struct dvb_frontend_ops stv0297_ops = {
 657
 658         .info = {
 659                  .name = "ST STV0297 DVB-C",
 660                  .type = FE_QAM,
 661                  .frequency_min = 64000000,
 662                  .frequency_max = 1300000000,
 663                  .frequency_stepsize = 62500,
 664                  .symbol_rate_min = 870000,
 665                  .symbol_rate_max = 11700000,
 666                  .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
 667                  FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO},
 668
 669         .release = stv0297_release,
 670
 671         .init = stv0297_init,
 672         .sleep = stv0297_sleep,
 673
 674         .set_frontend = stv0297_set_frontend,
 675         .get_frontend = stv0297_get_frontend,
 676
 677         .read_status = stv0297_read_status,
 678         .read_ber = stv0297_read_ber,
 679         .read_signal_strength = stv0297_read_signal_strength,
 680         .read_snr = stv0297_read_snr,
 681         .read_ucblocks = stv0297_read_ucblocks,
 682 };
 683
 684 MODULE_DESCRIPTION("ST STV0297 DVB-C Demodulator driver");
 685 MODULE_AUTHOR("Dennis Noermann and Andrew de Quincey");
 686 MODULE_LICENSE("GPL");
 687
 688 EXPORT_SYMBOL(stv0297_attach);
 689 EXPORT_SYMBOL(stv0297_enable_plli2c);