2 * sata_mv.c - Marvell SATA support
4 * Copyright 2005: EMC Corporation, all rights reserved.
6 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/init.h>
27 #include <linux/blkdev.h>
28 #include <linux/delay.h>
29 #include <linux/interrupt.h>
30 #include <linux/sched.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/device.h>
33 #include <scsi/scsi_host.h>
34 #include <scsi/scsi_cmnd.h>
35 #include <linux/libata.h>
38 #define DRV_NAME "sata_mv"
39 #define DRV_VERSION "0.25"
42 /* BAR's are enumerated in terms of pci_resource_start() terms */
43 MV_PRIMARY_BAR
= 0, /* offset 0x10: memory space */
44 MV_IO_BAR
= 2, /* offset 0x18: IO space */
45 MV_MISC_BAR
= 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
47 MV_MAJOR_REG_AREA_SZ
= 0x10000, /* 64KB */
48 MV_MINOR_REG_AREA_SZ
= 0x2000, /* 8KB */
51 MV_IRQ_COAL_REG_BASE
= 0x18000, /* 6xxx part only */
52 MV_SATAHC0_REG_BASE
= 0x20000,
53 MV_FLASH_CTL
= 0x1046c,
54 MV_GPIO_PORT_CTL
= 0x104f0,
55 MV_RESET_CFG
= 0x180d8,
57 MV_PCI_REG_SZ
= MV_MAJOR_REG_AREA_SZ
,
58 MV_SATAHC_REG_SZ
= MV_MAJOR_REG_AREA_SZ
,
59 MV_SATAHC_ARBTR_REG_SZ
= MV_MINOR_REG_AREA_SZ
, /* arbiter */
60 MV_PORT_REG_SZ
= MV_MINOR_REG_AREA_SZ
,
62 MV_USE_Q_DEPTH
= ATA_DEF_QUEUE
,
65 MV_MAX_Q_DEPTH_MASK
= MV_MAX_Q_DEPTH
- 1,
67 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
68 * CRPB needs alignment on a 256B boundary. Size == 256B
69 * SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB
70 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
72 MV_CRQB_Q_SZ
= (32 * MV_MAX_Q_DEPTH
),
73 MV_CRPB_Q_SZ
= (8 * MV_MAX_Q_DEPTH
),
75 MV_SG_TBL_SZ
= (16 * MV_MAX_SG_CT
),
76 MV_PORT_PRIV_DMA_SZ
= (MV_CRQB_Q_SZ
+ MV_CRPB_Q_SZ
+ MV_SG_TBL_SZ
),
79 /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */
81 /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */
85 MV_FLAG_DUAL_HC
= (1 << 30), /* two SATA Host Controllers */
86 MV_FLAG_IRQ_COALESCE
= (1 << 29), /* IRQ coalescing capability */
87 MV_COMMON_FLAGS
= (ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
88 ATA_FLAG_SATA_RESET
| ATA_FLAG_MMIO
),
89 MV_6XXX_FLAGS
= MV_FLAG_IRQ_COALESCE
,
91 CRQB_FLAG_READ
= (1 << 0),
93 CRQB_CMD_ADDR_SHIFT
= 8,
94 CRQB_CMD_CS
= (0x2 << 11),
95 CRQB_CMD_LAST
= (1 << 15),
97 CRPB_FLAG_STATUS_SHIFT
= 8,
99 EPRD_FLAG_END_OF_TBL
= (1 << 31),
101 /* PCI interface registers */
103 PCI_COMMAND_OFS
= 0xc00,
105 PCI_MAIN_CMD_STS_OFS
= 0xd30,
106 STOP_PCI_MASTER
= (1 << 2),
107 PCI_MASTER_EMPTY
= (1 << 3),
108 GLOB_SFT_RST
= (1 << 4),
111 MV_PCI_EXP_ROM_BAR_CTL
= 0xd2c,
112 MV_PCI_DISC_TIMER
= 0xd04,
113 MV_PCI_MSI_TRIGGER
= 0xc38,
114 MV_PCI_SERR_MASK
= 0xc28,
115 MV_PCI_XBAR_TMOUT
= 0x1d04,
116 MV_PCI_ERR_LOW_ADDRESS
= 0x1d40,
117 MV_PCI_ERR_HIGH_ADDRESS
= 0x1d44,
118 MV_PCI_ERR_ATTRIBUTE
= 0x1d48,
119 MV_PCI_ERR_COMMAND
= 0x1d50,
121 PCI_IRQ_CAUSE_OFS
= 0x1d58,
122 PCI_IRQ_MASK_OFS
= 0x1d5c,
123 PCI_UNMASK_ALL_IRQS
= 0x7fffff, /* bits 22-0 */
125 HC_MAIN_IRQ_CAUSE_OFS
= 0x1d60,
126 HC_MAIN_IRQ_MASK_OFS
= 0x1d64,
127 PORT0_ERR
= (1 << 0), /* shift by port # */
128 PORT0_DONE
= (1 << 1), /* shift by port # */
129 HC0_IRQ_PEND
= 0x1ff, /* bits 0-8 = HC0's ports */
130 HC_SHIFT
= 9, /* bits 9-17 = HC1's ports */
132 TRAN_LO_DONE
= (1 << 19), /* 6xxx: IRQ coalescing */
133 TRAN_HI_DONE
= (1 << 20), /* 6xxx: IRQ coalescing */
134 PORTS_0_7_COAL_DONE
= (1 << 21), /* 6xxx: IRQ coalescing */
135 GPIO_INT
= (1 << 22),
136 SELF_INT
= (1 << 23),
137 TWSI_INT
= (1 << 24),
138 HC_MAIN_RSVD
= (0x7f << 25), /* bits 31-25 */
139 HC_MAIN_MASKED_IRQS
= (TRAN_LO_DONE
| TRAN_HI_DONE
|
140 PORTS_0_7_COAL_DONE
| GPIO_INT
| TWSI_INT
|
143 /* SATAHC registers */
146 HC_IRQ_CAUSE_OFS
= 0x14,
147 CRPB_DMA_DONE
= (1 << 0), /* shift by port # */
148 HC_IRQ_COAL
= (1 << 4), /* IRQ coalescing */
149 DEV_IRQ
= (1 << 8), /* shift by port # */
151 /* Shadow block registers */
153 SHD_CTL_AST_OFS
= 0x20, /* ofs from SHD_BLK_OFS */
156 SATA_STATUS_OFS
= 0x300, /* ctrl, err regs follow status */
157 SATA_ACTIVE_OFS
= 0x350,
161 SATA_INTERFACE_CTL
= 0x050,
163 MV_M2_PREAMP_MASK
= 0x7e0,
167 EDMA_CFG_Q_DEPTH
= 0, /* queueing disabled */
168 EDMA_CFG_NCQ
= (1 << 5),
169 EDMA_CFG_NCQ_GO_ON_ERR
= (1 << 14), /* continue on error */
170 EDMA_CFG_RD_BRST_EXT
= (1 << 11), /* read burst 512B */
171 EDMA_CFG_WR_BUFF_LEN
= (1 << 13), /* write buffer 512B */
173 EDMA_ERR_IRQ_CAUSE_OFS
= 0x8,
174 EDMA_ERR_IRQ_MASK_OFS
= 0xc,
175 EDMA_ERR_D_PAR
= (1 << 0),
176 EDMA_ERR_PRD_PAR
= (1 << 1),
177 EDMA_ERR_DEV
= (1 << 2),
178 EDMA_ERR_DEV_DCON
= (1 << 3),
179 EDMA_ERR_DEV_CON
= (1 << 4),
180 EDMA_ERR_SERR
= (1 << 5),
181 EDMA_ERR_SELF_DIS
= (1 << 7),
182 EDMA_ERR_BIST_ASYNC
= (1 << 8),
183 EDMA_ERR_CRBQ_PAR
= (1 << 9),
184 EDMA_ERR_CRPB_PAR
= (1 << 10),
185 EDMA_ERR_INTRL_PAR
= (1 << 11),
186 EDMA_ERR_IORDY
= (1 << 12),
187 EDMA_ERR_LNK_CTRL_RX
= (0xf << 13),
188 EDMA_ERR_LNK_CTRL_RX_2
= (1 << 15),
189 EDMA_ERR_LNK_DATA_RX
= (0xf << 17),
190 EDMA_ERR_LNK_CTRL_TX
= (0x1f << 21),
191 EDMA_ERR_LNK_DATA_TX
= (0x1f << 26),
192 EDMA_ERR_TRANS_PROTO
= (1 << 31),
193 EDMA_ERR_FATAL
= (EDMA_ERR_D_PAR
| EDMA_ERR_PRD_PAR
|
194 EDMA_ERR_DEV_DCON
| EDMA_ERR_CRBQ_PAR
|
195 EDMA_ERR_CRPB_PAR
| EDMA_ERR_INTRL_PAR
|
196 EDMA_ERR_IORDY
| EDMA_ERR_LNK_CTRL_RX_2
|
197 EDMA_ERR_LNK_DATA_RX
|
198 EDMA_ERR_LNK_DATA_TX
|
199 EDMA_ERR_TRANS_PROTO
),
201 EDMA_REQ_Q_BASE_HI_OFS
= 0x10,
202 EDMA_REQ_Q_IN_PTR_OFS
= 0x14, /* also contains BASE_LO */
204 EDMA_REQ_Q_OUT_PTR_OFS
= 0x18,
205 EDMA_REQ_Q_PTR_SHIFT
= 5,
207 EDMA_RSP_Q_BASE_HI_OFS
= 0x1c,
208 EDMA_RSP_Q_IN_PTR_OFS
= 0x20,
209 EDMA_RSP_Q_OUT_PTR_OFS
= 0x24, /* also contains BASE_LO */
210 EDMA_RSP_Q_PTR_SHIFT
= 3,
219 /* Host private flags (hp_flags) */
220 MV_HP_FLAG_MSI
= (1 << 0),
221 MV_HP_ERRATA_50XXB0
= (1 << 1),
222 MV_HP_ERRATA_50XXB2
= (1 << 2),
223 MV_HP_ERRATA_60X1B2
= (1 << 3),
224 MV_HP_ERRATA_60X1C0
= (1 << 4),
225 MV_HP_50XX
= (1 << 5),
227 /* Port private flags (pp_flags) */
228 MV_PP_FLAG_EDMA_EN
= (1 << 0),
229 MV_PP_FLAG_EDMA_DS_ACT
= (1 << 1),
232 #define IS_60XX(hpriv) (((hpriv)->hp_flags & MV_HP_50XX) == 0)
235 /* Our DMA boundary is determined by an ePRD being unable to handle
236 * anything larger than 64KB
238 MV_DMA_BOUNDARY
= 0xffffU
,
240 EDMA_REQ_Q_BASE_LO_MASK
= 0xfffffc00U
,
242 EDMA_RSP_Q_BASE_LO_MASK
= 0xffffff00U
,
253 /* Command ReQuest Block: 32B */
261 /* Command ResPonse Block: 8B */
268 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
276 struct mv_port_priv
{
277 struct mv_crqb
*crqb
;
279 struct mv_crpb
*crpb
;
281 struct mv_sg
*sg_tbl
;
282 dma_addr_t sg_tbl_dma
;
284 unsigned req_producer
; /* cp of req_in_ptr */
285 unsigned rsp_consumer
; /* cp of rsp_out_ptr */
289 struct mv_port_signal
{
296 void (*phy_errata
)(struct ata_port
*ap
);
297 void (*enable_leds
)(struct mv_host_priv
*hpriv
, void __iomem
*mmio
);
298 void (*read_preamp
)(struct mv_host_priv
*hpriv
, int idx
,
300 int (*reset_hc
)(struct mv_host_priv
*hpriv
, void __iomem
*mmio
);
301 void (*reset_flash
)(struct mv_host_priv
*hpriv
, void __iomem
*mmio
);
302 void (*reset_bus
)(struct pci_dev
*pdev
, void __iomem
*mmio
);
305 struct mv_host_priv
{
307 struct mv_port_signal signal
[8];
308 const struct mv_hw_ops
*ops
;
311 static void mv_irq_clear(struct ata_port
*ap
);
312 static u32
mv_scr_read(struct ata_port
*ap
, unsigned int sc_reg_in
);
313 static void mv_scr_write(struct ata_port
*ap
, unsigned int sc_reg_in
, u32 val
);
314 static void mv_phy_reset(struct ata_port
*ap
);
315 static void mv_host_stop(struct ata_host_set
*host_set
);
316 static int mv_port_start(struct ata_port
*ap
);
317 static void mv_port_stop(struct ata_port
*ap
);
318 static void mv_qc_prep(struct ata_queued_cmd
*qc
);
319 static int mv_qc_issue(struct ata_queued_cmd
*qc
);
320 static irqreturn_t
mv_interrupt(int irq
, void *dev_instance
,
321 struct pt_regs
*regs
);
322 static void mv_eng_timeout(struct ata_port
*ap
);
323 static int mv_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
325 static void mv5_phy_errata(struct ata_port
*ap
);
326 static void mv5_enable_leds(struct mv_host_priv
*hpriv
, void __iomem
*mmio
);
327 static void mv5_read_preamp(struct mv_host_priv
*hpriv
, int idx
,
329 static int mv5_reset_hc(struct mv_host_priv
*hpriv
, void __iomem
*mmio
);
330 static void mv5_reset_flash(struct mv_host_priv
*hpriv
, void __iomem
*mmio
);
331 static void mv5_reset_bus(struct pci_dev
*pdev
, void __iomem
*mmio
);
333 static void mv6_phy_errata(struct ata_port
*ap
);
334 static void mv6_enable_leds(struct mv_host_priv
*hpriv
, void __iomem
*mmio
);
335 static void mv6_read_preamp(struct mv_host_priv
*hpriv
, int idx
,
337 static int mv6_reset_hc(struct mv_host_priv
*hpriv
, void __iomem
*mmio
);
338 static void mv6_reset_flash(struct mv_host_priv
*hpriv
, void __iomem
*mmio
);
339 static void mv_reset_pci_bus(struct pci_dev
*pdev
, void __iomem
*mmio
);
341 static struct scsi_host_template mv_sht
= {
342 .module
= THIS_MODULE
,
344 .ioctl
= ata_scsi_ioctl
,
345 .queuecommand
= ata_scsi_queuecmd
,
346 .eh_strategy_handler
= ata_scsi_error
,
347 .can_queue
= MV_USE_Q_DEPTH
,
348 .this_id
= ATA_SHT_THIS_ID
,
349 .sg_tablesize
= MV_MAX_SG_CT
,
350 .max_sectors
= ATA_MAX_SECTORS
,
351 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
352 .emulated
= ATA_SHT_EMULATED
,
353 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
354 .proc_name
= DRV_NAME
,
355 .dma_boundary
= MV_DMA_BOUNDARY
,
356 .slave_configure
= ata_scsi_slave_config
,
357 .bios_param
= ata_std_bios_param
,
361 static const struct ata_port_operations mv_ops
= {
362 .port_disable
= ata_port_disable
,
364 .tf_load
= ata_tf_load
,
365 .tf_read
= ata_tf_read
,
366 .check_status
= ata_check_status
,
367 .exec_command
= ata_exec_command
,
368 .dev_select
= ata_std_dev_select
,
370 .phy_reset
= mv_phy_reset
,
372 .qc_prep
= mv_qc_prep
,
373 .qc_issue
= mv_qc_issue
,
375 .eng_timeout
= mv_eng_timeout
,
377 .irq_handler
= mv_interrupt
,
378 .irq_clear
= mv_irq_clear
,
380 .scr_read
= mv_scr_read
,
381 .scr_write
= mv_scr_write
,
383 .port_start
= mv_port_start
,
384 .port_stop
= mv_port_stop
,
385 .host_stop
= mv_host_stop
,
388 static struct ata_port_info mv_port_info
[] = {
391 .host_flags
= MV_COMMON_FLAGS
,
392 .pio_mask
= 0x1f, /* pio0-4 */
393 .udma_mask
= 0, /* 0x7f (udma0-6 disabled for now) */
398 .host_flags
= (MV_COMMON_FLAGS
| MV_FLAG_DUAL_HC
),
399 .pio_mask
= 0x1f, /* pio0-4 */
400 .udma_mask
= 0, /* 0x7f (udma0-6 disabled for now) */
405 .host_flags
= (MV_COMMON_FLAGS
| MV_FLAG_DUAL_HC
),
406 .pio_mask
= 0x1f, /* pio0-4 */
407 .udma_mask
= 0, /* 0x7f (udma0-6 disabled for now) */
412 .host_flags
= (MV_COMMON_FLAGS
| MV_6XXX_FLAGS
),
413 .pio_mask
= 0x1f, /* pio0-4 */
414 .udma_mask
= 0x7f, /* udma0-6 */
419 .host_flags
= (MV_COMMON_FLAGS
| MV_6XXX_FLAGS
|
421 .pio_mask
= 0x1f, /* pio0-4 */
422 .udma_mask
= 0x7f, /* udma0-6 */
427 static const struct pci_device_id mv_pci_tbl
[] = {
428 #if 0 /* unusably broken right now */
429 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x5040), 0, 0, chip_504x
},
430 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x5041), 0, 0, chip_504x
},
431 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x5080), 0, 0, chip_5080
},
432 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x5081), 0, 0, chip_508x
},
435 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x6040), 0, 0, chip_604x
},
436 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x6041), 0, 0, chip_604x
},
437 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x6080), 0, 0, chip_608x
},
438 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x6081), 0, 0, chip_608x
},
440 {PCI_DEVICE(PCI_VENDOR_ID_ADAPTEC2
, 0x0241), 0, 0, chip_604x
},
441 {} /* terminate list */
444 static struct pci_driver mv_pci_driver
= {
446 .id_table
= mv_pci_tbl
,
447 .probe
= mv_init_one
,
448 .remove
= ata_pci_remove_one
,
451 static const struct mv_hw_ops mv5xxx_ops
= {
452 .phy_errata
= mv5_phy_errata
,
453 .enable_leds
= mv5_enable_leds
,
454 .read_preamp
= mv5_read_preamp
,
455 .reset_hc
= mv5_reset_hc
,
456 .reset_flash
= mv5_reset_flash
,
457 .reset_bus
= mv5_reset_bus
,
460 static const struct mv_hw_ops mv6xxx_ops
= {
461 .phy_errata
= mv6_phy_errata
,
462 .enable_leds
= mv6_enable_leds
,
463 .read_preamp
= mv6_read_preamp
,
464 .reset_hc
= mv6_reset_hc
,
465 .reset_flash
= mv6_reset_flash
,
466 .reset_bus
= mv_reset_pci_bus
,
473 static inline void writelfl(unsigned long data
, void __iomem
*addr
)
476 (void) readl(addr
); /* flush to avoid PCI posted write */
479 static inline void __iomem
*mv_hc_base(void __iomem
*base
, unsigned int hc
)
481 return (base
+ MV_SATAHC0_REG_BASE
+ (hc
* MV_SATAHC_REG_SZ
));
484 static inline void __iomem
*mv_port_base(void __iomem
*base
, unsigned int port
)
486 return (mv_hc_base(base
, port
>> MV_PORT_HC_SHIFT
) +
487 MV_SATAHC_ARBTR_REG_SZ
+
488 ((port
& MV_PORT_MASK
) * MV_PORT_REG_SZ
));
491 static inline void __iomem
*mv_ap_base(struct ata_port
*ap
)
493 return mv_port_base(ap
->host_set
->mmio_base
, ap
->port_no
);
496 static inline int mv_get_hc_count(unsigned long host_flags
)
498 return ((host_flags
& MV_FLAG_DUAL_HC
) ? 2 : 1);
501 static void mv_irq_clear(struct ata_port
*ap
)
506 * mv_start_dma - Enable eDMA engine
507 * @base: port base address
508 * @pp: port private data
510 * Verify the local cache of the eDMA state is accurate with an
514 * Inherited from caller.
516 static void mv_start_dma(void __iomem
*base
, struct mv_port_priv
*pp
)
518 if (!(MV_PP_FLAG_EDMA_EN
& pp
->pp_flags
)) {
519 writelfl(EDMA_EN
, base
+ EDMA_CMD_OFS
);
520 pp
->pp_flags
|= MV_PP_FLAG_EDMA_EN
;
522 assert(EDMA_EN
& readl(base
+ EDMA_CMD_OFS
));
526 * mv_stop_dma - Disable eDMA engine
527 * @ap: ATA channel to manipulate
529 * Verify the local cache of the eDMA state is accurate with an
533 * Inherited from caller.
535 static void mv_stop_dma(struct ata_port
*ap
)
537 void __iomem
*port_mmio
= mv_ap_base(ap
);
538 struct mv_port_priv
*pp
= ap
->private_data
;
542 if (MV_PP_FLAG_EDMA_EN
& pp
->pp_flags
) {
543 /* Disable EDMA if active. The disable bit auto clears.
545 writelfl(EDMA_DS
, port_mmio
+ EDMA_CMD_OFS
);
546 pp
->pp_flags
&= ~MV_PP_FLAG_EDMA_EN
;
548 assert(!(EDMA_EN
& readl(port_mmio
+ EDMA_CMD_OFS
)));
551 /* now properly wait for the eDMA to stop */
552 for (i
= 1000; i
> 0; i
--) {
553 reg
= readl(port_mmio
+ EDMA_CMD_OFS
);
554 if (!(EDMA_EN
& reg
)) {
561 printk(KERN_ERR
"ata%u: Unable to stop eDMA\n", ap
->id
);
562 /* FIXME: Consider doing a reset here to recover */
567 static void mv_dump_mem(void __iomem
*start
, unsigned bytes
)
570 for (b
= 0; b
< bytes
; ) {
571 DPRINTK("%p: ", start
+ b
);
572 for (w
= 0; b
< bytes
&& w
< 4; w
++) {
573 printk("%08x ",readl(start
+ b
));
581 static void mv_dump_pci_cfg(struct pci_dev
*pdev
, unsigned bytes
)
586 for (b
= 0; b
< bytes
; ) {
587 DPRINTK("%02x: ", b
);
588 for (w
= 0; b
< bytes
&& w
< 4; w
++) {
589 (void) pci_read_config_dword(pdev
,b
,&dw
);
597 static void mv_dump_all_regs(void __iomem
*mmio_base
, int port
,
598 struct pci_dev
*pdev
)
601 void __iomem
*hc_base
= mv_hc_base(mmio_base
,
602 port
>> MV_PORT_HC_SHIFT
);
603 void __iomem
*port_base
;
604 int start_port
, num_ports
, p
, start_hc
, num_hcs
, hc
;
607 start_hc
= start_port
= 0;
608 num_ports
= 8; /* shld be benign for 4 port devs */
611 start_hc
= port
>> MV_PORT_HC_SHIFT
;
613 num_ports
= num_hcs
= 1;
615 DPRINTK("All registers for port(s) %u-%u:\n", start_port
,
616 num_ports
> 1 ? num_ports
- 1 : start_port
);
619 DPRINTK("PCI config space regs:\n");
620 mv_dump_pci_cfg(pdev
, 0x68);
622 DPRINTK("PCI regs:\n");
623 mv_dump_mem(mmio_base
+0xc00, 0x3c);
624 mv_dump_mem(mmio_base
+0xd00, 0x34);
625 mv_dump_mem(mmio_base
+0xf00, 0x4);
626 mv_dump_mem(mmio_base
+0x1d00, 0x6c);
627 for (hc
= start_hc
; hc
< start_hc
+ num_hcs
; hc
++) {
628 hc_base
= mv_hc_base(mmio_base
, port
>> MV_PORT_HC_SHIFT
);
629 DPRINTK("HC regs (HC %i):\n", hc
);
630 mv_dump_mem(hc_base
, 0x1c);
632 for (p
= start_port
; p
< start_port
+ num_ports
; p
++) {
633 port_base
= mv_port_base(mmio_base
, p
);
634 DPRINTK("EDMA regs (port %i):\n",p
);
635 mv_dump_mem(port_base
, 0x54);
636 DPRINTK("SATA regs (port %i):\n",p
);
637 mv_dump_mem(port_base
+0x300, 0x60);
642 static unsigned int mv_scr_offset(unsigned int sc_reg_in
)
650 ofs
= SATA_STATUS_OFS
+ (sc_reg_in
* sizeof(u32
));
653 ofs
= SATA_ACTIVE_OFS
; /* active is not with the others */
662 static u32
mv_scr_read(struct ata_port
*ap
, unsigned int sc_reg_in
)
664 unsigned int ofs
= mv_scr_offset(sc_reg_in
);
666 if (0xffffffffU
!= ofs
) {
667 return readl(mv_ap_base(ap
) + ofs
);
673 static void mv_scr_write(struct ata_port
*ap
, unsigned int sc_reg_in
, u32 val
)
675 unsigned int ofs
= mv_scr_offset(sc_reg_in
);
677 if (0xffffffffU
!= ofs
) {
678 writelfl(val
, mv_ap_base(ap
) + ofs
);
683 #define ZERO(reg) writel(0, mmio + (reg))
684 static void mv_reset_pci_bus(struct pci_dev
*pdev
, void __iomem
*mmio
)
688 tmp
= readl(mmio
+ MV_PCI_MODE
);
690 writel(tmp
, mmio
+ MV_PCI_MODE
);
692 ZERO(MV_PCI_DISC_TIMER
);
693 ZERO(MV_PCI_MSI_TRIGGER
);
694 writel(0x000100ff, mmio
+ MV_PCI_XBAR_TMOUT
);
695 ZERO(HC_MAIN_IRQ_MASK_OFS
);
696 ZERO(MV_PCI_SERR_MASK
);
697 ZERO(PCI_IRQ_CAUSE_OFS
);
698 ZERO(PCI_IRQ_MASK_OFS
);
699 ZERO(MV_PCI_ERR_LOW_ADDRESS
);
700 ZERO(MV_PCI_ERR_HIGH_ADDRESS
);
701 ZERO(MV_PCI_ERR_ATTRIBUTE
);
702 ZERO(MV_PCI_ERR_COMMAND
);
706 static void mv6_reset_flash(struct mv_host_priv
*hpriv
, void __iomem
*mmio
)
710 mv5_reset_flash(hpriv
, mmio
);
712 tmp
= readl(mmio
+ MV_GPIO_PORT_CTL
);
714 tmp
|= (1 << 5) | (1 << 6);
715 writel(tmp
, mmio
+ MV_GPIO_PORT_CTL
);
719 * mv6_reset_hc - Perform the 6xxx global soft reset
720 * @mmio: base address of the HBA
722 * This routine only applies to 6xxx parts.
725 * Inherited from caller.
727 static int mv6_reset_hc(struct mv_host_priv
*hpriv
, void __iomem
*mmio
)
729 void __iomem
*reg
= mmio
+ PCI_MAIN_CMD_STS_OFS
;
733 /* Following procedure defined in PCI "main command and status
737 writel(t
| STOP_PCI_MASTER
, reg
);
739 for (i
= 0; i
< 1000; i
++) {
742 if (PCI_MASTER_EMPTY
& t
) {
746 if (!(PCI_MASTER_EMPTY
& t
)) {
747 printk(KERN_ERR DRV_NAME
": PCI master won't flush\n");
755 writel(t
| GLOB_SFT_RST
, reg
);
758 } while (!(GLOB_SFT_RST
& t
) && (i
-- > 0));
760 if (!(GLOB_SFT_RST
& t
)) {
761 printk(KERN_ERR DRV_NAME
": can't set global reset\n");
766 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
769 writel(t
& ~(GLOB_SFT_RST
| STOP_PCI_MASTER
), reg
);
772 } while ((GLOB_SFT_RST
& t
) && (i
-- > 0));
774 if (GLOB_SFT_RST
& t
) {
775 printk(KERN_ERR DRV_NAME
": can't clear global reset\n");
783 * mv_host_stop - Host specific cleanup/stop routine.
784 * @host_set: host data structure
786 * Disable ints, cleanup host memory, call general purpose
790 * Inherited from caller.
792 static void mv_host_stop(struct ata_host_set
*host_set
)
794 struct mv_host_priv
*hpriv
= host_set
->private_data
;
795 struct pci_dev
*pdev
= to_pci_dev(host_set
->dev
);
797 if (hpriv
->hp_flags
& MV_HP_FLAG_MSI
) {
798 pci_disable_msi(pdev
);
803 ata_host_stop(host_set
);
806 static inline void mv_priv_free(struct mv_port_priv
*pp
, struct device
*dev
)
808 dma_free_coherent(dev
, MV_PORT_PRIV_DMA_SZ
, pp
->crpb
, pp
->crpb_dma
);
812 * mv_port_start - Port specific init/start routine.
813 * @ap: ATA channel to manipulate
815 * Allocate and point to DMA memory, init port private memory,
819 * Inherited from caller.
821 static int mv_port_start(struct ata_port
*ap
)
823 struct device
*dev
= ap
->host_set
->dev
;
824 struct mv_port_priv
*pp
;
825 void __iomem
*port_mmio
= mv_ap_base(ap
);
830 pp
= kmalloc(sizeof(*pp
), GFP_KERNEL
);
833 memset(pp
, 0, sizeof(*pp
));
835 mem
= dma_alloc_coherent(dev
, MV_PORT_PRIV_DMA_SZ
, &mem_dma
,
839 memset(mem
, 0, MV_PORT_PRIV_DMA_SZ
);
841 rc
= ata_pad_alloc(ap
, dev
);
845 /* First item in chunk of DMA memory:
846 * 32-slot command request table (CRQB), 32 bytes each in size
849 pp
->crqb_dma
= mem_dma
;
851 mem_dma
+= MV_CRQB_Q_SZ
;
854 * 32-slot command response table (CRPB), 8 bytes each in size
857 pp
->crpb_dma
= mem_dma
;
859 mem_dma
+= MV_CRPB_Q_SZ
;
862 * Table of scatter-gather descriptors (ePRD), 16 bytes each
865 pp
->sg_tbl_dma
= mem_dma
;
867 writelfl(EDMA_CFG_Q_DEPTH
| EDMA_CFG_RD_BRST_EXT
|
868 EDMA_CFG_WR_BUFF_LEN
, port_mmio
+ EDMA_CFG_OFS
);
870 writel((pp
->crqb_dma
>> 16) >> 16, port_mmio
+ EDMA_REQ_Q_BASE_HI_OFS
);
871 writelfl(pp
->crqb_dma
& EDMA_REQ_Q_BASE_LO_MASK
,
872 port_mmio
+ EDMA_REQ_Q_IN_PTR_OFS
);
874 writelfl(0, port_mmio
+ EDMA_REQ_Q_OUT_PTR_OFS
);
875 writelfl(0, port_mmio
+ EDMA_RSP_Q_IN_PTR_OFS
);
877 writel((pp
->crpb_dma
>> 16) >> 16, port_mmio
+ EDMA_RSP_Q_BASE_HI_OFS
);
878 writelfl(pp
->crpb_dma
& EDMA_RSP_Q_BASE_LO_MASK
,
879 port_mmio
+ EDMA_RSP_Q_OUT_PTR_OFS
);
881 pp
->req_producer
= pp
->rsp_consumer
= 0;
883 /* Don't turn on EDMA here...do it before DMA commands only. Else
884 * we'll be unable to send non-data, PIO, etc due to restricted access
887 ap
->private_data
= pp
;
891 mv_priv_free(pp
, dev
);
899 * mv_port_stop - Port specific cleanup/stop routine.
900 * @ap: ATA channel to manipulate
902 * Stop DMA, cleanup port memory.
905 * This routine uses the host_set lock to protect the DMA stop.
907 static void mv_port_stop(struct ata_port
*ap
)
909 struct device
*dev
= ap
->host_set
->dev
;
910 struct mv_port_priv
*pp
= ap
->private_data
;
913 spin_lock_irqsave(&ap
->host_set
->lock
, flags
);
915 spin_unlock_irqrestore(&ap
->host_set
->lock
, flags
);
917 ap
->private_data
= NULL
;
918 ata_pad_free(ap
, dev
);
919 mv_priv_free(pp
, dev
);
924 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
925 * @qc: queued command whose SG list to source from
927 * Populate the SG list and mark the last entry.
930 * Inherited from caller.
932 static void mv_fill_sg(struct ata_queued_cmd
*qc
)
934 struct mv_port_priv
*pp
= qc
->ap
->private_data
;
936 struct scatterlist
*sg
;
938 ata_for_each_sg(sg
, qc
) {
942 addr
= sg_dma_address(sg
);
943 sg_len
= sg_dma_len(sg
);
945 pp
->sg_tbl
[i
].addr
= cpu_to_le32(addr
& 0xffffffff);
946 pp
->sg_tbl
[i
].addr_hi
= cpu_to_le32((addr
>> 16) >> 16);
947 assert(0 == (sg_len
& ~MV_DMA_BOUNDARY
));
948 pp
->sg_tbl
[i
].flags_size
= cpu_to_le32(sg_len
);
949 if (ata_sg_is_last(sg
, qc
))
950 pp
->sg_tbl
[i
].flags_size
|= cpu_to_le32(EPRD_FLAG_END_OF_TBL
);
956 static inline unsigned mv_inc_q_index(unsigned *index
)
958 *index
= (*index
+ 1) & MV_MAX_Q_DEPTH_MASK
;
962 static inline void mv_crqb_pack_cmd(u16
*cmdw
, u8 data
, u8 addr
, unsigned last
)
964 *cmdw
= data
| (addr
<< CRQB_CMD_ADDR_SHIFT
) | CRQB_CMD_CS
|
965 (last
? CRQB_CMD_LAST
: 0);
969 * mv_qc_prep - Host specific command preparation.
970 * @qc: queued command to prepare
972 * This routine simply redirects to the general purpose routine
973 * if command is not DMA. Else, it handles prep of the CRQB
974 * (command request block), does some sanity checking, and calls
975 * the SG load routine.
978 * Inherited from caller.
980 static void mv_qc_prep(struct ata_queued_cmd
*qc
)
982 struct ata_port
*ap
= qc
->ap
;
983 struct mv_port_priv
*pp
= ap
->private_data
;
985 struct ata_taskfile
*tf
;
988 if (ATA_PROT_DMA
!= qc
->tf
.protocol
) {
992 /* the req producer index should be the same as we remember it */
993 assert(((readl(mv_ap_base(qc
->ap
) + EDMA_REQ_Q_IN_PTR_OFS
) >>
994 EDMA_REQ_Q_PTR_SHIFT
) & MV_MAX_Q_DEPTH_MASK
) ==
997 /* Fill in command request block
999 if (!(qc
->tf
.flags
& ATA_TFLAG_WRITE
)) {
1000 flags
|= CRQB_FLAG_READ
;
1002 assert(MV_MAX_Q_DEPTH
> qc
->tag
);
1003 flags
|= qc
->tag
<< CRQB_TAG_SHIFT
;
1005 pp
->crqb
[pp
->req_producer
].sg_addr
=
1006 cpu_to_le32(pp
->sg_tbl_dma
& 0xffffffff);
1007 pp
->crqb
[pp
->req_producer
].sg_addr_hi
=
1008 cpu_to_le32((pp
->sg_tbl_dma
>> 16) >> 16);
1009 pp
->crqb
[pp
->req_producer
].ctrl_flags
= cpu_to_le16(flags
);
1011 cw
= &pp
->crqb
[pp
->req_producer
].ata_cmd
[0];
1014 /* Sadly, the CRQB cannot accomodate all registers--there are
1015 * only 11 bytes...so we must pick and choose required
1016 * registers based on the command. So, we drop feature and
1017 * hob_feature for [RW] DMA commands, but they are needed for
1018 * NCQ. NCQ will drop hob_nsect.
1020 switch (tf
->command
) {
1022 case ATA_CMD_READ_EXT
:
1024 case ATA_CMD_WRITE_EXT
:
1025 mv_crqb_pack_cmd(cw
++, tf
->hob_nsect
, ATA_REG_NSECT
, 0);
1027 #ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */
1028 case ATA_CMD_FPDMA_READ
:
1029 case ATA_CMD_FPDMA_WRITE
:
1030 mv_crqb_pack_cmd(cw
++, tf
->hob_feature
, ATA_REG_FEATURE
, 0);
1031 mv_crqb_pack_cmd(cw
++, tf
->feature
, ATA_REG_FEATURE
, 0);
1033 #endif /* FIXME: remove this line when NCQ added */
1035 /* The only other commands EDMA supports in non-queued and
1036 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1037 * of which are defined/used by Linux. If we get here, this
1038 * driver needs work.
1040 * FIXME: modify libata to give qc_prep a return value and
1041 * return error here.
1043 BUG_ON(tf
->command
);
1046 mv_crqb_pack_cmd(cw
++, tf
->nsect
, ATA_REG_NSECT
, 0);
1047 mv_crqb_pack_cmd(cw
++, tf
->hob_lbal
, ATA_REG_LBAL
, 0);
1048 mv_crqb_pack_cmd(cw
++, tf
->lbal
, ATA_REG_LBAL
, 0);
1049 mv_crqb_pack_cmd(cw
++, tf
->hob_lbam
, ATA_REG_LBAM
, 0);
1050 mv_crqb_pack_cmd(cw
++, tf
->lbam
, ATA_REG_LBAM
, 0);
1051 mv_crqb_pack_cmd(cw
++, tf
->hob_lbah
, ATA_REG_LBAH
, 0);
1052 mv_crqb_pack_cmd(cw
++, tf
->lbah
, ATA_REG_LBAH
, 0);
1053 mv_crqb_pack_cmd(cw
++, tf
->device
, ATA_REG_DEVICE
, 0);
1054 mv_crqb_pack_cmd(cw
++, tf
->command
, ATA_REG_CMD
, 1); /* last */
1056 if (!(qc
->flags
& ATA_QCFLAG_DMAMAP
)) {
1063 * mv_qc_issue - Initiate a command to the host
1064 * @qc: queued command to start
1066 * This routine simply redirects to the general purpose routine
1067 * if command is not DMA. Else, it sanity checks our local
1068 * caches of the request producer/consumer indices then enables
1069 * DMA and bumps the request producer index.
1072 * Inherited from caller.
1074 static int mv_qc_issue(struct ata_queued_cmd
*qc
)
1076 void __iomem
*port_mmio
= mv_ap_base(qc
->ap
);
1077 struct mv_port_priv
*pp
= qc
->ap
->private_data
;
1080 if (ATA_PROT_DMA
!= qc
->tf
.protocol
) {
1081 /* We're about to send a non-EDMA capable command to the
1082 * port. Turn off EDMA so there won't be problems accessing
1083 * shadow block, etc registers.
1085 mv_stop_dma(qc
->ap
);
1086 return ata_qc_issue_prot(qc
);
1089 in_ptr
= readl(port_mmio
+ EDMA_REQ_Q_IN_PTR_OFS
);
1091 /* the req producer index should be the same as we remember it */
1092 assert(((in_ptr
>> EDMA_REQ_Q_PTR_SHIFT
) & MV_MAX_Q_DEPTH_MASK
) ==
1094 /* until we do queuing, the queue should be empty at this point */
1095 assert(((in_ptr
>> EDMA_REQ_Q_PTR_SHIFT
) & MV_MAX_Q_DEPTH_MASK
) ==
1096 ((readl(port_mmio
+ EDMA_REQ_Q_OUT_PTR_OFS
) >>
1097 EDMA_REQ_Q_PTR_SHIFT
) & MV_MAX_Q_DEPTH_MASK
));
1099 mv_inc_q_index(&pp
->req_producer
); /* now incr producer index */
1101 mv_start_dma(port_mmio
, pp
);
1103 /* and write the request in pointer to kick the EDMA to life */
1104 in_ptr
&= EDMA_REQ_Q_BASE_LO_MASK
;
1105 in_ptr
|= pp
->req_producer
<< EDMA_REQ_Q_PTR_SHIFT
;
1106 writelfl(in_ptr
, port_mmio
+ EDMA_REQ_Q_IN_PTR_OFS
);
1112 * mv_get_crpb_status - get status from most recently completed cmd
1113 * @ap: ATA channel to manipulate
1115 * This routine is for use when the port is in DMA mode, when it
1116 * will be using the CRPB (command response block) method of
1117 * returning command completion information. We assert indices
1118 * are good, grab status, and bump the response consumer index to
1119 * prove that we're up to date.
1122 * Inherited from caller.
1124 static u8
mv_get_crpb_status(struct ata_port
*ap
)
1126 void __iomem
*port_mmio
= mv_ap_base(ap
);
1127 struct mv_port_priv
*pp
= ap
->private_data
;
1130 out_ptr
= readl(port_mmio
+ EDMA_RSP_Q_OUT_PTR_OFS
);
1132 /* the response consumer index should be the same as we remember it */
1133 assert(((out_ptr
>> EDMA_RSP_Q_PTR_SHIFT
) & MV_MAX_Q_DEPTH_MASK
) ==
1136 /* increment our consumer index... */
1137 pp
->rsp_consumer
= mv_inc_q_index(&pp
->rsp_consumer
);
1139 /* and, until we do NCQ, there should only be 1 CRPB waiting */
1140 assert(((readl(port_mmio
+ EDMA_RSP_Q_IN_PTR_OFS
) >>
1141 EDMA_RSP_Q_PTR_SHIFT
) & MV_MAX_Q_DEPTH_MASK
) ==
1144 /* write out our inc'd consumer index so EDMA knows we're caught up */
1145 out_ptr
&= EDMA_RSP_Q_BASE_LO_MASK
;
1146 out_ptr
|= pp
->rsp_consumer
<< EDMA_RSP_Q_PTR_SHIFT
;
1147 writelfl(out_ptr
, port_mmio
+ EDMA_RSP_Q_OUT_PTR_OFS
);
1149 /* Return ATA status register for completed CRPB */
1150 return (pp
->crpb
[pp
->rsp_consumer
].flags
>> CRPB_FLAG_STATUS_SHIFT
);
1154 * mv_err_intr - Handle error interrupts on the port
1155 * @ap: ATA channel to manipulate
1157 * In most cases, just clear the interrupt and move on. However,
1158 * some cases require an eDMA reset, which is done right before
1159 * the COMRESET in mv_phy_reset(). The SERR case requires a
1160 * clear of pending errors in the SATA SERROR register. Finally,
1161 * if the port disabled DMA, update our cached copy to match.
1164 * Inherited from caller.
1166 static void mv_err_intr(struct ata_port
*ap
)
1168 void __iomem
*port_mmio
= mv_ap_base(ap
);
1169 u32 edma_err_cause
, serr
= 0;
1171 edma_err_cause
= readl(port_mmio
+ EDMA_ERR_IRQ_CAUSE_OFS
);
1173 if (EDMA_ERR_SERR
& edma_err_cause
) {
1174 serr
= scr_read(ap
, SCR_ERROR
);
1175 scr_write_flush(ap
, SCR_ERROR
, serr
);
1177 if (EDMA_ERR_SELF_DIS
& edma_err_cause
) {
1178 struct mv_port_priv
*pp
= ap
->private_data
;
1179 pp
->pp_flags
&= ~MV_PP_FLAG_EDMA_EN
;
1181 DPRINTK(KERN_ERR
"ata%u: port error; EDMA err cause: 0x%08x "
1182 "SERR: 0x%08x\n", ap
->id
, edma_err_cause
, serr
);
1184 /* Clear EDMA now that SERR cleanup done */
1185 writelfl(0, port_mmio
+ EDMA_ERR_IRQ_CAUSE_OFS
);
1187 /* check for fatal here and recover if needed */
1188 if (EDMA_ERR_FATAL
& edma_err_cause
) {
1194 * mv_host_intr - Handle all interrupts on the given host controller
1195 * @host_set: host specific structure
1196 * @relevant: port error bits relevant to this host controller
1197 * @hc: which host controller we're to look at
1199 * Read then write clear the HC interrupt status then walk each
1200 * port connected to the HC and see if it needs servicing. Port
1201 * success ints are reported in the HC interrupt status reg, the
1202 * port error ints are reported in the higher level main
1203 * interrupt status register and thus are passed in via the
1204 * 'relevant' argument.
1207 * Inherited from caller.
1209 static void mv_host_intr(struct ata_host_set
*host_set
, u32 relevant
,
1212 void __iomem
*mmio
= host_set
->mmio_base
;
1213 void __iomem
*hc_mmio
= mv_hc_base(mmio
, hc
);
1214 struct ata_port
*ap
;
1215 struct ata_queued_cmd
*qc
;
1217 int shift
, port
, port0
, hard_port
, handled
;
1218 unsigned int err_mask
;
1224 port0
= MV_PORTS_PER_HC
;
1227 /* we'll need the HC success int register in most cases */
1228 hc_irq_cause
= readl(hc_mmio
+ HC_IRQ_CAUSE_OFS
);
1230 writelfl(~hc_irq_cause
, hc_mmio
+ HC_IRQ_CAUSE_OFS
);
1233 VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n",
1234 hc
,relevant
,hc_irq_cause
);
1236 for (port
= port0
; port
< port0
+ MV_PORTS_PER_HC
; port
++) {
1237 ap
= host_set
->ports
[port
];
1238 hard_port
= port
& MV_PORT_MASK
; /* range 0-3 */
1239 handled
= 0; /* ensure ata_status is set if handled++ */
1241 if ((CRPB_DMA_DONE
<< hard_port
) & hc_irq_cause
) {
1242 /* new CRPB on the queue; just one at a time until NCQ
1244 ata_status
= mv_get_crpb_status(ap
);
1246 } else if ((DEV_IRQ
<< hard_port
) & hc_irq_cause
) {
1247 /* received ATA IRQ; read the status reg to clear INTRQ
1249 ata_status
= readb((void __iomem
*)
1250 ap
->ioaddr
.status_addr
);
1254 err_mask
= ac_err_mask(ata_status
);
1256 shift
= port
<< 1; /* (port * 2) */
1257 if (port
>= MV_PORTS_PER_HC
) {
1258 shift
++; /* skip bit 8 in the HC Main IRQ reg */
1260 if ((PORT0_ERR
<< shift
) & relevant
) {
1262 err_mask
|= AC_ERR_OTHER
;
1266 if (handled
&& ap
) {
1267 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
1269 VPRINTK("port %u IRQ found for qc, "
1270 "ata_status 0x%x\n", port
,ata_status
);
1271 /* mark qc status appropriately */
1272 ata_qc_complete(qc
, err_mask
);
1282 * @dev_instance: private data; in this case the host structure
1285 * Read the read only register to determine if any host
1286 * controllers have pending interrupts. If so, call lower level
1287 * routine to handle. Also check for PCI errors which are only
1291 * This routine holds the host_set lock while processing pending
1294 static irqreturn_t
mv_interrupt(int irq
, void *dev_instance
,
1295 struct pt_regs
*regs
)
1297 struct ata_host_set
*host_set
= dev_instance
;
1298 unsigned int hc
, handled
= 0, n_hcs
;
1299 void __iomem
*mmio
= host_set
->mmio_base
;
1302 irq_stat
= readl(mmio
+ HC_MAIN_IRQ_CAUSE_OFS
);
1304 /* check the cases where we either have nothing pending or have read
1305 * a bogus register value which can indicate HW removal or PCI fault
1307 if (!irq_stat
|| (0xffffffffU
== irq_stat
)) {
1311 n_hcs
= mv_get_hc_count(host_set
->ports
[0]->flags
);
1312 spin_lock(&host_set
->lock
);
1314 for (hc
= 0; hc
< n_hcs
; hc
++) {
1315 u32 relevant
= irq_stat
& (HC0_IRQ_PEND
<< (hc
* HC_SHIFT
));
1317 mv_host_intr(host_set
, relevant
, hc
);
1321 if (PCI_ERR
& irq_stat
) {
1322 printk(KERN_ERR DRV_NAME
": PCI ERROR; PCI IRQ cause=0x%08x\n",
1323 readl(mmio
+ PCI_IRQ_CAUSE_OFS
));
1325 DPRINTK("All regs @ PCI error\n");
1326 mv_dump_all_regs(mmio
, -1, to_pci_dev(host_set
->dev
));
1328 writelfl(0, mmio
+ PCI_IRQ_CAUSE_OFS
);
1331 spin_unlock(&host_set
->lock
);
1333 return IRQ_RETVAL(handled
);
1336 static void mv5_reset_bus(struct pci_dev
*pdev
, void __iomem
*mmio
)
1341 pci_read_config_byte(pdev
, PCI_REVISION_ID
, &rev_id
);
1343 early_5080
= (pdev
->device
== 0x5080) && (rev_id
== 0);
1346 u32 tmp
= readl(mmio
+ MV_PCI_EXP_ROM_BAR_CTL
);
1348 writel(tmp
, mmio
+ MV_PCI_EXP_ROM_BAR_CTL
);
1351 mv_reset_pci_bus(pdev
, mmio
);
1354 static void mv5_reset_flash(struct mv_host_priv
*hpriv
, void __iomem
*mmio
)
1356 writel(0x0fcfffff, mmio
+ MV_FLASH_CTL
);
1359 static void mv5_read_preamp(struct mv_host_priv
*hpriv
, int idx
,
1365 static void mv5_enable_leds(struct mv_host_priv
*hpriv
, void __iomem
*mmio
)
1369 writel(0, mmio
+ MV_GPIO_PORT_CTL
);
1371 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
1373 tmp
= readl(mmio
+ MV_PCI_EXP_ROM_BAR_CTL
);
1375 writel(tmp
, mmio
+ MV_PCI_EXP_ROM_BAR_CTL
);
1378 static void mv5_phy_errata(struct ata_port
*ap
)
1383 static int mv5_reset_hc(struct mv_host_priv
*hpriv
, void __iomem
*mmio
)
1389 static void mv6_read_preamp(struct mv_host_priv
*hpriv
, int idx
,
1392 void __iomem
*port_mmio
;
1395 tmp
= readl(mmio
+ MV_RESET_CFG
);
1396 if ((tmp
& (1 << 0)) == 0) {
1397 hpriv
->signal
[idx
].amps
= 0x7 << 8;
1398 hpriv
->signal
[idx
].pre
= 0x1 << 5;
1402 port_mmio
= mv_port_base(mmio
, idx
);
1403 tmp
= readl(port_mmio
+ PHY_MODE2
);
1405 hpriv
->signal
[idx
].amps
= tmp
& 0x700; /* bits 10:8 */
1406 hpriv
->signal
[idx
].pre
= tmp
& 0xe0; /* bits 7:5 */
1409 static void mv6_enable_leds(struct mv_host_priv
*hpriv
, void __iomem
*mmio
)
1411 writel(0x00000060, mmio
+ MV_GPIO_PORT_CTL
);
1414 static void mv6_phy_errata(struct ata_port
*ap
)
1416 struct mv_host_priv
*hpriv
= ap
->host_set
->private_data
;
1417 u32 hp_flags
= hpriv
->hp_flags
;
1418 void __iomem
*port_mmio
= mv_ap_base(ap
);
1420 hp_flags
& (MV_HP_ERRATA_60X1B2
| MV_HP_ERRATA_60X1C0
);
1422 hp_flags
& (MV_HP_ERRATA_60X1B2
| MV_HP_ERRATA_60X1C0
);
1425 if (fix_phy_mode2
) {
1426 m2
= readl(port_mmio
+ PHY_MODE2
);
1429 writel(m2
, port_mmio
+ PHY_MODE2
);
1433 m2
= readl(port_mmio
+ PHY_MODE2
);
1434 m2
&= ~((1 << 16) | (1 << 31));
1435 writel(m2
, port_mmio
+ PHY_MODE2
);
1440 /* who knows what this magic does */
1441 tmp
= readl(port_mmio
+ PHY_MODE3
);
1444 writel(tmp
, port_mmio
+ PHY_MODE3
);
1446 if (fix_phy_mode4
) {
1449 m4
= readl(port_mmio
+ PHY_MODE4
);
1451 if (hp_flags
& MV_HP_ERRATA_60X1B2
)
1452 tmp
= readl(port_mmio
+ 0x310);
1454 m4
= (m4
& ~(1 << 1)) | (1 << 0);
1456 writel(m4
, port_mmio
+ PHY_MODE4
);
1458 if (hp_flags
& MV_HP_ERRATA_60X1B2
)
1459 writel(tmp
, port_mmio
+ 0x310);
1462 /* Revert values of pre-emphasis and signal amps to the saved ones */
1463 m2
= readl(port_mmio
+ PHY_MODE2
);
1465 m2
&= ~MV_M2_PREAMP_MASK
;
1466 m2
|= hpriv
->signal
[ap
->port_no
].amps
;
1467 m2
|= hpriv
->signal
[ap
->port_no
].pre
;
1470 writel(m2
, port_mmio
+ PHY_MODE2
);
1474 * mv_phy_reset - Perform eDMA reset followed by COMRESET
1475 * @ap: ATA channel to manipulate
1477 * Part of this is taken from __sata_phy_reset and modified to
1478 * not sleep since this routine gets called from interrupt level.
1481 * Inherited from caller. This is coded to safe to call at
1482 * interrupt level, i.e. it does not sleep.
1484 static void mv_phy_reset(struct ata_port
*ap
)
1486 struct mv_port_priv
*pp
= ap
->private_data
;
1487 struct mv_host_priv
*hpriv
= ap
->host_set
->private_data
;
1488 void __iomem
*port_mmio
= mv_ap_base(ap
);
1489 struct ata_taskfile tf
;
1490 struct ata_device
*dev
= &ap
->device
[0];
1491 unsigned long timeout
;
1493 VPRINTK("ENTER, port %u, mmio 0x%p\n", ap
->port_no
, port_mmio
);
1497 writelfl(ATA_RST
, port_mmio
+ EDMA_CMD_OFS
);
1499 if (IS_60XX(hpriv
)) {
1500 u32 ifctl
= readl(port_mmio
+ SATA_INTERFACE_CTL
);
1501 ifctl
|= (1 << 12) | (1 << 7);
1502 writelfl(ifctl
, port_mmio
+ SATA_INTERFACE_CTL
);
1505 udelay(25); /* allow reset propagation */
1507 /* Spec never mentions clearing the bit. Marvell's driver does
1508 * clear the bit, however.
1510 writelfl(0, port_mmio
+ EDMA_CMD_OFS
);
1512 hpriv
->ops
->phy_errata(ap
);
1514 DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
1515 "SCtrl 0x%08x\n", mv_scr_read(ap
, SCR_STATUS
),
1516 mv_scr_read(ap
, SCR_ERROR
), mv_scr_read(ap
, SCR_CONTROL
));
1518 /* proceed to init communications via the scr_control reg */
1519 scr_write_flush(ap
, SCR_CONTROL
, 0x301);
1521 scr_write_flush(ap
, SCR_CONTROL
, 0x300);
1522 timeout
= jiffies
+ (HZ
* 1);
1525 if ((scr_read(ap
, SCR_STATUS
) & 0xf) != 1)
1527 } while (time_before(jiffies
, timeout
));
1529 mv_scr_write(ap
, SCR_ERROR
, mv_scr_read(ap
, SCR_ERROR
));
1531 DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x "
1532 "SCtrl 0x%08x\n", mv_scr_read(ap
, SCR_STATUS
),
1533 mv_scr_read(ap
, SCR_ERROR
), mv_scr_read(ap
, SCR_CONTROL
));
1535 if (sata_dev_present(ap
)) {
1538 printk(KERN_INFO
"ata%u: no device found (phy stat %08x)\n",
1539 ap
->id
, scr_read(ap
, SCR_STATUS
));
1540 ata_port_disable(ap
);
1543 ap
->cbl
= ATA_CBL_SATA
;
1545 tf
.lbah
= readb((void __iomem
*) ap
->ioaddr
.lbah_addr
);
1546 tf
.lbam
= readb((void __iomem
*) ap
->ioaddr
.lbam_addr
);
1547 tf
.lbal
= readb((void __iomem
*) ap
->ioaddr
.lbal_addr
);
1548 tf
.nsect
= readb((void __iomem
*) ap
->ioaddr
.nsect_addr
);
1550 dev
->class = ata_dev_classify(&tf
);
1551 if (!ata_dev_present(dev
)) {
1552 VPRINTK("Port disabled post-sig: No device present.\n");
1553 ata_port_disable(ap
);
1556 writelfl(0, port_mmio
+ EDMA_ERR_IRQ_CAUSE_OFS
);
1558 pp
->pp_flags
&= ~MV_PP_FLAG_EDMA_EN
;
1564 * mv_eng_timeout - Routine called by libata when SCSI times out I/O
1565 * @ap: ATA channel to manipulate
1567 * Intent is to clear all pending error conditions, reset the
1568 * chip/bus, fail the command, and move on.
1571 * This routine holds the host_set lock while failing the command.
1573 static void mv_eng_timeout(struct ata_port
*ap
)
1575 struct ata_queued_cmd
*qc
;
1576 unsigned long flags
;
1578 printk(KERN_ERR
"ata%u: Entering mv_eng_timeout\n",ap
->id
);
1579 DPRINTK("All regs @ start of eng_timeout\n");
1580 mv_dump_all_regs(ap
->host_set
->mmio_base
, ap
->port_no
,
1581 to_pci_dev(ap
->host_set
->dev
));
1583 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
1584 printk(KERN_ERR
"mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n",
1585 ap
->host_set
->mmio_base
, ap
, qc
, qc
->scsicmd
,
1586 &qc
->scsicmd
->cmnd
);
1592 printk(KERN_ERR
"ata%u: BUG: timeout without command\n",
1595 /* hack alert! We cannot use the supplied completion
1596 * function from inside the ->eh_strategy_handler() thread.
1597 * libata is the only user of ->eh_strategy_handler() in
1598 * any kernel, so the default scsi_done() assumes it is
1599 * not being called from the SCSI EH.
1601 spin_lock_irqsave(&ap
->host_set
->lock
, flags
);
1602 qc
->scsidone
= scsi_finish_command
;
1603 ata_qc_complete(qc
, AC_ERR_OTHER
);
1604 spin_unlock_irqrestore(&ap
->host_set
->lock
, flags
);
1609 * mv_port_init - Perform some early initialization on a single port.
1610 * @port: libata data structure storing shadow register addresses
1611 * @port_mmio: base address of the port
1613 * Initialize shadow register mmio addresses, clear outstanding
1614 * interrupts on the port, and unmask interrupts for the future
1615 * start of the port.
1618 * Inherited from caller.
1620 static void mv_port_init(struct ata_ioports
*port
, void __iomem
*port_mmio
)
1622 unsigned long shd_base
= (unsigned long) port_mmio
+ SHD_BLK_OFS
;
1625 /* PIO related setup
1627 port
->data_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_DATA
);
1629 port
->feature_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_ERR
);
1630 port
->nsect_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_NSECT
);
1631 port
->lbal_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_LBAL
);
1632 port
->lbam_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_LBAM
);
1633 port
->lbah_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_LBAH
);
1634 port
->device_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_DEVICE
);
1636 port
->command_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_STATUS
);
1637 /* special case: control/altstatus doesn't have ATA_REG_ address */
1638 port
->altstatus_addr
= port
->ctl_addr
= shd_base
+ SHD_CTL_AST_OFS
;
1641 port
->cmd_addr
= port
->bmdma_addr
= port
->scr_addr
= 0;
1643 /* Clear any currently outstanding port interrupt conditions */
1644 serr_ofs
= mv_scr_offset(SCR_ERROR
);
1645 writelfl(readl(port_mmio
+ serr_ofs
), port_mmio
+ serr_ofs
);
1646 writelfl(0, port_mmio
+ EDMA_ERR_IRQ_CAUSE_OFS
);
1648 /* unmask all EDMA error interrupts */
1649 writelfl(~0, port_mmio
+ EDMA_ERR_IRQ_MASK_OFS
);
1651 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
1652 readl(port_mmio
+ EDMA_CFG_OFS
),
1653 readl(port_mmio
+ EDMA_ERR_IRQ_CAUSE_OFS
),
1654 readl(port_mmio
+ EDMA_ERR_IRQ_MASK_OFS
));
1657 static int mv_chip_id(struct pci_dev
*pdev
, struct mv_host_priv
*hpriv
,
1658 unsigned int board_idx
)
1661 u32 hp_flags
= hpriv
->hp_flags
;
1663 pci_read_config_byte(pdev
, PCI_REVISION_ID
, &rev_id
);
1667 hpriv
->ops
= &mv5xxx_ops
;
1668 hp_flags
|= MV_HP_50XX
;
1672 hp_flags
|= MV_HP_ERRATA_50XXB0
;
1675 hp_flags
|= MV_HP_ERRATA_50XXB2
;
1678 dev_printk(KERN_WARNING
, &pdev
->dev
,
1679 "Applying 50XXB2 workarounds to unknown rev\n");
1680 hp_flags
|= MV_HP_ERRATA_50XXB2
;
1687 hpriv
->ops
= &mv5xxx_ops
;
1688 hp_flags
|= MV_HP_50XX
;
1692 hp_flags
|= MV_HP_ERRATA_50XXB0
;
1695 hp_flags
|= MV_HP_ERRATA_50XXB2
;
1698 dev_printk(KERN_WARNING
, &pdev
->dev
,
1699 "Applying B2 workarounds to unknown rev\n");
1700 hp_flags
|= MV_HP_ERRATA_50XXB2
;
1707 hpriv
->ops
= &mv6xxx_ops
;
1711 hp_flags
|= MV_HP_ERRATA_60X1B2
;
1714 hp_flags
|= MV_HP_ERRATA_60X1C0
;
1717 dev_printk(KERN_WARNING
, &pdev
->dev
,
1718 "Applying B2 workarounds to unknown rev\n");
1719 hp_flags
|= MV_HP_ERRATA_60X1B2
;
1725 printk(KERN_ERR DRV_NAME
": BUG: invalid board index %u\n", board_idx
);
1729 hpriv
->hp_flags
= hp_flags
;
1735 * mv_init_host - Perform some early initialization of the host.
1736 * @pdev: host PCI device
1737 * @probe_ent: early data struct representing the host
1739 * If possible, do an early global reset of the host. Then do
1740 * our port init and clear/unmask all/relevant host interrupts.
1743 * Inherited from caller.
1745 static int mv_init_host(struct pci_dev
*pdev
, struct ata_probe_ent
*probe_ent
,
1746 unsigned int board_idx
)
1748 int rc
= 0, n_hc
, port
, hc
;
1749 void __iomem
*mmio
= probe_ent
->mmio_base
;
1750 void __iomem
*port_mmio
;
1751 struct mv_host_priv
*hpriv
= probe_ent
->private_data
;
1753 /* global interrupt mask */
1754 writel(0, mmio
+ HC_MAIN_IRQ_MASK_OFS
);
1756 rc
= mv_chip_id(pdev
, hpriv
, board_idx
);
1760 n_hc
= mv_get_hc_count(probe_ent
->host_flags
);
1761 probe_ent
->n_ports
= MV_PORTS_PER_HC
* n_hc
;
1763 for (port
= 0; port
< probe_ent
->n_ports
; port
++)
1764 hpriv
->ops
->read_preamp(hpriv
, port
, mmio
);
1766 rc
= hpriv
->ops
->reset_hc(hpriv
, mmio
);
1770 hpriv
->ops
->reset_flash(hpriv
, mmio
);
1771 hpriv
->ops
->reset_bus(pdev
, mmio
);
1772 hpriv
->ops
->enable_leds(hpriv
, mmio
);
1774 for (port
= 0; port
< probe_ent
->n_ports
; port
++) {
1775 port_mmio
= mv_port_base(mmio
, port
);
1776 mv_port_init(&probe_ent
->port
[port
], port_mmio
);
1779 for (hc
= 0; hc
< n_hc
; hc
++) {
1780 void __iomem
*hc_mmio
= mv_hc_base(mmio
, hc
);
1782 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
1783 "(before clear)=0x%08x\n", hc
,
1784 readl(hc_mmio
+ HC_CFG_OFS
),
1785 readl(hc_mmio
+ HC_IRQ_CAUSE_OFS
));
1787 /* Clear any currently outstanding hc interrupt conditions */
1788 writelfl(0, hc_mmio
+ HC_IRQ_CAUSE_OFS
);
1791 /* Clear any currently outstanding host interrupt conditions */
1792 writelfl(0, mmio
+ PCI_IRQ_CAUSE_OFS
);
1794 /* and unmask interrupt generation for host regs */
1795 writelfl(PCI_UNMASK_ALL_IRQS
, mmio
+ PCI_IRQ_MASK_OFS
);
1796 writelfl(~HC_MAIN_MASKED_IRQS
, mmio
+ HC_MAIN_IRQ_MASK_OFS
);
1798 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
1799 "PCI int cause/mask=0x%08x/0x%08x\n",
1800 readl(mmio
+ HC_MAIN_IRQ_CAUSE_OFS
),
1801 readl(mmio
+ HC_MAIN_IRQ_MASK_OFS
),
1802 readl(mmio
+ PCI_IRQ_CAUSE_OFS
),
1803 readl(mmio
+ PCI_IRQ_MASK_OFS
));
1810 * mv_print_info - Dump key info to kernel log for perusal.
1811 * @probe_ent: early data struct representing the host
1813 * FIXME: complete this.
1816 * Inherited from caller.
1818 static void mv_print_info(struct ata_probe_ent
*probe_ent
)
1820 struct pci_dev
*pdev
= to_pci_dev(probe_ent
->dev
);
1821 struct mv_host_priv
*hpriv
= probe_ent
->private_data
;
1825 /* Use this to determine the HW stepping of the chip so we know
1826 * what errata to workaround
1828 pci_read_config_byte(pdev
, PCI_REVISION_ID
, &rev_id
);
1830 pci_read_config_byte(pdev
, PCI_CLASS_DEVICE
, &scc
);
1833 else if (scc
== 0x01)
1838 dev_printk(KERN_INFO
, &pdev
->dev
,
1839 "%u slots %u ports %s mode IRQ via %s\n",
1840 (unsigned)MV_MAX_Q_DEPTH
, probe_ent
->n_ports
,
1841 scc_s
, (MV_HP_FLAG_MSI
& hpriv
->hp_flags
) ? "MSI" : "INTx");
1845 * mv_init_one - handle a positive probe of a Marvell host
1846 * @pdev: PCI device found
1847 * @ent: PCI device ID entry for the matched host
1850 * Inherited from caller.
1852 static int mv_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1854 static int printed_version
= 0;
1855 struct ata_probe_ent
*probe_ent
= NULL
;
1856 struct mv_host_priv
*hpriv
;
1857 unsigned int board_idx
= (unsigned int)ent
->driver_data
;
1858 void __iomem
*mmio_base
;
1859 int pci_dev_busy
= 0, rc
;
1861 if (!printed_version
++)
1862 dev_printk(KERN_INFO
, &pdev
->dev
, "version " DRV_VERSION
"\n");
1864 rc
= pci_enable_device(pdev
);
1869 rc
= pci_request_regions(pdev
, DRV_NAME
);
1875 probe_ent
= kmalloc(sizeof(*probe_ent
), GFP_KERNEL
);
1876 if (probe_ent
== NULL
) {
1878 goto err_out_regions
;
1881 memset(probe_ent
, 0, sizeof(*probe_ent
));
1882 probe_ent
->dev
= pci_dev_to_dev(pdev
);
1883 INIT_LIST_HEAD(&probe_ent
->node
);
1885 mmio_base
= pci_iomap(pdev
, MV_PRIMARY_BAR
, 0);
1886 if (mmio_base
== NULL
) {
1888 goto err_out_free_ent
;
1891 hpriv
= kmalloc(sizeof(*hpriv
), GFP_KERNEL
);
1894 goto err_out_iounmap
;
1896 memset(hpriv
, 0, sizeof(*hpriv
));
1898 probe_ent
->sht
= mv_port_info
[board_idx
].sht
;
1899 probe_ent
->host_flags
= mv_port_info
[board_idx
].host_flags
;
1900 probe_ent
->pio_mask
= mv_port_info
[board_idx
].pio_mask
;
1901 probe_ent
->udma_mask
= mv_port_info
[board_idx
].udma_mask
;
1902 probe_ent
->port_ops
= mv_port_info
[board_idx
].port_ops
;
1904 probe_ent
->irq
= pdev
->irq
;
1905 probe_ent
->irq_flags
= SA_SHIRQ
;
1906 probe_ent
->mmio_base
= mmio_base
;
1907 probe_ent
->private_data
= hpriv
;
1909 /* initialize adapter */
1910 rc
= mv_init_host(pdev
, probe_ent
, board_idx
);
1915 /* Enable interrupts */
1916 if (pci_enable_msi(pdev
) == 0) {
1917 hpriv
->hp_flags
|= MV_HP_FLAG_MSI
;
1922 mv_dump_pci_cfg(pdev
, 0x68);
1923 mv_print_info(probe_ent
);
1925 if (ata_device_add(probe_ent
) == 0) {
1926 rc
= -ENODEV
; /* No devices discovered */
1927 goto err_out_dev_add
;
1934 if (MV_HP_FLAG_MSI
& hpriv
->hp_flags
) {
1935 pci_disable_msi(pdev
);
1942 pci_iounmap(pdev
, mmio_base
);
1946 pci_release_regions(pdev
);
1948 if (!pci_dev_busy
) {
1949 pci_disable_device(pdev
);
1955 static int __init
mv_init(void)
1957 return pci_module_init(&mv_pci_driver
);
1960 static void __exit
mv_exit(void)
1962 pci_unregister_driver(&mv_pci_driver
);
1965 MODULE_AUTHOR("Brett Russ");
1966 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
1967 MODULE_LICENSE("GPL");
1968 MODULE_DEVICE_TABLE(pci
, mv_pci_tbl
);
1969 MODULE_VERSION(DRV_VERSION
);
1971 module_init(mv_init
);
1972 module_exit(mv_exit
);