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IB/mthca: Fix SRQ cleanup during QP destroy
[linux-2.6/verdex.git] / drivers / infiniband / hw / mthca / mthca_cq.c
blobfcef8dc2c121d2645db2cefe8cc8e2e7f0185f84
1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005 Cisco Systems, Inc. All rights reserved.
5 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7 *
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
13 *
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
16 * conditions are met:
17 *
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer.
21 *
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * SOFTWARE.
35 *
36 * $Id: mthca_cq.c 1369 2004-12-20 16:17:07Z roland $
37 */
38
39 #include <linux/init.h>
40 #include <linux/hardirq.h>
41
42 #include <rdma/ib_pack.h>
43
44 #include "mthca_dev.h"
45 #include "mthca_cmd.h"
46 #include "mthca_memfree.h"
47
48 enum {
49 MTHCA_MAX_DIRECT_CQ_SIZE = 4 * PAGE_SIZE
50 };
51
52 enum {
53 MTHCA_CQ_ENTRY_SIZE = 0x20
54 };
55
56 /*
57 * Must be packed because start is 64 bits but only aligned to 32 bits.
58 */
59 struct mthca_cq_context {
60 __be32 flags;
61 __be64 start;
62 __be32 logsize_usrpage;
63 __be32 error_eqn; /* Tavor only */
64 __be32 comp_eqn;
65 __be32 pd;
66 __be32 lkey;
67 __be32 last_notified_index;
68 __be32 solicit_producer_index;
69 __be32 consumer_index;
70 __be32 producer_index;
71 __be32 cqn;
72 __be32 ci_db; /* Arbel only */
73 __be32 state_db; /* Arbel only */
74 u32 reserved;
75 } __attribute__((packed));
76
77 #define MTHCA_CQ_STATUS_OK ( 0 << 28)
78 #define MTHCA_CQ_STATUS_OVERFLOW ( 9 << 28)
79 #define MTHCA_CQ_STATUS_WRITE_FAIL (10 << 28)
80 #define MTHCA_CQ_FLAG_TR ( 1 << 18)
81 #define MTHCA_CQ_FLAG_OI ( 1 << 17)
82 #define MTHCA_CQ_STATE_DISARMED ( 0 << 8)
83 #define MTHCA_CQ_STATE_ARMED ( 1 << 8)
84 #define MTHCA_CQ_STATE_ARMED_SOL ( 4 << 8)
85 #define MTHCA_EQ_STATE_FIRED (10 << 8)
86
87 enum {
88 MTHCA_ERROR_CQE_OPCODE_MASK = 0xfe
89 };
90
91 enum {
92 SYNDROME_LOCAL_LENGTH_ERR = 0x01,
93 SYNDROME_LOCAL_QP_OP_ERR = 0x02,
94 SYNDROME_LOCAL_EEC_OP_ERR = 0x03,
95 SYNDROME_LOCAL_PROT_ERR = 0x04,
96 SYNDROME_WR_FLUSH_ERR = 0x05,
97 SYNDROME_MW_BIND_ERR = 0x06,
98 SYNDROME_BAD_RESP_ERR = 0x10,
99 SYNDROME_LOCAL_ACCESS_ERR = 0x11,
100 SYNDROME_REMOTE_INVAL_REQ_ERR = 0x12,
101 SYNDROME_REMOTE_ACCESS_ERR = 0x13,
102 SYNDROME_REMOTE_OP_ERR = 0x14,
103 SYNDROME_RETRY_EXC_ERR = 0x15,
104 SYNDROME_RNR_RETRY_EXC_ERR = 0x16,
105 SYNDROME_LOCAL_RDD_VIOL_ERR = 0x20,
106 SYNDROME_REMOTE_INVAL_RD_REQ_ERR = 0x21,
107 SYNDROME_REMOTE_ABORTED_ERR = 0x22,
108 SYNDROME_INVAL_EECN_ERR = 0x23,
109 SYNDROME_INVAL_EEC_STATE_ERR = 0x24
110 };
111
112 struct mthca_cqe {
113 __be32 my_qpn;
114 __be32 my_ee;
115 __be32 rqpn;
116 __be16 sl_g_mlpath;
117 __be16 rlid;
118 __be32 imm_etype_pkey_eec;
119 __be32 byte_cnt;
120 __be32 wqe;
121 u8 opcode;
122 u8 is_send;
123 u8 reserved;
124 u8 owner;
125 };
126
127 struct mthca_err_cqe {
128 __be32 my_qpn;
129 u32 reserved1[3];
130 u8 syndrome;
131 u8 reserved2;
132 __be16 db_cnt;
133 u32 reserved3;
134 __be32 wqe;
135 u8 opcode;
136 u8 reserved4[2];
137 u8 owner;
138 };
139
140 #define MTHCA_CQ_ENTRY_OWNER_SW (0 << 7)
141 #define MTHCA_CQ_ENTRY_OWNER_HW (1 << 7)
142
143 #define MTHCA_TAVOR_CQ_DB_INC_CI (1 << 24)
144 #define MTHCA_TAVOR_CQ_DB_REQ_NOT (2 << 24)
145 #define MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL (3 << 24)
146 #define MTHCA_TAVOR_CQ_DB_SET_CI (4 << 24)
147 #define MTHCA_TAVOR_CQ_DB_REQ_NOT_MULT (5 << 24)
148
149 #define MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL (1 << 24)
150 #define MTHCA_ARBEL_CQ_DB_REQ_NOT (2 << 24)
151 #define MTHCA_ARBEL_CQ_DB_REQ_NOT_MULT (3 << 24)
152
153 static inline struct mthca_cqe *get_cqe(struct mthca_cq *cq, int entry)
154 {
155 if (cq->is_direct)
156 return cq->queue.direct.buf + (entry * MTHCA_CQ_ENTRY_SIZE);
157 else
158 return cq->queue.page_list[entry * MTHCA_CQ_ENTRY_SIZE / PAGE_SIZE].buf
159 + (entry * MTHCA_CQ_ENTRY_SIZE) % PAGE_SIZE;
160 }
161
162 static inline struct mthca_cqe *cqe_sw(struct mthca_cq *cq, int i)
163 {
164 struct mthca_cqe *cqe = get_cqe(cq, i);
165 return MTHCA_CQ_ENTRY_OWNER_HW & cqe->owner ? NULL : cqe;
166 }
167
168 static inline struct mthca_cqe *next_cqe_sw(struct mthca_cq *cq)
169 {
170 return cqe_sw(cq, cq->cons_index & cq->ibcq.cqe);
171 }
172
173 static inline void set_cqe_hw(struct mthca_cqe *cqe)
174 {
175 cqe->owner = MTHCA_CQ_ENTRY_OWNER_HW;
176 }
177
178 static void dump_cqe(struct mthca_dev *dev, void *cqe_ptr)
179 {
180 __be32 *cqe = cqe_ptr;
181
182 (void) cqe; /* avoid warning if mthca_dbg compiled away... */
183 mthca_dbg(dev, "CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n",
184 be32_to_cpu(cqe[0]), be32_to_cpu(cqe[1]), be32_to_cpu(cqe[2]),
185 be32_to_cpu(cqe[3]), be32_to_cpu(cqe[4]), be32_to_cpu(cqe[5]),
186 be32_to_cpu(cqe[6]), be32_to_cpu(cqe[7]));
187 }
188
189 /*
190 * incr is ignored in native Arbel (mem-free) mode, so cq->cons_index
191 * should be correct before calling update_cons_index().
192 */
193 static inline void update_cons_index(struct mthca_dev *dev, struct mthca_cq *cq,
194 int incr)
195 {
196 __be32 doorbell[2];
197
198 if (mthca_is_memfree(dev)) {
199 *cq->set_ci_db = cpu_to_be32(cq->cons_index);
200 wmb();
201 } else {
202 doorbell[0] = cpu_to_be32(MTHCA_TAVOR_CQ_DB_INC_CI | cq->cqn);
203 doorbell[1] = cpu_to_be32(incr - 1);
204
205 mthca_write64(doorbell,
206 dev->kar + MTHCA_CQ_DOORBELL,
207 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
208 }
209 }
210
211 void mthca_cq_completion(struct mthca_dev *dev, u32 cqn)
212 {
213 struct mthca_cq *cq;
214
215 cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1));
216
217 if (!cq) {
218 mthca_warn(dev, "Completion event for bogus CQ %08x\n", cqn);
219 return;
220 }
221
222 ++cq->arm_sn;
223
224 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
225 }
226
227 void mthca_cq_event(struct mthca_dev *dev, u32 cqn,
228 enum ib_event_type event_type)
229 {
230 struct mthca_cq *cq;
231 struct ib_event event;
232
233 spin_lock(&dev->cq_table.lock);
234
235 cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1));
236
237 if (cq)
238 atomic_inc(&cq->refcount);
239 spin_unlock(&dev->cq_table.lock);
240
241 if (!cq) {
242 mthca_warn(dev, "Async event for bogus CQ %08x\n", cqn);
243 return;
244 }
245
246 event.device = &dev->ib_dev;
247 event.event = event_type;
248 event.element.cq = &cq->ibcq;
249 if (cq->ibcq.event_handler)
250 cq->ibcq.event_handler(&event, cq->ibcq.cq_context);
251
252 if (atomic_dec_and_test(&cq->refcount))
253 wake_up(&cq->wait);
254 }
255
256 static inline int is_recv_cqe(struct mthca_cqe *cqe)
257 {
258 if ((cqe->opcode & MTHCA_ERROR_CQE_OPCODE_MASK) ==
259 MTHCA_ERROR_CQE_OPCODE_MASK)
260 return !(cqe->opcode & 0x01);
261 else
262 return !(cqe->is_send & 0x80);
263 }
264
265 void mthca_cq_clean(struct mthca_dev *dev, u32 cqn, u32 qpn,
266 struct mthca_srq *srq)
267 {
268 struct mthca_cq *cq;
269 struct mthca_cqe *cqe;
270 u32 prod_index;
271 int nfreed = 0;
272
273 spin_lock_irq(&dev->cq_table.lock);
274 cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1));
275 if (cq)
276 atomic_inc(&cq->refcount);
277 spin_unlock_irq(&dev->cq_table.lock);
278
279 if (!cq)
280 return;
281
282 spin_lock_irq(&cq->lock);
283
284 /*
285 * First we need to find the current producer index, so we
286 * know where to start cleaning from. It doesn't matter if HW
287 * adds new entries after this loop -- the QP we're worried
288 * about is already in RESET, so the new entries won't come
289 * from our QP and therefore don't need to be checked.
290 */
291 for (prod_index = cq->cons_index;
292 cqe_sw(cq, prod_index & cq->ibcq.cqe);
293 ++prod_index)
294 if (prod_index == cq->cons_index + cq->ibcq.cqe)
295 break;
296
297 if (0)
298 mthca_dbg(dev, "Cleaning QPN %06x from CQN %06x; ci %d, pi %d\n",
299 qpn, cqn, cq->cons_index, prod_index);
300
301 /*
302 * Now sweep backwards through the CQ, removing CQ entries
303 * that match our QP by copying older entries on top of them.
304 */
305 while ((int) --prod_index - (int) cq->cons_index >= 0) {
306 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
307 if (cqe->my_qpn == cpu_to_be32(qpn)) {
308 if (srq && is_recv_cqe(cqe))
309 mthca_free_srq_wqe(srq, be32_to_cpu(cqe->wqe));
310 ++nfreed;
311 } else if (nfreed)
312 memcpy(get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe),
313 cqe, MTHCA_CQ_ENTRY_SIZE);
314 }
315
316 if (nfreed) {
317 wmb();
318 cq->cons_index += nfreed;
319 update_cons_index(dev, cq, nfreed);
320 }
321
322 spin_unlock_irq(&cq->lock);
323 if (atomic_dec_and_test(&cq->refcount))
324 wake_up(&cq->wait);
325 }
326
327 static int handle_error_cqe(struct mthca_dev *dev, struct mthca_cq *cq,
328 struct mthca_qp *qp, int wqe_index, int is_send,
329 struct mthca_err_cqe *cqe,
330 struct ib_wc *entry, int *free_cqe)
331 {
332 int err;
333 int dbd;
334 __be32 new_wqe;
335
336 if (cqe->syndrome == SYNDROME_LOCAL_QP_OP_ERR) {
337 mthca_dbg(dev, "local QP operation err "
338 "(QPN %06x, WQE @ %08x, CQN %06x, index %d)\n",
339 be32_to_cpu(cqe->my_qpn), be32_to_cpu(cqe->wqe),
340 cq->cqn, cq->cons_index);
341 dump_cqe(dev, cqe);
342 }
343
344 /*
345 * For completions in error, only work request ID, status (and
346 * freed resource count for RD) have to be set.
347 */
348 switch (cqe->syndrome) {
349 case SYNDROME_LOCAL_LENGTH_ERR:
350 entry->status = IB_WC_LOC_LEN_ERR;
351 break;
352 case SYNDROME_LOCAL_QP_OP_ERR:
353 entry->status = IB_WC_LOC_QP_OP_ERR;
354 break;
355 case SYNDROME_LOCAL_EEC_OP_ERR:
356 entry->status = IB_WC_LOC_EEC_OP_ERR;
357 break;
358 case SYNDROME_LOCAL_PROT_ERR:
359 entry->status = IB_WC_LOC_PROT_ERR;
360 break;
361 case SYNDROME_WR_FLUSH_ERR:
362 entry->status = IB_WC_WR_FLUSH_ERR;
363 break;
364 case SYNDROME_MW_BIND_ERR:
365 entry->status = IB_WC_MW_BIND_ERR;
366 break;
367 case SYNDROME_BAD_RESP_ERR:
368 entry->status = IB_WC_BAD_RESP_ERR;
369 break;
370 case SYNDROME_LOCAL_ACCESS_ERR:
371 entry->status = IB_WC_LOC_ACCESS_ERR;
372 break;
373 case SYNDROME_REMOTE_INVAL_REQ_ERR:
374 entry->status = IB_WC_REM_INV_REQ_ERR;
375 break;
376 case SYNDROME_REMOTE_ACCESS_ERR:
377 entry->status = IB_WC_REM_ACCESS_ERR;
378 break;
379 case SYNDROME_REMOTE_OP_ERR:
380 entry->status = IB_WC_REM_OP_ERR;
381 break;
382 case SYNDROME_RETRY_EXC_ERR:
383 entry->status = IB_WC_RETRY_EXC_ERR;
384 break;
385 case SYNDROME_RNR_RETRY_EXC_ERR:
386 entry->status = IB_WC_RNR_RETRY_EXC_ERR;
387 break;
388 case SYNDROME_LOCAL_RDD_VIOL_ERR:
389 entry->status = IB_WC_LOC_RDD_VIOL_ERR;
390 break;
391 case SYNDROME_REMOTE_INVAL_RD_REQ_ERR:
392 entry->status = IB_WC_REM_INV_RD_REQ_ERR;
393 break;
394 case SYNDROME_REMOTE_ABORTED_ERR:
395 entry->status = IB_WC_REM_ABORT_ERR;
396 break;
397 case SYNDROME_INVAL_EECN_ERR:
398 entry->status = IB_WC_INV_EECN_ERR;
399 break;
400 case SYNDROME_INVAL_EEC_STATE_ERR:
401 entry->status = IB_WC_INV_EEC_STATE_ERR;
402 break;
403 default:
404 entry->status = IB_WC_GENERAL_ERR;
405 break;
406 }
407
408 /*
409 * Mem-free HCAs always generate one CQE per WQE, even in the
410 * error case, so we don't have to check the doorbell count, etc.
411 */
412 if (mthca_is_memfree(dev))
413 return 0;
414
415 err = mthca_free_err_wqe(dev, qp, is_send, wqe_index, &dbd, &new_wqe);
416 if (err)
417 return err;
418
419 /*
420 * If we're at the end of the WQE chain, or we've used up our
421 * doorbell count, free the CQE. Otherwise just update it for
422 * the next poll operation.
423 */
424 if (!(new_wqe & cpu_to_be32(0x3f)) || (!cqe->db_cnt && dbd))
425 return 0;
426
427 cqe->db_cnt = cpu_to_be16(be16_to_cpu(cqe->db_cnt) - dbd);
428 cqe->wqe = new_wqe;
429 cqe->syndrome = SYNDROME_WR_FLUSH_ERR;
430
431 *free_cqe = 0;
432
433 return 0;
434 }
435
436 static inline int mthca_poll_one(struct mthca_dev *dev,
437 struct mthca_cq *cq,
438 struct mthca_qp **cur_qp,
439 int *freed,
440 struct ib_wc *entry)
441 {
442 struct mthca_wq *wq;
443 struct mthca_cqe *cqe;
444 int wqe_index;
445 int is_error;
446 int is_send;
447 int free_cqe = 1;
448 int err = 0;
449
450 cqe = next_cqe_sw(cq);
451 if (!cqe)
452 return -EAGAIN;
453
454 /*
455 * Make sure we read CQ entry contents after we've checked the
456 * ownership bit.
457 */
458 rmb();
459
460 if (0) {
461 mthca_dbg(dev, "%x/%d: CQE -> QPN %06x, WQE @ %08x\n",
462 cq->cqn, cq->cons_index, be32_to_cpu(cqe->my_qpn),
463 be32_to_cpu(cqe->wqe));
464 dump_cqe(dev, cqe);
465 }
466
467 is_error = (cqe->opcode & MTHCA_ERROR_CQE_OPCODE_MASK) ==
468 MTHCA_ERROR_CQE_OPCODE_MASK;
469 is_send = is_error ? cqe->opcode & 0x01 : cqe->is_send & 0x80;
470
471 if (!*cur_qp || be32_to_cpu(cqe->my_qpn) != (*cur_qp)->qpn) {
472 /*
473 * We do not have to take the QP table lock here,
474 * because CQs will be locked while QPs are removed
475 * from the table.
476 */
477 *cur_qp = mthca_array_get(&dev->qp_table.qp,
478 be32_to_cpu(cqe->my_qpn) &
479 (dev->limits.num_qps - 1));
480 if (!*cur_qp) {
481 mthca_warn(dev, "CQ entry for unknown QP %06x\n",
482 be32_to_cpu(cqe->my_qpn) & 0xffffff);
483 err = -EINVAL;
484 goto out;
485 }
486 }
487
488 entry->qp_num = (*cur_qp)->qpn;
489
490 if (is_send) {
491 wq = &(*cur_qp)->sq;
492 wqe_index = ((be32_to_cpu(cqe->wqe) - (*cur_qp)->send_wqe_offset)
493 >> wq->wqe_shift);
494 entry->wr_id = (*cur_qp)->wrid[wqe_index +
495 (*cur_qp)->rq.max];
496 } else if ((*cur_qp)->ibqp.srq) {
497 struct mthca_srq *srq = to_msrq((*cur_qp)->ibqp.srq);
498 u32 wqe = be32_to_cpu(cqe->wqe);
499 wq = NULL;
500 wqe_index = wqe >> srq->wqe_shift;
501 entry->wr_id = srq->wrid[wqe_index];
502 mthca_free_srq_wqe(srq, wqe);
503 } else {
504 wq = &(*cur_qp)->rq;
505 wqe_index = be32_to_cpu(cqe->wqe) >> wq->wqe_shift;
506 entry->wr_id = (*cur_qp)->wrid[wqe_index];
507 }
508
509 if (wq) {
510 if (wq->last_comp < wqe_index)
511 wq->tail += wqe_index - wq->last_comp;
512 else
513 wq->tail += wqe_index + wq->max - wq->last_comp;
514
515 wq->last_comp = wqe_index;
516 }
517
518 if (is_error) {
519 err = handle_error_cqe(dev, cq, *cur_qp, wqe_index, is_send,
520 (struct mthca_err_cqe *) cqe,
521 entry, &free_cqe);
522 goto out;
523 }
524
525 if (is_send) {
526 entry->wc_flags = 0;
527 switch (cqe->opcode) {
528 case MTHCA_OPCODE_RDMA_WRITE:
529 entry->opcode = IB_WC_RDMA_WRITE;
530 break;
531 case MTHCA_OPCODE_RDMA_WRITE_IMM:
532 entry->opcode = IB_WC_RDMA_WRITE;
533 entry->wc_flags |= IB_WC_WITH_IMM;
534 break;
535 case MTHCA_OPCODE_SEND:
536 entry->opcode = IB_WC_SEND;
537 break;
538 case MTHCA_OPCODE_SEND_IMM:
539 entry->opcode = IB_WC_SEND;
540 entry->wc_flags |= IB_WC_WITH_IMM;
541 break;
542 case MTHCA_OPCODE_RDMA_READ:
543 entry->opcode = IB_WC_RDMA_READ;
544 entry->byte_len = be32_to_cpu(cqe->byte_cnt);
545 break;
546 case MTHCA_OPCODE_ATOMIC_CS:
547 entry->opcode = IB_WC_COMP_SWAP;
548 entry->byte_len = be32_to_cpu(cqe->byte_cnt);
549 break;
550 case MTHCA_OPCODE_ATOMIC_FA:
551 entry->opcode = IB_WC_FETCH_ADD;
552 entry->byte_len = be32_to_cpu(cqe->byte_cnt);
553 break;
554 case MTHCA_OPCODE_BIND_MW:
555 entry->opcode = IB_WC_BIND_MW;
556 break;
557 default:
558 entry->opcode = MTHCA_OPCODE_INVALID;
559 break;
560 }
561 } else {
562 entry->byte_len = be32_to_cpu(cqe->byte_cnt);
563 switch (cqe->opcode & 0x1f) {
564 case IB_OPCODE_SEND_LAST_WITH_IMMEDIATE:
565 case IB_OPCODE_SEND_ONLY_WITH_IMMEDIATE:
566 entry->wc_flags = IB_WC_WITH_IMM;
567 entry->imm_data = cqe->imm_etype_pkey_eec;
568 entry->opcode = IB_WC_RECV;
569 break;
570 case IB_OPCODE_RDMA_WRITE_LAST_WITH_IMMEDIATE:
571 case IB_OPCODE_RDMA_WRITE_ONLY_WITH_IMMEDIATE:
572 entry->wc_flags = IB_WC_WITH_IMM;
573 entry->imm_data = cqe->imm_etype_pkey_eec;
574 entry->opcode = IB_WC_RECV_RDMA_WITH_IMM;
575 break;
576 default:
577 entry->wc_flags = 0;
578 entry->opcode = IB_WC_RECV;
579 break;
580 }
581 entry->slid = be16_to_cpu(cqe->rlid);
582 entry->sl = be16_to_cpu(cqe->sl_g_mlpath) >> 12;
583 entry->src_qp = be32_to_cpu(cqe->rqpn) & 0xffffff;
584 entry->dlid_path_bits = be16_to_cpu(cqe->sl_g_mlpath) & 0x7f;
585 entry->pkey_index = be32_to_cpu(cqe->imm_etype_pkey_eec) >> 16;
586 entry->wc_flags |= be16_to_cpu(cqe->sl_g_mlpath) & 0x80 ?
587 IB_WC_GRH : 0;
588 }
589
590 entry->status = IB_WC_SUCCESS;
591
592 out:
593 if (likely(free_cqe)) {
594 set_cqe_hw(cqe);
595 ++(*freed);
596 ++cq->cons_index;
597 }
598
599 return err;
600 }
601
602 int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,
603 struct ib_wc *entry)
604 {
605 struct mthca_dev *dev = to_mdev(ibcq->device);
606 struct mthca_cq *cq = to_mcq(ibcq);
607 struct mthca_qp *qp = NULL;
608 unsigned long flags;
609 int err = 0;
610 int freed = 0;
611 int npolled;
612
613 spin_lock_irqsave(&cq->lock, flags);
614
615 for (npolled = 0; npolled < num_entries; ++npolled) {
616 err = mthca_poll_one(dev, cq, &qp,
617 &freed, entry + npolled);
618 if (err)
619 break;
620 }
621
622 if (freed) {
623 wmb();
624 update_cons_index(dev, cq, freed);
625 }
626
627 spin_unlock_irqrestore(&cq->lock, flags);
628
629 return err == 0 || err == -EAGAIN ? npolled : err;
630 }
631
632 int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify)
633 {
634 __be32 doorbell[2];
635
636 doorbell[0] = cpu_to_be32((notify == IB_CQ_SOLICITED ?
637 MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL :
638 MTHCA_TAVOR_CQ_DB_REQ_NOT) |
639 to_mcq(cq)->cqn);
640 doorbell[1] = (__force __be32) 0xffffffff;
641
642 mthca_write64(doorbell,
643 to_mdev(cq->device)->kar + MTHCA_CQ_DOORBELL,
644 MTHCA_GET_DOORBELL_LOCK(&to_mdev(cq->device)->doorbell_lock));
645
646 return 0;
647 }
648
649 int mthca_arbel_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify notify)
650 {
651 struct mthca_cq *cq = to_mcq(ibcq);
652 __be32 doorbell[2];
653 u32 sn;
654 __be32 ci;
655
656 sn = cq->arm_sn & 3;
657 ci = cpu_to_be32(cq->cons_index);
658
659 doorbell[0] = ci;
660 doorbell[1] = cpu_to_be32((cq->cqn << 8) | (2 << 5) | (sn << 3) |
661 (notify == IB_CQ_SOLICITED ? 1 : 2));
662
663 mthca_write_db_rec(doorbell, cq->arm_db);
664
665 /*
666 * Make sure that the doorbell record in host memory is
667 * written before ringing the doorbell via PCI MMIO.
668 */
669 wmb();
670
671 doorbell[0] = cpu_to_be32((sn << 28) |
672 (notify == IB_CQ_SOLICITED ?
673 MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL :
674 MTHCA_ARBEL_CQ_DB_REQ_NOT) |
675 cq->cqn);
676 doorbell[1] = ci;
677
678 mthca_write64(doorbell,
679 to_mdev(ibcq->device)->kar + MTHCA_CQ_DOORBELL,
680 MTHCA_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->doorbell_lock));
681
682 return 0;
683 }
684
685 static void mthca_free_cq_buf(struct mthca_dev *dev, struct mthca_cq *cq)
686 {
687 mthca_buf_free(dev, (cq->ibcq.cqe + 1) * MTHCA_CQ_ENTRY_SIZE,
688 &cq->queue, cq->is_direct, &cq->mr);
689 }
690
691 int mthca_init_cq(struct mthca_dev *dev, int nent,
692 struct mthca_ucontext *ctx, u32 pdn,
693 struct mthca_cq *cq)
694 {
695 int size = nent * MTHCA_CQ_ENTRY_SIZE;
696 struct mthca_mailbox *mailbox;
697 struct mthca_cq_context *cq_context;
698 int err = -ENOMEM;
699 u8 status;
700 int i;
701
702 might_sleep();
703
704 cq->ibcq.cqe = nent - 1;
705 cq->is_kernel = !ctx;
706
707 cq->cqn = mthca_alloc(&dev->cq_table.alloc);
708 if (cq->cqn == -1)
709 return -ENOMEM;
710
711 if (mthca_is_memfree(dev)) {
712 err = mthca_table_get(dev, dev->cq_table.table, cq->cqn);
713 if (err)
714 goto err_out;
715
716 if (cq->is_kernel) {
717 cq->arm_sn = 1;
718
719 err = -ENOMEM;
720
721 cq->set_ci_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_SET_CI,
722 cq->cqn, &cq->set_ci_db);
723 if (cq->set_ci_db_index < 0)
724 goto err_out_icm;
725
726 cq->arm_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_ARM,
727 cq->cqn, &cq->arm_db);
728 if (cq->arm_db_index < 0)
729 goto err_out_ci;
730 }
731 }
732
733 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
734 if (IS_ERR(mailbox))
735 goto err_out_arm;
736
737 cq_context = mailbox->buf;
738
739 if (cq->is_kernel) {
740 err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_CQ_SIZE,
741 &cq->queue, &cq->is_direct,
742 &dev->driver_pd, 1, &cq->mr);
743 if (err)
744 goto err_out_mailbox;
745
746 for (i = 0; i < nent; ++i)
747 set_cqe_hw(get_cqe(cq, i));
748 }
749
750 spin_lock_init(&cq->lock);
751 atomic_set(&cq->refcount, 1);
752 init_waitqueue_head(&cq->wait);
753
754 memset(cq_context, 0, sizeof *cq_context);
755 cq_context->flags = cpu_to_be32(MTHCA_CQ_STATUS_OK |
756 MTHCA_CQ_STATE_DISARMED |
757 MTHCA_CQ_FLAG_TR);
758 cq_context->logsize_usrpage = cpu_to_be32((ffs(nent) - 1) << 24);
759 if (ctx)
760 cq_context->logsize_usrpage |= cpu_to_be32(ctx->uar.index);
761 else
762 cq_context->logsize_usrpage |= cpu_to_be32(dev->driver_uar.index);
763 cq_context->error_eqn = cpu_to_be32(dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn);
764 cq_context->comp_eqn = cpu_to_be32(dev->eq_table.eq[MTHCA_EQ_COMP].eqn);
765 cq_context->pd = cpu_to_be32(pdn);
766 cq_context->lkey = cpu_to_be32(cq->mr.ibmr.lkey);
767 cq_context->cqn = cpu_to_be32(cq->cqn);
768
769 if (mthca_is_memfree(dev)) {
770 cq_context->ci_db = cpu_to_be32(cq->set_ci_db_index);
771 cq_context->state_db = cpu_to_be32(cq->arm_db_index);
772 }
773
774 err = mthca_SW2HW_CQ(dev, mailbox, cq->cqn, &status);
775 if (err) {
776 mthca_warn(dev, "SW2HW_CQ failed (%d)\n", err);
777 goto err_out_free_mr;
778 }
779
780 if (status) {
781 mthca_warn(dev, "SW2HW_CQ returned status 0x%02x\n",
782 status);
783 err = -EINVAL;
784 goto err_out_free_mr;
785 }
786
787 spin_lock_irq(&dev->cq_table.lock);
788 if (mthca_array_set(&dev->cq_table.cq,
789 cq->cqn & (dev->limits.num_cqs - 1),
790 cq)) {
791 spin_unlock_irq(&dev->cq_table.lock);
792 goto err_out_free_mr;
793 }
794 spin_unlock_irq(&dev->cq_table.lock);
795
796 cq->cons_index = 0;
797
798 mthca_free_mailbox(dev, mailbox);
799
800 return 0;
801
802 err_out_free_mr:
803 if (cq->is_kernel)
804 mthca_free_cq_buf(dev, cq);
805
806 err_out_mailbox:
807 mthca_free_mailbox(dev, mailbox);
808
809 err_out_arm:
810 if (cq->is_kernel && mthca_is_memfree(dev))
811 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM, cq->arm_db_index);
812
813 err_out_ci:
814 if (cq->is_kernel && mthca_is_memfree(dev))
815 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index);
816
817 err_out_icm:
818 mthca_table_put(dev, dev->cq_table.table, cq->cqn);
819
820 err_out:
821 mthca_free(&dev->cq_table.alloc, cq->cqn);
822
823 return err;
824 }
825
826 void mthca_free_cq(struct mthca_dev *dev,
827 struct mthca_cq *cq)
828 {
829 struct mthca_mailbox *mailbox;
830 int err;
831 u8 status;
832
833 might_sleep();
834
835 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
836 if (IS_ERR(mailbox)) {
837 mthca_warn(dev, "No memory for mailbox to free CQ.\n");
838 return;
839 }
840
841 err = mthca_HW2SW_CQ(dev, mailbox, cq->cqn, &status);
842 if (err)
843 mthca_warn(dev, "HW2SW_CQ failed (%d)\n", err);
844 else if (status)
845 mthca_warn(dev, "HW2SW_CQ returned status 0x%02x\n", status);
846
847 if (0) {
848 __be32 *ctx = mailbox->buf;
849 int j;
850
851 printk(KERN_ERR "context for CQN %x (cons index %x, next sw %d)\n",
852 cq->cqn, cq->cons_index,
853 cq->is_kernel ? !!next_cqe_sw(cq) : 0);
854 for (j = 0; j < 16; ++j)
855 printk(KERN_ERR "[%2x] %08x\n", j * 4, be32_to_cpu(ctx[j]));
856 }
857
858 spin_lock_irq(&dev->cq_table.lock);
859 mthca_array_clear(&dev->cq_table.cq,
860 cq->cqn & (dev->limits.num_cqs - 1));
861 spin_unlock_irq(&dev->cq_table.lock);
862
863 if (dev->mthca_flags & MTHCA_FLAG_MSI_X)
864 synchronize_irq(dev->eq_table.eq[MTHCA_EQ_COMP].msi_x_vector);
865 else
866 synchronize_irq(dev->pdev->irq);
867
868 atomic_dec(&cq->refcount);
869 wait_event(cq->wait, !atomic_read(&cq->refcount));
870
871 if (cq->is_kernel) {
872 mthca_free_cq_buf(dev, cq);
873 if (mthca_is_memfree(dev)) {
874 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM, cq->arm_db_index);
875 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index);
876 }
877 }
878
879 mthca_table_put(dev, dev->cq_table.table, cq->cqn);
880 mthca_free(&dev->cq_table.alloc, cq->cqn);
881 mthca_free_mailbox(dev, mailbox);
882 }
883
884 int __devinit mthca_init_cq_table(struct mthca_dev *dev)
885 {
886 int err;
887
888 spin_lock_init(&dev->cq_table.lock);
889
890 err = mthca_alloc_init(&dev->cq_table.alloc,
891 dev->limits.num_cqs,
892 (1 << 24) - 1,
893 dev->limits.reserved_cqs);
894 if (err)
895 return err;
896
897 err = mthca_array_init(&dev->cq_table.cq,
898 dev->limits.num_cqs);
899 if (err)
900 mthca_alloc_cleanup(&dev->cq_table.alloc);
901
902 return err;
903 }
904
905 void __devexit mthca_cleanup_cq_table(struct mthca_dev *dev)
906 {
907 mthca_array_cleanup(&dev->cq_table.cq, dev->limits.num_cqs);
908 mthca_alloc_cleanup(&dev->cq_table.alloc);
909 }
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