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[MMC] PXA and i.MX: don't avoid sending stop command on error
[linux-2.6/verdex.git] / drivers / mmc / pxamci.c
blob15a5caa0bdeb60b75c88bd713814ae3abdcf67e4
1 /*
2 * linux/drivers/mmc/pxa.c - PXA MMCI driver
3 *
4 * Copyright (C) 2003 Russell King, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This hardware is really sick:
11 * - No way to clear interrupts.
12 * - Have to turn off the clock whenever we touch the device.
13 * - Doesn't tell you how many data blocks were transferred.
14 * Yuck!
15 *
16 * 1 and 3 byte data transfers not supported
17 * max block length up to 1023
18 */
19 #include <linux/config.h>
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/ioport.h>
23 #include <linux/platform_device.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/mmc/host.h>
28 #include <linux/mmc/protocol.h>
29
30 #include <asm/dma.h>
31 #include <asm/io.h>
32 #include <asm/scatterlist.h>
33 #include <asm/sizes.h>
34
35 #include <asm/arch/pxa-regs.h>
36 #include <asm/arch/mmc.h>
37
38 #include "pxamci.h"
39
40 #define DRIVER_NAME "pxa2xx-mci"
41
42 #define NR_SG 1
43
44 struct pxamci_host {
45 struct mmc_host *mmc;
46 spinlock_t lock;
47 struct resource *res;
48 void __iomem *base;
49 int irq;
50 int dma;
51 unsigned int clkrt;
52 unsigned int cmdat;
53 unsigned int imask;
54 unsigned int power_mode;
55 struct pxamci_platform_data *pdata;
56
57 struct mmc_request *mrq;
58 struct mmc_command *cmd;
59 struct mmc_data *data;
60
61 dma_addr_t sg_dma;
62 struct pxa_dma_desc *sg_cpu;
63 unsigned int dma_len;
64
65 unsigned int dma_dir;
66 };
67
68 static void pxamci_stop_clock(struct pxamci_host *host)
69 {
70 if (readl(host->base + MMC_STAT) & STAT_CLK_EN) {
71 unsigned long timeout = 10000;
72 unsigned int v;
73
74 writel(STOP_CLOCK, host->base + MMC_STRPCL);
75
76 do {
77 v = readl(host->base + MMC_STAT);
78 if (!(v & STAT_CLK_EN))
79 break;
80 udelay(1);
81 } while (timeout--);
82
83 if (v & STAT_CLK_EN)
84 dev_err(mmc_dev(host->mmc), "unable to stop clock\n");
85 }
86 }
87
88 static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask)
89 {
90 unsigned long flags;
91
92 spin_lock_irqsave(&host->lock, flags);
93 host->imask &= ~mask;
94 writel(host->imask, host->base + MMC_I_MASK);
95 spin_unlock_irqrestore(&host->lock, flags);
96 }
97
98 static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask)
99 {
100 unsigned long flags;
101
102 spin_lock_irqsave(&host->lock, flags);
103 host->imask |= mask;
104 writel(host->imask, host->base + MMC_I_MASK);
105 spin_unlock_irqrestore(&host->lock, flags);
106 }
107
108 static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data)
109 {
110 unsigned int nob = data->blocks;
111 unsigned long long clks;
112 unsigned int timeout;
113 u32 dcmd;
114 int i;
115
116 host->data = data;
117
118 if (data->flags & MMC_DATA_STREAM)
119 nob = 0xffff;
120
121 writel(nob, host->base + MMC_NOB);
122 writel(1 << data->blksz_bits, host->base + MMC_BLKLEN);
123
124 clks = (unsigned long long)data->timeout_ns * CLOCKRATE;
125 do_div(clks, 1000000000UL);
126 timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt);
127 writel((timeout + 255) / 256, host->base + MMC_RDTO);
128
129 if (data->flags & MMC_DATA_READ) {
130 host->dma_dir = DMA_FROM_DEVICE;
131 dcmd = DCMD_INCTRGADDR | DCMD_FLOWTRG;
132 DRCMRTXMMC = 0;
133 DRCMRRXMMC = host->dma | DRCMR_MAPVLD;
134 } else {
135 host->dma_dir = DMA_TO_DEVICE;
136 dcmd = DCMD_INCSRCADDR | DCMD_FLOWSRC;
137 DRCMRRXMMC = 0;
138 DRCMRTXMMC = host->dma | DRCMR_MAPVLD;
139 }
140
141 dcmd |= DCMD_BURST32 | DCMD_WIDTH1;
142
143 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
144 host->dma_dir);
145
146 for (i = 0; i < host->dma_len; i++) {
147 if (data->flags & MMC_DATA_READ) {
148 host->sg_cpu[i].dsadr = host->res->start + MMC_RXFIFO;
149 host->sg_cpu[i].dtadr = sg_dma_address(&data->sg[i]);
150 } else {
151 host->sg_cpu[i].dsadr = sg_dma_address(&data->sg[i]);
152 host->sg_cpu[i].dtadr = host->res->start + MMC_TXFIFO;
153 }
154 host->sg_cpu[i].dcmd = dcmd | sg_dma_len(&data->sg[i]);
155 host->sg_cpu[i].ddadr = host->sg_dma + (i + 1) *
156 sizeof(struct pxa_dma_desc);
157 }
158 host->sg_cpu[host->dma_len - 1].ddadr = DDADR_STOP;
159 wmb();
160
161 DDADR(host->dma) = host->sg_dma;
162 DCSR(host->dma) = DCSR_RUN;
163 }
164
165 static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat)
166 {
167 WARN_ON(host->cmd != NULL);
168 host->cmd = cmd;
169
170 if (cmd->flags & MMC_RSP_BUSY)
171 cmdat |= CMDAT_BUSY;
172
173 #define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE))
174 switch (RSP_TYPE(mmc_resp_type(cmd))) {
175 case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6 */
176 cmdat |= CMDAT_RESP_SHORT;
177 break;
178 case RSP_TYPE(MMC_RSP_R3):
179 cmdat |= CMDAT_RESP_R3;
180 break;
181 case RSP_TYPE(MMC_RSP_R2):
182 cmdat |= CMDAT_RESP_R2;
183 break;
184 default:
185 break;
186 }
187
188 writel(cmd->opcode, host->base + MMC_CMD);
189 writel(cmd->arg >> 16, host->base + MMC_ARGH);
190 writel(cmd->arg & 0xffff, host->base + MMC_ARGL);
191 writel(cmdat, host->base + MMC_CMDAT);
192 writel(host->clkrt, host->base + MMC_CLKRT);
193
194 writel(START_CLOCK, host->base + MMC_STRPCL);
195
196 pxamci_enable_irq(host, END_CMD_RES);
197 }
198
199 static void pxamci_finish_request(struct pxamci_host *host, struct mmc_request *mrq)
200 {
201 pr_debug("PXAMCI: request done\n");
202 host->mrq = NULL;
203 host->cmd = NULL;
204 host->data = NULL;
205 mmc_request_done(host->mmc, mrq);
206 }
207
208 static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat)
209 {
210 struct mmc_command *cmd = host->cmd;
211 int i;
212 u32 v;
213
214 if (!cmd)
215 return 0;
216
217 host->cmd = NULL;
218
219 /*
220 * Did I mention this is Sick. We always need to
221 * discard the upper 8 bits of the first 16-bit word.
222 */
223 v = readl(host->base + MMC_RES) & 0xffff;
224 for (i = 0; i < 4; i++) {
225 u32 w1 = readl(host->base + MMC_RES) & 0xffff;
226 u32 w2 = readl(host->base + MMC_RES) & 0xffff;
227 cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8;
228 v = w2;
229 }
230
231 if (stat & STAT_TIME_OUT_RESPONSE) {
232 cmd->error = MMC_ERR_TIMEOUT;
233 } else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
234 #ifdef CONFIG_PXA27x
235 /*
236 * workaround for erratum #42:
237 * Intel PXA27x Family Processor Specification Update Rev 001
238 */
239 if (cmd->opcode == MMC_ALL_SEND_CID ||
240 cmd->opcode == MMC_SEND_CSD ||
241 cmd->opcode == MMC_SEND_CID) {
242 /* a bogus CRC error can appear if the msb of
243 the 15 byte response is a one */
244 if ((cmd->resp[0] & 0x80000000) == 0)
245 cmd->error = MMC_ERR_BADCRC;
246 } else {
247 pr_debug("ignoring CRC from command %d - *risky*\n",cmd->opcode);
248 }
249 #else
250 cmd->error = MMC_ERR_BADCRC;
251 #endif
252 }
253
254 pxamci_disable_irq(host, END_CMD_RES);
255 if (host->data && cmd->error == MMC_ERR_NONE) {
256 pxamci_enable_irq(host, DATA_TRAN_DONE);
257 } else {
258 pxamci_finish_request(host, host->mrq);
259 }
260
261 return 1;
262 }
263
264 static int pxamci_data_done(struct pxamci_host *host, unsigned int stat)
265 {
266 struct mmc_data *data = host->data;
267
268 if (!data)
269 return 0;
270
271 DCSR(host->dma) = 0;
272 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
273 host->dma_dir);
274
275 if (stat & STAT_READ_TIME_OUT)
276 data->error = MMC_ERR_TIMEOUT;
277 else if (stat & (STAT_CRC_READ_ERROR|STAT_CRC_WRITE_ERROR))
278 data->error = MMC_ERR_BADCRC;
279
280 /*
281 * There appears to be a hardware design bug here. There seems to
282 * be no way to find out how much data was transferred to the card.
283 * This means that if there was an error on any block, we mark all
284 * data blocks as being in error.
285 */
286 if (data->error == MMC_ERR_NONE)
287 data->bytes_xfered = data->blocks << data->blksz_bits;
288 else
289 data->bytes_xfered = 0;
290
291 pxamci_disable_irq(host, DATA_TRAN_DONE);
292
293 host->data = NULL;
294 if (host->mrq->stop) {
295 pxamci_stop_clock(host);
296 pxamci_start_cmd(host, host->mrq->stop, 0);
297 } else {
298 pxamci_finish_request(host, host->mrq);
299 }
300
301 return 1;
302 }
303
304 static irqreturn_t pxamci_irq(int irq, void *devid, struct pt_regs *regs)
305 {
306 struct pxamci_host *host = devid;
307 unsigned int ireg;
308 int handled = 0;
309
310 ireg = readl(host->base + MMC_I_REG);
311
312 pr_debug("PXAMCI: irq %08x\n", ireg);
313
314 if (ireg) {
315 unsigned stat = readl(host->base + MMC_STAT);
316
317 pr_debug("PXAMCI: stat %08x\n", stat);
318
319 if (ireg & END_CMD_RES)
320 handled |= pxamci_cmd_done(host, stat);
321 if (ireg & DATA_TRAN_DONE)
322 handled |= pxamci_data_done(host, stat);
323 }
324
325 return IRQ_RETVAL(handled);
326 }
327
328 static void pxamci_request(struct mmc_host *mmc, struct mmc_request *mrq)
329 {
330 struct pxamci_host *host = mmc_priv(mmc);
331 unsigned int cmdat;
332
333 WARN_ON(host->mrq != NULL);
334
335 host->mrq = mrq;
336
337 pxamci_stop_clock(host);
338
339 cmdat = host->cmdat;
340 host->cmdat &= ~CMDAT_INIT;
341
342 if (mrq->data) {
343 pxamci_setup_data(host, mrq->data);
344
345 cmdat &= ~CMDAT_BUSY;
346 cmdat |= CMDAT_DATAEN | CMDAT_DMAEN;
347 if (mrq->data->flags & MMC_DATA_WRITE)
348 cmdat |= CMDAT_WRITE;
349
350 if (mrq->data->flags & MMC_DATA_STREAM)
351 cmdat |= CMDAT_STREAM;
352 }
353
354 pxamci_start_cmd(host, mrq->cmd, cmdat);
355 }
356
357 static int pxamci_get_ro(struct mmc_host *mmc)
358 {
359 struct pxamci_host *host = mmc_priv(mmc);
360
361 if (host->pdata && host->pdata->get_ro)
362 return host->pdata->get_ro(mmc->dev);
363 /* Host doesn't support read only detection so assume writeable */
364 return 0;
365 }
366
367 static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
368 {
369 struct pxamci_host *host = mmc_priv(mmc);
370
371 pr_debug("pxamci_set_ios: clock %u power %u vdd %u.%02u\n",
372 ios->clock, ios->power_mode, ios->vdd / 100,
373 ios->vdd % 100);
374
375 if (ios->clock) {
376 unsigned int clk = CLOCKRATE / ios->clock;
377 if (CLOCKRATE / clk > ios->clock)
378 clk <<= 1;
379 host->clkrt = fls(clk) - 1;
380 pxa_set_cken(CKEN12_MMC, 1);
381
382 /*
383 * we write clkrt on the next command
384 */
385 } else {
386 pxamci_stop_clock(host);
387 pxa_set_cken(CKEN12_MMC, 0);
388 }
389
390 if (host->power_mode != ios->power_mode) {
391 host->power_mode = ios->power_mode;
392
393 if (host->pdata && host->pdata->setpower)
394 host->pdata->setpower(mmc->dev, ios->vdd);
395
396 if (ios->power_mode == MMC_POWER_ON)
397 host->cmdat |= CMDAT_INIT;
398 }
399
400 pr_debug("pxamci_set_ios: clkrt = %x cmdat = %x\n",
401 host->clkrt, host->cmdat);
402 }
403
404 static struct mmc_host_ops pxamci_ops = {
405 .request = pxamci_request,
406 .get_ro = pxamci_get_ro,
407 .set_ios = pxamci_set_ios,
408 };
409
410 static void pxamci_dma_irq(int dma, void *devid, struct pt_regs *regs)
411 {
412 printk(KERN_ERR "DMA%d: IRQ???\n", dma);
413 DCSR(dma) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;
414 }
415
416 static irqreturn_t pxamci_detect_irq(int irq, void *devid, struct pt_regs *regs)
417 {
418 struct pxamci_host *host = mmc_priv(devid);
419
420 mmc_detect_change(devid, host->pdata->detect_delay);
421 return IRQ_HANDLED;
422 }
423
424 static int pxamci_probe(struct platform_device *pdev)
425 {
426 struct mmc_host *mmc;
427 struct pxamci_host *host = NULL;
428 struct resource *r;
429 int ret, irq;
430
431 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
432 irq = platform_get_irq(pdev, 0);
433 if (!r || irq < 0)
434 return -ENXIO;
435
436 r = request_mem_region(r->start, SZ_4K, DRIVER_NAME);
437 if (!r)
438 return -EBUSY;
439
440 mmc = mmc_alloc_host(sizeof(struct pxamci_host), &pdev->dev);
441 if (!mmc) {
442 ret = -ENOMEM;
443 goto out;
444 }
445
446 mmc->ops = &pxamci_ops;
447 mmc->f_min = CLOCKRATE_MIN;
448 mmc->f_max = CLOCKRATE_MAX;
449
450 /*
451 * We can do SG-DMA, but we don't because we never know how much
452 * data we successfully wrote to the card.
453 */
454 mmc->max_phys_segs = NR_SG;
455
456 /*
457 * Our hardware DMA can handle a maximum of one page per SG entry.
458 */
459 mmc->max_seg_size = PAGE_SIZE;
460
461 host = mmc_priv(mmc);
462 host->mmc = mmc;
463 host->dma = -1;
464 host->pdata = pdev->dev.platform_data;
465 mmc->ocr_avail = host->pdata ?
466 host->pdata->ocr_mask :
467 MMC_VDD_32_33|MMC_VDD_33_34;
468
469 host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL);
470 if (!host->sg_cpu) {
471 ret = -ENOMEM;
472 goto out;
473 }
474
475 spin_lock_init(&host->lock);
476 host->res = r;
477 host->irq = irq;
478 host->imask = MMC_I_MASK_ALL;
479
480 host->base = ioremap(r->start, SZ_4K);
481 if (!host->base) {
482 ret = -ENOMEM;
483 goto out;
484 }
485
486 /*
487 * Ensure that the host controller is shut down, and setup
488 * with our defaults.
489 */
490 pxamci_stop_clock(host);
491 writel(0, host->base + MMC_SPI);
492 writel(64, host->base + MMC_RESTO);
493 writel(host->imask, host->base + MMC_I_MASK);
494
495 host->dma = pxa_request_dma(DRIVER_NAME, DMA_PRIO_LOW,
496 pxamci_dma_irq, host);
497 if (host->dma < 0) {
498 ret = -EBUSY;
499 goto out;
500 }
501
502 ret = request_irq(host->irq, pxamci_irq, 0, DRIVER_NAME, host);
503 if (ret)
504 goto out;
505
506 platform_set_drvdata(pdev, mmc);
507
508 if (host->pdata && host->pdata->init)
509 host->pdata->init(&pdev->dev, pxamci_detect_irq, mmc);
510
511 mmc_add_host(mmc);
512
513 return 0;
514
515 out:
516 if (host) {
517 if (host->dma >= 0)
518 pxa_free_dma(host->dma);
519 if (host->base)
520 iounmap(host->base);
521 if (host->sg_cpu)
522 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
523 }
524 if (mmc)
525 mmc_free_host(mmc);
526 release_resource(r);
527 return ret;
528 }
529
530 static int pxamci_remove(struct platform_device *pdev)
531 {
532 struct mmc_host *mmc = platform_get_drvdata(pdev);
533
534 platform_set_drvdata(pdev, NULL);
535
536 if (mmc) {
537 struct pxamci_host *host = mmc_priv(mmc);
538
539 if (host->pdata && host->pdata->exit)
540 host->pdata->exit(&pdev->dev, mmc);
541
542 mmc_remove_host(mmc);
543
544 pxamci_stop_clock(host);
545 writel(TXFIFO_WR_REQ|RXFIFO_RD_REQ|CLK_IS_OFF|STOP_CMD|
546 END_CMD_RES|PRG_DONE|DATA_TRAN_DONE,
547 host->base + MMC_I_MASK);
548
549 DRCMRRXMMC = 0;
550 DRCMRTXMMC = 0;
551
552 free_irq(host->irq, host);
553 pxa_free_dma(host->dma);
554 iounmap(host->base);
555 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
556
557 release_resource(host->res);
558
559 mmc_free_host(mmc);
560 }
561 return 0;
562 }
563
564 #ifdef CONFIG_PM
565 static int pxamci_suspend(struct platform_device *dev, pm_message_t state)
566 {
567 struct mmc_host *mmc = platform_get_drvdata(dev);
568 int ret = 0;
569
570 if (mmc)
571 ret = mmc_suspend_host(mmc, state);
572
573 return ret;
574 }
575
576 static int pxamci_resume(struct platform_device *dev)
577 {
578 struct mmc_host *mmc = platform_get_drvdata(dev);
579 int ret = 0;
580
581 if (mmc)
582 ret = mmc_resume_host(mmc);
583
584 return ret;
585 }
586 #else
587 #define pxamci_suspend NULL
588 #define pxamci_resume NULL
589 #endif
590
591 static struct platform_driver pxamci_driver = {
592 .probe = pxamci_probe,
593 .remove = pxamci_remove,
594 .suspend = pxamci_suspend,
595 .resume = pxamci_resume,
596 .driver = {
597 .name = DRIVER_NAME,
598 },
599 };
600
601 static int __init pxamci_init(void)
602 {
603 return platform_driver_register(&pxamci_driver);
604 }
605
606 static void __exit pxamci_exit(void)
607 {
608 platform_driver_unregister(&pxamci_driver);
609 }
610
611 module_init(pxamci_init);
612 module_exit(pxamci_exit);
613
614 MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver");
615 MODULE_LICENSE("GPL");
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