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[PATCH] ia64: desc_empty thinko/typo fix
[linux-2.6/verdex.git] / drivers / media / dvb / frontends / tda1004x.c
blobf4a9cf9d26d07d11d44ceee4cdb378ebfe909a21
1 /*
2 Driver for Philips tda1004xh OFDM Demodulator
3
4 (c) 2003, 2004 Andrew de Quincey & Robert Schlabbach
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20
21 */
22 /*
23 * This driver needs external firmware. Please use the commands
24 * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10045",
25 * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10046" to
26 * download/extract them, and then copy them to /usr/lib/hotplug/firmware
27 * or /lib/firmware (depending on configuration of firmware hotplug).
28 */
29 #define TDA10045_DEFAULT_FIRMWARE "dvb-fe-tda10045.fw"
30 #define TDA10046_DEFAULT_FIRMWARE "dvb-fe-tda10046.fw"
31
32 #include <linux/init.h>
33 #include <linux/module.h>
34 #include <linux/moduleparam.h>
35 #include <linux/device.h>
36 #include <linux/jiffies.h>
37 #include <linux/string.h>
38 #include <linux/slab.h>
39
40 #include "dvb_frontend.h"
41 #include "tda1004x.h"
42
43 enum tda1004x_demod {
44 TDA1004X_DEMOD_TDA10045,
45 TDA1004X_DEMOD_TDA10046,
46 };
47
48 struct tda1004x_state {
49 struct i2c_adapter* i2c;
50 const struct tda1004x_config* config;
51 struct dvb_frontend frontend;
52
53 /* private demod data */
54 enum tda1004x_demod demod_type;
55 };
56
57 static int debug;
58 #define dprintk(args...) \
59 do { \
60 if (debug) printk(KERN_DEBUG "tda1004x: " args); \
61 } while (0)
62
63 #define TDA1004X_CHIPID 0x00
64 #define TDA1004X_AUTO 0x01
65 #define TDA1004X_IN_CONF1 0x02
66 #define TDA1004X_IN_CONF2 0x03
67 #define TDA1004X_OUT_CONF1 0x04
68 #define TDA1004X_OUT_CONF2 0x05
69 #define TDA1004X_STATUS_CD 0x06
70 #define TDA1004X_CONFC4 0x07
71 #define TDA1004X_DSSPARE2 0x0C
72 #define TDA10045H_CODE_IN 0x0D
73 #define TDA10045H_FWPAGE 0x0E
74 #define TDA1004X_SCAN_CPT 0x10
75 #define TDA1004X_DSP_CMD 0x11
76 #define TDA1004X_DSP_ARG 0x12
77 #define TDA1004X_DSP_DATA1 0x13
78 #define TDA1004X_DSP_DATA2 0x14
79 #define TDA1004X_CONFADC1 0x15
80 #define TDA1004X_CONFC1 0x16
81 #define TDA10045H_S_AGC 0x1a
82 #define TDA10046H_AGC_TUN_LEVEL 0x1a
83 #define TDA1004X_SNR 0x1c
84 #define TDA1004X_CONF_TS1 0x1e
85 #define TDA1004X_CONF_TS2 0x1f
86 #define TDA1004X_CBER_RESET 0x20
87 #define TDA1004X_CBER_MSB 0x21
88 #define TDA1004X_CBER_LSB 0x22
89 #define TDA1004X_CVBER_LUT 0x23
90 #define TDA1004X_VBER_MSB 0x24
91 #define TDA1004X_VBER_MID 0x25
92 #define TDA1004X_VBER_LSB 0x26
93 #define TDA1004X_UNCOR 0x27
94
95 #define TDA10045H_CONFPLL_P 0x2D
96 #define TDA10045H_CONFPLL_M_MSB 0x2E
97 #define TDA10045H_CONFPLL_M_LSB 0x2F
98 #define TDA10045H_CONFPLL_N 0x30
99
100 #define TDA10046H_CONFPLL1 0x2D
101 #define TDA10046H_CONFPLL2 0x2F
102 #define TDA10046H_CONFPLL3 0x30
103 #define TDA10046H_TIME_WREF1 0x31
104 #define TDA10046H_TIME_WREF2 0x32
105 #define TDA10046H_TIME_WREF3 0x33
106 #define TDA10046H_TIME_WREF4 0x34
107 #define TDA10046H_TIME_WREF5 0x35
108
109 #define TDA10045H_UNSURW_MSB 0x31
110 #define TDA10045H_UNSURW_LSB 0x32
111 #define TDA10045H_WREF_MSB 0x33
112 #define TDA10045H_WREF_MID 0x34
113 #define TDA10045H_WREF_LSB 0x35
114 #define TDA10045H_MUXOUT 0x36
115 #define TDA1004X_CONFADC2 0x37
116
117 #define TDA10045H_IOFFSET 0x38
118
119 #define TDA10046H_CONF_TRISTATE1 0x3B
120 #define TDA10046H_CONF_TRISTATE2 0x3C
121 #define TDA10046H_CONF_POLARITY 0x3D
122 #define TDA10046H_FREQ_OFFSET 0x3E
123 #define TDA10046H_GPIO_OUT_SEL 0x41
124 #define TDA10046H_GPIO_SELECT 0x42
125 #define TDA10046H_AGC_CONF 0x43
126 #define TDA10046H_AGC_THR 0x44
127 #define TDA10046H_AGC_RENORM 0x45
128 #define TDA10046H_AGC_GAINS 0x46
129 #define TDA10046H_AGC_TUN_MIN 0x47
130 #define TDA10046H_AGC_TUN_MAX 0x48
131 #define TDA10046H_AGC_IF_MIN 0x49
132 #define TDA10046H_AGC_IF_MAX 0x4A
133
134 #define TDA10046H_FREQ_PHY2_MSB 0x4D
135 #define TDA10046H_FREQ_PHY2_LSB 0x4E
136
137 #define TDA10046H_CVBER_CTRL 0x4F
138 #define TDA10046H_AGC_IF_LEVEL 0x52
139 #define TDA10046H_CODE_CPT 0x57
140 #define TDA10046H_CODE_IN 0x58
141
142
143 static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data)
144 {
145 int ret;
146 u8 buf[] = { reg, data };
147 struct i2c_msg msg = { .flags = 0, .buf = buf, .len = 2 };
148
149 dprintk("%s: reg=0x%x, data=0x%x\n", __FUNCTION__, reg, data);
150
151 msg.addr = state->config->demod_address;
152 ret = i2c_transfer(state->i2c, &msg, 1);
153
154 if (ret != 1)
155 dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
156 __FUNCTION__, reg, data, ret);
157
158 dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
159 reg, data, ret);
160 return (ret != 1) ? -1 : 0;
161 }
162
163 static int tda1004x_read_byte(struct tda1004x_state *state, int reg)
164 {
165 int ret;
166 u8 b0[] = { reg };
167 u8 b1[] = { 0 };
168 struct i2c_msg msg[] = {{ .flags = 0, .buf = b0, .len = 1 },
169 { .flags = I2C_M_RD, .buf = b1, .len = 1 }};
170
171 dprintk("%s: reg=0x%x\n", __FUNCTION__, reg);
172
173 msg[0].addr = state->config->demod_address;
174 msg[1].addr = state->config->demod_address;
175 ret = i2c_transfer(state->i2c, msg, 2);
176
177 if (ret != 2) {
178 dprintk("%s: error reg=0x%x, ret=%i\n", __FUNCTION__, reg,
179 ret);
180 return -1;
181 }
182
183 dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
184 reg, b1[0], ret);
185 return b1[0];
186 }
187
188 static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data)
189 {
190 int val;
191 dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __FUNCTION__, reg,
192 mask, data);
193
194 // read a byte and check
195 val = tda1004x_read_byte(state, reg);
196 if (val < 0)
197 return val;
198
199 // mask if off
200 val = val & ~mask;
201 val |= data & 0xff;
202
203 // write it out again
204 return tda1004x_write_byteI(state, reg, val);
205 }
206
207 static int tda1004x_write_buf(struct tda1004x_state *state, int reg, unsigned char *buf, int len)
208 {
209 int i;
210 int result;
211
212 dprintk("%s: reg=0x%x, len=0x%x\n", __FUNCTION__, reg, len);
213
214 result = 0;
215 for (i = 0; i < len; i++) {
216 result = tda1004x_write_byteI(state, reg + i, buf[i]);
217 if (result != 0)
218 break;
219 }
220
221 return result;
222 }
223
224 static int tda1004x_enable_tuner_i2c(struct tda1004x_state *state)
225 {
226 int result;
227 dprintk("%s\n", __FUNCTION__);
228
229 result = tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 2);
230 msleep(20);
231 return result;
232 }
233
234 static int tda1004x_disable_tuner_i2c(struct tda1004x_state *state)
235 {
236 dprintk("%s\n", __FUNCTION__);
237
238 return tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 0);
239 }
240
241 static int tda10045h_set_bandwidth(struct tda1004x_state *state,
242 fe_bandwidth_t bandwidth)
243 {
244 static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f };
245 static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb };
246 static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 };
247
248 switch (bandwidth) {
249 case BANDWIDTH_6_MHZ:
250 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz));
251 break;
252
253 case BANDWIDTH_7_MHZ:
254 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz));
255 break;
256
257 case BANDWIDTH_8_MHZ:
258 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz));
259 break;
260
261 default:
262 return -EINVAL;
263 }
264
265 tda1004x_write_byteI(state, TDA10045H_IOFFSET, 0);
266
267 return 0;
268 }
269
270 static int tda10046h_set_bandwidth(struct tda1004x_state *state,
271 fe_bandwidth_t bandwidth)
272 {
273 static u8 bandwidth_6mhz_53M[] = { 0x7b, 0x2e, 0x11, 0xf0, 0xd2 };
274 static u8 bandwidth_7mhz_53M[] = { 0x6a, 0x02, 0x6a, 0x43, 0x9f };
275 static u8 bandwidth_8mhz_53M[] = { 0x5c, 0x32, 0xc2, 0x96, 0x6d };
276
277 static u8 bandwidth_6mhz_48M[] = { 0x70, 0x02, 0x49, 0x24, 0x92 };
278 static u8 bandwidth_7mhz_48M[] = { 0x60, 0x02, 0xaa, 0xaa, 0xab };
279 static u8 bandwidth_8mhz_48M[] = { 0x54, 0x03, 0x0c, 0x30, 0xc3 };
280 int tda10046_clk53m;
281
282 if ((state->config->if_freq == TDA10046_FREQ_045) ||
283 (state->config->if_freq == TDA10046_FREQ_052))
284 tda10046_clk53m = 0;
285 else
286 tda10046_clk53m = 1;
287 switch (bandwidth) {
288 case BANDWIDTH_6_MHZ:
289 if (tda10046_clk53m)
290 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_53M,
291 sizeof(bandwidth_6mhz_53M));
292 else
293 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_48M,
294 sizeof(bandwidth_6mhz_48M));
295 if (state->config->if_freq == TDA10046_FREQ_045) {
296 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0a);
297 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xab);
298 }
299 break;
300
301 case BANDWIDTH_7_MHZ:
302 if (tda10046_clk53m)
303 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_53M,
304 sizeof(bandwidth_7mhz_53M));
305 else
306 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_48M,
307 sizeof(bandwidth_7mhz_48M));
308 if (state->config->if_freq == TDA10046_FREQ_045) {
309 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
310 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
311 }
312 break;
313
314 case BANDWIDTH_8_MHZ:
315 if (tda10046_clk53m)
316 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_53M,
317 sizeof(bandwidth_8mhz_53M));
318 else
319 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_48M,
320 sizeof(bandwidth_8mhz_48M));
321 if (state->config->if_freq == TDA10046_FREQ_045) {
322 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
323 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x55);
324 }
325 break;
326
327 default:
328 return -EINVAL;
329 }
330
331 return 0;
332 }
333
334 static int tda1004x_do_upload(struct tda1004x_state *state,
335 unsigned char *mem, unsigned int len,
336 u8 dspCodeCounterReg, u8 dspCodeInReg)
337 {
338 u8 buf[65];
339 struct i2c_msg fw_msg = { .flags = 0, .buf = buf, .len = 0 };
340 int tx_size;
341 int pos = 0;
342
343 /* clear code counter */
344 tda1004x_write_byteI(state, dspCodeCounterReg, 0);
345 fw_msg.addr = state->config->demod_address;
346
347 buf[0] = dspCodeInReg;
348 while (pos != len) {
349 // work out how much to send this time
350 tx_size = len - pos;
351 if (tx_size > 0x10)
352 tx_size = 0x10;
353
354 // send the chunk
355 memcpy(buf + 1, mem + pos, tx_size);
356 fw_msg.len = tx_size + 1;
357 if (i2c_transfer(state->i2c, &fw_msg, 1) != 1) {
358 printk(KERN_ERR "tda1004x: Error during firmware upload\n");
359 return -EIO;
360 }
361 pos += tx_size;
362
363 dprintk("%s: fw_pos=0x%x\n", __FUNCTION__, pos);
364 }
365 // give the DSP a chance to settle 03/10/05 Hac
366 msleep(100);
367
368 return 0;
369 }
370
371 static int tda1004x_check_upload_ok(struct tda1004x_state *state)
372 {
373 u8 data1, data2;
374 unsigned long timeout;
375
376 if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
377 timeout = jiffies + 2 * HZ;
378 while(!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) {
379 if (time_after(jiffies, timeout)) {
380 printk(KERN_ERR "tda1004x: timeout waiting for DSP ready\n");
381 break;
382 }
383 msleep(1);
384 }
385 } else
386 msleep(100);
387
388 // check upload was OK
389 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP
390 tda1004x_write_byteI(state, TDA1004X_DSP_CMD, 0x67);
391
392 data1 = tda1004x_read_byte(state, TDA1004X_DSP_DATA1);
393 data2 = tda1004x_read_byte(state, TDA1004X_DSP_DATA2);
394 if (data1 != 0x67 || data2 < 0x20 || data2 > 0x2e) {
395 printk(KERN_INFO "tda1004x: found firmware revision %x -- invalid\n", data2);
396 return -EIO;
397 }
398 printk(KERN_INFO "tda1004x: found firmware revision %x -- ok\n", data2);
399 return 0;
400 }
401
402 static int tda10045_fwupload(struct dvb_frontend* fe)
403 {
404 struct tda1004x_state* state = fe->demodulator_priv;
405 int ret;
406 const struct firmware *fw;
407
408 /* don't re-upload unless necessary */
409 if (tda1004x_check_upload_ok(state) == 0)
410 return 0;
411
412 /* request the firmware, this will block until someone uploads it */
413 printk(KERN_INFO "tda1004x: waiting for firmware upload (%s)...\n", TDA10045_DEFAULT_FIRMWARE);
414 ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE);
415 if (ret) {
416 printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
417 return ret;
418 }
419
420 /* reset chip */
421 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0);
422 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
423 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
424 msleep(10);
425
426 /* set parameters */
427 tda10045h_set_bandwidth(state, BANDWIDTH_8_MHZ);
428
429 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN);
430 release_firmware(fw);
431 if (ret)
432 return ret;
433 printk(KERN_INFO "tda1004x: firmware upload complete\n");
434
435 /* wait for DSP to initialise */
436 /* DSPREADY doesn't seem to work on the TDA10045H */
437 msleep(100);
438
439 return tda1004x_check_upload_ok(state);
440 }
441
442 static void tda10046_init_plls(struct dvb_frontend* fe)
443 {
444 struct tda1004x_state* state = fe->demodulator_priv;
445 int tda10046_clk53m;
446
447 if ((state->config->if_freq == TDA10046_FREQ_045) ||
448 (state->config->if_freq == TDA10046_FREQ_052))
449 tda10046_clk53m = 0;
450 else
451 tda10046_clk53m = 1;
452
453 tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0);
454 if(tda10046_clk53m) {
455 printk(KERN_INFO "tda1004x: setting up plls for 53MHz sampling clock\n");
456 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x08); // PLL M = 8
457 } else {
458 printk(KERN_INFO "tda1004x: setting up plls for 48MHz sampling clock\n");
459 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x03); // PLL M = 3
460 }
461 if (state->config->xtal_freq == TDA10046_XTAL_4M ) {
462 dprintk("%s: setting up PLLs for a 4 MHz Xtal\n", __FUNCTION__);
463 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0
464 } else {
465 dprintk("%s: setting up PLLs for a 16 MHz Xtal\n", __FUNCTION__);
466 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3
467 }
468 if(tda10046_clk53m)
469 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x67);
470 else
471 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x72);
472 /* Note clock frequency is handled implicitly */
473 switch (state->config->if_freq) {
474 case TDA10046_FREQ_045:
475 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
476 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
477 break;
478 case TDA10046_FREQ_052:
479 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
480 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xc7);
481 break;
482 case TDA10046_FREQ_3617:
483 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
484 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x59);
485 break;
486 case TDA10046_FREQ_3613:
487 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
488 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x3f);
489 break;
490 }
491 tda10046h_set_bandwidth(state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz
492 /* let the PLLs settle */
493 msleep(120);
494 }
495
496 static int tda10046_fwupload(struct dvb_frontend* fe)
497 {
498 struct tda1004x_state* state = fe->demodulator_priv;
499 int ret;
500 const struct firmware *fw;
501
502 /* reset + wake up chip */
503 if (state->config->xtal_freq == TDA10046_XTAL_4M) {
504 tda1004x_write_byteI(state, TDA1004X_CONFC4, 0);
505 } else {
506 dprintk("%s: 16MHz Xtal, reducing I2C speed\n", __FUNCTION__);
507 tda1004x_write_byteI(state, TDA1004X_CONFC4, 0x80);
508 }
509 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0);
510 /* let the clocks recover from sleep */
511 msleep(5);
512
513 /* The PLLs need to be reprogrammed after sleep */
514 tda10046_init_plls(fe);
515
516 /* don't re-upload unless necessary */
517 if (tda1004x_check_upload_ok(state) == 0)
518 return 0;
519
520 if (state->config->request_firmware != NULL) {
521 /* request the firmware, this will block until someone uploads it */
522 printk(KERN_INFO "tda1004x: waiting for firmware upload...\n");
523 ret = state->config->request_firmware(fe, &fw, TDA10046_DEFAULT_FIRMWARE);
524 if (ret) {
525 printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
526 return ret;
527 }
528 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST
529 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN);
530 release_firmware(fw);
531 if (ret)
532 return ret;
533 } else {
534 /* boot from firmware eeprom */
535 printk(KERN_INFO "tda1004x: booting from eeprom\n");
536 tda1004x_write_mask(state, TDA1004X_CONFC4, 4, 4);
537 msleep(300);
538 }
539 return tda1004x_check_upload_ok(state);
540 }
541
542 static int tda1004x_encode_fec(int fec)
543 {
544 // convert known FEC values
545 switch (fec) {
546 case FEC_1_2:
547 return 0;
548 case FEC_2_3:
549 return 1;
550 case FEC_3_4:
551 return 2;
552 case FEC_5_6:
553 return 3;
554 case FEC_7_8:
555 return 4;
556 }
557
558 // unsupported
559 return -EINVAL;
560 }
561
562 static int tda1004x_decode_fec(int tdafec)
563 {
564 // convert known FEC values
565 switch (tdafec) {
566 case 0:
567 return FEC_1_2;
568 case 1:
569 return FEC_2_3;
570 case 2:
571 return FEC_3_4;
572 case 3:
573 return FEC_5_6;
574 case 4:
575 return FEC_7_8;
576 }
577
578 // unsupported
579 return -1;
580 }
581
582 static int tda1004x_write(struct dvb_frontend* fe, u8 *buf, int len)
583 {
584 struct tda1004x_state* state = fe->demodulator_priv;
585
586 if (len != 2)
587 return -EINVAL;
588
589 return tda1004x_write_byteI(state, buf[0], buf[1]);
590 }
591
592 static int tda10045_init(struct dvb_frontend* fe)
593 {
594 struct tda1004x_state* state = fe->demodulator_priv;
595
596 dprintk("%s\n", __FUNCTION__);
597
598 if (tda10045_fwupload(fe)) {
599 printk("tda1004x: firmware upload failed\n");
600 return -EIO;
601 }
602
603 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC
604
605 // tda setup
606 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
607 tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream
608 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0); // set polarity of VAGC signal
609 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer
610 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset
611 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset
612 tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface
613 tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface
614 tda1004x_write_mask(state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits
615 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity
616 tda1004x_write_byteI(state, TDA1004X_CONFADC1, 0x2e);
617
618 tda1004x_write_mask(state, 0x1f, 0x01, state->config->invert_oclk);
619
620 return 0;
621 }
622
623 static int tda10046_init(struct dvb_frontend* fe)
624 {
625 struct tda1004x_state* state = fe->demodulator_priv;
626 dprintk("%s\n", __FUNCTION__);
627
628 if (tda10046_fwupload(fe)) {
629 printk("tda1004x: firmware upload failed\n");
630 return -EIO;
631 }
632
633 // tda setup
634 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
635 tda1004x_write_byteI(state, TDA1004X_AUTO, 0x87); // 100 ppm crystal, select HP stream
636 tda1004x_write_byteI(state, TDA1004X_CONFC1, 0x88); // enable pulse killer
637
638 switch (state->config->agc_config) {
639 case TDA10046_AGC_DEFAULT:
640 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x00); // AGC setup
641 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
642 break;
643 case TDA10046_AGC_IFO_AUTO_NEG:
644 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
645 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
646 break;
647 case TDA10046_AGC_IFO_AUTO_POS:
648 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
649 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x00); // set AGC polarities
650 break;
651 case TDA10046_AGC_TDA827X_GP11:
652 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02); // AGC setup
653 tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70); // AGC Threshold
654 tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x08); // Gain Renormalize
655 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x6a); // set AGC polarities
656 break;
657 case TDA10046_AGC_TDA827X_GP00:
658 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02); // AGC setup
659 tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70); // AGC Threshold
660 tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x08); // Gain Renormalize
661 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
662 break;
663 case TDA10046_AGC_TDA827X_GP01:
664 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02); // AGC setup
665 tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70); // AGC Threshold
666 tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x08); // Gain Renormalize
667 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x62); // set AGC polarities
668 break;
669 }
670 tda1004x_write_byteI(state, TDA1004X_CONFADC2, 0x38);
671 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0x61); // Turn both AGC outputs on
672 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0); // }
673 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
674 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0); // }
675 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff); // }
676 tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 0x12); // IF gain 2, TUN gain 1
677 tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, 0x1a); // 10^6 VBER measurement bits
678 tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
679 tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config
680 // tda1004x_write_mask(state, 0x50, 0x80, 0x80); // handle out of guard echoes
681 tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7);
682
683 return 0;
684 }
685
686 static int tda1004x_set_fe(struct dvb_frontend* fe,
687 struct dvb_frontend_parameters *fe_params)
688 {
689 struct tda1004x_state* state = fe->demodulator_priv;
690 int tmp;
691 int inversion;
692
693 dprintk("%s\n", __FUNCTION__);
694
695 if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
696 // setup auto offset
697 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10);
698 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x80, 0);
699 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0);
700
701 // disable agc_conf[2]
702 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 0);
703 }
704
705 // set frequency
706 if (fe->ops.tuner_ops.set_params) {
707 fe->ops.tuner_ops.set_params(fe, fe_params);
708 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
709 }
710
711 // Hardcoded to use auto as much as possible on the TDA10045 as it
712 // is very unreliable if AUTO mode is _not_ used.
713 if (state->demod_type == TDA1004X_DEMOD_TDA10045) {
714 fe_params->u.ofdm.code_rate_HP = FEC_AUTO;
715 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_AUTO;
716 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_AUTO;
717 }
718
719 // Set standard params.. or put them to auto
720 if ((fe_params->u.ofdm.code_rate_HP == FEC_AUTO) ||
721 (fe_params->u.ofdm.code_rate_LP == FEC_AUTO) ||
722 (fe_params->u.ofdm.constellation == QAM_AUTO) ||
723 (fe_params->u.ofdm.hierarchy_information == HIERARCHY_AUTO)) {
724 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1); // enable auto
725 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); // turn off constellation bits
726 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits
727 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits
728 } else {
729 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0); // disable auto
730
731 // set HP FEC
732 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_HP);
733 if (tmp < 0)
734 return tmp;
735 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp);
736
737 // set LP FEC
738 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_LP);
739 if (tmp < 0)
740 return tmp;
741 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3);
742
743 // set constellation
744 switch (fe_params->u.ofdm.constellation) {
745 case QPSK:
746 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0);
747 break;
748
749 case QAM_16:
750 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 1);
751 break;
752
753 case QAM_64:
754 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 2);
755 break;
756
757 default:
758 return -EINVAL;
759 }
760
761 // set hierarchy
762 switch (fe_params->u.ofdm.hierarchy_information) {
763 case HIERARCHY_NONE:
764 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5);
765 break;
766
767 case HIERARCHY_1:
768 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 1 << 5);
769 break;
770
771 case HIERARCHY_2:
772 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 2 << 5);
773 break;
774
775 case HIERARCHY_4:
776 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 3 << 5);
777 break;
778
779 default:
780 return -EINVAL;
781 }
782 }
783
784 // set bandwidth
785 switch (state->demod_type) {
786 case TDA1004X_DEMOD_TDA10045:
787 tda10045h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
788 break;
789
790 case TDA1004X_DEMOD_TDA10046:
791 tda10046h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
792 break;
793 }
794
795 // set inversion
796 inversion = fe_params->inversion;
797 if (state->config->invert)
798 inversion = inversion ? INVERSION_OFF : INVERSION_ON;
799 switch (inversion) {
800 case INVERSION_OFF:
801 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0);
802 break;
803
804 case INVERSION_ON:
805 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0x20);
806 break;
807
808 default:
809 return -EINVAL;
810 }
811
812 // set guard interval
813 switch (fe_params->u.ofdm.guard_interval) {
814 case GUARD_INTERVAL_1_32:
815 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
816 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
817 break;
818
819 case GUARD_INTERVAL_1_16:
820 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
821 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 1 << 2);
822 break;
823
824 case GUARD_INTERVAL_1_8:
825 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
826 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 2 << 2);
827 break;
828
829 case GUARD_INTERVAL_1_4:
830 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
831 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 3 << 2);
832 break;
833
834 case GUARD_INTERVAL_AUTO:
835 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 2);
836 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
837 break;
838
839 default:
840 return -EINVAL;
841 }
842
843 // set transmission mode
844 switch (fe_params->u.ofdm.transmission_mode) {
845 case TRANSMISSION_MODE_2K:
846 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
847 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4);
848 break;
849
850 case TRANSMISSION_MODE_8K:
851 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
852 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 1 << 4);
853 break;
854
855 case TRANSMISSION_MODE_AUTO:
856 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 4);
857 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0);
858 break;
859
860 default:
861 return -EINVAL;
862 }
863
864 // start the lock
865 switch (state->demod_type) {
866 case TDA1004X_DEMOD_TDA10045:
867 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
868 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
869 break;
870
871 case TDA1004X_DEMOD_TDA10046:
872 tda1004x_write_mask(state, TDA1004X_AUTO, 0x40, 0x40);
873 msleep(1);
874 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 1);
875 break;
876 }
877
878 msleep(10);
879
880 return 0;
881 }
882
883 static int tda1004x_get_fe(struct dvb_frontend* fe, struct dvb_frontend_parameters *fe_params)
884 {
885 struct tda1004x_state* state = fe->demodulator_priv;
886
887 dprintk("%s\n", __FUNCTION__);
888
889 // inversion status
890 fe_params->inversion = INVERSION_OFF;
891 if (tda1004x_read_byte(state, TDA1004X_CONFC1) & 0x20)
892 fe_params->inversion = INVERSION_ON;
893 if (state->config->invert)
894 fe_params->inversion = fe_params->inversion ? INVERSION_OFF : INVERSION_ON;
895
896 // bandwidth
897 switch (state->demod_type) {
898 case TDA1004X_DEMOD_TDA10045:
899 switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) {
900 case 0x14:
901 fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
902 break;
903 case 0xdb:
904 fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
905 break;
906 case 0x4f:
907 fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
908 break;
909 }
910 break;
911 case TDA1004X_DEMOD_TDA10046:
912 switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) {
913 case 0x5c:
914 case 0x54:
915 fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
916 break;
917 case 0x6a:
918 case 0x60:
919 fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
920 break;
921 case 0x7b:
922 case 0x70:
923 fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
924 break;
925 }
926 break;
927 }
928
929 // FEC
930 fe_params->u.ofdm.code_rate_HP =
931 tda1004x_decode_fec(tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7);
932 fe_params->u.ofdm.code_rate_LP =
933 tda1004x_decode_fec((tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7);
934
935 // constellation
936 switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) {
937 case 0:
938 fe_params->u.ofdm.constellation = QPSK;
939 break;
940 case 1:
941 fe_params->u.ofdm.constellation = QAM_16;
942 break;
943 case 2:
944 fe_params->u.ofdm.constellation = QAM_64;
945 break;
946 }
947
948 // transmission mode
949 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
950 if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10)
951 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
952
953 // guard interval
954 switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) {
955 case 0:
956 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
957 break;
958 case 1:
959 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
960 break;
961 case 2:
962 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
963 break;
964 case 3:
965 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
966 break;
967 }
968
969 // hierarchy
970 switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) {
971 case 0:
972 fe_params->u.ofdm.hierarchy_information = HIERARCHY_NONE;
973 break;
974 case 1:
975 fe_params->u.ofdm.hierarchy_information = HIERARCHY_1;
976 break;
977 case 2:
978 fe_params->u.ofdm.hierarchy_information = HIERARCHY_2;
979 break;
980 case 3:
981 fe_params->u.ofdm.hierarchy_information = HIERARCHY_4;
982 break;
983 }
984
985 return 0;
986 }
987
988 static int tda1004x_read_status(struct dvb_frontend* fe, fe_status_t * fe_status)
989 {
990 struct tda1004x_state* state = fe->demodulator_priv;
991 int status;
992 int cber;
993 int vber;
994
995 dprintk("%s\n", __FUNCTION__);
996
997 // read status
998 status = tda1004x_read_byte(state, TDA1004X_STATUS_CD);
999 if (status == -1)
1000 return -EIO;
1001
1002 // decode
1003 *fe_status = 0;
1004 if (status & 4)
1005 *fe_status |= FE_HAS_SIGNAL;
1006 if (status & 2)
1007 *fe_status |= FE_HAS_CARRIER;
1008 if (status & 8)
1009 *fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
1010
1011 // if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi
1012 // is getting anything valid
1013 if (!(*fe_status & FE_HAS_VITERBI)) {
1014 // read the CBER
1015 cber = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
1016 if (cber == -1)
1017 return -EIO;
1018 status = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
1019 if (status == -1)
1020 return -EIO;
1021 cber |= (status << 8);
1022 // The address 0x20 should be read to cope with a TDA10046 bug
1023 tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1024
1025 if (cber != 65535)
1026 *fe_status |= FE_HAS_VITERBI;
1027 }
1028
1029 // if we DO have some valid VITERBI output, but don't already have SYNC
1030 // bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid.
1031 if ((*fe_status & FE_HAS_VITERBI) && (!(*fe_status & FE_HAS_SYNC))) {
1032 // read the VBER
1033 vber = tda1004x_read_byte(state, TDA1004X_VBER_LSB);
1034 if (vber == -1)
1035 return -EIO;
1036 status = tda1004x_read_byte(state, TDA1004X_VBER_MID);
1037 if (status == -1)
1038 return -EIO;
1039 vber |= (status << 8);
1040 status = tda1004x_read_byte(state, TDA1004X_VBER_MSB);
1041 if (status == -1)
1042 return -EIO;
1043 vber |= (status & 0x0f) << 16;
1044 // The CVBER_LUT should be read to cope with TDA10046 hardware bug
1045 tda1004x_read_byte(state, TDA1004X_CVBER_LUT);
1046
1047 // if RS has passed some valid TS packets, then we must be
1048 // getting some SYNC bytes
1049 if (vber < 16632)
1050 *fe_status |= FE_HAS_SYNC;
1051 }
1052
1053 // success
1054 dprintk("%s: fe_status=0x%x\n", __FUNCTION__, *fe_status);
1055 return 0;
1056 }
1057
1058 static int tda1004x_read_signal_strength(struct dvb_frontend* fe, u16 * signal)
1059 {
1060 struct tda1004x_state* state = fe->demodulator_priv;
1061 int tmp;
1062 int reg = 0;
1063
1064 dprintk("%s\n", __FUNCTION__);
1065
1066 // determine the register to use
1067 switch (state->demod_type) {
1068 case TDA1004X_DEMOD_TDA10045:
1069 reg = TDA10045H_S_AGC;
1070 break;
1071
1072 case TDA1004X_DEMOD_TDA10046:
1073 reg = TDA10046H_AGC_IF_LEVEL;
1074 break;
1075 }
1076
1077 // read it
1078 tmp = tda1004x_read_byte(state, reg);
1079 if (tmp < 0)
1080 return -EIO;
1081
1082 *signal = (tmp << 8) | tmp;
1083 dprintk("%s: signal=0x%x\n", __FUNCTION__, *signal);
1084 return 0;
1085 }
1086
1087 static int tda1004x_read_snr(struct dvb_frontend* fe, u16 * snr)
1088 {
1089 struct tda1004x_state* state = fe->demodulator_priv;
1090 int tmp;
1091
1092 dprintk("%s\n", __FUNCTION__);
1093
1094 // read it
1095 tmp = tda1004x_read_byte(state, TDA1004X_SNR);
1096 if (tmp < 0)
1097 return -EIO;
1098 tmp = 255 - tmp;
1099
1100 *snr = ((tmp << 8) | tmp);
1101 dprintk("%s: snr=0x%x\n", __FUNCTION__, *snr);
1102 return 0;
1103 }
1104
1105 static int tda1004x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
1106 {
1107 struct tda1004x_state* state = fe->demodulator_priv;
1108 int tmp;
1109 int tmp2;
1110 int counter;
1111
1112 dprintk("%s\n", __FUNCTION__);
1113
1114 // read the UCBLOCKS and reset
1115 counter = 0;
1116 tmp = tda1004x_read_byte(state, TDA1004X_UNCOR);
1117 if (tmp < 0)
1118 return -EIO;
1119 tmp &= 0x7f;
1120 while (counter++ < 5) {
1121 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1122 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1123 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1124
1125 tmp2 = tda1004x_read_byte(state, TDA1004X_UNCOR);
1126 if (tmp2 < 0)
1127 return -EIO;
1128 tmp2 &= 0x7f;
1129 if ((tmp2 < tmp) || (tmp2 == 0))
1130 break;
1131 }
1132
1133 if (tmp != 0x7f)
1134 *ucblocks = tmp;
1135 else
1136 *ucblocks = 0xffffffff;
1137
1138 dprintk("%s: ucblocks=0x%x\n", __FUNCTION__, *ucblocks);
1139 return 0;
1140 }
1141
1142 static int tda1004x_read_ber(struct dvb_frontend* fe, u32* ber)
1143 {
1144 struct tda1004x_state* state = fe->demodulator_priv;
1145 int tmp;
1146
1147 dprintk("%s\n", __FUNCTION__);
1148
1149 // read it in
1150 tmp = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
1151 if (tmp < 0)
1152 return -EIO;
1153 *ber = tmp << 1;
1154 tmp = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
1155 if (tmp < 0)
1156 return -EIO;
1157 *ber |= (tmp << 9);
1158 // The address 0x20 should be read to cope with a TDA10046 bug
1159 tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1160
1161 dprintk("%s: ber=0x%x\n", __FUNCTION__, *ber);
1162 return 0;
1163 }
1164
1165 static int tda1004x_sleep(struct dvb_frontend* fe)
1166 {
1167 struct tda1004x_state* state = fe->demodulator_priv;
1168
1169 switch (state->demod_type) {
1170 case TDA1004X_DEMOD_TDA10045:
1171 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0x10);
1172 break;
1173
1174 case TDA1004X_DEMOD_TDA10046:
1175 /* set outputs to tristate */
1176 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0xff);
1177 tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1);
1178 break;
1179 }
1180
1181 return 0;
1182 }
1183
1184 static int tda1004x_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
1185 {
1186 struct tda1004x_state* state = fe->demodulator_priv;
1187
1188 if (enable) {
1189 return tda1004x_enable_tuner_i2c(state);
1190 } else {
1191 return tda1004x_disable_tuner_i2c(state);
1192 }
1193 }
1194
1195 static int tda1004x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
1196 {
1197 fesettings->min_delay_ms = 800;
1198 /* Drift compensation makes no sense for DVB-T */
1199 fesettings->step_size = 0;
1200 fesettings->max_drift = 0;
1201 return 0;
1202 }
1203
1204 static void tda1004x_release(struct dvb_frontend* fe)
1205 {
1206 struct tda1004x_state *state = fe->demodulator_priv;
1207 kfree(state);
1208 }
1209
1210 static struct dvb_frontend_ops tda10045_ops = {
1211 .info = {
1212 .name = "Philips TDA10045H DVB-T",
1213 .type = FE_OFDM,
1214 .frequency_min = 51000000,
1215 .frequency_max = 858000000,
1216 .frequency_stepsize = 166667,
1217 .caps =
1218 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1219 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1220 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1221 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1222 },
1223
1224 .release = tda1004x_release,
1225
1226 .init = tda10045_init,
1227 .sleep = tda1004x_sleep,
1228 .write = tda1004x_write,
1229 .i2c_gate_ctrl = tda1004x_i2c_gate_ctrl,
1230
1231 .set_frontend = tda1004x_set_fe,
1232 .get_frontend = tda1004x_get_fe,
1233 .get_tune_settings = tda1004x_get_tune_settings,
1234
1235 .read_status = tda1004x_read_status,
1236 .read_ber = tda1004x_read_ber,
1237 .read_signal_strength = tda1004x_read_signal_strength,
1238 .read_snr = tda1004x_read_snr,
1239 .read_ucblocks = tda1004x_read_ucblocks,
1240 };
1241
1242 struct dvb_frontend* tda10045_attach(const struct tda1004x_config* config,
1243 struct i2c_adapter* i2c)
1244 {
1245 struct tda1004x_state *state;
1246
1247 /* allocate memory for the internal state */
1248 state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1249 if (!state)
1250 return NULL;
1251
1252 /* setup the state */
1253 state->config = config;
1254 state->i2c = i2c;
1255 state->demod_type = TDA1004X_DEMOD_TDA10045;
1256
1257 /* check if the demod is there */
1258 if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x25) {
1259 kfree(state);
1260 return NULL;
1261 }
1262
1263 /* create dvb_frontend */
1264 memcpy(&state->frontend.ops, &tda10045_ops, sizeof(struct dvb_frontend_ops));
1265 state->frontend.demodulator_priv = state;
1266 return &state->frontend;
1267 }
1268
1269 static struct dvb_frontend_ops tda10046_ops = {
1270 .info = {
1271 .name = "Philips TDA10046H DVB-T",
1272 .type = FE_OFDM,
1273 .frequency_min = 51000000,
1274 .frequency_max = 858000000,
1275 .frequency_stepsize = 166667,
1276 .caps =
1277 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1278 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1279 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1280 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1281 },
1282
1283 .release = tda1004x_release,
1284
1285 .init = tda10046_init,
1286 .sleep = tda1004x_sleep,
1287 .write = tda1004x_write,
1288 .i2c_gate_ctrl = tda1004x_i2c_gate_ctrl,
1289
1290 .set_frontend = tda1004x_set_fe,
1291 .get_frontend = tda1004x_get_fe,
1292 .get_tune_settings = tda1004x_get_tune_settings,
1293
1294 .read_status = tda1004x_read_status,
1295 .read_ber = tda1004x_read_ber,
1296 .read_signal_strength = tda1004x_read_signal_strength,
1297 .read_snr = tda1004x_read_snr,
1298 .read_ucblocks = tda1004x_read_ucblocks,
1299 };
1300
1301 struct dvb_frontend* tda10046_attach(const struct tda1004x_config* config,
1302 struct i2c_adapter* i2c)
1303 {
1304 struct tda1004x_state *state;
1305
1306 /* allocate memory for the internal state */
1307 state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1308 if (!state)
1309 return NULL;
1310
1311 /* setup the state */
1312 state->config = config;
1313 state->i2c = i2c;
1314 state->demod_type = TDA1004X_DEMOD_TDA10046;
1315
1316 /* check if the demod is there */
1317 if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x46) {
1318 kfree(state);
1319 return NULL;
1320 }
1321
1322 /* create dvb_frontend */
1323 memcpy(&state->frontend.ops, &tda10046_ops, sizeof(struct dvb_frontend_ops));
1324 state->frontend.demodulator_priv = state;
1325 return &state->frontend;
1326 }
1327
1328 module_param(debug, int, 0644);
1329 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
1330
1331 MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Demodulator");
1332 MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach");
1333 MODULE_LICENSE("GPL");
1334
1335 EXPORT_SYMBOL(tda10045_attach);
1336 EXPORT_SYMBOL(tda10046_attach);
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