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[PATCH] uml: remove pte_mkexec
[linux-2.6/verdex.git] / drivers / net / 8139cp.c
blob5a4990ae3730575bf3d19167e95a727f7616126b
1 /* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
2 /*
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
4
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
11
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
18
19 See the file COPYING in this distribution for more information.
20
21 Contributors:
22
23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
26
27 TODO:
28 * Test Tx checksumming thoroughly
29 * Implement dev->tx_timeout
30
31 Low priority TODO:
32 * Complete reset on PciErr
33 * Consider Rx interrupt mitigation using TimerIntr
34 * Investigate using skb->priority with h/w VLAN priority
35 * Investigate using High Priority Tx Queue with skb->priority
36 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
37 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
38 * Implement Tx software interrupt mitigation via
39 Tx descriptor bit
40 * The real minimum of CP_MIN_MTU is 4 bytes. However,
41 for this to be supported, one must(?) turn on packet padding.
42 * Support external MII transceivers (patch available)
43
44 NOTES:
45 * TX checksumming is considered experimental. It is off by
46 default, use ethtool to turn it on.
47
48 */
49
50 #define DRV_NAME "8139cp"
51 #define DRV_VERSION "1.3"
52 #define DRV_RELDATE "Mar 22, 2004"
53
54
55 #include <linux/module.h>
56 #include <linux/moduleparam.h>
57 #include <linux/kernel.h>
58 #include <linux/compiler.h>
59 #include <linux/netdevice.h>
60 #include <linux/etherdevice.h>
61 #include <linux/init.h>
62 #include <linux/pci.h>
63 #include <linux/dma-mapping.h>
64 #include <linux/delay.h>
65 #include <linux/ethtool.h>
66 #include <linux/mii.h>
67 #include <linux/if_vlan.h>
68 #include <linux/crc32.h>
69 #include <linux/in.h>
70 #include <linux/ip.h>
71 #include <linux/tcp.h>
72 #include <linux/udp.h>
73 #include <linux/cache.h>
74 #include <asm/io.h>
75 #include <asm/irq.h>
76 #include <asm/uaccess.h>
77
78 /* VLAN tagging feature enable/disable */
79 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
80 #define CP_VLAN_TAG_USED 1
81 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
82 do { (tx_desc)->opts2 = (vlan_tag_value); } while (0)
83 #else
84 #define CP_VLAN_TAG_USED 0
85 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
86 do { (tx_desc)->opts2 = 0; } while (0)
87 #endif
88
89 /* These identify the driver base version and may not be removed. */
90 static char version[] =
91 KERN_INFO DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
92
93 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
94 MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
95 MODULE_VERSION(DRV_VERSION);
96 MODULE_LICENSE("GPL");
97
98 static int debug = -1;
99 module_param(debug, int, 0);
100 MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
101
102 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
103 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
104 static int multicast_filter_limit = 32;
105 module_param(multicast_filter_limit, int, 0);
106 MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
107
108 #define PFX DRV_NAME ": "
109
110 #ifndef TRUE
111 #define FALSE 0
112 #define TRUE (!FALSE)
113 #endif
114
115 #define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
116 NETIF_MSG_PROBE | \
117 NETIF_MSG_LINK)
118 #define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
119 #define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
120 #define CP_REGS_SIZE (0xff + 1)
121 #define CP_REGS_VER 1 /* version 1 */
122 #define CP_RX_RING_SIZE 64
123 #define CP_TX_RING_SIZE 64
124 #define CP_RING_BYTES \
125 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
126 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
127 CP_STATS_SIZE)
128 #define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
129 #define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
130 #define TX_BUFFS_AVAIL(CP) \
131 (((CP)->tx_tail <= (CP)->tx_head) ? \
132 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
133 (CP)->tx_tail - (CP)->tx_head - 1)
134
135 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
136 #define RX_OFFSET 2
137 #define CP_INTERNAL_PHY 32
138
139 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
140 #define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
141 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
142 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
143 #define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
144
145 /* Time in jiffies before concluding the transmitter is hung. */
146 #define TX_TIMEOUT (6*HZ)
147
148 /* hardware minimum and maximum for a single frame's data payload */
149 #define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
150 #define CP_MAX_MTU 4096
151
152 enum {
153 /* NIC register offsets */
154 MAC0 = 0x00, /* Ethernet hardware address. */
155 MAR0 = 0x08, /* Multicast filter. */
156 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
157 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
158 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
159 Cmd = 0x37, /* Command register */
160 IntrMask = 0x3C, /* Interrupt mask */
161 IntrStatus = 0x3E, /* Interrupt status */
162 TxConfig = 0x40, /* Tx configuration */
163 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
164 RxConfig = 0x44, /* Rx configuration */
165 RxMissed = 0x4C, /* 24 bits valid, write clears */
166 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
167 Config1 = 0x52, /* Config1 */
168 Config3 = 0x59, /* Config3 */
169 Config4 = 0x5A, /* Config4 */
170 MultiIntr = 0x5C, /* Multiple interrupt select */
171 BasicModeCtrl = 0x62, /* MII BMCR */
172 BasicModeStatus = 0x64, /* MII BMSR */
173 NWayAdvert = 0x66, /* MII ADVERTISE */
174 NWayLPAR = 0x68, /* MII LPA */
175 NWayExpansion = 0x6A, /* MII Expansion */
176 Config5 = 0xD8, /* Config5 */
177 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
178 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
179 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
180 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
181 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
182 TxThresh = 0xEC, /* Early Tx threshold */
183 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
184 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
185
186 /* Tx and Rx status descriptors */
187 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
188 RingEnd = (1 << 30), /* End of descriptor ring */
189 FirstFrag = (1 << 29), /* First segment of a packet */
190 LastFrag = (1 << 28), /* Final segment of a packet */
191 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
192 MSSShift = 16, /* MSS value position */
193 MSSMask = 0xfff, /* MSS value: 11 bits */
194 TxError = (1 << 23), /* Tx error summary */
195 RxError = (1 << 20), /* Rx error summary */
196 IPCS = (1 << 18), /* Calculate IP checksum */
197 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
198 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
199 TxVlanTag = (1 << 17), /* Add VLAN tag */
200 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
201 IPFail = (1 << 15), /* IP checksum failed */
202 UDPFail = (1 << 14), /* UDP/IP checksum failed */
203 TCPFail = (1 << 13), /* TCP/IP checksum failed */
204 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
205 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
206 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
207 RxProtoTCP = 1,
208 RxProtoUDP = 2,
209 RxProtoIP = 3,
210 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
211 TxOWC = (1 << 22), /* Tx Out-of-window collision */
212 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
213 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
214 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
215 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
216 RxErrFrame = (1 << 27), /* Rx frame alignment error */
217 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
218 RxErrCRC = (1 << 18), /* Rx CRC error */
219 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
220 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
221 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
222
223 /* StatsAddr register */
224 DumpStats = (1 << 3), /* Begin stats dump */
225
226 /* RxConfig register */
227 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
228 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
229 AcceptErr = 0x20, /* Accept packets with CRC errors */
230 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
231 AcceptBroadcast = 0x08, /* Accept broadcast packets */
232 AcceptMulticast = 0x04, /* Accept multicast packets */
233 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
234 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
235
236 /* IntrMask / IntrStatus registers */
237 PciErr = (1 << 15), /* System error on the PCI bus */
238 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
239 LenChg = (1 << 13), /* Cable length change */
240 SWInt = (1 << 8), /* Software-requested interrupt */
241 TxEmpty = (1 << 7), /* No Tx descriptors available */
242 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
243 LinkChg = (1 << 5), /* Packet underrun, or link change */
244 RxEmpty = (1 << 4), /* No Rx descriptors available */
245 TxErr = (1 << 3), /* Tx error */
246 TxOK = (1 << 2), /* Tx packet sent */
247 RxErr = (1 << 1), /* Rx error */
248 RxOK = (1 << 0), /* Rx packet received */
249 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
250 but hardware likes to raise it */
251
252 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
253 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
254 RxErr | RxOK | IntrResvd,
255
256 /* C mode command register */
257 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
258 RxOn = (1 << 3), /* Rx mode enable */
259 TxOn = (1 << 2), /* Tx mode enable */
260
261 /* C+ mode command register */
262 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
263 RxChkSum = (1 << 5), /* Rx checksum offload enable */
264 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
265 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
266 CpRxOn = (1 << 1), /* Rx mode enable */
267 CpTxOn = (1 << 0), /* Tx mode enable */
268
269 /* Cfg9436 EEPROM control register */
270 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
271 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
272
273 /* TxConfig register */
274 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
275 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
276
277 /* Early Tx Threshold register */
278 TxThreshMask = 0x3f, /* Mask bits 5-0 */
279 TxThreshMax = 2048, /* Max early Tx threshold */
280
281 /* Config1 register */
282 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
283 LWACT = (1 << 4), /* LWAKE active mode */
284 PMEnable = (1 << 0), /* Enable various PM features of chip */
285
286 /* Config3 register */
287 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
288 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
289 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
290
291 /* Config4 register */
292 LWPTN = (1 << 1), /* LWAKE Pattern */
293 LWPME = (1 << 4), /* LANWAKE vs PMEB */
294
295 /* Config5 register */
296 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
297 MWF = (1 << 5), /* Accept Multicast wakeup frame */
298 UWF = (1 << 4), /* Accept Unicast wakeup frame */
299 LANWake = (1 << 1), /* Enable LANWake signal */
300 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
301
302 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
303 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
304 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
305 };
306
307 static const unsigned int cp_rx_config =
308 (RX_FIFO_THRESH << RxCfgFIFOShift) |
309 (RX_DMA_BURST << RxCfgDMAShift);
310
311 struct cp_desc {
312 u32 opts1;
313 u32 opts2;
314 u64 addr;
315 };
316
317 struct cp_dma_stats {
318 u64 tx_ok;
319 u64 rx_ok;
320 u64 tx_err;
321 u32 rx_err;
322 u16 rx_fifo;
323 u16 frame_align;
324 u32 tx_ok_1col;
325 u32 tx_ok_mcol;
326 u64 rx_ok_phys;
327 u64 rx_ok_bcast;
328 u32 rx_ok_mcast;
329 u16 tx_abort;
330 u16 tx_underrun;
331 } __attribute__((packed));
332
333 struct cp_extra_stats {
334 unsigned long rx_frags;
335 };
336
337 struct cp_private {
338 void __iomem *regs;
339 struct net_device *dev;
340 spinlock_t lock;
341 u32 msg_enable;
342
343 struct pci_dev *pdev;
344 u32 rx_config;
345 u16 cpcmd;
346
347 struct net_device_stats net_stats;
348 struct cp_extra_stats cp_stats;
349
350 unsigned rx_head ____cacheline_aligned;
351 unsigned rx_tail;
352 struct cp_desc *rx_ring;
353 struct sk_buff *rx_skb[CP_RX_RING_SIZE];
354
355 unsigned tx_head ____cacheline_aligned;
356 unsigned tx_tail;
357 struct cp_desc *tx_ring;
358 struct sk_buff *tx_skb[CP_TX_RING_SIZE];
359
360 unsigned rx_buf_sz;
361 unsigned wol_enabled : 1; /* Is Wake-on-LAN enabled? */
362
363 #if CP_VLAN_TAG_USED
364 struct vlan_group *vlgrp;
365 #endif
366 dma_addr_t ring_dma;
367
368 struct mii_if_info mii_if;
369 };
370
371 #define cpr8(reg) readb(cp->regs + (reg))
372 #define cpr16(reg) readw(cp->regs + (reg))
373 #define cpr32(reg) readl(cp->regs + (reg))
374 #define cpw8(reg,val) writeb((val), cp->regs + (reg))
375 #define cpw16(reg,val) writew((val), cp->regs + (reg))
376 #define cpw32(reg,val) writel((val), cp->regs + (reg))
377 #define cpw8_f(reg,val) do { \
378 writeb((val), cp->regs + (reg)); \
379 readb(cp->regs + (reg)); \
380 } while (0)
381 #define cpw16_f(reg,val) do { \
382 writew((val), cp->regs + (reg)); \
383 readw(cp->regs + (reg)); \
384 } while (0)
385 #define cpw32_f(reg,val) do { \
386 writel((val), cp->regs + (reg)); \
387 readl(cp->regs + (reg)); \
388 } while (0)
389
390
391 static void __cp_set_rx_mode (struct net_device *dev);
392 static void cp_tx (struct cp_private *cp);
393 static void cp_clean_rings (struct cp_private *cp);
394 #ifdef CONFIG_NET_POLL_CONTROLLER
395 static void cp_poll_controller(struct net_device *dev);
396 #endif
397 static int cp_get_eeprom_len(struct net_device *dev);
398 static int cp_get_eeprom(struct net_device *dev,
399 struct ethtool_eeprom *eeprom, u8 *data);
400 static int cp_set_eeprom(struct net_device *dev,
401 struct ethtool_eeprom *eeprom, u8 *data);
402
403 static struct pci_device_id cp_pci_tbl[] = {
404 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139), },
405 { PCI_DEVICE(PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322), },
406 { },
407 };
408 MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
409
410 static struct {
411 const char str[ETH_GSTRING_LEN];
412 } ethtool_stats_keys[] = {
413 { "tx_ok" },
414 { "rx_ok" },
415 { "tx_err" },
416 { "rx_err" },
417 { "rx_fifo" },
418 { "frame_align" },
419 { "tx_ok_1col" },
420 { "tx_ok_mcol" },
421 { "rx_ok_phys" },
422 { "rx_ok_bcast" },
423 { "rx_ok_mcast" },
424 { "tx_abort" },
425 { "tx_underrun" },
426 { "rx_frags" },
427 };
428
429
430 #if CP_VLAN_TAG_USED
431 static void cp_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
432 {
433 struct cp_private *cp = netdev_priv(dev);
434 unsigned long flags;
435
436 spin_lock_irqsave(&cp->lock, flags);
437 cp->vlgrp = grp;
438 cp->cpcmd |= RxVlanOn;
439 cpw16(CpCmd, cp->cpcmd);
440 spin_unlock_irqrestore(&cp->lock, flags);
441 }
442
443 static void cp_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
444 {
445 struct cp_private *cp = netdev_priv(dev);
446 unsigned long flags;
447
448 spin_lock_irqsave(&cp->lock, flags);
449 cp->cpcmd &= ~RxVlanOn;
450 cpw16(CpCmd, cp->cpcmd);
451 if (cp->vlgrp)
452 cp->vlgrp->vlan_devices[vid] = NULL;
453 spin_unlock_irqrestore(&cp->lock, flags);
454 }
455 #endif /* CP_VLAN_TAG_USED */
456
457 static inline void cp_set_rxbufsize (struct cp_private *cp)
458 {
459 unsigned int mtu = cp->dev->mtu;
460
461 if (mtu > ETH_DATA_LEN)
462 /* MTU + ethernet header + FCS + optional VLAN tag */
463 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
464 else
465 cp->rx_buf_sz = PKT_BUF_SZ;
466 }
467
468 static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
469 struct cp_desc *desc)
470 {
471 skb->protocol = eth_type_trans (skb, cp->dev);
472
473 cp->net_stats.rx_packets++;
474 cp->net_stats.rx_bytes += skb->len;
475 cp->dev->last_rx = jiffies;
476
477 #if CP_VLAN_TAG_USED
478 if (cp->vlgrp && (desc->opts2 & RxVlanTagged)) {
479 vlan_hwaccel_receive_skb(skb, cp->vlgrp,
480 be16_to_cpu(desc->opts2 & 0xffff));
481 } else
482 #endif
483 netif_receive_skb(skb);
484 }
485
486 static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
487 u32 status, u32 len)
488 {
489 if (netif_msg_rx_err (cp))
490 printk (KERN_DEBUG
491 "%s: rx err, slot %d status 0x%x len %d\n",
492 cp->dev->name, rx_tail, status, len);
493 cp->net_stats.rx_errors++;
494 if (status & RxErrFrame)
495 cp->net_stats.rx_frame_errors++;
496 if (status & RxErrCRC)
497 cp->net_stats.rx_crc_errors++;
498 if ((status & RxErrRunt) || (status & RxErrLong))
499 cp->net_stats.rx_length_errors++;
500 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
501 cp->net_stats.rx_length_errors++;
502 if (status & RxErrFIFO)
503 cp->net_stats.rx_fifo_errors++;
504 }
505
506 static inline unsigned int cp_rx_csum_ok (u32 status)
507 {
508 unsigned int protocol = (status >> 16) & 0x3;
509
510 if (likely((protocol == RxProtoTCP) && (!(status & TCPFail))))
511 return 1;
512 else if ((protocol == RxProtoUDP) && (!(status & UDPFail)))
513 return 1;
514 else if ((protocol == RxProtoIP) && (!(status & IPFail)))
515 return 1;
516 return 0;
517 }
518
519 static int cp_rx_poll (struct net_device *dev, int *budget)
520 {
521 struct cp_private *cp = netdev_priv(dev);
522 unsigned rx_tail = cp->rx_tail;
523 unsigned rx_work = dev->quota;
524 unsigned rx;
525
526 rx_status_loop:
527 rx = 0;
528 cpw16(IntrStatus, cp_rx_intr_mask);
529
530 while (1) {
531 u32 status, len;
532 dma_addr_t mapping;
533 struct sk_buff *skb, *new_skb;
534 struct cp_desc *desc;
535 unsigned buflen;
536
537 skb = cp->rx_skb[rx_tail];
538 BUG_ON(!skb);
539
540 desc = &cp->rx_ring[rx_tail];
541 status = le32_to_cpu(desc->opts1);
542 if (status & DescOwn)
543 break;
544
545 len = (status & 0x1fff) - 4;
546 mapping = le64_to_cpu(desc->addr);
547
548 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
549 /* we don't support incoming fragmented frames.
550 * instead, we attempt to ensure that the
551 * pre-allocated RX skbs are properly sized such
552 * that RX fragments are never encountered
553 */
554 cp_rx_err_acct(cp, rx_tail, status, len);
555 cp->net_stats.rx_dropped++;
556 cp->cp_stats.rx_frags++;
557 goto rx_next;
558 }
559
560 if (status & (RxError | RxErrFIFO)) {
561 cp_rx_err_acct(cp, rx_tail, status, len);
562 goto rx_next;
563 }
564
565 if (netif_msg_rx_status(cp))
566 printk(KERN_DEBUG "%s: rx slot %d status 0x%x len %d\n",
567 dev->name, rx_tail, status, len);
568
569 buflen = cp->rx_buf_sz + RX_OFFSET;
570 new_skb = dev_alloc_skb (buflen);
571 if (!new_skb) {
572 cp->net_stats.rx_dropped++;
573 goto rx_next;
574 }
575
576 skb_reserve(new_skb, RX_OFFSET);
577 new_skb->dev = dev;
578
579 pci_unmap_single(cp->pdev, mapping,
580 buflen, PCI_DMA_FROMDEVICE);
581
582 /* Handle checksum offloading for incoming packets. */
583 if (cp_rx_csum_ok(status))
584 skb->ip_summed = CHECKSUM_UNNECESSARY;
585 else
586 skb->ip_summed = CHECKSUM_NONE;
587
588 skb_put(skb, len);
589
590 mapping = pci_map_single(cp->pdev, new_skb->data, buflen,
591 PCI_DMA_FROMDEVICE);
592 cp->rx_skb[rx_tail] = new_skb;
593
594 cp_rx_skb(cp, skb, desc);
595 rx++;
596
597 rx_next:
598 cp->rx_ring[rx_tail].opts2 = 0;
599 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
600 if (rx_tail == (CP_RX_RING_SIZE - 1))
601 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
602 cp->rx_buf_sz);
603 else
604 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
605 rx_tail = NEXT_RX(rx_tail);
606
607 if (!rx_work--)
608 break;
609 }
610
611 cp->rx_tail = rx_tail;
612
613 dev->quota -= rx;
614 *budget -= rx;
615
616 /* if we did not reach work limit, then we're done with
617 * this round of polling
618 */
619 if (rx_work) {
620 if (cpr16(IntrStatus) & cp_rx_intr_mask)
621 goto rx_status_loop;
622
623 local_irq_disable();
624 cpw16_f(IntrMask, cp_intr_mask);
625 __netif_rx_complete(dev);
626 local_irq_enable();
627
628 return 0; /* done */
629 }
630
631 return 1; /* not done */
632 }
633
634 static irqreturn_t
635 cp_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
636 {
637 struct net_device *dev = dev_instance;
638 struct cp_private *cp;
639 u16 status;
640
641 if (unlikely(dev == NULL))
642 return IRQ_NONE;
643 cp = netdev_priv(dev);
644
645 status = cpr16(IntrStatus);
646 if (!status || (status == 0xFFFF))
647 return IRQ_NONE;
648
649 if (netif_msg_intr(cp))
650 printk(KERN_DEBUG "%s: intr, status %04x cmd %02x cpcmd %04x\n",
651 dev->name, status, cpr8(Cmd), cpr16(CpCmd));
652
653 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
654
655 spin_lock(&cp->lock);
656
657 /* close possible race's with dev_close */
658 if (unlikely(!netif_running(dev))) {
659 cpw16(IntrMask, 0);
660 spin_unlock(&cp->lock);
661 return IRQ_HANDLED;
662 }
663
664 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
665 if (netif_rx_schedule_prep(dev)) {
666 cpw16_f(IntrMask, cp_norx_intr_mask);
667 __netif_rx_schedule(dev);
668 }
669
670 if (status & (TxOK | TxErr | TxEmpty | SWInt))
671 cp_tx(cp);
672 if (status & LinkChg)
673 mii_check_media(&cp->mii_if, netif_msg_link(cp), FALSE);
674
675 spin_unlock(&cp->lock);
676
677 if (status & PciErr) {
678 u16 pci_status;
679
680 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
681 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
682 printk(KERN_ERR "%s: PCI bus error, status=%04x, PCI status=%04x\n",
683 dev->name, status, pci_status);
684
685 /* TODO: reset hardware */
686 }
687
688 return IRQ_HANDLED;
689 }
690
691 #ifdef CONFIG_NET_POLL_CONTROLLER
692 /*
693 * Polling receive - used by netconsole and other diagnostic tools
694 * to allow network i/o with interrupts disabled.
695 */
696 static void cp_poll_controller(struct net_device *dev)
697 {
698 disable_irq(dev->irq);
699 cp_interrupt(dev->irq, dev, NULL);
700 enable_irq(dev->irq);
701 }
702 #endif
703
704 static void cp_tx (struct cp_private *cp)
705 {
706 unsigned tx_head = cp->tx_head;
707 unsigned tx_tail = cp->tx_tail;
708
709 while (tx_tail != tx_head) {
710 struct cp_desc *txd = cp->tx_ring + tx_tail;
711 struct sk_buff *skb;
712 u32 status;
713
714 rmb();
715 status = le32_to_cpu(txd->opts1);
716 if (status & DescOwn)
717 break;
718
719 skb = cp->tx_skb[tx_tail];
720 BUG_ON(!skb);
721
722 pci_unmap_single(cp->pdev, le64_to_cpu(txd->addr),
723 le32_to_cpu(txd->opts1) & 0xffff,
724 PCI_DMA_TODEVICE);
725
726 if (status & LastFrag) {
727 if (status & (TxError | TxFIFOUnder)) {
728 if (netif_msg_tx_err(cp))
729 printk(KERN_DEBUG "%s: tx err, status 0x%x\n",
730 cp->dev->name, status);
731 cp->net_stats.tx_errors++;
732 if (status & TxOWC)
733 cp->net_stats.tx_window_errors++;
734 if (status & TxMaxCol)
735 cp->net_stats.tx_aborted_errors++;
736 if (status & TxLinkFail)
737 cp->net_stats.tx_carrier_errors++;
738 if (status & TxFIFOUnder)
739 cp->net_stats.tx_fifo_errors++;
740 } else {
741 cp->net_stats.collisions +=
742 ((status >> TxColCntShift) & TxColCntMask);
743 cp->net_stats.tx_packets++;
744 cp->net_stats.tx_bytes += skb->len;
745 if (netif_msg_tx_done(cp))
746 printk(KERN_DEBUG "%s: tx done, slot %d\n", cp->dev->name, tx_tail);
747 }
748 dev_kfree_skb_irq(skb);
749 }
750
751 cp->tx_skb[tx_tail] = NULL;
752
753 tx_tail = NEXT_TX(tx_tail);
754 }
755
756 cp->tx_tail = tx_tail;
757
758 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
759 netif_wake_queue(cp->dev);
760 }
761
762 static int cp_start_xmit (struct sk_buff *skb, struct net_device *dev)
763 {
764 struct cp_private *cp = netdev_priv(dev);
765 unsigned entry;
766 u32 eor, flags;
767 #if CP_VLAN_TAG_USED
768 u32 vlan_tag = 0;
769 #endif
770 int mss = 0;
771
772 spin_lock_irq(&cp->lock);
773
774 /* This is a hard error, log it. */
775 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
776 netif_stop_queue(dev);
777 spin_unlock_irq(&cp->lock);
778 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
779 dev->name);
780 return 1;
781 }
782
783 #if CP_VLAN_TAG_USED
784 if (cp->vlgrp && vlan_tx_tag_present(skb))
785 vlan_tag = TxVlanTag | cpu_to_be16(vlan_tx_tag_get(skb));
786 #endif
787
788 entry = cp->tx_head;
789 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
790 if (dev->features & NETIF_F_TSO)
791 mss = skb_shinfo(skb)->gso_size;
792
793 if (skb_shinfo(skb)->nr_frags == 0) {
794 struct cp_desc *txd = &cp->tx_ring[entry];
795 u32 len;
796 dma_addr_t mapping;
797
798 len = skb->len;
799 mapping = pci_map_single(cp->pdev, skb->data, len, PCI_DMA_TODEVICE);
800 CP_VLAN_TX_TAG(txd, vlan_tag);
801 txd->addr = cpu_to_le64(mapping);
802 wmb();
803
804 flags = eor | len | DescOwn | FirstFrag | LastFrag;
805
806 if (mss)
807 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
808 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
809 const struct iphdr *ip = skb->nh.iph;
810 if (ip->protocol == IPPROTO_TCP)
811 flags |= IPCS | TCPCS;
812 else if (ip->protocol == IPPROTO_UDP)
813 flags |= IPCS | UDPCS;
814 else
815 WARN_ON(1); /* we need a WARN() */
816 }
817
818 txd->opts1 = cpu_to_le32(flags);
819 wmb();
820
821 cp->tx_skb[entry] = skb;
822 entry = NEXT_TX(entry);
823 } else {
824 struct cp_desc *txd;
825 u32 first_len, first_eor;
826 dma_addr_t first_mapping;
827 int frag, first_entry = entry;
828 const struct iphdr *ip = skb->nh.iph;
829
830 /* We must give this initial chunk to the device last.
831 * Otherwise we could race with the device.
832 */
833 first_eor = eor;
834 first_len = skb_headlen(skb);
835 first_mapping = pci_map_single(cp->pdev, skb->data,
836 first_len, PCI_DMA_TODEVICE);
837 cp->tx_skb[entry] = skb;
838 entry = NEXT_TX(entry);
839
840 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
841 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
842 u32 len;
843 u32 ctrl;
844 dma_addr_t mapping;
845
846 len = this_frag->size;
847 mapping = pci_map_single(cp->pdev,
848 ((void *) page_address(this_frag->page) +
849 this_frag->page_offset),
850 len, PCI_DMA_TODEVICE);
851 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
852
853 ctrl = eor | len | DescOwn;
854
855 if (mss)
856 ctrl |= LargeSend |
857 ((mss & MSSMask) << MSSShift);
858 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
859 if (ip->protocol == IPPROTO_TCP)
860 ctrl |= IPCS | TCPCS;
861 else if (ip->protocol == IPPROTO_UDP)
862 ctrl |= IPCS | UDPCS;
863 else
864 BUG();
865 }
866
867 if (frag == skb_shinfo(skb)->nr_frags - 1)
868 ctrl |= LastFrag;
869
870 txd = &cp->tx_ring[entry];
871 CP_VLAN_TX_TAG(txd, vlan_tag);
872 txd->addr = cpu_to_le64(mapping);
873 wmb();
874
875 txd->opts1 = cpu_to_le32(ctrl);
876 wmb();
877
878 cp->tx_skb[entry] = skb;
879 entry = NEXT_TX(entry);
880 }
881
882 txd = &cp->tx_ring[first_entry];
883 CP_VLAN_TX_TAG(txd, vlan_tag);
884 txd->addr = cpu_to_le64(first_mapping);
885 wmb();
886
887 if (skb->ip_summed == CHECKSUM_PARTIAL) {
888 if (ip->protocol == IPPROTO_TCP)
889 txd->opts1 = cpu_to_le32(first_eor | first_len |
890 FirstFrag | DescOwn |
891 IPCS | TCPCS);
892 else if (ip->protocol == IPPROTO_UDP)
893 txd->opts1 = cpu_to_le32(first_eor | first_len |
894 FirstFrag | DescOwn |
895 IPCS | UDPCS);
896 else
897 BUG();
898 } else
899 txd->opts1 = cpu_to_le32(first_eor | first_len |
900 FirstFrag | DescOwn);
901 wmb();
902 }
903 cp->tx_head = entry;
904 if (netif_msg_tx_queued(cp))
905 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
906 dev->name, entry, skb->len);
907 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
908 netif_stop_queue(dev);
909
910 spin_unlock_irq(&cp->lock);
911
912 cpw8(TxPoll, NormalTxPoll);
913 dev->trans_start = jiffies;
914
915 return 0;
916 }
917
918 /* Set or clear the multicast filter for this adaptor.
919 This routine is not state sensitive and need not be SMP locked. */
920
921 static void __cp_set_rx_mode (struct net_device *dev)
922 {
923 struct cp_private *cp = netdev_priv(dev);
924 u32 mc_filter[2]; /* Multicast hash filter */
925 int i, rx_mode;
926 u32 tmp;
927
928 /* Note: do not reorder, GCC is clever about common statements. */
929 if (dev->flags & IFF_PROMISC) {
930 /* Unconditionally log net taps. */
931 rx_mode =
932 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
933 AcceptAllPhys;
934 mc_filter[1] = mc_filter[0] = 0xffffffff;
935 } else if ((dev->mc_count > multicast_filter_limit)
936 || (dev->flags & IFF_ALLMULTI)) {
937 /* Too many to filter perfectly -- accept all multicasts. */
938 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
939 mc_filter[1] = mc_filter[0] = 0xffffffff;
940 } else {
941 struct dev_mc_list *mclist;
942 rx_mode = AcceptBroadcast | AcceptMyPhys;
943 mc_filter[1] = mc_filter[0] = 0;
944 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
945 i++, mclist = mclist->next) {
946 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
947
948 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
949 rx_mode |= AcceptMulticast;
950 }
951 }
952
953 /* We can safely update without stopping the chip. */
954 tmp = cp_rx_config | rx_mode;
955 if (cp->rx_config != tmp) {
956 cpw32_f (RxConfig, tmp);
957 cp->rx_config = tmp;
958 }
959 cpw32_f (MAR0 + 0, mc_filter[0]);
960 cpw32_f (MAR0 + 4, mc_filter[1]);
961 }
962
963 static void cp_set_rx_mode (struct net_device *dev)
964 {
965 unsigned long flags;
966 struct cp_private *cp = netdev_priv(dev);
967
968 spin_lock_irqsave (&cp->lock, flags);
969 __cp_set_rx_mode(dev);
970 spin_unlock_irqrestore (&cp->lock, flags);
971 }
972
973 static void __cp_get_stats(struct cp_private *cp)
974 {
975 /* only lower 24 bits valid; write any value to clear */
976 cp->net_stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
977 cpw32 (RxMissed, 0);
978 }
979
980 static struct net_device_stats *cp_get_stats(struct net_device *dev)
981 {
982 struct cp_private *cp = netdev_priv(dev);
983 unsigned long flags;
984
985 /* The chip only need report frame silently dropped. */
986 spin_lock_irqsave(&cp->lock, flags);
987 if (netif_running(dev) && netif_device_present(dev))
988 __cp_get_stats(cp);
989 spin_unlock_irqrestore(&cp->lock, flags);
990
991 return &cp->net_stats;
992 }
993
994 static void cp_stop_hw (struct cp_private *cp)
995 {
996 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
997 cpw16_f(IntrMask, 0);
998 cpw8(Cmd, 0);
999 cpw16_f(CpCmd, 0);
1000 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
1001
1002 cp->rx_tail = 0;
1003 cp->tx_head = cp->tx_tail = 0;
1004 }
1005
1006 static void cp_reset_hw (struct cp_private *cp)
1007 {
1008 unsigned work = 1000;
1009
1010 cpw8(Cmd, CmdReset);
1011
1012 while (work--) {
1013 if (!(cpr8(Cmd) & CmdReset))
1014 return;
1015
1016 schedule_timeout_uninterruptible(10);
1017 }
1018
1019 printk(KERN_ERR "%s: hardware reset timeout\n", cp->dev->name);
1020 }
1021
1022 static inline void cp_start_hw (struct cp_private *cp)
1023 {
1024 cpw16(CpCmd, cp->cpcmd);
1025 cpw8(Cmd, RxOn | TxOn);
1026 }
1027
1028 static void cp_init_hw (struct cp_private *cp)
1029 {
1030 struct net_device *dev = cp->dev;
1031 dma_addr_t ring_dma;
1032
1033 cp_reset_hw(cp);
1034
1035 cpw8_f (Cfg9346, Cfg9346_Unlock);
1036
1037 /* Restore our idea of the MAC address. */
1038 cpw32_f (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1039 cpw32_f (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1040
1041 cp_start_hw(cp);
1042 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1043
1044 __cp_set_rx_mode(dev);
1045 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1046
1047 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1048 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1049 cpw8(Config3, PARMEnable);
1050 cp->wol_enabled = 0;
1051
1052 cpw8(Config5, cpr8(Config5) & PMEStatus);
1053
1054 cpw32_f(HiTxRingAddr, 0);
1055 cpw32_f(HiTxRingAddr + 4, 0);
1056
1057 ring_dma = cp->ring_dma;
1058 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1059 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1060
1061 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1062 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1063 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1064
1065 cpw16(MultiIntr, 0);
1066
1067 cpw16_f(IntrMask, cp_intr_mask);
1068
1069 cpw8_f(Cfg9346, Cfg9346_Lock);
1070 }
1071
1072 static int cp_refill_rx (struct cp_private *cp)
1073 {
1074 unsigned i;
1075
1076 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1077 struct sk_buff *skb;
1078 dma_addr_t mapping;
1079
1080 skb = dev_alloc_skb(cp->rx_buf_sz + RX_OFFSET);
1081 if (!skb)
1082 goto err_out;
1083
1084 skb->dev = cp->dev;
1085 skb_reserve(skb, RX_OFFSET);
1086
1087 mapping = pci_map_single(cp->pdev, skb->data, cp->rx_buf_sz,
1088 PCI_DMA_FROMDEVICE);
1089 cp->rx_skb[i] = skb;
1090
1091 cp->rx_ring[i].opts2 = 0;
1092 cp->rx_ring[i].addr = cpu_to_le64(mapping);
1093 if (i == (CP_RX_RING_SIZE - 1))
1094 cp->rx_ring[i].opts1 =
1095 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1096 else
1097 cp->rx_ring[i].opts1 =
1098 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1099 }
1100
1101 return 0;
1102
1103 err_out:
1104 cp_clean_rings(cp);
1105 return -ENOMEM;
1106 }
1107
1108 static void cp_init_rings_index (struct cp_private *cp)
1109 {
1110 cp->rx_tail = 0;
1111 cp->tx_head = cp->tx_tail = 0;
1112 }
1113
1114 static int cp_init_rings (struct cp_private *cp)
1115 {
1116 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1117 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1118
1119 cp_init_rings_index(cp);
1120
1121 return cp_refill_rx (cp);
1122 }
1123
1124 static int cp_alloc_rings (struct cp_private *cp)
1125 {
1126 void *mem;
1127
1128 mem = pci_alloc_consistent(cp->pdev, CP_RING_BYTES, &cp->ring_dma);
1129 if (!mem)
1130 return -ENOMEM;
1131
1132 cp->rx_ring = mem;
1133 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1134
1135 return cp_init_rings(cp);
1136 }
1137
1138 static void cp_clean_rings (struct cp_private *cp)
1139 {
1140 struct cp_desc *desc;
1141 unsigned i;
1142
1143 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1144 if (cp->rx_skb[i]) {
1145 desc = cp->rx_ring + i;
1146 pci_unmap_single(cp->pdev, le64_to_cpu(desc->addr),
1147 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1148 dev_kfree_skb(cp->rx_skb[i]);
1149 }
1150 }
1151
1152 for (i = 0; i < CP_TX_RING_SIZE; i++) {
1153 if (cp->tx_skb[i]) {
1154 struct sk_buff *skb = cp->tx_skb[i];
1155
1156 desc = cp->tx_ring + i;
1157 pci_unmap_single(cp->pdev, le64_to_cpu(desc->addr),
1158 le32_to_cpu(desc->opts1) & 0xffff,
1159 PCI_DMA_TODEVICE);
1160 if (le32_to_cpu(desc->opts1) & LastFrag)
1161 dev_kfree_skb(skb);
1162 cp->net_stats.tx_dropped++;
1163 }
1164 }
1165
1166 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1167 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1168
1169 memset(cp->rx_skb, 0, sizeof(struct sk_buff *) * CP_RX_RING_SIZE);
1170 memset(cp->tx_skb, 0, sizeof(struct sk_buff *) * CP_TX_RING_SIZE);
1171 }
1172
1173 static void cp_free_rings (struct cp_private *cp)
1174 {
1175 cp_clean_rings(cp);
1176 pci_free_consistent(cp->pdev, CP_RING_BYTES, cp->rx_ring, cp->ring_dma);
1177 cp->rx_ring = NULL;
1178 cp->tx_ring = NULL;
1179 }
1180
1181 static int cp_open (struct net_device *dev)
1182 {
1183 struct cp_private *cp = netdev_priv(dev);
1184 int rc;
1185
1186 if (netif_msg_ifup(cp))
1187 printk(KERN_DEBUG "%s: enabling interface\n", dev->name);
1188
1189 rc = cp_alloc_rings(cp);
1190 if (rc)
1191 return rc;
1192
1193 cp_init_hw(cp);
1194
1195 rc = request_irq(dev->irq, cp_interrupt, IRQF_SHARED, dev->name, dev);
1196 if (rc)
1197 goto err_out_hw;
1198
1199 netif_carrier_off(dev);
1200 mii_check_media(&cp->mii_if, netif_msg_link(cp), TRUE);
1201 netif_start_queue(dev);
1202
1203 return 0;
1204
1205 err_out_hw:
1206 cp_stop_hw(cp);
1207 cp_free_rings(cp);
1208 return rc;
1209 }
1210
1211 static int cp_close (struct net_device *dev)
1212 {
1213 struct cp_private *cp = netdev_priv(dev);
1214 unsigned long flags;
1215
1216 if (netif_msg_ifdown(cp))
1217 printk(KERN_DEBUG "%s: disabling interface\n", dev->name);
1218
1219 spin_lock_irqsave(&cp->lock, flags);
1220
1221 netif_stop_queue(dev);
1222 netif_carrier_off(dev);
1223
1224 cp_stop_hw(cp);
1225
1226 spin_unlock_irqrestore(&cp->lock, flags);
1227
1228 synchronize_irq(dev->irq);
1229 free_irq(dev->irq, dev);
1230
1231 cp_free_rings(cp);
1232 return 0;
1233 }
1234
1235 #ifdef BROKEN
1236 static int cp_change_mtu(struct net_device *dev, int new_mtu)
1237 {
1238 struct cp_private *cp = netdev_priv(dev);
1239 int rc;
1240 unsigned long flags;
1241
1242 /* check for invalid MTU, according to hardware limits */
1243 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1244 return -EINVAL;
1245
1246 /* if network interface not up, no need for complexity */
1247 if (!netif_running(dev)) {
1248 dev->mtu = new_mtu;
1249 cp_set_rxbufsize(cp); /* set new rx buf size */
1250 return 0;
1251 }
1252
1253 spin_lock_irqsave(&cp->lock, flags);
1254
1255 cp_stop_hw(cp); /* stop h/w and free rings */
1256 cp_clean_rings(cp);
1257
1258 dev->mtu = new_mtu;
1259 cp_set_rxbufsize(cp); /* set new rx buf size */
1260
1261 rc = cp_init_rings(cp); /* realloc and restart h/w */
1262 cp_start_hw(cp);
1263
1264 spin_unlock_irqrestore(&cp->lock, flags);
1265
1266 return rc;
1267 }
1268 #endif /* BROKEN */
1269
1270 static const char mii_2_8139_map[8] = {
1271 BasicModeCtrl,
1272 BasicModeStatus,
1273 0,
1274 0,
1275 NWayAdvert,
1276 NWayLPAR,
1277 NWayExpansion,
1278 0
1279 };
1280
1281 static int mdio_read(struct net_device *dev, int phy_id, int location)
1282 {
1283 struct cp_private *cp = netdev_priv(dev);
1284
1285 return location < 8 && mii_2_8139_map[location] ?
1286 readw(cp->regs + mii_2_8139_map[location]) : 0;
1287 }
1288
1289
1290 static void mdio_write(struct net_device *dev, int phy_id, int location,
1291 int value)
1292 {
1293 struct cp_private *cp = netdev_priv(dev);
1294
1295 if (location == 0) {
1296 cpw8(Cfg9346, Cfg9346_Unlock);
1297 cpw16(BasicModeCtrl, value);
1298 cpw8(Cfg9346, Cfg9346_Lock);
1299 } else if (location < 8 && mii_2_8139_map[location])
1300 cpw16(mii_2_8139_map[location], value);
1301 }
1302
1303 /* Set the ethtool Wake-on-LAN settings */
1304 static int netdev_set_wol (struct cp_private *cp,
1305 const struct ethtool_wolinfo *wol)
1306 {
1307 u8 options;
1308
1309 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1310 /* If WOL is being disabled, no need for complexity */
1311 if (wol->wolopts) {
1312 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1313 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1314 }
1315
1316 cpw8 (Cfg9346, Cfg9346_Unlock);
1317 cpw8 (Config3, options);
1318 cpw8 (Cfg9346, Cfg9346_Lock);
1319
1320 options = 0; /* Paranoia setting */
1321 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1322 /* If WOL is being disabled, no need for complexity */
1323 if (wol->wolopts) {
1324 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1325 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1326 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1327 }
1328
1329 cpw8 (Config5, options);
1330
1331 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1332
1333 return 0;
1334 }
1335
1336 /* Get the ethtool Wake-on-LAN settings */
1337 static void netdev_get_wol (struct cp_private *cp,
1338 struct ethtool_wolinfo *wol)
1339 {
1340 u8 options;
1341
1342 wol->wolopts = 0; /* Start from scratch */
1343 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1344 WAKE_MCAST | WAKE_UCAST;
1345 /* We don't need to go on if WOL is disabled */
1346 if (!cp->wol_enabled) return;
1347
1348 options = cpr8 (Config3);
1349 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1350 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1351
1352 options = 0; /* Paranoia setting */
1353 options = cpr8 (Config5);
1354 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1355 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1356 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1357 }
1358
1359 static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1360 {
1361 struct cp_private *cp = netdev_priv(dev);
1362
1363 strcpy (info->driver, DRV_NAME);
1364 strcpy (info->version, DRV_VERSION);
1365 strcpy (info->bus_info, pci_name(cp->pdev));
1366 }
1367
1368 static int cp_get_regs_len(struct net_device *dev)
1369 {
1370 return CP_REGS_SIZE;
1371 }
1372
1373 static int cp_get_stats_count (struct net_device *dev)
1374 {
1375 return CP_NUM_STATS;
1376 }
1377
1378 static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1379 {
1380 struct cp_private *cp = netdev_priv(dev);
1381 int rc;
1382 unsigned long flags;
1383
1384 spin_lock_irqsave(&cp->lock, flags);
1385 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1386 spin_unlock_irqrestore(&cp->lock, flags);
1387
1388 return rc;
1389 }
1390
1391 static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1392 {
1393 struct cp_private *cp = netdev_priv(dev);
1394 int rc;
1395 unsigned long flags;
1396
1397 spin_lock_irqsave(&cp->lock, flags);
1398 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1399 spin_unlock_irqrestore(&cp->lock, flags);
1400
1401 return rc;
1402 }
1403
1404 static int cp_nway_reset(struct net_device *dev)
1405 {
1406 struct cp_private *cp = netdev_priv(dev);
1407 return mii_nway_restart(&cp->mii_if);
1408 }
1409
1410 static u32 cp_get_msglevel(struct net_device *dev)
1411 {
1412 struct cp_private *cp = netdev_priv(dev);
1413 return cp->msg_enable;
1414 }
1415
1416 static void cp_set_msglevel(struct net_device *dev, u32 value)
1417 {
1418 struct cp_private *cp = netdev_priv(dev);
1419 cp->msg_enable = value;
1420 }
1421
1422 static u32 cp_get_rx_csum(struct net_device *dev)
1423 {
1424 struct cp_private *cp = netdev_priv(dev);
1425 return (cpr16(CpCmd) & RxChkSum) ? 1 : 0;
1426 }
1427
1428 static int cp_set_rx_csum(struct net_device *dev, u32 data)
1429 {
1430 struct cp_private *cp = netdev_priv(dev);
1431 u16 cmd = cp->cpcmd, newcmd;
1432
1433 newcmd = cmd;
1434
1435 if (data)
1436 newcmd |= RxChkSum;
1437 else
1438 newcmd &= ~RxChkSum;
1439
1440 if (newcmd != cmd) {
1441 unsigned long flags;
1442
1443 spin_lock_irqsave(&cp->lock, flags);
1444 cp->cpcmd = newcmd;
1445 cpw16_f(CpCmd, newcmd);
1446 spin_unlock_irqrestore(&cp->lock, flags);
1447 }
1448
1449 return 0;
1450 }
1451
1452 static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1453 void *p)
1454 {
1455 struct cp_private *cp = netdev_priv(dev);
1456 unsigned long flags;
1457
1458 if (regs->len < CP_REGS_SIZE)
1459 return /* -EINVAL */;
1460
1461 regs->version = CP_REGS_VER;
1462
1463 spin_lock_irqsave(&cp->lock, flags);
1464 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1465 spin_unlock_irqrestore(&cp->lock, flags);
1466 }
1467
1468 static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1469 {
1470 struct cp_private *cp = netdev_priv(dev);
1471 unsigned long flags;
1472
1473 spin_lock_irqsave (&cp->lock, flags);
1474 netdev_get_wol (cp, wol);
1475 spin_unlock_irqrestore (&cp->lock, flags);
1476 }
1477
1478 static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1479 {
1480 struct cp_private *cp = netdev_priv(dev);
1481 unsigned long flags;
1482 int rc;
1483
1484 spin_lock_irqsave (&cp->lock, flags);
1485 rc = netdev_set_wol (cp, wol);
1486 spin_unlock_irqrestore (&cp->lock, flags);
1487
1488 return rc;
1489 }
1490
1491 static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1492 {
1493 switch (stringset) {
1494 case ETH_SS_STATS:
1495 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
1496 break;
1497 default:
1498 BUG();
1499 break;
1500 }
1501 }
1502
1503 static void cp_get_ethtool_stats (struct net_device *dev,
1504 struct ethtool_stats *estats, u64 *tmp_stats)
1505 {
1506 struct cp_private *cp = netdev_priv(dev);
1507 struct cp_dma_stats *nic_stats;
1508 dma_addr_t dma;
1509 int i;
1510
1511 nic_stats = pci_alloc_consistent(cp->pdev, sizeof(*nic_stats), &dma);
1512 if (!nic_stats)
1513 return;
1514
1515 /* begin NIC statistics dump */
1516 cpw32(StatsAddr + 4, (u64)dma >> 32);
1517 cpw32(StatsAddr, ((u64)dma & DMA_32BIT_MASK) | DumpStats);
1518 cpr32(StatsAddr);
1519
1520 for (i = 0; i < 1000; i++) {
1521 if ((cpr32(StatsAddr) & DumpStats) == 0)
1522 break;
1523 udelay(10);
1524 }
1525 cpw32(StatsAddr, 0);
1526 cpw32(StatsAddr + 4, 0);
1527 cpr32(StatsAddr);
1528
1529 i = 0;
1530 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok);
1531 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok);
1532 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err);
1533 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err);
1534 tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo);
1535 tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align);
1536 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col);
1537 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol);
1538 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys);
1539 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast);
1540 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast);
1541 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort);
1542 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun);
1543 tmp_stats[i++] = cp->cp_stats.rx_frags;
1544 BUG_ON(i != CP_NUM_STATS);
1545
1546 pci_free_consistent(cp->pdev, sizeof(*nic_stats), nic_stats, dma);
1547 }
1548
1549 static const struct ethtool_ops cp_ethtool_ops = {
1550 .get_drvinfo = cp_get_drvinfo,
1551 .get_regs_len = cp_get_regs_len,
1552 .get_stats_count = cp_get_stats_count,
1553 .get_settings = cp_get_settings,
1554 .set_settings = cp_set_settings,
1555 .nway_reset = cp_nway_reset,
1556 .get_link = ethtool_op_get_link,
1557 .get_msglevel = cp_get_msglevel,
1558 .set_msglevel = cp_set_msglevel,
1559 .get_rx_csum = cp_get_rx_csum,
1560 .set_rx_csum = cp_set_rx_csum,
1561 .get_tx_csum = ethtool_op_get_tx_csum,
1562 .set_tx_csum = ethtool_op_set_tx_csum, /* local! */
1563 .get_sg = ethtool_op_get_sg,
1564 .set_sg = ethtool_op_set_sg,
1565 .get_tso = ethtool_op_get_tso,
1566 .set_tso = ethtool_op_set_tso,
1567 .get_regs = cp_get_regs,
1568 .get_wol = cp_get_wol,
1569 .set_wol = cp_set_wol,
1570 .get_strings = cp_get_strings,
1571 .get_ethtool_stats = cp_get_ethtool_stats,
1572 .get_perm_addr = ethtool_op_get_perm_addr,
1573 .get_eeprom_len = cp_get_eeprom_len,
1574 .get_eeprom = cp_get_eeprom,
1575 .set_eeprom = cp_set_eeprom,
1576 };
1577
1578 static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1579 {
1580 struct cp_private *cp = netdev_priv(dev);
1581 int rc;
1582 unsigned long flags;
1583
1584 if (!netif_running(dev))
1585 return -EINVAL;
1586
1587 spin_lock_irqsave(&cp->lock, flags);
1588 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1589 spin_unlock_irqrestore(&cp->lock, flags);
1590 return rc;
1591 }
1592
1593 /* Serial EEPROM section. */
1594
1595 /* EEPROM_Ctrl bits. */
1596 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1597 #define EE_CS 0x08 /* EEPROM chip select. */
1598 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1599 #define EE_WRITE_0 0x00
1600 #define EE_WRITE_1 0x02
1601 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1602 #define EE_ENB (0x80 | EE_CS)
1603
1604 /* Delay between EEPROM clock transitions.
1605 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1606 */
1607
1608 #define eeprom_delay() readl(ee_addr)
1609
1610 /* The EEPROM commands include the alway-set leading bit. */
1611 #define EE_EXTEND_CMD (4)
1612 #define EE_WRITE_CMD (5)
1613 #define EE_READ_CMD (6)
1614 #define EE_ERASE_CMD (7)
1615
1616 #define EE_EWDS_ADDR (0)
1617 #define EE_WRAL_ADDR (1)
1618 #define EE_ERAL_ADDR (2)
1619 #define EE_EWEN_ADDR (3)
1620
1621 #define CP_EEPROM_MAGIC PCI_DEVICE_ID_REALTEK_8139
1622
1623 static void eeprom_cmd_start(void __iomem *ee_addr)
1624 {
1625 writeb (EE_ENB & ~EE_CS, ee_addr);
1626 writeb (EE_ENB, ee_addr);
1627 eeprom_delay ();
1628 }
1629
1630 static void eeprom_cmd(void __iomem *ee_addr, int cmd, int cmd_len)
1631 {
1632 int i;
1633
1634 /* Shift the command bits out. */
1635 for (i = cmd_len - 1; i >= 0; i--) {
1636 int dataval = (cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1637 writeb (EE_ENB | dataval, ee_addr);
1638 eeprom_delay ();
1639 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1640 eeprom_delay ();
1641 }
1642 writeb (EE_ENB, ee_addr);
1643 eeprom_delay ();
1644 }
1645
1646 static void eeprom_cmd_end(void __iomem *ee_addr)
1647 {
1648 writeb (~EE_CS, ee_addr);
1649 eeprom_delay ();
1650 }
1651
1652 static void eeprom_extend_cmd(void __iomem *ee_addr, int extend_cmd,
1653 int addr_len)
1654 {
1655 int cmd = (EE_EXTEND_CMD << addr_len) | (extend_cmd << (addr_len - 2));
1656
1657 eeprom_cmd_start(ee_addr);
1658 eeprom_cmd(ee_addr, cmd, 3 + addr_len);
1659 eeprom_cmd_end(ee_addr);
1660 }
1661
1662 static u16 read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1663 {
1664 int i;
1665 u16 retval = 0;
1666 void __iomem *ee_addr = ioaddr + Cfg9346;
1667 int read_cmd = location | (EE_READ_CMD << addr_len);
1668
1669 eeprom_cmd_start(ee_addr);
1670 eeprom_cmd(ee_addr, read_cmd, 3 + addr_len);
1671
1672 for (i = 16; i > 0; i--) {
1673 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1674 eeprom_delay ();
1675 retval =
1676 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1677 0);
1678 writeb (EE_ENB, ee_addr);
1679 eeprom_delay ();
1680 }
1681
1682 eeprom_cmd_end(ee_addr);
1683
1684 return retval;
1685 }
1686
1687 static void write_eeprom(void __iomem *ioaddr, int location, u16 val,
1688 int addr_len)
1689 {
1690 int i;
1691 void __iomem *ee_addr = ioaddr + Cfg9346;
1692 int write_cmd = location | (EE_WRITE_CMD << addr_len);
1693
1694 eeprom_extend_cmd(ee_addr, EE_EWEN_ADDR, addr_len);
1695
1696 eeprom_cmd_start(ee_addr);
1697 eeprom_cmd(ee_addr, write_cmd, 3 + addr_len);
1698 eeprom_cmd(ee_addr, val, 16);
1699 eeprom_cmd_end(ee_addr);
1700
1701 eeprom_cmd_start(ee_addr);
1702 for (i = 0; i < 20000; i++)
1703 if (readb(ee_addr) & EE_DATA_READ)
1704 break;
1705 eeprom_cmd_end(ee_addr);
1706
1707 eeprom_extend_cmd(ee_addr, EE_EWDS_ADDR, addr_len);
1708 }
1709
1710 static int cp_get_eeprom_len(struct net_device *dev)
1711 {
1712 struct cp_private *cp = netdev_priv(dev);
1713 int size;
1714
1715 spin_lock_irq(&cp->lock);
1716 size = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 256 : 128;
1717 spin_unlock_irq(&cp->lock);
1718
1719 return size;
1720 }
1721
1722 static int cp_get_eeprom(struct net_device *dev,
1723 struct ethtool_eeprom *eeprom, u8 *data)
1724 {
1725 struct cp_private *cp = netdev_priv(dev);
1726 unsigned int addr_len;
1727 u16 val;
1728 u32 offset = eeprom->offset >> 1;
1729 u32 len = eeprom->len;
1730 u32 i = 0;
1731
1732 eeprom->magic = CP_EEPROM_MAGIC;
1733
1734 spin_lock_irq(&cp->lock);
1735
1736 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1737
1738 if (eeprom->offset & 1) {
1739 val = read_eeprom(cp->regs, offset, addr_len);
1740 data[i++] = (u8)(val >> 8);
1741 offset++;
1742 }
1743
1744 while (i < len - 1) {
1745 val = read_eeprom(cp->regs, offset, addr_len);
1746 data[i++] = (u8)val;
1747 data[i++] = (u8)(val >> 8);
1748 offset++;
1749 }
1750
1751 if (i < len) {
1752 val = read_eeprom(cp->regs, offset, addr_len);
1753 data[i] = (u8)val;
1754 }
1755
1756 spin_unlock_irq(&cp->lock);
1757 return 0;
1758 }
1759
1760 static int cp_set_eeprom(struct net_device *dev,
1761 struct ethtool_eeprom *eeprom, u8 *data)
1762 {
1763 struct cp_private *cp = netdev_priv(dev);
1764 unsigned int addr_len;
1765 u16 val;
1766 u32 offset = eeprom->offset >> 1;
1767 u32 len = eeprom->len;
1768 u32 i = 0;
1769
1770 if (eeprom->magic != CP_EEPROM_MAGIC)
1771 return -EINVAL;
1772
1773 spin_lock_irq(&cp->lock);
1774
1775 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1776
1777 if (eeprom->offset & 1) {
1778 val = read_eeprom(cp->regs, offset, addr_len) & 0xff;
1779 val |= (u16)data[i++] << 8;
1780 write_eeprom(cp->regs, offset, val, addr_len);
1781 offset++;
1782 }
1783
1784 while (i < len - 1) {
1785 val = (u16)data[i++];
1786 val |= (u16)data[i++] << 8;
1787 write_eeprom(cp->regs, offset, val, addr_len);
1788 offset++;
1789 }
1790
1791 if (i < len) {
1792 val = read_eeprom(cp->regs, offset, addr_len) & 0xff00;
1793 val |= (u16)data[i];
1794 write_eeprom(cp->regs, offset, val, addr_len);
1795 }
1796
1797 spin_unlock_irq(&cp->lock);
1798 return 0;
1799 }
1800
1801 /* Put the board into D3cold state and wait for WakeUp signal */
1802 static void cp_set_d3_state (struct cp_private *cp)
1803 {
1804 pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
1805 pci_set_power_state (cp->pdev, PCI_D3hot);
1806 }
1807
1808 static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1809 {
1810 struct net_device *dev;
1811 struct cp_private *cp;
1812 int rc;
1813 void __iomem *regs;
1814 resource_size_t pciaddr;
1815 unsigned int addr_len, i, pci_using_dac;
1816 u8 pci_rev;
1817
1818 #ifndef MODULE
1819 static int version_printed;
1820 if (version_printed++ == 0)
1821 printk("%s", version);
1822 #endif
1823
1824 pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
1825
1826 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
1827 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev < 0x20) {
1828 dev_err(&pdev->dev,
1829 "This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip\n",
1830 pdev->vendor, pdev->device, pci_rev);
1831 dev_err(&pdev->dev, "Try the \"8139too\" driver instead.\n");
1832 return -ENODEV;
1833 }
1834
1835 dev = alloc_etherdev(sizeof(struct cp_private));
1836 if (!dev)
1837 return -ENOMEM;
1838 SET_MODULE_OWNER(dev);
1839 SET_NETDEV_DEV(dev, &pdev->dev);
1840
1841 cp = netdev_priv(dev);
1842 cp->pdev = pdev;
1843 cp->dev = dev;
1844 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1845 spin_lock_init (&cp->lock);
1846 cp->mii_if.dev = dev;
1847 cp->mii_if.mdio_read = mdio_read;
1848 cp->mii_if.mdio_write = mdio_write;
1849 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1850 cp->mii_if.phy_id_mask = 0x1f;
1851 cp->mii_if.reg_num_mask = 0x1f;
1852 cp_set_rxbufsize(cp);
1853
1854 rc = pci_enable_device(pdev);
1855 if (rc)
1856 goto err_out_free;
1857
1858 rc = pci_set_mwi(pdev);
1859 if (rc)
1860 goto err_out_disable;
1861
1862 rc = pci_request_regions(pdev, DRV_NAME);
1863 if (rc)
1864 goto err_out_mwi;
1865
1866 pciaddr = pci_resource_start(pdev, 1);
1867 if (!pciaddr) {
1868 rc = -EIO;
1869 dev_err(&pdev->dev, "no MMIO resource\n");
1870 goto err_out_res;
1871 }
1872 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1873 rc = -EIO;
1874 dev_err(&pdev->dev, "MMIO resource (%llx) too small\n",
1875 (unsigned long long)pci_resource_len(pdev, 1));
1876 goto err_out_res;
1877 }
1878
1879 /* Configure DMA attributes. */
1880 if ((sizeof(dma_addr_t) > 4) &&
1881 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) &&
1882 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1883 pci_using_dac = 1;
1884 } else {
1885 pci_using_dac = 0;
1886
1887 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1888 if (rc) {
1889 dev_err(&pdev->dev,
1890 "No usable DMA configuration, aborting.\n");
1891 goto err_out_res;
1892 }
1893 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1894 if (rc) {
1895 dev_err(&pdev->dev,
1896 "No usable consistent DMA configuration, "
1897 "aborting.\n");
1898 goto err_out_res;
1899 }
1900 }
1901
1902 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1903 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1904
1905 regs = ioremap(pciaddr, CP_REGS_SIZE);
1906 if (!regs) {
1907 rc = -EIO;
1908 dev_err(&pdev->dev, "Cannot map PCI MMIO (%Lx@%Lx)\n",
1909 (unsigned long long)pci_resource_len(pdev, 1),
1910 (unsigned long long)pciaddr);
1911 goto err_out_res;
1912 }
1913 dev->base_addr = (unsigned long) regs;
1914 cp->regs = regs;
1915
1916 cp_stop_hw(cp);
1917
1918 /* read MAC address from EEPROM */
1919 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1920 for (i = 0; i < 3; i++)
1921 ((u16 *) (dev->dev_addr))[i] =
1922 le16_to_cpu (read_eeprom (regs, i + 7, addr_len));
1923 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1924
1925 dev->open = cp_open;
1926 dev->stop = cp_close;
1927 dev->set_multicast_list = cp_set_rx_mode;
1928 dev->hard_start_xmit = cp_start_xmit;
1929 dev->get_stats = cp_get_stats;
1930 dev->do_ioctl = cp_ioctl;
1931 dev->poll = cp_rx_poll;
1932 #ifdef CONFIG_NET_POLL_CONTROLLER
1933 dev->poll_controller = cp_poll_controller;
1934 #endif
1935 dev->weight = 16; /* arbitrary? from NAPI_HOWTO.txt. */
1936 #ifdef BROKEN
1937 dev->change_mtu = cp_change_mtu;
1938 #endif
1939 dev->ethtool_ops = &cp_ethtool_ops;
1940 #if 0
1941 dev->tx_timeout = cp_tx_timeout;
1942 dev->watchdog_timeo = TX_TIMEOUT;
1943 #endif
1944
1945 #if CP_VLAN_TAG_USED
1946 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1947 dev->vlan_rx_register = cp_vlan_rx_register;
1948 dev->vlan_rx_kill_vid = cp_vlan_rx_kill_vid;
1949 #endif
1950
1951 if (pci_using_dac)
1952 dev->features |= NETIF_F_HIGHDMA;
1953
1954 #if 0 /* disabled by default until verified */
1955 dev->features |= NETIF_F_TSO;
1956 #endif
1957
1958 dev->irq = pdev->irq;
1959
1960 rc = register_netdev(dev);
1961 if (rc)
1962 goto err_out_iomap;
1963
1964 printk (KERN_INFO "%s: RTL-8139C+ at 0x%lx, "
1965 "%02x:%02x:%02x:%02x:%02x:%02x, "
1966 "IRQ %d\n",
1967 dev->name,
1968 dev->base_addr,
1969 dev->dev_addr[0], dev->dev_addr[1],
1970 dev->dev_addr[2], dev->dev_addr[3],
1971 dev->dev_addr[4], dev->dev_addr[5],
1972 dev->irq);
1973
1974 pci_set_drvdata(pdev, dev);
1975
1976 /* enable busmastering and memory-write-invalidate */
1977 pci_set_master(pdev);
1978
1979 if (cp->wol_enabled)
1980 cp_set_d3_state (cp);
1981
1982 return 0;
1983
1984 err_out_iomap:
1985 iounmap(regs);
1986 err_out_res:
1987 pci_release_regions(pdev);
1988 err_out_mwi:
1989 pci_clear_mwi(pdev);
1990 err_out_disable:
1991 pci_disable_device(pdev);
1992 err_out_free:
1993 free_netdev(dev);
1994 return rc;
1995 }
1996
1997 static void cp_remove_one (struct pci_dev *pdev)
1998 {
1999 struct net_device *dev = pci_get_drvdata(pdev);
2000 struct cp_private *cp = netdev_priv(dev);
2001
2002 unregister_netdev(dev);
2003 iounmap(cp->regs);
2004 if (cp->wol_enabled)
2005 pci_set_power_state (pdev, PCI_D0);
2006 pci_release_regions(pdev);
2007 pci_clear_mwi(pdev);
2008 pci_disable_device(pdev);
2009 pci_set_drvdata(pdev, NULL);
2010 free_netdev(dev);
2011 }
2012
2013 #ifdef CONFIG_PM
2014 static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
2015 {
2016 struct net_device *dev = pci_get_drvdata(pdev);
2017 struct cp_private *cp = netdev_priv(dev);
2018 unsigned long flags;
2019
2020 if (!netif_running(dev))
2021 return 0;
2022
2023 netif_device_detach (dev);
2024 netif_stop_queue (dev);
2025
2026 spin_lock_irqsave (&cp->lock, flags);
2027
2028 /* Disable Rx and Tx */
2029 cpw16 (IntrMask, 0);
2030 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
2031
2032 spin_unlock_irqrestore (&cp->lock, flags);
2033
2034 pci_save_state(pdev);
2035 pci_enable_wake(pdev, pci_choose_state(pdev, state), cp->wol_enabled);
2036 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2037
2038 return 0;
2039 }
2040
2041 static int cp_resume (struct pci_dev *pdev)
2042 {
2043 struct net_device *dev = pci_get_drvdata (pdev);
2044 struct cp_private *cp = netdev_priv(dev);
2045 unsigned long flags;
2046
2047 if (!netif_running(dev))
2048 return 0;
2049
2050 netif_device_attach (dev);
2051
2052 pci_set_power_state(pdev, PCI_D0);
2053 pci_restore_state(pdev);
2054 pci_enable_wake(pdev, PCI_D0, 0);
2055
2056 /* FIXME: sh*t may happen if the Rx ring buffer is depleted */
2057 cp_init_rings_index (cp);
2058 cp_init_hw (cp);
2059 netif_start_queue (dev);
2060
2061 spin_lock_irqsave (&cp->lock, flags);
2062
2063 mii_check_media(&cp->mii_if, netif_msg_link(cp), FALSE);
2064
2065 spin_unlock_irqrestore (&cp->lock, flags);
2066
2067 return 0;
2068 }
2069 #endif /* CONFIG_PM */
2070
2071 static struct pci_driver cp_driver = {
2072 .name = DRV_NAME,
2073 .id_table = cp_pci_tbl,
2074 .probe = cp_init_one,
2075 .remove = cp_remove_one,
2076 #ifdef CONFIG_PM
2077 .resume = cp_resume,
2078 .suspend = cp_suspend,
2079 #endif
2080 };
2081
2082 static int __init cp_init (void)
2083 {
2084 #ifdef MODULE
2085 printk("%s", version);
2086 #endif
2087 return pci_register_driver(&cp_driver);
2088 }
2089
2090 static void __exit cp_exit (void)
2091 {
2092 pci_unregister_driver (&cp_driver);
2093 }
2094
2095 module_init(cp_init);
2096 module_exit(cp_exit);
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