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rt2x00: Move beacon and atim queue defines into rt2x00
[linux-2.6/verdex.git] / drivers / net / wireless / rt2x00 / rt61pci.c
blob59e87a1d96a43e9844f79d452bea4353dd7b6674
1 /*
2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 Module: rt61pci
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
25 */
26
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
34
35 #include "rt2x00.h"
36 #include "rt2x00pci.h"
37 #include "rt61pci.h"
38
39 /*
40 * Register access.
41 * BBP and RF register require indirect register access,
42 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
43 * These indirect registers work with busy bits,
44 * and we will try maximal REGISTER_BUSY_COUNT times to access
45 * the register while taking a REGISTER_BUSY_DELAY us delay
46 * between each attampt. When the busy bit is still set at that time,
47 * the access attempt is considered to have failed,
48 * and we will print an error.
49 */
50 static u32 rt61pci_bbp_check(struct rt2x00_dev *rt2x00dev)
51 {
52 u32 reg;
53 unsigned int i;
54
55 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
56 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, &reg);
57 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
58 break;
59 udelay(REGISTER_BUSY_DELAY);
60 }
61
62 return reg;
63 }
64
65 static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
66 const unsigned int word, const u8 value)
67 {
68 u32 reg;
69
70 /*
71 * Wait until the BBP becomes ready.
72 */
73 reg = rt61pci_bbp_check(rt2x00dev);
74 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
75 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
76 return;
77 }
78
79 /*
80 * Write the data into the BBP.
81 */
82 reg = 0;
83 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
84 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
85 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
86 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
87
88 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
89 }
90
91 static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
92 const unsigned int word, u8 *value)
93 {
94 u32 reg;
95
96 /*
97 * Wait until the BBP becomes ready.
98 */
99 reg = rt61pci_bbp_check(rt2x00dev);
100 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
101 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
102 return;
103 }
104
105 /*
106 * Write the request into the BBP.
107 */
108 reg = 0;
109 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
110 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
111 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
112
113 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
114
115 /*
116 * Wait until the BBP becomes ready.
117 */
118 reg = rt61pci_bbp_check(rt2x00dev);
119 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
120 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
121 *value = 0xff;
122 return;
123 }
124
125 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
126 }
127
128 static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
129 const unsigned int word, const u32 value)
130 {
131 u32 reg;
132 unsigned int i;
133
134 if (!word)
135 return;
136
137 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
138 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, &reg);
139 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
140 goto rf_write;
141 udelay(REGISTER_BUSY_DELAY);
142 }
143
144 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
145 return;
146
147 rf_write:
148 reg = 0;
149 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
150 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
151 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
152 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
153
154 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
155 rt2x00_rf_write(rt2x00dev, word, value);
156 }
157
158 static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
159 const u8 command, const u8 token,
160 const u8 arg0, const u8 arg1)
161 {
162 u32 reg;
163
164 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, &reg);
165
166 if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
167 ERROR(rt2x00dev, "mcu request error. "
168 "Request 0x%02x failed for token 0x%02x.\n",
169 command, token);
170 return;
171 }
172
173 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
174 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
175 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
176 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
177 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
178
179 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
180 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
181 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
182 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
183 }
184
185 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
186 {
187 struct rt2x00_dev *rt2x00dev = eeprom->data;
188 u32 reg;
189
190 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
191
192 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
193 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
194 eeprom->reg_data_clock =
195 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
196 eeprom->reg_chip_select =
197 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
198 }
199
200 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
201 {
202 struct rt2x00_dev *rt2x00dev = eeprom->data;
203 u32 reg = 0;
204
205 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
206 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
207 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
208 !!eeprom->reg_data_clock);
209 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
210 !!eeprom->reg_chip_select);
211
212 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
213 }
214
215 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
216 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
217
218 static void rt61pci_read_csr(struct rt2x00_dev *rt2x00dev,
219 const unsigned int word, u32 *data)
220 {
221 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
222 }
223
224 static void rt61pci_write_csr(struct rt2x00_dev *rt2x00dev,
225 const unsigned int word, u32 data)
226 {
227 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
228 }
229
230 static const struct rt2x00debug rt61pci_rt2x00debug = {
231 .owner = THIS_MODULE,
232 .csr = {
233 .read = rt61pci_read_csr,
234 .write = rt61pci_write_csr,
235 .word_size = sizeof(u32),
236 .word_count = CSR_REG_SIZE / sizeof(u32),
237 },
238 .eeprom = {
239 .read = rt2x00_eeprom_read,
240 .write = rt2x00_eeprom_write,
241 .word_size = sizeof(u16),
242 .word_count = EEPROM_SIZE / sizeof(u16),
243 },
244 .bbp = {
245 .read = rt61pci_bbp_read,
246 .write = rt61pci_bbp_write,
247 .word_size = sizeof(u8),
248 .word_count = BBP_SIZE / sizeof(u8),
249 },
250 .rf = {
251 .read = rt2x00_rf_read,
252 .write = rt61pci_rf_write,
253 .word_size = sizeof(u32),
254 .word_count = RF_SIZE / sizeof(u32),
255 },
256 };
257 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
258
259 #ifdef CONFIG_RT61PCI_RFKILL
260 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
261 {
262 u32 reg;
263
264 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
265 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
266 }
267 #else
268 #define rt61pci_rfkill_poll NULL
269 #endif /* CONFIG_RT61PCI_RFKILL */
270
271 /*
272 * Configuration handlers.
273 */
274 static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
275 struct rt2x00_intf *intf,
276 struct rt2x00intf_conf *conf,
277 const unsigned int flags)
278 {
279 unsigned int beacon_base;
280 u32 reg;
281
282 if (flags & CONFIG_UPDATE_TYPE) {
283 /*
284 * Clear current synchronisation setup.
285 * For the Beacon base registers we only need to clear
286 * the first byte since that byte contains the VALID and OWNER
287 * bits which (when set to 0) will invalidate the entire beacon.
288 */
289 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
290 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
291 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
292
293 /*
294 * Enable synchronisation.
295 */
296 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
297 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
298 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE,
299 (conf->sync == TSF_SYNC_BEACON));
300 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
301 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
302 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
303 }
304
305 if (flags & CONFIG_UPDATE_MAC) {
306 reg = le32_to_cpu(conf->mac[1]);
307 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
308 conf->mac[1] = cpu_to_le32(reg);
309
310 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
311 conf->mac, sizeof(conf->mac));
312 }
313
314 if (flags & CONFIG_UPDATE_BSSID) {
315 reg = le32_to_cpu(conf->bssid[1]);
316 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
317 conf->bssid[1] = cpu_to_le32(reg);
318
319 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
320 conf->bssid, sizeof(conf->bssid));
321 }
322 }
323
324 static int rt61pci_config_preamble(struct rt2x00_dev *rt2x00dev,
325 const int short_preamble,
326 const int ack_timeout,
327 const int ack_consume_time)
328 {
329 u32 reg;
330
331 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
332 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, ack_timeout);
333 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
334
335 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
336 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
337 !!short_preamble);
338 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
339
340 return 0;
341 }
342
343 static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
344 const int basic_rate_mask)
345 {
346 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
347 }
348
349 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
350 struct rf_channel *rf, const int txpower)
351 {
352 u8 r3;
353 u8 r94;
354 u8 smart;
355
356 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
357 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
358
359 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
360 rt2x00_rf(&rt2x00dev->chip, RF2527));
361
362 rt61pci_bbp_read(rt2x00dev, 3, &r3);
363 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
364 rt61pci_bbp_write(rt2x00dev, 3, r3);
365
366 r94 = 6;
367 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
368 r94 += txpower - MAX_TXPOWER;
369 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
370 r94 += txpower;
371 rt61pci_bbp_write(rt2x00dev, 94, r94);
372
373 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
374 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
375 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
376 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
377
378 udelay(200);
379
380 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
381 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
382 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
383 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
384
385 udelay(200);
386
387 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
388 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
389 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
390 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
391
392 msleep(1);
393 }
394
395 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
396 const int txpower)
397 {
398 struct rf_channel rf;
399
400 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
401 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
402 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
403 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
404
405 rt61pci_config_channel(rt2x00dev, &rf, txpower);
406 }
407
408 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
409 struct antenna_setup *ant)
410 {
411 u8 r3;
412 u8 r4;
413 u8 r77;
414
415 rt61pci_bbp_read(rt2x00dev, 3, &r3);
416 rt61pci_bbp_read(rt2x00dev, 4, &r4);
417 rt61pci_bbp_read(rt2x00dev, 77, &r77);
418
419 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
420 rt2x00_rf(&rt2x00dev->chip, RF5325));
421
422 /*
423 * Configure the RX antenna.
424 */
425 switch (ant->rx) {
426 case ANTENNA_HW_DIVERSITY:
427 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
428 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
429 (rt2x00dev->curr_hwmode != HWMODE_A));
430 break;
431 case ANTENNA_A:
432 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
433 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
434 if (rt2x00dev->curr_hwmode == HWMODE_A)
435 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
436 else
437 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
438 break;
439 case ANTENNA_SW_DIVERSITY:
440 /*
441 * NOTE: We should never come here because rt2x00lib is
442 * supposed to catch this and send us the correct antenna
443 * explicitely. However we are nog going to bug about this.
444 * Instead, just default to antenna B.
445 */
446 case ANTENNA_B:
447 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
448 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
449 if (rt2x00dev->curr_hwmode == HWMODE_A)
450 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
451 else
452 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
453 break;
454 }
455
456 rt61pci_bbp_write(rt2x00dev, 77, r77);
457 rt61pci_bbp_write(rt2x00dev, 3, r3);
458 rt61pci_bbp_write(rt2x00dev, 4, r4);
459 }
460
461 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
462 struct antenna_setup *ant)
463 {
464 u8 r3;
465 u8 r4;
466 u8 r77;
467
468 rt61pci_bbp_read(rt2x00dev, 3, &r3);
469 rt61pci_bbp_read(rt2x00dev, 4, &r4);
470 rt61pci_bbp_read(rt2x00dev, 77, &r77);
471
472 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
473 rt2x00_rf(&rt2x00dev->chip, RF2529));
474 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
475 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
476
477 /*
478 * Configure the RX antenna.
479 */
480 switch (ant->rx) {
481 case ANTENNA_HW_DIVERSITY:
482 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
483 break;
484 case ANTENNA_A:
485 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
486 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
487 break;
488 case ANTENNA_SW_DIVERSITY:
489 /*
490 * NOTE: We should never come here because rt2x00lib is
491 * supposed to catch this and send us the correct antenna
492 * explicitely. However we are nog going to bug about this.
493 * Instead, just default to antenna B.
494 */
495 case ANTENNA_B:
496 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
497 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
498 break;
499 }
500
501 rt61pci_bbp_write(rt2x00dev, 77, r77);
502 rt61pci_bbp_write(rt2x00dev, 3, r3);
503 rt61pci_bbp_write(rt2x00dev, 4, r4);
504 }
505
506 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
507 const int p1, const int p2)
508 {
509 u32 reg;
510
511 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
512
513 rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
514 rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
515
516 rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
517 rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
518
519 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
520 }
521
522 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
523 struct antenna_setup *ant)
524 {
525 u8 r3;
526 u8 r4;
527 u8 r77;
528
529 rt61pci_bbp_read(rt2x00dev, 3, &r3);
530 rt61pci_bbp_read(rt2x00dev, 4, &r4);
531 rt61pci_bbp_read(rt2x00dev, 77, &r77);
532
533 /* FIXME: Antenna selection for the rf 2529 is very confusing in the
534 * legacy driver. The code below should be ok for non-diversity setups.
535 */
536
537 /*
538 * Configure the RX antenna.
539 */
540 switch (ant->rx) {
541 case ANTENNA_A:
542 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
543 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
544 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
545 break;
546 case ANTENNA_SW_DIVERSITY:
547 case ANTENNA_HW_DIVERSITY:
548 /*
549 * NOTE: We should never come here because rt2x00lib is
550 * supposed to catch this and send us the correct antenna
551 * explicitely. However we are nog going to bug about this.
552 * Instead, just default to antenna B.
553 */
554 case ANTENNA_B:
555 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
556 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
557 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
558 break;
559 }
560
561 rt61pci_bbp_write(rt2x00dev, 77, r77);
562 rt61pci_bbp_write(rt2x00dev, 3, r3);
563 rt61pci_bbp_write(rt2x00dev, 4, r4);
564 }
565
566 struct antenna_sel {
567 u8 word;
568 /*
569 * value[0] -> non-LNA
570 * value[1] -> LNA
571 */
572 u8 value[2];
573 };
574
575 static const struct antenna_sel antenna_sel_a[] = {
576 { 96, { 0x58, 0x78 } },
577 { 104, { 0x38, 0x48 } },
578 { 75, { 0xfe, 0x80 } },
579 { 86, { 0xfe, 0x80 } },
580 { 88, { 0xfe, 0x80 } },
581 { 35, { 0x60, 0x60 } },
582 { 97, { 0x58, 0x58 } },
583 { 98, { 0x58, 0x58 } },
584 };
585
586 static const struct antenna_sel antenna_sel_bg[] = {
587 { 96, { 0x48, 0x68 } },
588 { 104, { 0x2c, 0x3c } },
589 { 75, { 0xfe, 0x80 } },
590 { 86, { 0xfe, 0x80 } },
591 { 88, { 0xfe, 0x80 } },
592 { 35, { 0x50, 0x50 } },
593 { 97, { 0x48, 0x48 } },
594 { 98, { 0x48, 0x48 } },
595 };
596
597 static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
598 struct antenna_setup *ant)
599 {
600 const struct antenna_sel *sel;
601 unsigned int lna;
602 unsigned int i;
603 u32 reg;
604
605 if (rt2x00dev->curr_hwmode == HWMODE_A) {
606 sel = antenna_sel_a;
607 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
608 } else {
609 sel = antenna_sel_bg;
610 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
611 }
612
613 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
614 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
615
616 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
617
618 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
619 (rt2x00dev->curr_hwmode == HWMODE_B ||
620 rt2x00dev->curr_hwmode == HWMODE_G));
621 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
622 (rt2x00dev->curr_hwmode == HWMODE_A));
623
624 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
625
626 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
627 rt2x00_rf(&rt2x00dev->chip, RF5325))
628 rt61pci_config_antenna_5x(rt2x00dev, ant);
629 else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
630 rt61pci_config_antenna_2x(rt2x00dev, ant);
631 else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
632 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
633 rt61pci_config_antenna_2x(rt2x00dev, ant);
634 else
635 rt61pci_config_antenna_2529(rt2x00dev, ant);
636 }
637 }
638
639 static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
640 struct rt2x00lib_conf *libconf)
641 {
642 u32 reg;
643
644 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
645 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
646 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
647
648 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
649 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
650 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
651 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
652 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
653
654 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
655 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
656 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
657
658 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
659 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
660 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
661
662 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
663 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
664 libconf->conf->beacon_int * 16);
665 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
666 }
667
668 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
669 struct rt2x00lib_conf *libconf,
670 const unsigned int flags)
671 {
672 if (flags & CONFIG_UPDATE_PHYMODE)
673 rt61pci_config_phymode(rt2x00dev, libconf->basic_rates);
674 if (flags & CONFIG_UPDATE_CHANNEL)
675 rt61pci_config_channel(rt2x00dev, &libconf->rf,
676 libconf->conf->power_level);
677 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
678 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
679 if (flags & CONFIG_UPDATE_ANTENNA)
680 rt61pci_config_antenna(rt2x00dev, &libconf->ant);
681 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
682 rt61pci_config_duration(rt2x00dev, libconf);
683 }
684
685 /*
686 * LED functions.
687 */
688 static void rt61pci_enable_led(struct rt2x00_dev *rt2x00dev)
689 {
690 u32 reg;
691 u8 arg0;
692 u8 arg1;
693
694 rt2x00pci_register_read(rt2x00dev, MAC_CSR14, &reg);
695 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70);
696 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30);
697 rt2x00pci_register_write(rt2x00dev, MAC_CSR14, reg);
698
699 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_RADIO_STATUS, 1);
700 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_A_STATUS,
701 (rt2x00dev->rx_status.phymode == MODE_IEEE80211A));
702 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_BG_STATUS,
703 (rt2x00dev->rx_status.phymode != MODE_IEEE80211A));
704
705 arg0 = rt2x00dev->led_reg & 0xff;
706 arg1 = (rt2x00dev->led_reg >> 8) & 0xff;
707
708 rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
709 }
710
711 static void rt61pci_disable_led(struct rt2x00_dev *rt2x00dev)
712 {
713 u16 led_reg;
714 u8 arg0;
715 u8 arg1;
716
717 led_reg = rt2x00dev->led_reg;
718 rt2x00_set_field16(&led_reg, MCU_LEDCS_RADIO_STATUS, 0);
719 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_BG_STATUS, 0);
720 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_A_STATUS, 0);
721
722 arg0 = led_reg & 0xff;
723 arg1 = (led_reg >> 8) & 0xff;
724
725 rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
726 }
727
728 static void rt61pci_activity_led(struct rt2x00_dev *rt2x00dev, int rssi)
729 {
730 u8 led;
731
732 if (rt2x00dev->led_mode != LED_MODE_SIGNAL_STRENGTH)
733 return;
734
735 /*
736 * Led handling requires a positive value for the rssi,
737 * to do that correctly we need to add the correction.
738 */
739 rssi += rt2x00dev->rssi_offset;
740
741 if (rssi <= 30)
742 led = 0;
743 else if (rssi <= 39)
744 led = 1;
745 else if (rssi <= 49)
746 led = 2;
747 else if (rssi <= 53)
748 led = 3;
749 else if (rssi <= 63)
750 led = 4;
751 else
752 led = 5;
753
754 rt61pci_mcu_request(rt2x00dev, MCU_LED_STRENGTH, 0xff, led, 0);
755 }
756
757 /*
758 * Link tuning
759 */
760 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
761 struct link_qual *qual)
762 {
763 u32 reg;
764
765 /*
766 * Update FCS error count from register.
767 */
768 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
769 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
770
771 /*
772 * Update False CCA count from register.
773 */
774 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
775 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
776 }
777
778 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
779 {
780 rt61pci_bbp_write(rt2x00dev, 17, 0x20);
781 rt2x00dev->link.vgc_level = 0x20;
782 }
783
784 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
785 {
786 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
787 u8 r17;
788 u8 up_bound;
789 u8 low_bound;
790
791 /*
792 * Update Led strength
793 */
794 rt61pci_activity_led(rt2x00dev, rssi);
795
796 rt61pci_bbp_read(rt2x00dev, 17, &r17);
797
798 /*
799 * Determine r17 bounds.
800 */
801 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
802 low_bound = 0x28;
803 up_bound = 0x48;
804 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
805 low_bound += 0x10;
806 up_bound += 0x10;
807 }
808 } else {
809 low_bound = 0x20;
810 up_bound = 0x40;
811 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
812 low_bound += 0x10;
813 up_bound += 0x10;
814 }
815 }
816
817 /*
818 * If we are not associated, we should go straight to the
819 * dynamic CCA tuning.
820 */
821 if (!rt2x00dev->intf_associated)
822 goto dynamic_cca_tune;
823
824 /*
825 * Special big-R17 for very short distance
826 */
827 if (rssi >= -35) {
828 if (r17 != 0x60)
829 rt61pci_bbp_write(rt2x00dev, 17, 0x60);
830 return;
831 }
832
833 /*
834 * Special big-R17 for short distance
835 */
836 if (rssi >= -58) {
837 if (r17 != up_bound)
838 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
839 return;
840 }
841
842 /*
843 * Special big-R17 for middle-short distance
844 */
845 if (rssi >= -66) {
846 low_bound += 0x10;
847 if (r17 != low_bound)
848 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
849 return;
850 }
851
852 /*
853 * Special mid-R17 for middle distance
854 */
855 if (rssi >= -74) {
856 low_bound += 0x08;
857 if (r17 != low_bound)
858 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
859 return;
860 }
861
862 /*
863 * Special case: Change up_bound based on the rssi.
864 * Lower up_bound when rssi is weaker then -74 dBm.
865 */
866 up_bound -= 2 * (-74 - rssi);
867 if (low_bound > up_bound)
868 up_bound = low_bound;
869
870 if (r17 > up_bound) {
871 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
872 return;
873 }
874
875 dynamic_cca_tune:
876
877 /*
878 * r17 does not yet exceed upper limit, continue and base
879 * the r17 tuning on the false CCA count.
880 */
881 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
882 if (++r17 > up_bound)
883 r17 = up_bound;
884 rt61pci_bbp_write(rt2x00dev, 17, r17);
885 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
886 if (--r17 < low_bound)
887 r17 = low_bound;
888 rt61pci_bbp_write(rt2x00dev, 17, r17);
889 }
890 }
891
892 /*
893 * Firmware name function.
894 */
895 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
896 {
897 char *fw_name;
898
899 switch (rt2x00dev->chip.rt) {
900 case RT2561:
901 fw_name = FIRMWARE_RT2561;
902 break;
903 case RT2561s:
904 fw_name = FIRMWARE_RT2561s;
905 break;
906 case RT2661:
907 fw_name = FIRMWARE_RT2661;
908 break;
909 default:
910 fw_name = NULL;
911 break;
912 }
913
914 return fw_name;
915 }
916
917 /*
918 * Initialization functions.
919 */
920 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
921 const size_t len)
922 {
923 int i;
924 u32 reg;
925
926 /*
927 * Wait for stable hardware.
928 */
929 for (i = 0; i < 100; i++) {
930 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
931 if (reg)
932 break;
933 msleep(1);
934 }
935
936 if (!reg) {
937 ERROR(rt2x00dev, "Unstable hardware.\n");
938 return -EBUSY;
939 }
940
941 /*
942 * Prepare MCU and mailbox for firmware loading.
943 */
944 reg = 0;
945 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
946 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
947 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
948 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
949 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
950
951 /*
952 * Write firmware to device.
953 */
954 reg = 0;
955 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
956 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
957 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
958
959 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
960 data, len);
961
962 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
963 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
964
965 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
966 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
967
968 for (i = 0; i < 100; i++) {
969 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
970 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
971 break;
972 msleep(1);
973 }
974
975 if (i == 100) {
976 ERROR(rt2x00dev, "MCU Control register not ready.\n");
977 return -EBUSY;
978 }
979
980 /*
981 * Reset MAC and BBP registers.
982 */
983 reg = 0;
984 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
985 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
986 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
987
988 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
989 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
990 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
991 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
992
993 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
994 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
995 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
996
997 return 0;
998 }
999
1000 static void rt61pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
1001 struct queue_entry *entry)
1002 {
1003 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
1004 u32 word;
1005
1006 rt2x00_desc_read(priv_rx->desc, 5, &word);
1007 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS, priv_rx->dma);
1008 rt2x00_desc_write(priv_rx->desc, 5, word);
1009
1010 rt2x00_desc_read(priv_rx->desc, 0, &word);
1011 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1012 rt2x00_desc_write(priv_rx->desc, 0, word);
1013 }
1014
1015 static void rt61pci_init_txentry(struct rt2x00_dev *rt2x00dev,
1016 struct queue_entry *entry)
1017 {
1018 struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
1019 u32 word;
1020
1021 rt2x00_desc_read(priv_tx->desc, 1, &word);
1022 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1023 rt2x00_desc_write(priv_tx->desc, 1, word);
1024
1025 rt2x00_desc_read(priv_tx->desc, 5, &word);
1026 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid);
1027 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, entry->entry_idx);
1028 rt2x00_desc_write(priv_tx->desc, 5, word);
1029
1030 rt2x00_desc_read(priv_tx->desc, 6, &word);
1031 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS, priv_tx->dma);
1032 rt2x00_desc_write(priv_tx->desc, 6, word);
1033
1034 rt2x00_desc_read(priv_tx->desc, 0, &word);
1035 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1036 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1037 rt2x00_desc_write(priv_tx->desc, 0, word);
1038 }
1039
1040 static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1041 {
1042 struct queue_entry_priv_pci_rx *priv_rx;
1043 struct queue_entry_priv_pci_tx *priv_tx;
1044 u32 reg;
1045
1046 /*
1047 * Initialize registers.
1048 */
1049 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1050 rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
1051 rt2x00dev->tx[0].limit);
1052 rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
1053 rt2x00dev->tx[1].limit);
1054 rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
1055 rt2x00dev->tx[2].limit);
1056 rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
1057 rt2x00dev->tx[3].limit);
1058 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1059
1060 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
1061 rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
1062 rt2x00dev->tx[0].desc_size / 4);
1063 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1064
1065 priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
1066 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1067 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER, priv_tx->dma);
1068 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1069
1070 priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
1071 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1072 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER, priv_tx->dma);
1073 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1074
1075 priv_tx = rt2x00dev->tx[2].entries[0].priv_data;
1076 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1077 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER, priv_tx->dma);
1078 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1079
1080 priv_tx = rt2x00dev->tx[3].entries[0].priv_data;
1081 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1082 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER, priv_tx->dma);
1083 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1084
1085 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
1086 rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
1087 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1088 rt2x00dev->rx->desc_size / 4);
1089 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1090 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1091
1092 priv_rx = rt2x00dev->rx->entries[0].priv_data;
1093 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1094 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER, priv_rx->dma);
1095 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1096
1097 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1098 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1099 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1100 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1101 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
1102 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_MGMT, 0);
1103 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1104
1105 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1106 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1107 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1108 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1109 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1110 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_MGMT, 0);
1111 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1112
1113 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1114 rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1115 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1116
1117 return 0;
1118 }
1119
1120 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1121 {
1122 u32 reg;
1123
1124 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1125 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1126 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1127 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1128 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1129
1130 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1131 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1132 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1133 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1134 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1135 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1136 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1137 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1138 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1139 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1140
1141 /*
1142 * CCK TXD BBP registers
1143 */
1144 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1145 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1146 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1147 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1148 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1149 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1150 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1151 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1152 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1153 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1154
1155 /*
1156 * OFDM TXD BBP registers
1157 */
1158 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1159 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1160 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1161 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1162 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1163 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1164 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1165 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1166
1167 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1168 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1169 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1170 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1171 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1172 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1173
1174 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1175 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1176 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1177 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1178 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1179 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1180
1181 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1182
1183 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1184
1185 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1186 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1187 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1188
1189 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1190
1191 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1192 return -EBUSY;
1193
1194 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1195
1196 /*
1197 * Invalidate all Shared Keys (SEC_CSR0),
1198 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1199 */
1200 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1201 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1202 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1203
1204 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1205 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1206 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1207 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1208
1209 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1210
1211 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1212
1213 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1214
1215 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1216 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1217 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1218 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1219
1220 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1221 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1222 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1223 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1224
1225 /*
1226 * Clear all beacons
1227 * For the Beacon base registers we only need to clear
1228 * the first byte since that byte contains the VALID and OWNER
1229 * bits which (when set to 0) will invalidate the entire beacon.
1230 */
1231 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1232 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1233 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1234 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1235
1236 /*
1237 * We must clear the error counters.
1238 * These registers are cleared on read,
1239 * so we may pass a useless variable to store the value.
1240 */
1241 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1242 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1243 rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1244
1245 /*
1246 * Reset MAC and BBP registers.
1247 */
1248 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1249 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1250 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1251 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1252
1253 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1254 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1255 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1256 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1257
1258 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1259 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1260 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1261
1262 return 0;
1263 }
1264
1265 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1266 {
1267 unsigned int i;
1268 u16 eeprom;
1269 u8 reg_id;
1270 u8 value;
1271
1272 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1273 rt61pci_bbp_read(rt2x00dev, 0, &value);
1274 if ((value != 0xff) && (value != 0x00))
1275 goto continue_csr_init;
1276 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1277 udelay(REGISTER_BUSY_DELAY);
1278 }
1279
1280 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1281 return -EACCES;
1282
1283 continue_csr_init:
1284 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1285 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1286 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1287 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1288 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1289 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1290 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1291 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1292 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1293 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1294 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1295 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1296 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1297 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1298 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1299 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1300 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1301 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1302 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1303 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1304 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1305 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1306 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1307 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1308
1309 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
1310 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1311 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1312
1313 if (eeprom != 0xffff && eeprom != 0x0000) {
1314 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1315 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1316 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
1317 reg_id, value);
1318 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1319 }
1320 }
1321 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
1322
1323 return 0;
1324 }
1325
1326 /*
1327 * Device state switch handlers.
1328 */
1329 static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1330 enum dev_state state)
1331 {
1332 u32 reg;
1333
1334 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1335 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1336 state == STATE_RADIO_RX_OFF);
1337 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1338 }
1339
1340 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1341 enum dev_state state)
1342 {
1343 int mask = (state == STATE_RADIO_IRQ_OFF);
1344 u32 reg;
1345
1346 /*
1347 * When interrupts are being enabled, the interrupt registers
1348 * should clear the register to assure a clean state.
1349 */
1350 if (state == STATE_RADIO_IRQ_ON) {
1351 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1352 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1353
1354 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1355 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1356 }
1357
1358 /*
1359 * Only toggle the interrupts bits we are going to use.
1360 * Non-checked interrupt bits are disabled by default.
1361 */
1362 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1363 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1364 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1365 rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1366 rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1367 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1368
1369 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1370 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1371 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1372 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1373 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1374 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1375 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1376 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1377 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1378 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1379 }
1380
1381 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1382 {
1383 u32 reg;
1384
1385 /*
1386 * Initialize all registers.
1387 */
1388 if (rt61pci_init_queues(rt2x00dev) ||
1389 rt61pci_init_registers(rt2x00dev) ||
1390 rt61pci_init_bbp(rt2x00dev)) {
1391 ERROR(rt2x00dev, "Register initialization failed.\n");
1392 return -EIO;
1393 }
1394
1395 /*
1396 * Enable interrupts.
1397 */
1398 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1399
1400 /*
1401 * Enable RX.
1402 */
1403 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1404 rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1405 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1406
1407 /*
1408 * Enable LED
1409 */
1410 rt61pci_enable_led(rt2x00dev);
1411
1412 return 0;
1413 }
1414
1415 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1416 {
1417 u32 reg;
1418
1419 /*
1420 * Disable LED
1421 */
1422 rt61pci_disable_led(rt2x00dev);
1423
1424 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1425
1426 /*
1427 * Disable synchronisation.
1428 */
1429 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1430
1431 /*
1432 * Cancel RX and TX.
1433 */
1434 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1435 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1436 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1437 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1438 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1439 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1440
1441 /*
1442 * Disable interrupts.
1443 */
1444 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1445 }
1446
1447 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1448 {
1449 u32 reg;
1450 unsigned int i;
1451 char put_to_sleep;
1452 char current_state;
1453
1454 put_to_sleep = (state != STATE_AWAKE);
1455
1456 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1457 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1458 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1459 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1460
1461 /*
1462 * Device is not guaranteed to be in the requested state yet.
1463 * We must wait until the register indicates that the
1464 * device has entered the correct state.
1465 */
1466 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1467 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1468 current_state =
1469 rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1470 if (current_state == !put_to_sleep)
1471 return 0;
1472 msleep(10);
1473 }
1474
1475 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1476 "current device state %d.\n", !put_to_sleep, current_state);
1477
1478 return -EBUSY;
1479 }
1480
1481 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1482 enum dev_state state)
1483 {
1484 int retval = 0;
1485
1486 switch (state) {
1487 case STATE_RADIO_ON:
1488 retval = rt61pci_enable_radio(rt2x00dev);
1489 break;
1490 case STATE_RADIO_OFF:
1491 rt61pci_disable_radio(rt2x00dev);
1492 break;
1493 case STATE_RADIO_RX_ON:
1494 case STATE_RADIO_RX_ON_LINK:
1495 rt61pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1496 break;
1497 case STATE_RADIO_RX_OFF:
1498 case STATE_RADIO_RX_OFF_LINK:
1499 rt61pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
1500 break;
1501 case STATE_DEEP_SLEEP:
1502 case STATE_SLEEP:
1503 case STATE_STANDBY:
1504 case STATE_AWAKE:
1505 retval = rt61pci_set_state(rt2x00dev, state);
1506 break;
1507 default:
1508 retval = -ENOTSUPP;
1509 break;
1510 }
1511
1512 return retval;
1513 }
1514
1515 /*
1516 * TX descriptor initialization
1517 */
1518 static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1519 struct sk_buff *skb,
1520 struct txentry_desc *txdesc,
1521 struct ieee80211_tx_control *control)
1522 {
1523 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1524 __le32 *txd = skbdesc->desc;
1525 u32 word;
1526
1527 /*
1528 * Start writing the descriptor words.
1529 */
1530 rt2x00_desc_read(txd, 1, &word);
1531 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1532 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1533 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1534 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1535 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1536 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1537 rt2x00_desc_write(txd, 1, word);
1538
1539 rt2x00_desc_read(txd, 2, &word);
1540 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1541 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1542 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1543 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1544 rt2x00_desc_write(txd, 2, word);
1545
1546 rt2x00_desc_read(txd, 5, &word);
1547 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1548 TXPOWER_TO_DEV(control->power_level));
1549 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1550 rt2x00_desc_write(txd, 5, word);
1551
1552 if (skbdesc->desc_len > TXINFO_SIZE) {
1553 rt2x00_desc_read(txd, 11, &word);
1554 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skbdesc->data_len);
1555 rt2x00_desc_write(txd, 11, word);
1556 }
1557
1558 rt2x00_desc_read(txd, 0, &word);
1559 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1560 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1561 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1562 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1563 rt2x00_set_field32(&word, TXD_W0_ACK,
1564 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1565 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1566 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1567 rt2x00_set_field32(&word, TXD_W0_OFDM,
1568 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1569 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1570 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1571 !!(control->flags &
1572 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1573 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1574 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
1575 rt2x00_set_field32(&word, TXD_W0_BURST,
1576 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1577 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1578 rt2x00_desc_write(txd, 0, word);
1579 }
1580
1581 /*
1582 * TX data initialization
1583 */
1584 static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1585 const unsigned int queue)
1586 {
1587 u32 reg;
1588
1589 if (queue == RT2X00_BCN_QUEUE_BEACON) {
1590 /*
1591 * For Wi-Fi faily generated beacons between participating
1592 * stations. Set TBTT phase adaptive adjustment step to 8us.
1593 */
1594 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1595
1596 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1597 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1598 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1599 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1600 }
1601 return;
1602 }
1603
1604 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1605 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0,
1606 (queue == IEEE80211_TX_QUEUE_DATA0));
1607 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1,
1608 (queue == IEEE80211_TX_QUEUE_DATA1));
1609 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2,
1610 (queue == IEEE80211_TX_QUEUE_DATA2));
1611 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3,
1612 (queue == IEEE80211_TX_QUEUE_DATA3));
1613 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1614 }
1615
1616 /*
1617 * RX control handlers
1618 */
1619 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1620 {
1621 u16 eeprom;
1622 u8 offset;
1623 u8 lna;
1624
1625 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1626 switch (lna) {
1627 case 3:
1628 offset = 90;
1629 break;
1630 case 2:
1631 offset = 74;
1632 break;
1633 case 1:
1634 offset = 64;
1635 break;
1636 default:
1637 return 0;
1638 }
1639
1640 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
1641 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1642 offset += 14;
1643
1644 if (lna == 3 || lna == 2)
1645 offset += 10;
1646
1647 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1648 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1649 } else {
1650 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1651 offset += 14;
1652
1653 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1654 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1655 }
1656
1657 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1658 }
1659
1660 static void rt61pci_fill_rxdone(struct queue_entry *entry,
1661 struct rxdone_entry_desc *rxdesc)
1662 {
1663 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
1664 u32 word0;
1665 u32 word1;
1666
1667 rt2x00_desc_read(priv_rx->desc, 0, &word0);
1668 rt2x00_desc_read(priv_rx->desc, 1, &word1);
1669
1670 rxdesc->flags = 0;
1671 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1672 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1673
1674 /*
1675 * Obtain the status about this packet.
1676 */
1677 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1678 rxdesc->rssi = rt61pci_agc_to_rssi(entry->queue->rt2x00dev, word1);
1679 rxdesc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1680 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1681 rxdesc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
1682 }
1683
1684 /*
1685 * Interrupt functions.
1686 */
1687 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1688 {
1689 struct data_queue *queue;
1690 struct queue_entry *entry;
1691 struct queue_entry *entry_done;
1692 struct queue_entry_priv_pci_tx *priv_tx;
1693 struct txdone_entry_desc txdesc;
1694 u32 word;
1695 u32 reg;
1696 u32 old_reg;
1697 int type;
1698 int index;
1699
1700 /*
1701 * During each loop we will compare the freshly read
1702 * STA_CSR4 register value with the value read from
1703 * the previous loop. If the 2 values are equal then
1704 * we should stop processing because the chance it
1705 * quite big that the device has been unplugged and
1706 * we risk going into an endless loop.
1707 */
1708 old_reg = 0;
1709
1710 while (1) {
1711 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
1712 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
1713 break;
1714
1715 if (old_reg == reg)
1716 break;
1717 old_reg = reg;
1718
1719 /*
1720 * Skip this entry when it contains an invalid
1721 * queue identication number.
1722 */
1723 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
1724 queue = rt2x00queue_get_queue(rt2x00dev, type);
1725 if (unlikely(!queue))
1726 continue;
1727
1728 /*
1729 * Skip this entry when it contains an invalid
1730 * index number.
1731 */
1732 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
1733 if (unlikely(index >= queue->limit))
1734 continue;
1735
1736 entry = &queue->entries[index];
1737 priv_tx = entry->priv_data;
1738 rt2x00_desc_read(priv_tx->desc, 0, &word);
1739
1740 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1741 !rt2x00_get_field32(word, TXD_W0_VALID))
1742 return;
1743
1744 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1745 while (entry != entry_done) {
1746 /* Catch up.
1747 * Just report any entries we missed as failed.
1748 */
1749 WARNING(rt2x00dev,
1750 "TX status report missed for entry %d\n",
1751 entry_done->entry_idx);
1752
1753 txdesc.status = TX_FAIL_OTHER;
1754 txdesc.retry = 0;
1755
1756 rt2x00pci_txdone(rt2x00dev, entry_done, &txdesc);
1757 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1758 }
1759
1760 /*
1761 * Obtain the status about this packet.
1762 */
1763 txdesc.status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT);
1764 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
1765
1766 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
1767 }
1768 }
1769
1770 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
1771 {
1772 struct rt2x00_dev *rt2x00dev = dev_instance;
1773 u32 reg_mcu;
1774 u32 reg;
1775
1776 /*
1777 * Get the interrupt sources & saved to local variable.
1778 * Write register value back to clear pending interrupts.
1779 */
1780 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
1781 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
1782
1783 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1784 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1785
1786 if (!reg && !reg_mcu)
1787 return IRQ_NONE;
1788
1789 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1790 return IRQ_HANDLED;
1791
1792 /*
1793 * Handle interrupts, walk through all bits
1794 * and run the tasks, the bits are checked in order of
1795 * priority.
1796 */
1797
1798 /*
1799 * 1 - Rx ring done interrupt.
1800 */
1801 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
1802 rt2x00pci_rxdone(rt2x00dev);
1803
1804 /*
1805 * 2 - Tx ring done interrupt.
1806 */
1807 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
1808 rt61pci_txdone(rt2x00dev);
1809
1810 /*
1811 * 3 - Handle MCU command done.
1812 */
1813 if (reg_mcu)
1814 rt2x00pci_register_write(rt2x00dev,
1815 M2H_CMD_DONE_CSR, 0xffffffff);
1816
1817 return IRQ_HANDLED;
1818 }
1819
1820 /*
1821 * Device probe functions.
1822 */
1823 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1824 {
1825 struct eeprom_93cx6 eeprom;
1826 u32 reg;
1827 u16 word;
1828 u8 *mac;
1829 s8 value;
1830
1831 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
1832
1833 eeprom.data = rt2x00dev;
1834 eeprom.register_read = rt61pci_eepromregister_read;
1835 eeprom.register_write = rt61pci_eepromregister_write;
1836 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
1837 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1838 eeprom.reg_data_in = 0;
1839 eeprom.reg_data_out = 0;
1840 eeprom.reg_data_clock = 0;
1841 eeprom.reg_chip_select = 0;
1842
1843 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1844 EEPROM_SIZE / sizeof(u16));
1845
1846 /*
1847 * Start validation of the data that has been read.
1848 */
1849 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1850 if (!is_valid_ether_addr(mac)) {
1851 DECLARE_MAC_BUF(macbuf);
1852
1853 random_ether_addr(mac);
1854 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1855 }
1856
1857 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1858 if (word == 0xffff) {
1859 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1860 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1861 ANTENNA_B);
1862 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1863 ANTENNA_B);
1864 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1865 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1866 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1867 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
1868 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1869 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1870 }
1871
1872 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1873 if (word == 0xffff) {
1874 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
1875 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
1876 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
1877 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1878 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1879 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1880 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1881 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1882 }
1883
1884 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1885 if (word == 0xffff) {
1886 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1887 LED_MODE_DEFAULT);
1888 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1889 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1890 }
1891
1892 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1893 if (word == 0xffff) {
1894 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1895 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1896 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1897 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1898 }
1899
1900 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1901 if (word == 0xffff) {
1902 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1903 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1904 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1905 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1906 } else {
1907 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1908 if (value < -10 || value > 10)
1909 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1910 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1911 if (value < -10 || value > 10)
1912 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1913 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1914 }
1915
1916 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1917 if (word == 0xffff) {
1918 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1919 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1920 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1921 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1922 } else {
1923 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1924 if (value < -10 || value > 10)
1925 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1926 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1927 if (value < -10 || value > 10)
1928 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1929 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1930 }
1931
1932 return 0;
1933 }
1934
1935 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1936 {
1937 u32 reg;
1938 u16 value;
1939 u16 eeprom;
1940 u16 device;
1941
1942 /*
1943 * Read EEPROM word for configuration.
1944 */
1945 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1946
1947 /*
1948 * Identify RF chipset.
1949 * To determine the RT chip we have to read the
1950 * PCI header of the device.
1951 */
1952 pci_read_config_word(rt2x00dev_pci(rt2x00dev),
1953 PCI_CONFIG_HEADER_DEVICE, &device);
1954 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1955 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1956 rt2x00_set_chip(rt2x00dev, device, value, reg);
1957
1958 if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1959 !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
1960 !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
1961 !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
1962 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1963 return -ENODEV;
1964 }
1965
1966 /*
1967 * Determine number of antenna's.
1968 */
1969 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
1970 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
1971
1972 /*
1973 * Identify default antenna configuration.
1974 */
1975 rt2x00dev->default_ant.tx =
1976 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1977 rt2x00dev->default_ant.rx =
1978 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1979
1980 /*
1981 * Read the Frame type.
1982 */
1983 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1984 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1985
1986 /*
1987 * Detect if this device has an hardware controlled radio.
1988 */
1989 #ifdef CONFIG_RT61PCI_RFKILL
1990 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1991 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1992 #endif /* CONFIG_RT61PCI_RFKILL */
1993
1994 /*
1995 * Read frequency offset and RF programming sequence.
1996 */
1997 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1998 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
1999 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2000
2001 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2002
2003 /*
2004 * Read external LNA informations.
2005 */
2006 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2007
2008 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2009 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2010 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2011 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2012
2013 /*
2014 * When working with a RF2529 chip without double antenna
2015 * the antenna settings should be gathered from the NIC
2016 * eeprom word.
2017 */
2018 if (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
2019 !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
2020 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
2021 case 0:
2022 rt2x00dev->default_ant.tx = ANTENNA_B;
2023 rt2x00dev->default_ant.rx = ANTENNA_A;
2024 break;
2025 case 1:
2026 rt2x00dev->default_ant.tx = ANTENNA_B;
2027 rt2x00dev->default_ant.rx = ANTENNA_B;
2028 break;
2029 case 2:
2030 rt2x00dev->default_ant.tx = ANTENNA_A;
2031 rt2x00dev->default_ant.rx = ANTENNA_A;
2032 break;
2033 case 3:
2034 rt2x00dev->default_ant.tx = ANTENNA_A;
2035 rt2x00dev->default_ant.rx = ANTENNA_B;
2036 break;
2037 }
2038
2039 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2040 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2041 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2042 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2043 }
2044
2045 /*
2046 * Store led settings, for correct led behaviour.
2047 * If the eeprom value is invalid,
2048 * switch to default led mode.
2049 */
2050 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2051
2052 rt2x00dev->led_mode = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2053
2054 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LED_MODE,
2055 rt2x00dev->led_mode);
2056 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_0,
2057 rt2x00_get_field16(eeprom,
2058 EEPROM_LED_POLARITY_GPIO_0));
2059 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_1,
2060 rt2x00_get_field16(eeprom,
2061 EEPROM_LED_POLARITY_GPIO_1));
2062 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_2,
2063 rt2x00_get_field16(eeprom,
2064 EEPROM_LED_POLARITY_GPIO_2));
2065 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_3,
2066 rt2x00_get_field16(eeprom,
2067 EEPROM_LED_POLARITY_GPIO_3));
2068 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_4,
2069 rt2x00_get_field16(eeprom,
2070 EEPROM_LED_POLARITY_GPIO_4));
2071 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_ACT,
2072 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2073 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_BG,
2074 rt2x00_get_field16(eeprom,
2075 EEPROM_LED_POLARITY_RDY_G));
2076 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_A,
2077 rt2x00_get_field16(eeprom,
2078 EEPROM_LED_POLARITY_RDY_A));
2079
2080 return 0;
2081 }
2082
2083 /*
2084 * RF value list for RF5225 & RF5325
2085 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2086 */
2087 static const struct rf_channel rf_vals_noseq[] = {
2088 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2089 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2090 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2091 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2092 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2093 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2094 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2095 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2096 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2097 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2098 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2099 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2100 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2101 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2102
2103 /* 802.11 UNI / HyperLan 2 */
2104 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2105 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2106 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2107 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2108 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2109 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2110 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2111 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2112
2113 /* 802.11 HyperLan 2 */
2114 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2115 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2116 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2117 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2118 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2119 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2120 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2121 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2122 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2123 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2124
2125 /* 802.11 UNII */
2126 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2127 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2128 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2129 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2130 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2131 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2132
2133 /* MMAC(Japan)J52 ch 34,38,42,46 */
2134 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2135 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2136 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2137 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2138 };
2139
2140 /*
2141 * RF value list for RF5225 & RF5325
2142 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2143 */
2144 static const struct rf_channel rf_vals_seq[] = {
2145 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2146 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2147 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2148 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2149 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2150 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2151 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2152 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2153 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2154 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2155 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2156 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2157 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2158 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2159
2160 /* 802.11 UNI / HyperLan 2 */
2161 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2162 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2163 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2164 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2165 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2166 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2167 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2168 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2169
2170 /* 802.11 HyperLan 2 */
2171 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2172 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2173 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2174 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2175 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2176 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2177 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2178 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2179 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2180 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2181
2182 /* 802.11 UNII */
2183 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2184 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2185 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2186 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2187 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2188 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2189
2190 /* MMAC(Japan)J52 ch 34,38,42,46 */
2191 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2192 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2193 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2194 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2195 };
2196
2197 static void rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2198 {
2199 struct hw_mode_spec *spec = &rt2x00dev->spec;
2200 u8 *txpower;
2201 unsigned int i;
2202
2203 /*
2204 * Initialize all hw fields.
2205 */
2206 rt2x00dev->hw->flags =
2207 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
2208 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
2209 rt2x00dev->hw->extra_tx_headroom = 0;
2210 rt2x00dev->hw->max_signal = MAX_SIGNAL;
2211 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
2212 rt2x00dev->hw->queues = 4;
2213
2214 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
2215 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2216 rt2x00_eeprom_addr(rt2x00dev,
2217 EEPROM_MAC_ADDR_0));
2218
2219 /*
2220 * Convert tx_power array in eeprom.
2221 */
2222 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2223 for (i = 0; i < 14; i++)
2224 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2225
2226 /*
2227 * Initialize hw_mode information.
2228 */
2229 spec->num_modes = 2;
2230 spec->num_rates = 12;
2231 spec->tx_power_a = NULL;
2232 spec->tx_power_bg = txpower;
2233 spec->tx_power_default = DEFAULT_TXPOWER;
2234
2235 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2236 spec->num_channels = 14;
2237 spec->channels = rf_vals_noseq;
2238 } else {
2239 spec->num_channels = 14;
2240 spec->channels = rf_vals_seq;
2241 }
2242
2243 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2244 rt2x00_rf(&rt2x00dev->chip, RF5325)) {
2245 spec->num_modes = 3;
2246 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2247
2248 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2249 for (i = 0; i < 14; i++)
2250 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2251
2252 spec->tx_power_a = txpower;
2253 }
2254 }
2255
2256 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2257 {
2258 int retval;
2259
2260 /*
2261 * Allocate eeprom data.
2262 */
2263 retval = rt61pci_validate_eeprom(rt2x00dev);
2264 if (retval)
2265 return retval;
2266
2267 retval = rt61pci_init_eeprom(rt2x00dev);
2268 if (retval)
2269 return retval;
2270
2271 /*
2272 * Initialize hw specifications.
2273 */
2274 rt61pci_probe_hw_mode(rt2x00dev);
2275
2276 /*
2277 * This device requires firmware.
2278 */
2279 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2280 __set_bit(DRIVER_REQUIRE_FIRMWARE_CRC_ITU_T, &rt2x00dev->flags);
2281
2282 /*
2283 * Set the rssi offset.
2284 */
2285 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2286
2287 return 0;
2288 }
2289
2290 /*
2291 * IEEE80211 stack callback functions.
2292 */
2293 static void rt61pci_configure_filter(struct ieee80211_hw *hw,
2294 unsigned int changed_flags,
2295 unsigned int *total_flags,
2296 int mc_count,
2297 struct dev_addr_list *mc_list)
2298 {
2299 struct rt2x00_dev *rt2x00dev = hw->priv;
2300 u32 reg;
2301
2302 /*
2303 * Mask off any flags we are going to ignore from
2304 * the total_flags field.
2305 */
2306 *total_flags &=
2307 FIF_ALLMULTI |
2308 FIF_FCSFAIL |
2309 FIF_PLCPFAIL |
2310 FIF_CONTROL |
2311 FIF_OTHER_BSS |
2312 FIF_PROMISC_IN_BSS;
2313
2314 /*
2315 * Apply some rules to the filters:
2316 * - Some filters imply different filters to be set.
2317 * - Some things we can't filter out at all.
2318 */
2319 if (mc_count)
2320 *total_flags |= FIF_ALLMULTI;
2321 if (*total_flags & FIF_OTHER_BSS ||
2322 *total_flags & FIF_PROMISC_IN_BSS)
2323 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
2324
2325 /*
2326 * Check if there is any work left for us.
2327 */
2328 if (rt2x00dev->packet_filter == *total_flags)
2329 return;
2330 rt2x00dev->packet_filter = *total_flags;
2331
2332 /*
2333 * Start configuration steps.
2334 * Note that the version error will always be dropped
2335 * and broadcast frames will always be accepted since
2336 * there is no filter for it at this time.
2337 */
2338 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
2339 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
2340 !(*total_flags & FIF_FCSFAIL));
2341 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
2342 !(*total_flags & FIF_PLCPFAIL));
2343 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
2344 !(*total_flags & FIF_CONTROL));
2345 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
2346 !(*total_flags & FIF_PROMISC_IN_BSS));
2347 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
2348 !(*total_flags & FIF_PROMISC_IN_BSS));
2349 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
2350 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
2351 !(*total_flags & FIF_ALLMULTI));
2352 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BORADCAST, 0);
2353 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS, 1);
2354 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
2355 }
2356
2357 static int rt61pci_set_retry_limit(struct ieee80211_hw *hw,
2358 u32 short_retry, u32 long_retry)
2359 {
2360 struct rt2x00_dev *rt2x00dev = hw->priv;
2361 u32 reg;
2362
2363 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
2364 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
2365 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
2366 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
2367
2368 return 0;
2369 }
2370
2371 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2372 {
2373 struct rt2x00_dev *rt2x00dev = hw->priv;
2374 u64 tsf;
2375 u32 reg;
2376
2377 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2378 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2379 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2380 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2381
2382 return tsf;
2383 }
2384
2385 static void rt61pci_reset_tsf(struct ieee80211_hw *hw)
2386 {
2387 struct rt2x00_dev *rt2x00dev = hw->priv;
2388
2389 rt2x00pci_register_write(rt2x00dev, TXRX_CSR12, 0);
2390 rt2x00pci_register_write(rt2x00dev, TXRX_CSR13, 0);
2391 }
2392
2393 static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
2394 struct ieee80211_tx_control *control)
2395 {
2396 struct rt2x00_dev *rt2x00dev = hw->priv;
2397 struct rt2x00_intf *intf = vif_to_intf(control->vif);
2398 struct skb_frame_desc *skbdesc;
2399 unsigned int beacon_base;
2400
2401 if (unlikely(!intf->beacon))
2402 return -ENOBUFS;
2403
2404 /*
2405 * We need to append the descriptor in front of the
2406 * beacon frame.
2407 */
2408 if (skb_headroom(skb) < intf->beacon->queue->desc_size) {
2409 if (pskb_expand_head(skb, intf->beacon->queue->desc_size,
2410 0, GFP_ATOMIC)) {
2411 dev_kfree_skb(skb);
2412 return -ENOMEM;
2413 }
2414 }
2415
2416 /*
2417 * Add the descriptor in front of the skb.
2418 */
2419 skb_push(skb, intf->beacon->queue->desc_size);
2420 memset(skb->data, 0, intf->beacon->queue->desc_size);
2421
2422 /*
2423 * Fill in skb descriptor
2424 */
2425 skbdesc = get_skb_frame_desc(skb);
2426 memset(skbdesc, 0, sizeof(*skbdesc));
2427 skbdesc->data = skb->data + intf->beacon->queue->desc_size;
2428 skbdesc->data_len = skb->len - intf->beacon->queue->desc_size;
2429 skbdesc->desc = skb->data;
2430 skbdesc->desc_len = intf->beacon->queue->desc_size;
2431 skbdesc->entry = intf->beacon;
2432
2433 /*
2434 * mac80211 doesn't provide the control->queue variable
2435 * for beacons. Set our own queue identification so
2436 * it can be used during descriptor initialization.
2437 */
2438 control->queue = RT2X00_BCN_QUEUE_BEACON;
2439 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
2440
2441 /*
2442 * Write entire beacon with descriptor to register,
2443 * and kick the beacon generator.
2444 */
2445 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
2446 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base,
2447 skb->data, skb->len);
2448 rt61pci_kick_tx_queue(rt2x00dev, control->queue);
2449
2450 return 0;
2451 }
2452
2453 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2454 .tx = rt2x00mac_tx,
2455 .start = rt2x00mac_start,
2456 .stop = rt2x00mac_stop,
2457 .add_interface = rt2x00mac_add_interface,
2458 .remove_interface = rt2x00mac_remove_interface,
2459 .config = rt2x00mac_config,
2460 .config_interface = rt2x00mac_config_interface,
2461 .configure_filter = rt61pci_configure_filter,
2462 .get_stats = rt2x00mac_get_stats,
2463 .set_retry_limit = rt61pci_set_retry_limit,
2464 .bss_info_changed = rt2x00mac_bss_info_changed,
2465 .conf_tx = rt2x00mac_conf_tx,
2466 .get_tx_stats = rt2x00mac_get_tx_stats,
2467 .get_tsf = rt61pci_get_tsf,
2468 .reset_tsf = rt61pci_reset_tsf,
2469 .beacon_update = rt61pci_beacon_update,
2470 };
2471
2472 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2473 .irq_handler = rt61pci_interrupt,
2474 .probe_hw = rt61pci_probe_hw,
2475 .get_firmware_name = rt61pci_get_firmware_name,
2476 .load_firmware = rt61pci_load_firmware,
2477 .initialize = rt2x00pci_initialize,
2478 .uninitialize = rt2x00pci_uninitialize,
2479 .init_rxentry = rt61pci_init_rxentry,
2480 .init_txentry = rt61pci_init_txentry,
2481 .set_device_state = rt61pci_set_device_state,
2482 .rfkill_poll = rt61pci_rfkill_poll,
2483 .link_stats = rt61pci_link_stats,
2484 .reset_tuner = rt61pci_reset_tuner,
2485 .link_tuner = rt61pci_link_tuner,
2486 .write_tx_desc = rt61pci_write_tx_desc,
2487 .write_tx_data = rt2x00pci_write_tx_data,
2488 .kick_tx_queue = rt61pci_kick_tx_queue,
2489 .fill_rxdone = rt61pci_fill_rxdone,
2490 .config_intf = rt61pci_config_intf,
2491 .config_preamble = rt61pci_config_preamble,
2492 .config = rt61pci_config,
2493 };
2494
2495 static const struct data_queue_desc rt61pci_queue_rx = {
2496 .entry_num = RX_ENTRIES,
2497 .data_size = DATA_FRAME_SIZE,
2498 .desc_size = RXD_DESC_SIZE,
2499 .priv_size = sizeof(struct queue_entry_priv_pci_rx),
2500 };
2501
2502 static const struct data_queue_desc rt61pci_queue_tx = {
2503 .entry_num = TX_ENTRIES,
2504 .data_size = DATA_FRAME_SIZE,
2505 .desc_size = TXD_DESC_SIZE,
2506 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
2507 };
2508
2509 static const struct data_queue_desc rt61pci_queue_bcn = {
2510 .entry_num = 4 * BEACON_ENTRIES,
2511 .data_size = MGMT_FRAME_SIZE,
2512 .desc_size = TXINFO_SIZE,
2513 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
2514 };
2515
2516 static const struct rt2x00_ops rt61pci_ops = {
2517 .name = KBUILD_MODNAME,
2518 .max_sta_intf = 1,
2519 .max_ap_intf = 4,
2520 .eeprom_size = EEPROM_SIZE,
2521 .rf_size = RF_SIZE,
2522 .rx = &rt61pci_queue_rx,
2523 .tx = &rt61pci_queue_tx,
2524 .bcn = &rt61pci_queue_bcn,
2525 .lib = &rt61pci_rt2x00_ops,
2526 .hw = &rt61pci_mac80211_ops,
2527 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2528 .debugfs = &rt61pci_rt2x00debug,
2529 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2530 };
2531
2532 /*
2533 * RT61pci module information.
2534 */
2535 static struct pci_device_id rt61pci_device_table[] = {
2536 /* RT2561s */
2537 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2538 /* RT2561 v2 */
2539 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2540 /* RT2661 */
2541 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2542 { 0, }
2543 };
2544
2545 MODULE_AUTHOR(DRV_PROJECT);
2546 MODULE_VERSION(DRV_VERSION);
2547 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2548 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2549 "PCI & PCMCIA chipset based cards");
2550 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2551 MODULE_FIRMWARE(FIRMWARE_RT2561);
2552 MODULE_FIRMWARE(FIRMWARE_RT2561s);
2553 MODULE_FIRMWARE(FIRMWARE_RT2661);
2554 MODULE_LICENSE("GPL");
2555
2556 static struct pci_driver rt61pci_driver = {
2557 .name = KBUILD_MODNAME,
2558 .id_table = rt61pci_device_table,
2559 .probe = rt2x00pci_probe,
2560 .remove = __devexit_p(rt2x00pci_remove),
2561 .suspend = rt2x00pci_suspend,
2562 .resume = rt2x00pci_resume,
2563 };
2564
2565 static int __init rt61pci_init(void)
2566 {
2567 return pci_register_driver(&rt61pci_driver);
2568 }
2569
2570 static void __exit rt61pci_exit(void)
2571 {
2572 pci_unregister_driver(&rt61pci_driver);
2573 }
2574
2575 module_init(rt61pci_init);
2576 module_exit(rt61pci_exit);
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