arch/arm/mach-ixp2000/uengine.c

   1 /*
   2  * Generic library functions for the microengines found on the Intel
   3  * IXP2000 series of network processors.
   4  *
   5  * Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org>
   6  * Dedicated to Marija Kulikova.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU Lesser General Public License as
  10  * published by the Free Software Foundation; either version 2.1 of the
  11  * License, or (at your option) any later version.
  12  */
  13
  14 #include <linux/config.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/slab.h>
  18 #include <linux/module.h>
  19 #include <linux/string.h>
  20 #include <asm/hardware.h>
  21 #include <asm/arch/ixp2000-regs.h>
  22 #include <asm/arch/uengine.h>
  23 #include <asm/io.h>
  24
  25 #define USTORE_ADDRESS                  0x000
  26 #define USTORE_DATA_LOWER               0x004
  27 #define USTORE_DATA_UPPER               0x008
  28 #define CTX_ENABLES                     0x018
  29 #define CC_ENABLE                       0x01c
  30 #define CSR_CTX_POINTER                 0x020
  31 #define INDIRECT_CTX_STS                0x040
  32 #define ACTIVE_CTX_STS                  0x044
  33 #define INDIRECT_CTX_SIG_EVENTS         0x048
  34 #define INDIRECT_CTX_WAKEUP_EVENTS      0x050
  35 #define NN_PUT                          0x080
  36 #define NN_GET                          0x084
  37 #define TIMESTAMP_LOW                   0x0c0
  38 #define TIMESTAMP_HIGH                  0x0c4
  39 #define T_INDEX_BYTE_INDEX              0x0f4
  40 #define LOCAL_CSR_STATUS                0x180
  41
  42 u32 ixp2000_uengine_mask;
  43
  44 static void *ixp2000_uengine_csr_area(int uengine)
  45 {
  46         return ((void *)IXP2000_UENGINE_CSR_VIRT_BASE) + (uengine << 10);
  47 }
  48
  49 /*
  50  * LOCAL_CSR_STATUS=1 after a read or write to a microengine's CSR
  51  * space means that the microengine we tried to access was also trying
  52  * to access its own CSR space on the same clock cycle as we did.  When
  53  * this happens, we lose the arbitration process by default, and the
  54  * read or write we tried to do was not actually performed, so we try
  55  * again until it succeeds.
  56  */
  57 u32 ixp2000_uengine_csr_read(int uengine, int offset)
  58 {
  59         void *uebase;
  60         u32 *local_csr_status;
  61         u32 *reg;
  62         u32 value;
  63
  64         uebase = ixp2000_uengine_csr_area(uengine);
  65
  66         local_csr_status = (u32 *)(uebase + LOCAL_CSR_STATUS);
  67         reg = (u32 *)(uebase + offset);
  68         do {
  69                 value = ixp2000_reg_read(reg);
  70         } while (ixp2000_reg_read(local_csr_status) & 1);
  71
  72         return value;
  73 }
  74 EXPORT_SYMBOL(ixp2000_uengine_csr_read);
  75
  76 void ixp2000_uengine_csr_write(int uengine, int offset, u32 value)
  77 {
  78         void *uebase;
  79         u32 *local_csr_status;
  80         u32 *reg;
  81
  82         uebase = ixp2000_uengine_csr_area(uengine);
  83
  84         local_csr_status = (u32 *)(uebase + LOCAL_CSR_STATUS);
  85         reg = (u32 *)(uebase + offset);
  86         do {
  87                 ixp2000_reg_write(reg, value);
  88         } while (ixp2000_reg_read(local_csr_status) & 1);
  89 }
  90 EXPORT_SYMBOL(ixp2000_uengine_csr_write);
  91
  92 void ixp2000_uengine_reset(u32 uengine_mask)
  93 {
  94         ixp2000_reg_wrb(IXP2000_RESET1, uengine_mask & ixp2000_uengine_mask);
  95         ixp2000_reg_wrb(IXP2000_RESET1, 0);
  96 }
  97 EXPORT_SYMBOL(ixp2000_uengine_reset);
  98
  99 void ixp2000_uengine_set_mode(int uengine, u32 mode)
 100 {
 101         /*
 102          * CTL_STR_PAR_EN: unconditionally enable parity checking on
 103          * control store.
 104          */
 105         mode |= 0x10000000;
 106         ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mode);
 107
 108         /*
 109          * Enable updating of condition codes.
 110          */
 111         ixp2000_uengine_csr_write(uengine, CC_ENABLE, 0x00002000);
 112
 113         /*
 114          * Initialise other per-microengine registers.
 115          */
 116         ixp2000_uengine_csr_write(uengine, NN_PUT, 0x00);
 117         ixp2000_uengine_csr_write(uengine, NN_GET, 0x00);
 118         ixp2000_uengine_csr_write(uengine, T_INDEX_BYTE_INDEX, 0);
 119 }
 120 EXPORT_SYMBOL(ixp2000_uengine_set_mode);
 121
 122 static int make_even_parity(u32 x)
 123 {
 124         return hweight32(x) & 1;
 125 }
 126
 127 static void ustore_write(int uengine, u64 insn)
 128 {
 129         /*
 130          * Generate even parity for top and bottom 20 bits.
 131          */
 132         insn |= (u64)make_even_parity((insn >> 20) & 0x000fffff) << 41;
 133         insn |= (u64)make_even_parity(insn & 0x000fffff) << 40;
 134
 135         /*
 136          * Write to microstore.  The second write auto-increments
 137          * the USTORE_ADDRESS index register.
 138          */
 139         ixp2000_uengine_csr_write(uengine, USTORE_DATA_LOWER, (u32)insn);
 140         ixp2000_uengine_csr_write(uengine, USTORE_DATA_UPPER, (u32)(insn >> 32));
 141 }
 142
 143 void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns)
 144 {
 145         int i;
 146
 147         /*
 148          * Start writing to microstore at address 0.
 149          */
 150         ixp2000_uengine_csr_write(uengine, USTORE_ADDRESS, 0x80000000);
 151         for (i = 0; i < insns; i++) {
 152                 u64 insn;
 153
 154                 insn = (((u64)ucode[0]) << 32) |
 155                         (((u64)ucode[1]) << 24) |
 156                         (((u64)ucode[2]) << 16) |
 157                         (((u64)ucode[3]) << 8) |
 158                         ((u64)ucode[4]);
 159                 ucode += 5;
 160
 161                 ustore_write(uengine, insn);
 162         }
 163
 164         /*
 165          * Pad with a few NOPs at the end (to avoid the microengine
 166          * aborting as it prefetches beyond the last instruction), unless
 167          * we run off the end of the instruction store first, at which
 168          * point the address register will wrap back to zero.
 169          */
 170         for (i = 0; i < 4; i++) {
 171                 u32 addr;
 172
 173                 addr = ixp2000_uengine_csr_read(uengine, USTORE_ADDRESS);
 174                 if (addr == 0x80000000)
 175                         break;
 176                 ustore_write(uengine, 0xf0000c0300ULL);
 177         }
 178
 179         /*
 180          * End programming.
 181          */
 182         ixp2000_uengine_csr_write(uengine, USTORE_ADDRESS, 0x00000000);
 183 }
 184 EXPORT_SYMBOL(ixp2000_uengine_load_microcode);
 185
 186 void ixp2000_uengine_init_context(int uengine, int context, int pc)
 187 {
 188         /*
 189          * Select the right context for indirect access.
 190          */
 191         ixp2000_uengine_csr_write(uengine, CSR_CTX_POINTER, context);
 192
 193         /*
 194          * Initialise signal masks to immediately go to Ready state.
 195          */
 196         ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_SIG_EVENTS, 1);
 197         ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_WAKEUP_EVENTS, 1);
 198
 199         /*
 200          * Set program counter.
 201          */
 202         ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_STS, pc);
 203 }
 204 EXPORT_SYMBOL(ixp2000_uengine_init_context);
 205
 206 void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask)
 207 {
 208         u32 mask;
 209
 210         /*
 211          * Enable the specified context to go to Executing state.
 212          */
 213         mask = ixp2000_uengine_csr_read(uengine, CTX_ENABLES);
 214         mask |= ctx_mask << 8;
 215         ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mask);
 216 }
 217 EXPORT_SYMBOL(ixp2000_uengine_start_contexts);
 218
 219 void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask)
 220 {
 221         u32 mask;
 222
 223         /*
 224          * Disable the Ready->Executing transition.  Note that this
 225          * does not stop the context until it voluntarily yields.
 226          */
 227         mask = ixp2000_uengine_csr_read(uengine, CTX_ENABLES);
 228         mask &= ~(ctx_mask << 8);
 229         ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mask);
 230 }
 231 EXPORT_SYMBOL(ixp2000_uengine_stop_contexts);
 232
 233 static int check_ixp_type(struct ixp2000_uengine_code *c)
 234 {
 235         u32 product_id;
 236         u32 rev;
 237
 238         product_id = ixp2000_reg_read(IXP2000_PRODUCT_ID);
 239         if (((product_id >> 16) & 0x1f) != 0)
 240                 return 0;
 241
 242         switch ((product_id >> 8) & 0xff) {
 243         case 0:         /* IXP2800 */
 244                 if (!(c->cpu_model_bitmask & 4))
 245                         return 0;
 246                 break;
 247
 248         case 1:         /* IXP2850 */
 249                 if (!(c->cpu_model_bitmask & 8))
 250                         return 0;
 251                 break;
 252
 253         case 2:         /* IXP2400 */
 254                 if (!(c->cpu_model_bitmask & 2))
 255                         return 0;
 256                 break;
 257
 258         default:
 259                 return 0;
 260         }
 261
 262         rev = product_id & 0xff;
 263         if (rev < c->cpu_min_revision || rev > c->cpu_max_revision)
 264                 return 0;
 265
 266         return 1;
 267 }
 268
 269 static void generate_ucode(u8 *ucode, u32 *gpr_a, u32 *gpr_b)
 270 {
 271         int offset;
 272         int i;
 273
 274         offset = 0;
 275
 276         for (i = 0; i < 128; i++) {
 277                 u8 b3;
 278                 u8 b2;
 279                 u8 b1;
 280                 u8 b0;
 281
 282                 b3 = (gpr_a[i] >> 24) & 0xff;
 283                 b2 = (gpr_a[i] >> 16) & 0xff;
 284                 b1 = (gpr_a[i] >> 8) & 0xff;
 285                 b0 = gpr_a[i] & 0xff;
 286
 287                 // immed[@ai, (b1 << 8) | b0]
 288                 // 11110000 0000VVVV VVVV11VV VVVVVV00 1IIIIIII
 289                 ucode[offset++] = 0xf0;
 290                 ucode[offset++] = (b1 >> 4);
 291                 ucode[offset++] = (b1 << 4) | 0x0c | (b0 >> 6);
 292                 ucode[offset++] = (b0 << 2);
 293                 ucode[offset++] = 0x80 | i;
 294
 295                 // immed_w1[@ai, (b3 << 8) | b2]
 296                 // 11110100 0100VVVV VVVV11VV VVVVVV00 1IIIIIII
 297                 ucode[offset++] = 0xf4;
 298                 ucode[offset++] = 0x40 | (b3 >> 4);
 299                 ucode[offset++] = (b3 << 4) | 0x0c | (b2 >> 6);
 300                 ucode[offset++] = (b2 << 2);
 301                 ucode[offset++] = 0x80 | i;
 302         }
 303
 304         for (i = 0; i < 128; i++) {
 305                 u8 b3;
 306                 u8 b2;
 307                 u8 b1;
 308                 u8 b0;
 309
 310                 b3 = (gpr_b[i] >> 24) & 0xff;
 311                 b2 = (gpr_b[i] >> 16) & 0xff;
 312                 b1 = (gpr_b[i] >> 8) & 0xff;
 313                 b0 = gpr_b[i] & 0xff;
 314
 315                 // immed[@bi, (b1 << 8) | b0]
 316                 // 11110000 0000VVVV VVVV001I IIIIII11 VVVVVVVV
 317                 ucode[offset++] = 0xf0;
 318                 ucode[offset++] = (b1 >> 4);
 319                 ucode[offset++] = (b1 << 4) | 0x02 | (i >> 6);
 320                 ucode[offset++] = (i << 2) | 0x03;
 321                 ucode[offset++] = b0;
 322
 323                 // immed_w1[@bi, (b3 << 8) | b2]
 324                 // 11110100 0100VVVV VVVV001I IIIIII11 VVVVVVVV
 325                 ucode[offset++] = 0xf4;
 326                 ucode[offset++] = 0x40 | (b3 >> 4);
 327                 ucode[offset++] = (b3 << 4) | 0x02 | (i >> 6);
 328                 ucode[offset++] = (i << 2) | 0x03;
 329                 ucode[offset++] = b2;
 330         }
 331
 332         // ctx_arb[kill]
 333         ucode[offset++] = 0xe0;
 334         ucode[offset++] = 0x00;
 335         ucode[offset++] = 0x01;
 336         ucode[offset++] = 0x00;
 337         ucode[offset++] = 0x00;
 338 }
 339
 340 static int set_initial_registers(int uengine, struct ixp2000_uengine_code *c)
 341 {
 342         int per_ctx_regs;
 343         u32 *gpr_a;
 344         u32 *gpr_b;
 345         u8 *ucode;
 346         int i;
 347
 348         gpr_a = kmalloc(128 * sizeof(u32), GFP_KERNEL);
 349         gpr_b = kmalloc(128 * sizeof(u32), GFP_KERNEL);
 350         ucode = kmalloc(513 * 5, GFP_KERNEL);
 351         if (gpr_a == NULL || gpr_b == NULL || ucode == NULL) {
 352                 kfree(ucode);
 353                 kfree(gpr_b);
 354                 kfree(gpr_a);
 355                 return 1;
 356         }
 357
 358         per_ctx_regs = 16;
 359         if (c->uengine_parameters & IXP2000_UENGINE_4_CONTEXTS)
 360                 per_ctx_regs = 32;
 361
 362         memset(gpr_a, 0, sizeof(gpr_a));
 363         memset(gpr_b, 0, sizeof(gpr_b));
 364         for (i = 0; i < 256; i++) {
 365                 struct ixp2000_reg_value *r = c->initial_reg_values + i;
 366                 u32 *bank;
 367                 int inc;
 368                 int j;
 369
 370                 if (r->reg == -1)
 371                         break;
 372
 373                 bank = (r->reg & 0x400) ? gpr_b : gpr_a;
 374                 inc = (r->reg & 0x80) ? 128 : per_ctx_regs;
 375
 376                 j = r->reg & 0x7f;
 377                 while (j < 128) {
 378                         bank[j] = r->value;
 379                         j += inc;
 380                 }
 381         }
 382
 383         generate_ucode(ucode, gpr_a, gpr_b);
 384         ixp2000_uengine_load_microcode(uengine, ucode, 513);
 385         ixp2000_uengine_init_context(uengine, 0, 0);
 386         ixp2000_uengine_start_contexts(uengine, 0x01);
 387         for (i = 0; i < 100; i++) {
 388                 u32 status;
 389
 390                 status = ixp2000_uengine_csr_read(uengine, ACTIVE_CTX_STS);
 391                 if (!(status & 0x80000000))
 392                         break;
 393         }
 394         ixp2000_uengine_stop_contexts(uengine, 0x01);
 395
 396         kfree(ucode);
 397         kfree(gpr_b);
 398         kfree(gpr_a);
 399
 400         return !!(i == 100);
 401 }
 402
 403 int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c)
 404 {
 405         int ctx;
 406
 407         if (!check_ixp_type(c))
 408                 return 1;
 409
 410         if (!(ixp2000_uengine_mask & (1 << uengine)))
 411                 return 1;
 412
 413         ixp2000_uengine_reset(1 << uengine);
 414         ixp2000_uengine_set_mode(uengine, c->uengine_parameters);
 415         if (set_initial_registers(uengine, c))
 416                 return 1;
 417         ixp2000_uengine_load_microcode(uengine, c->insns, c->num_insns);
 418
 419         for (ctx = 0; ctx < 8; ctx++)
 420                 ixp2000_uengine_init_context(uengine, ctx, 0);
 421
 422         return 0;
 423 }
 424 EXPORT_SYMBOL(ixp2000_uengine_load);
 425
 426
 427 static int __init ixp2000_uengine_init(void)
 428 {
 429         int uengine;
 430         u32 value;
 431
 432         /*
 433          * Determine number of microengines present.
 434          */
 435         switch ((ixp2000_reg_read(IXP2000_PRODUCT_ID) >> 8) & 0x1fff) {
 436         case 0:         /* IXP2800 */
 437         case 1:         /* IXP2850 */
 438                 ixp2000_uengine_mask = 0x00ff00ff;
 439                 break;
 440
 441         case 2:         /* IXP2400 */
 442                 ixp2000_uengine_mask = 0x000f000f;
 443                 break;
 444
 445         default:
 446                 printk(KERN_INFO "Detected unknown IXP2000 model (%.8x)\n",
 447                         (unsigned int)ixp2000_reg_read(IXP2000_PRODUCT_ID));
 448                 ixp2000_uengine_mask = 0x00000000;
 449                 break;
 450         }
 451
 452         /*
 453          * Reset microengines.
 454          */
 455         ixp2000_uengine_reset(ixp2000_uengine_mask);
 456
 457         /*
 458          * Synchronise timestamp counters across all microengines.
 459          */
 460         value = ixp2000_reg_read(IXP2000_MISC_CONTROL);
 461         ixp2000_reg_wrb(IXP2000_MISC_CONTROL, value & ~0x80);
 462         for (uengine = 0; uengine < 32; uengine++) {
 463                 if (ixp2000_uengine_mask & (1 << uengine)) {
 464                         ixp2000_uengine_csr_write(uengine, TIMESTAMP_LOW, 0);
 465                         ixp2000_uengine_csr_write(uengine, TIMESTAMP_HIGH, 0);
 466                 }
 467         }
 468         ixp2000_reg_wrb(IXP2000_MISC_CONTROL, value | 0x80);
 469
 470         return 0;
 471 }
 472
 473 subsys_initcall(ixp2000_uengine_init);