2 * linux/include/linux/mtd/nand.h
4 * Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
8 * $Id: nand.h,v 1.74 2005/09/15 13:58:50 vwool Exp $
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 * Contains standard defines and IDs for NAND flash devices
20 #ifndef __LINUX_MTD_NAND_H
21 #define __LINUX_MTD_NAND_H
23 #include <linux/config.h>
24 #include <linux/wait.h>
25 #include <linux/spinlock.h>
26 #include <linux/mtd/mtd.h>
29 /* Scan and identify a NAND device */
30 extern int nand_scan (struct mtd_info
*mtd
, int max_chips
);
31 /* Free resources held by the NAND device */
32 extern void nand_release (struct mtd_info
*mtd
);
34 /* Read raw data from the device without ECC */
35 extern int nand_read_raw (struct mtd_info
*mtd
, uint8_t *buf
, loff_t from
,
36 size_t len
, size_t ooblen
);
39 extern int nand_write_raw(struct mtd_info
*mtd
, loff_t to
, size_t len
,
40 size_t *retlen
, const uint8_t *buf
, uint8_t *oob
);
42 /* The maximum number of NAND chips in an array */
43 #define NAND_MAX_CHIPS 8
45 /* This constant declares the max. oobsize / page, which
46 * is supported now. If you add a chip with bigger oobsize/page
47 * adjust this accordingly.
49 #define NAND_MAX_OOBSIZE 64
50 #define NAND_MAX_PAGESIZE 2048
53 * Constants for hardware specific CLE/ALE/NCE function
55 * These are bits which can be or'ed to set/clear multiple
58 /* Select the chip by setting nCE to low */
60 /* Select the command latch by setting CLE to high */
62 /* Select the address latch by setting ALE to high */
65 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
66 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
67 #define NAND_CTRL_CHANGE 0x80
70 * Standard NAND flash commands
72 #define NAND_CMD_READ0 0
73 #define NAND_CMD_READ1 1
74 #define NAND_CMD_PAGEPROG 0x10
75 #define NAND_CMD_READOOB 0x50
76 #define NAND_CMD_ERASE1 0x60
77 #define NAND_CMD_STATUS 0x70
78 #define NAND_CMD_STATUS_MULTI 0x71
79 #define NAND_CMD_SEQIN 0x80
80 #define NAND_CMD_READID 0x90
81 #define NAND_CMD_ERASE2 0xd0
82 #define NAND_CMD_RESET 0xff
84 /* Extended commands for large page devices */
85 #define NAND_CMD_READSTART 0x30
86 #define NAND_CMD_CACHEDPROG 0x15
88 /* Extended commands for AG-AND device */
90 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
91 * there is no way to distinguish that from NAND_CMD_READ0
92 * until the remaining sequence of commands has been completed
93 * so add a high order bit and mask it off in the command.
95 #define NAND_CMD_DEPLETE1 0x100
96 #define NAND_CMD_DEPLETE2 0x38
97 #define NAND_CMD_STATUS_MULTI 0x71
98 #define NAND_CMD_STATUS_ERROR 0x72
99 /* multi-bank error status (banks 0-3) */
100 #define NAND_CMD_STATUS_ERROR0 0x73
101 #define NAND_CMD_STATUS_ERROR1 0x74
102 #define NAND_CMD_STATUS_ERROR2 0x75
103 #define NAND_CMD_STATUS_ERROR3 0x76
104 #define NAND_CMD_STATUS_RESET 0x7f
105 #define NAND_CMD_STATUS_CLEAR 0xff
107 #define NAND_CMD_NONE -1
110 #define NAND_STATUS_FAIL 0x01
111 #define NAND_STATUS_FAIL_N1 0x02
112 #define NAND_STATUS_TRUE_READY 0x20
113 #define NAND_STATUS_READY 0x40
114 #define NAND_STATUS_WP 0x80
117 * Constants for ECC_MODES
123 NAND_ECC_HW_SYNDROME
,
127 * Constants for Hardware ECC
129 /* Reset Hardware ECC for read */
130 #define NAND_ECC_READ 0
131 /* Reset Hardware ECC for write */
132 #define NAND_ECC_WRITE 1
133 /* Enable Hardware ECC before syndrom is read back from flash */
134 #define NAND_ECC_READSYN 2
136 /* Bit mask for flags passed to do_nand_read_ecc */
137 #define NAND_GET_DEVICE 0x80
140 /* Option constants for bizarre disfunctionality and real
143 /* Chip can not auto increment pages */
144 #define NAND_NO_AUTOINCR 0x00000001
145 /* Buswitdh is 16 bit */
146 #define NAND_BUSWIDTH_16 0x00000002
147 /* Device supports partial programming without padding */
148 #define NAND_NO_PADDING 0x00000004
149 /* Chip has cache program function */
150 #define NAND_CACHEPRG 0x00000008
151 /* Chip has copy back function */
152 #define NAND_COPYBACK 0x00000010
153 /* AND Chip which has 4 banks and a confusing page / block
154 * assignment. See Renesas datasheet for further information */
155 #define NAND_IS_AND 0x00000020
156 /* Chip has a array of 4 pages which can be read without
157 * additional ready /busy waits */
158 #define NAND_4PAGE_ARRAY 0x00000040
159 /* Chip requires that BBT is periodically rewritten to prevent
160 * bits from adjacent blocks from 'leaking' in altering data.
161 * This happens with the Renesas AG-AND chips, possibly others. */
162 #define BBT_AUTO_REFRESH 0x00000080
163 /* Chip does not require ready check on read. True
164 * for all large page devices, as they do not support
166 #define NAND_NO_READRDY 0x00000100
168 /* Options valid for Samsung large page devices */
169 #define NAND_SAMSUNG_LP_OPTIONS \
170 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
172 /* Macros to identify the above */
173 #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
174 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
175 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
176 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
178 /* Mask to zero out the chip options, which come from the id table */
179 #define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
181 /* Non chip related options */
182 /* Use a flash based bad block table. This option is passed to the
183 * default bad block table function. */
184 #define NAND_USE_FLASH_BBT 0x00010000
185 /* This option skips the bbt scan during initialization. */
186 #define NAND_SKIP_BBTSCAN 0x00020000
188 /* Options set by nand scan */
189 /* Nand scan has allocated controller struct */
190 #define NAND_CONTROLLER_ALLOC 0x80000000
194 * nand_state_t - chip states
195 * Enumeration for NAND flash chip state
211 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independend devices
212 * @lock: protection lock
213 * @active: the mtd device which holds the controller currently
214 * @wq: wait queue to sleep on if a NAND operation is in progress
215 * used instead of the per chip wait queue when a hw controller is available
217 struct nand_hw_control
{
219 struct nand_chip
*active
;
220 wait_queue_head_t wq
;
224 * struct nand_ecc_ctrl - Control structure for ecc
226 * @steps: number of ecc steps per page
227 * @size: data bytes per ecc step
228 * @bytes: ecc bytes per step
229 * @total: total number of ecc bytes per page
230 * @prepad: padding information for syndrome based ecc generators
231 * @postpad: padding information for syndrome based ecc generators
232 * @hwctl: function to control hardware ecc generator. Must only
233 * be provided if an hardware ECC is available
234 * @calculate: function for ecc calculation or readback from ecc hardware
235 * @correct: function for ecc correction, matching to ecc generator (sw/hw)
236 * @read_page: function to read a page according to the ecc generator requirements
237 * @write_page: function to write a page according to the ecc generator requirements
239 struct nand_ecc_ctrl
{
240 nand_ecc_modes_t mode
;
247 struct nand_ecclayout
*layout
;
248 void (*hwctl
)(struct mtd_info
*mtd
, int mode
);
249 int (*calculate
)(struct mtd_info
*mtd
,
252 int (*correct
)(struct mtd_info
*mtd
, uint8_t *dat
,
255 int (*read_page
)(struct mtd_info
*mtd
,
256 struct nand_chip
*chip
,
258 void (*write_page
)(struct mtd_info
*mtd
,
259 struct nand_chip
*chip
,
264 * struct nand_buffers - buffer structure for read/write
265 * @ecccalc: buffer for calculated ecc
266 * @ecccode: buffer for ecc read from flash
267 * @oobwbuf: buffer for write oob data
268 * @databuf: buffer for data - dynamically sized
269 * @oobrbuf: buffer to read oob data
271 * Do not change the order of buffers. databuf and oobrbuf must be in
274 struct nand_buffers
{
275 uint8_t ecccalc
[NAND_MAX_OOBSIZE
];
276 uint8_t ecccode
[NAND_MAX_OOBSIZE
];
277 uint8_t oobwbuf
[NAND_MAX_OOBSIZE
];
278 uint8_t databuf
[NAND_MAX_PAGESIZE
];
279 uint8_t oobrbuf
[NAND_MAX_OOBSIZE
];
283 * struct nand_chip - NAND Private Flash Chip Data
284 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
285 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
286 * @read_byte: [REPLACEABLE] read one byte from the chip
287 * @read_word: [REPLACEABLE] read one word from the chip
288 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
289 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
290 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data
291 * @select_chip: [REPLACEABLE] select chip nr
292 * @block_bad: [REPLACEABLE] check, if the block is bad
293 * @block_markbad: [REPLACEABLE] mark the block bad
294 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling
295 * ALE/CLE/nCE. Also used to write command and address
296 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
297 * If set to NULL no access to ready/busy is available and the ready/busy information
298 * is read from the chip status register
299 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
300 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
301 * @ecc: [BOARDSPECIFIC] ecc control ctructure
302 * @erase_cmd: [INTERN] erase command write function, selectable due to AND support
303 * @scan_bbt: [REPLACEABLE] function to scan bad block table
304 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
305 * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress
306 * @state: [INTERN] the current state of the NAND device
307 * @page_shift: [INTERN] number of address bits in a page (column address bits)
308 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
309 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
310 * @chip_shift: [INTERN] number of address bits in one chip
311 * @datbuf: [INTERN] internal buffer for one page + oob
312 * @oobbuf: [INTERN] oob buffer for one eraseblock
313 * @oobdirty: [INTERN] indicates that oob_buf must be reinitialized
314 * @data_poi: [INTERN] pointer to a data buffer
315 * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
316 * special functionality. See the defines for further explanation
317 * @badblockpos: [INTERN] position of the bad block marker in the oob area
318 * @numchips: [INTERN] number of physical chips
319 * @chipsize: [INTERN] the size of one chip for multichip arrays
320 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
321 * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf
322 * @ecclayout: [REPLACEABLE] the default ecc placement scheme
323 * @bbt: [INTERN] bad block table pointer
324 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup
325 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
326 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
327 * @controller: [REPLACEABLE] a pointer to a hardware controller structure
328 * which is shared among multiple independend devices
329 * @priv: [OPTIONAL] pointer to private chip date
330 * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks
331 * (determine if errors are correctable)
335 void __iomem
*IO_ADDR_R
;
336 void __iomem
*IO_ADDR_W
;
338 uint8_t (*read_byte
)(struct mtd_info
*mtd
);
339 u16 (*read_word
)(struct mtd_info
*mtd
);
340 void (*write_buf
)(struct mtd_info
*mtd
, const uint8_t *buf
, int len
);
341 void (*read_buf
)(struct mtd_info
*mtd
, uint8_t *buf
, int len
);
342 int (*verify_buf
)(struct mtd_info
*mtd
, const uint8_t *buf
, int len
);
343 void (*select_chip
)(struct mtd_info
*mtd
, int chip
);
344 int (*block_bad
)(struct mtd_info
*mtd
, loff_t ofs
, int getchip
);
345 int (*block_markbad
)(struct mtd_info
*mtd
, loff_t ofs
);
346 void (*cmd_ctrl
)(struct mtd_info
*mtd
, int dat
,
348 int (*dev_ready
)(struct mtd_info
*mtd
);
349 void (*cmdfunc
)(struct mtd_info
*mtd
, unsigned command
, int column
, int page_addr
);
350 int (*waitfunc
)(struct mtd_info
*mtd
, struct nand_chip
*this, int state
);
351 void (*erase_cmd
)(struct mtd_info
*mtd
, int page
);
352 int (*scan_bbt
)(struct mtd_info
*mtd
);
353 int (*errstat
)(struct mtd_info
*mtd
, struct nand_chip
*this, int state
, int status
, int page
);
356 unsigned int options
;
359 int phys_erase_shift
;
363 unsigned long chipsize
;
371 struct nand_hw_control
*controller
;
372 struct nand_ecclayout
*ecclayout
;
374 struct nand_ecc_ctrl ecc
;
375 struct nand_buffers buffers
;
376 struct nand_hw_control hwcontrol
;
379 struct nand_bbt_descr
*bbt_td
;
380 struct nand_bbt_descr
*bbt_md
;
382 struct nand_bbt_descr
*badblock_pattern
;
388 * NAND Flash Manufacturer ID Codes
390 #define NAND_MFR_TOSHIBA 0x98
391 #define NAND_MFR_SAMSUNG 0xec
392 #define NAND_MFR_FUJITSU 0x04
393 #define NAND_MFR_NATIONAL 0x8f
394 #define NAND_MFR_RENESAS 0x07
395 #define NAND_MFR_STMICRO 0x20
396 #define NAND_MFR_HYNIX 0xad
399 * struct nand_flash_dev - NAND Flash Device ID Structure
401 * @name: Identify the device type
402 * @id: device ID code
403 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
404 * If the pagesize is 0, then the real pagesize
405 * and the eraseize are determined from the
406 * extended id bytes in the chip
407 * @erasesize: Size of an erase block in the flash device.
408 * @chipsize: Total chipsize in Mega Bytes
409 * @options: Bitfield to store chip relevant options
411 struct nand_flash_dev
{
414 unsigned long pagesize
;
415 unsigned long chipsize
;
416 unsigned long erasesize
;
417 unsigned long options
;
421 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
422 * @name: Manufacturer name
423 * @id: manufacturer ID code of device.
425 struct nand_manufacturers
{
430 extern struct nand_flash_dev nand_flash_ids
[];
431 extern struct nand_manufacturers nand_manuf_ids
[];
434 * struct nand_bbt_descr - bad block table descriptor
435 * @options: options for this descriptor
436 * @pages: the page(s) where we find the bbt, used with option BBT_ABSPAGE
437 * when bbt is searched, then we store the found bbts pages here.
438 * Its an array and supports up to 8 chips now
439 * @offs: offset of the pattern in the oob area of the page
440 * @veroffs: offset of the bbt version counter in the oob are of the page
441 * @version: version read from the bbt page during scan
442 * @len: length of the pattern, if 0 no pattern check is performed
443 * @maxblocks: maximum number of blocks to search for a bbt. This number of
444 * blocks is reserved at the end of the device where the tables are
446 * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
447 * bad) block in the stored bbt
448 * @pattern: pattern to identify bad block table or factory marked good /
449 * bad blocks, can be NULL, if len = 0
451 * Descriptor for the bad block table marker and the descriptor for the
452 * pattern which identifies good and bad blocks. The assumption is made
453 * that the pattern and the version count are always located in the oob area
454 * of the first block.
456 struct nand_bbt_descr
{
458 int pages
[NAND_MAX_CHIPS
];
461 uint8_t version
[NAND_MAX_CHIPS
];
464 int reserved_block_code
;
468 /* Options for the bad block table descriptors */
470 /* The number of bits used per block in the bbt on the device */
471 #define NAND_BBT_NRBITS_MSK 0x0000000F
472 #define NAND_BBT_1BIT 0x00000001
473 #define NAND_BBT_2BIT 0x00000002
474 #define NAND_BBT_4BIT 0x00000004
475 #define NAND_BBT_8BIT 0x00000008
476 /* The bad block table is in the last good block of the device */
477 #define NAND_BBT_LASTBLOCK 0x00000010
478 /* The bbt is at the given page, else we must scan for the bbt */
479 #define NAND_BBT_ABSPAGE 0x00000020
480 /* The bbt is at the given page, else we must scan for the bbt */
481 #define NAND_BBT_SEARCH 0x00000040
482 /* bbt is stored per chip on multichip devices */
483 #define NAND_BBT_PERCHIP 0x00000080
484 /* bbt has a version counter at offset veroffs */
485 #define NAND_BBT_VERSION 0x00000100
486 /* Create a bbt if none axists */
487 #define NAND_BBT_CREATE 0x00000200
488 /* Search good / bad pattern through all pages of a block */
489 #define NAND_BBT_SCANALLPAGES 0x00000400
490 /* Scan block empty during good / bad block scan */
491 #define NAND_BBT_SCANEMPTY 0x00000800
492 /* Write bbt if neccecary */
493 #define NAND_BBT_WRITE 0x00001000
494 /* Read and write back block contents when writing bbt */
495 #define NAND_BBT_SAVECONTENT 0x00002000
496 /* Search good / bad pattern on the first and the second page */
497 #define NAND_BBT_SCAN2NDPAGE 0x00004000
499 /* The maximum number of blocks to scan for a bbt */
500 #define NAND_BBT_SCAN_MAXBLOCKS 4
502 extern int nand_scan_bbt(struct mtd_info
*mtd
, struct nand_bbt_descr
*bd
);
503 extern int nand_update_bbt(struct mtd_info
*mtd
, loff_t offs
);
504 extern int nand_default_bbt(struct mtd_info
*mtd
);
505 extern int nand_isbad_bbt(struct mtd_info
*mtd
, loff_t offs
, int allowbbt
);
506 extern int nand_erase_nand(struct mtd_info
*mtd
, struct erase_info
*instr
,
508 extern int nand_do_read(struct mtd_info
*mtd
, loff_t from
, size_t len
,
509 size_t * retlen
, uint8_t * buf
);
512 * Constants for oob configuration
514 #define NAND_SMALL_BADBLOCK_POS 5
515 #define NAND_LARGE_BADBLOCK_POS 0
518 * struct platform_nand_chip - chip level device structure
520 * @nr_chips: max. number of chips to scan for
521 * @chip_offs: chip number offset
522 * @nr_partitions: number of partitions pointed to by partitions (or zero)
523 * @partitions: mtd partition list
524 * @chip_delay: R/B delay value in us
525 * @options: Option flags, e.g. 16bit buswidth
526 * @ecclayout: ecc layout info structure
527 * @priv: hardware controller specific settings
529 struct platform_nand_chip
{
533 struct mtd_partition
*partitions
;
534 struct nand_ecclayout
*ecclayout
;
536 unsigned int options
;
541 * struct platform_nand_ctrl - controller level device structure
543 * @hwcontrol: platform specific hardware control structure
544 * @dev_ready: platform specific function to read ready/busy pin
545 * @select_chip: platform specific chip select function
546 * @priv_data: private data to transport driver specific settings
548 * All fields are optional and depend on the hardware driver requirements
550 struct platform_nand_ctrl
{
551 void (*hwcontrol
)(struct mtd_info
*mtd
, int cmd
);
552 int (*dev_ready
)(struct mtd_info
*mtd
);
553 void (*select_chip
)(struct mtd_info
*mtd
, int chip
);
557 /* Some helpers to access the data structures */
559 struct platform_nand_chip
*get_platform_nandchip(struct mtd_info
*mtd
)
561 struct nand_chip
*chip
= mtd
->priv
;
566 #endif /* __LINUX_MTD_NAND_H */