arch/arm/plat-mxc/irq.c

   1 /*
   2  *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3  */
   4
   5 /*
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/init.h>
  14 #include <linux/device.h>
  15 #include <linux/errno.h>
  16 #include <asm/hardware.h>
  17 #include <asm/io.h>
  18 #include <asm/irq.h>
  19 #include <asm/mach/irq.h>
  20 #include <asm/arch/common.h>
  21
  22 /*!
  23  * Disable interrupt number "irq" in the AVIC
  24  *
  25  * @param  irq          interrupt source number
  26  */
  27 static void mxc_mask_irq(unsigned int irq)
  28 {
  29         __raw_writel(irq, AVIC_INTDISNUM);
  30 }
  31
  32 /*!
  33  * Enable interrupt number "irq" in the AVIC
  34  *
  35  * @param  irq          interrupt source number
  36  */
  37 static void mxc_unmask_irq(unsigned int irq)
  38 {
  39         __raw_writel(irq, AVIC_INTENNUM);
  40 }
  41
  42 static struct irq_chip mxc_avic_chip = {
  43         .mask_ack = mxc_mask_irq,
  44         .mask = mxc_mask_irq,
  45         .unmask = mxc_unmask_irq,
  46 };
  47
  48 /*!
  49  * This function initializes the AVIC hardware and disables all the
  50  * interrupts. It registers the interrupt enable and disable functions
  51  * to the kernel for each interrupt source.
  52  */
  53 void __init mxc_init_irq(void)
  54 {
  55         int i;
  56         u32 reg;
  57
  58         /* put the AVIC into the reset value with
  59          * all interrupts disabled
  60          */
  61         __raw_writel(0, AVIC_INTCNTL);
  62         __raw_writel(0x1f, AVIC_NIMASK);
  63
  64         /* disable all interrupts */
  65         __raw_writel(0, AVIC_INTENABLEH);
  66         __raw_writel(0, AVIC_INTENABLEL);
  67
  68         /* all IRQ no FIQ */
  69         __raw_writel(0, AVIC_INTTYPEH);
  70         __raw_writel(0, AVIC_INTTYPEL);
  71         for (i = 0; i < MXC_MAX_INT_LINES; i++) {
  72                 set_irq_chip(i, &mxc_avic_chip);
  73                 set_irq_handler(i, handle_level_irq);
  74                 set_irq_flags(i, IRQF_VALID);
  75         }
  76
  77         /* Set WDOG2's interrupt the highest priority level (bit 28-31) */
  78         reg = __raw_readl(AVIC_NIPRIORITY6);
  79         reg |= (0xF << 28);
  80         __raw_writel(reg, AVIC_NIPRIORITY6);
  81
  82         printk(KERN_INFO "MXC IRQ initialized\n");
  83 }