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[SCSI] qla1280: convert to use the data buffer accessors
[linux-2.6/verdex.git] / arch / powerpc / mm / hash_utils_64.c
blobc78dc912411f9f6aa57c951023a733a7370b81c7
1 /*
2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
4 *
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
6 *
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
9 *
10 * Module name: htab.c
11 *
12 * Description:
13 * PowerPC Hashed Page Table functions
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 */
20
21 #undef DEBUG
22 #undef DEBUG_LOW
23
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/sched.h>
27 #include <linux/proc_fs.h>
28 #include <linux/stat.h>
29 #include <linux/sysctl.h>
30 #include <linux/ctype.h>
31 #include <linux/cache.h>
32 #include <linux/init.h>
33 #include <linux/signal.h>
34
35 #include <asm/processor.h>
36 #include <asm/pgtable.h>
37 #include <asm/mmu.h>
38 #include <asm/mmu_context.h>
39 #include <asm/page.h>
40 #include <asm/types.h>
41 #include <asm/system.h>
42 #include <asm/uaccess.h>
43 #include <asm/machdep.h>
44 #include <asm/lmb.h>
45 #include <asm/abs_addr.h>
46 #include <asm/tlbflush.h>
47 #include <asm/io.h>
48 #include <asm/eeh.h>
49 #include <asm/tlb.h>
50 #include <asm/cacheflush.h>
51 #include <asm/cputable.h>
52 #include <asm/sections.h>
53 #include <asm/spu.h>
54
55 #ifdef DEBUG
56 #define DBG(fmt...) udbg_printf(fmt)
57 #else
58 #define DBG(fmt...)
59 #endif
60
61 #ifdef DEBUG_LOW
62 #define DBG_LOW(fmt...) udbg_printf(fmt)
63 #else
64 #define DBG_LOW(fmt...)
65 #endif
66
67 #define KB (1024)
68 #define MB (1024*KB)
69
70 /*
71 * Note: pte --> Linux PTE
72 * HPTE --> PowerPC Hashed Page Table Entry
73 *
74 * Execution context:
75 * htab_initialize is called with the MMU off (of course), but
76 * the kernel has been copied down to zero so it can directly
77 * reference global data. At this point it is very difficult
78 * to print debug info.
79 *
80 */
81
82 #ifdef CONFIG_U3_DART
83 extern unsigned long dart_tablebase;
84 #endif /* CONFIG_U3_DART */
85
86 static unsigned long _SDR1;
87 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
88
89 struct hash_pte *htab_address;
90 unsigned long htab_size_bytes;
91 unsigned long htab_hash_mask;
92 int mmu_linear_psize = MMU_PAGE_4K;
93 int mmu_virtual_psize = MMU_PAGE_4K;
94 int mmu_vmalloc_psize = MMU_PAGE_4K;
95 int mmu_io_psize = MMU_PAGE_4K;
96 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
97 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
98 #ifdef CONFIG_HUGETLB_PAGE
99 int mmu_huge_psize = MMU_PAGE_16M;
100 unsigned int HPAGE_SHIFT;
101 #endif
102 #ifdef CONFIG_PPC_64K_PAGES
103 int mmu_ci_restrictions;
104 #endif
105 #ifdef CONFIG_DEBUG_PAGEALLOC
106 static u8 *linear_map_hash_slots;
107 static unsigned long linear_map_hash_count;
108 static DEFINE_SPINLOCK(linear_map_hash_lock);
109 #endif /* CONFIG_DEBUG_PAGEALLOC */
110
111 /* There are definitions of page sizes arrays to be used when none
112 * is provided by the firmware.
113 */
114
115 /* Pre-POWER4 CPUs (4k pages only)
116 */
117 struct mmu_psize_def mmu_psize_defaults_old[] = {
118 [MMU_PAGE_4K] = {
119 .shift = 12,
120 .sllp = 0,
121 .penc = 0,
122 .avpnm = 0,
123 .tlbiel = 0,
124 },
125 };
126
127 /* POWER4, GPUL, POWER5
128 *
129 * Support for 16Mb large pages
130 */
131 struct mmu_psize_def mmu_psize_defaults_gp[] = {
132 [MMU_PAGE_4K] = {
133 .shift = 12,
134 .sllp = 0,
135 .penc = 0,
136 .avpnm = 0,
137 .tlbiel = 1,
138 },
139 [MMU_PAGE_16M] = {
140 .shift = 24,
141 .sllp = SLB_VSID_L,
142 .penc = 0,
143 .avpnm = 0x1UL,
144 .tlbiel = 0,
145 },
146 };
147
148
149 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
150 unsigned long pstart, unsigned long mode,
151 int psize, int ssize)
152 {
153 unsigned long vaddr, paddr;
154 unsigned int step, shift;
155 unsigned long tmp_mode;
156 int ret = 0;
157
158 shift = mmu_psize_defs[psize].shift;
159 step = 1 << shift;
160
161 for (vaddr = vstart, paddr = pstart; vaddr < vend;
162 vaddr += step, paddr += step) {
163 unsigned long hash, hpteg;
164 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
165 unsigned long va = hpt_va(vaddr, vsid, ssize);
166
167 tmp_mode = mode;
168
169 /* Make non-kernel text non-executable */
170 if (!in_kernel_text(vaddr))
171 tmp_mode = mode | HPTE_R_N;
172
173 hash = hpt_hash(va, shift, ssize);
174 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
175
176 DBG("htab_bolt_mapping: calling %p\n", ppc_md.hpte_insert);
177
178 BUG_ON(!ppc_md.hpte_insert);
179 ret = ppc_md.hpte_insert(hpteg, va, paddr,
180 tmp_mode, HPTE_V_BOLTED, psize, ssize);
181
182 if (ret < 0)
183 break;
184 #ifdef CONFIG_DEBUG_PAGEALLOC
185 if ((paddr >> PAGE_SHIFT) < linear_map_hash_count)
186 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
187 #endif /* CONFIG_DEBUG_PAGEALLOC */
188 }
189 return ret < 0 ? ret : 0;
190 }
191
192 static int __init htab_dt_scan_seg_sizes(unsigned long node,
193 const char *uname, int depth,
194 void *data)
195 {
196 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
197 u32 *prop;
198 unsigned long size = 0;
199
200 /* We are scanning "cpu" nodes only */
201 if (type == NULL || strcmp(type, "cpu") != 0)
202 return 0;
203
204 prop = (u32 *)of_get_flat_dt_prop(node, "ibm,processor-segment-sizes",
205 &size);
206 if (prop == NULL)
207 return 0;
208 for (; size >= 4; size -= 4, ++prop) {
209 if (prop[0] == 40) {
210 DBG("1T segment support detected\n");
211 cur_cpu_spec->cpu_features |= CPU_FTR_1T_SEGMENT;
212 return 1;
213 }
214 }
215 cur_cpu_spec->cpu_features &= ~CPU_FTR_NO_SLBIE_B;
216 return 0;
217 }
218
219 static void __init htab_init_seg_sizes(void)
220 {
221 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
222 }
223
224 static int __init htab_dt_scan_page_sizes(unsigned long node,
225 const char *uname, int depth,
226 void *data)
227 {
228 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
229 u32 *prop;
230 unsigned long size = 0;
231
232 /* We are scanning "cpu" nodes only */
233 if (type == NULL || strcmp(type, "cpu") != 0)
234 return 0;
235
236 prop = (u32 *)of_get_flat_dt_prop(node,
237 "ibm,segment-page-sizes", &size);
238 if (prop != NULL) {
239 DBG("Page sizes from device-tree:\n");
240 size /= 4;
241 cur_cpu_spec->cpu_features &= ~(CPU_FTR_16M_PAGE);
242 while(size > 0) {
243 unsigned int shift = prop[0];
244 unsigned int slbenc = prop[1];
245 unsigned int lpnum = prop[2];
246 unsigned int lpenc = 0;
247 struct mmu_psize_def *def;
248 int idx = -1;
249
250 size -= 3; prop += 3;
251 while(size > 0 && lpnum) {
252 if (prop[0] == shift)
253 lpenc = prop[1];
254 prop += 2; size -= 2;
255 lpnum--;
256 }
257 switch(shift) {
258 case 0xc:
259 idx = MMU_PAGE_4K;
260 break;
261 case 0x10:
262 idx = MMU_PAGE_64K;
263 break;
264 case 0x14:
265 idx = MMU_PAGE_1M;
266 break;
267 case 0x18:
268 idx = MMU_PAGE_16M;
269 cur_cpu_spec->cpu_features |= CPU_FTR_16M_PAGE;
270 break;
271 case 0x22:
272 idx = MMU_PAGE_16G;
273 break;
274 }
275 if (idx < 0)
276 continue;
277 def = &mmu_psize_defs[idx];
278 def->shift = shift;
279 if (shift <= 23)
280 def->avpnm = 0;
281 else
282 def->avpnm = (1 << (shift - 23)) - 1;
283 def->sllp = slbenc;
284 def->penc = lpenc;
285 /* We don't know for sure what's up with tlbiel, so
286 * for now we only set it for 4K and 64K pages
287 */
288 if (idx == MMU_PAGE_4K || idx == MMU_PAGE_64K)
289 def->tlbiel = 1;
290 else
291 def->tlbiel = 0;
292
293 DBG(" %d: shift=%02x, sllp=%04x, avpnm=%08x, "
294 "tlbiel=%d, penc=%d\n",
295 idx, shift, def->sllp, def->avpnm, def->tlbiel,
296 def->penc);
297 }
298 return 1;
299 }
300 return 0;
301 }
302
303 static void __init htab_init_page_sizes(void)
304 {
305 int rc;
306
307 /* Default to 4K pages only */
308 memcpy(mmu_psize_defs, mmu_psize_defaults_old,
309 sizeof(mmu_psize_defaults_old));
310
311 /*
312 * Try to find the available page sizes in the device-tree
313 */
314 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
315 if (rc != 0) /* Found */
316 goto found;
317
318 /*
319 * Not in the device-tree, let's fallback on known size
320 * list for 16M capable GP & GR
321 */
322 if (cpu_has_feature(CPU_FTR_16M_PAGE))
323 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
324 sizeof(mmu_psize_defaults_gp));
325 found:
326 #ifndef CONFIG_DEBUG_PAGEALLOC
327 /*
328 * Pick a size for the linear mapping. Currently, we only support
329 * 16M, 1M and 4K which is the default
330 */
331 if (mmu_psize_defs[MMU_PAGE_16M].shift)
332 mmu_linear_psize = MMU_PAGE_16M;
333 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
334 mmu_linear_psize = MMU_PAGE_1M;
335 #endif /* CONFIG_DEBUG_PAGEALLOC */
336
337 #ifdef CONFIG_PPC_64K_PAGES
338 /*
339 * Pick a size for the ordinary pages. Default is 4K, we support
340 * 64K for user mappings and vmalloc if supported by the processor.
341 * We only use 64k for ioremap if the processor
342 * (and firmware) support cache-inhibited large pages.
343 * If not, we use 4k and set mmu_ci_restrictions so that
344 * hash_page knows to switch processes that use cache-inhibited
345 * mappings to 4k pages.
346 */
347 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
348 mmu_virtual_psize = MMU_PAGE_64K;
349 mmu_vmalloc_psize = MMU_PAGE_64K;
350 if (mmu_linear_psize == MMU_PAGE_4K)
351 mmu_linear_psize = MMU_PAGE_64K;
352 if (cpu_has_feature(CPU_FTR_CI_LARGE_PAGE))
353 mmu_io_psize = MMU_PAGE_64K;
354 else
355 mmu_ci_restrictions = 1;
356 }
357 #endif /* CONFIG_PPC_64K_PAGES */
358
359 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
360 "virtual = %d, io = %d\n",
361 mmu_psize_defs[mmu_linear_psize].shift,
362 mmu_psize_defs[mmu_virtual_psize].shift,
363 mmu_psize_defs[mmu_io_psize].shift);
364
365 #ifdef CONFIG_HUGETLB_PAGE
366 /* Init large page size. Currently, we pick 16M or 1M depending
367 * on what is available
368 */
369 if (mmu_psize_defs[MMU_PAGE_16M].shift)
370 mmu_huge_psize = MMU_PAGE_16M;
371 /* With 4k/4level pagetables, we can't (for now) cope with a
372 * huge page size < PMD_SIZE */
373 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
374 mmu_huge_psize = MMU_PAGE_1M;
375
376 /* Calculate HPAGE_SHIFT and sanity check it */
377 if (mmu_psize_defs[mmu_huge_psize].shift > MIN_HUGEPTE_SHIFT &&
378 mmu_psize_defs[mmu_huge_psize].shift < SID_SHIFT)
379 HPAGE_SHIFT = mmu_psize_defs[mmu_huge_psize].shift;
380 else
381 HPAGE_SHIFT = 0; /* No huge pages dude ! */
382 #endif /* CONFIG_HUGETLB_PAGE */
383 }
384
385 static int __init htab_dt_scan_pftsize(unsigned long node,
386 const char *uname, int depth,
387 void *data)
388 {
389 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
390 u32 *prop;
391
392 /* We are scanning "cpu" nodes only */
393 if (type == NULL || strcmp(type, "cpu") != 0)
394 return 0;
395
396 prop = (u32 *)of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
397 if (prop != NULL) {
398 /* pft_size[0] is the NUMA CEC cookie */
399 ppc64_pft_size = prop[1];
400 return 1;
401 }
402 return 0;
403 }
404
405 static unsigned long __init htab_get_table_size(void)
406 {
407 unsigned long mem_size, rnd_mem_size, pteg_count;
408
409 /* If hash size isn't already provided by the platform, we try to
410 * retrieve it from the device-tree. If it's not there neither, we
411 * calculate it now based on the total RAM size
412 */
413 if (ppc64_pft_size == 0)
414 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
415 if (ppc64_pft_size)
416 return 1UL << ppc64_pft_size;
417
418 /* round mem_size up to next power of 2 */
419 mem_size = lmb_phys_mem_size();
420 rnd_mem_size = 1UL << __ilog2(mem_size);
421 if (rnd_mem_size < mem_size)
422 rnd_mem_size <<= 1;
423
424 /* # pages / 2 */
425 pteg_count = max(rnd_mem_size >> (12 + 1), 1UL << 11);
426
427 return pteg_count << 7;
428 }
429
430 #ifdef CONFIG_MEMORY_HOTPLUG
431 void create_section_mapping(unsigned long start, unsigned long end)
432 {
433 BUG_ON(htab_bolt_mapping(start, end, __pa(start),
434 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_COHERENT | PP_RWXX,
435 mmu_linear_psize, mmu_kernel_ssize));
436 }
437 #endif /* CONFIG_MEMORY_HOTPLUG */
438
439 static inline void make_bl(unsigned int *insn_addr, void *func)
440 {
441 unsigned long funcp = *((unsigned long *)func);
442 int offset = funcp - (unsigned long)insn_addr;
443
444 *insn_addr = (unsigned int)(0x48000001 | (offset & 0x03fffffc));
445 flush_icache_range((unsigned long)insn_addr, 4+
446 (unsigned long)insn_addr);
447 }
448
449 static void __init htab_finish_init(void)
450 {
451 extern unsigned int *htab_call_hpte_insert1;
452 extern unsigned int *htab_call_hpte_insert2;
453 extern unsigned int *htab_call_hpte_remove;
454 extern unsigned int *htab_call_hpte_updatepp;
455
456 #ifdef CONFIG_PPC_HAS_HASH_64K
457 extern unsigned int *ht64_call_hpte_insert1;
458 extern unsigned int *ht64_call_hpte_insert2;
459 extern unsigned int *ht64_call_hpte_remove;
460 extern unsigned int *ht64_call_hpte_updatepp;
461
462 make_bl(ht64_call_hpte_insert1, ppc_md.hpte_insert);
463 make_bl(ht64_call_hpte_insert2, ppc_md.hpte_insert);
464 make_bl(ht64_call_hpte_remove, ppc_md.hpte_remove);
465 make_bl(ht64_call_hpte_updatepp, ppc_md.hpte_updatepp);
466 #endif /* CONFIG_PPC_HAS_HASH_64K */
467
468 make_bl(htab_call_hpte_insert1, ppc_md.hpte_insert);
469 make_bl(htab_call_hpte_insert2, ppc_md.hpte_insert);
470 make_bl(htab_call_hpte_remove, ppc_md.hpte_remove);
471 make_bl(htab_call_hpte_updatepp, ppc_md.hpte_updatepp);
472 }
473
474 void __init htab_initialize(void)
475 {
476 unsigned long table;
477 unsigned long pteg_count;
478 unsigned long mode_rw;
479 unsigned long base = 0, size = 0;
480 int i;
481
482 extern unsigned long tce_alloc_start, tce_alloc_end;
483
484 DBG(" -> htab_initialize()\n");
485
486 /* Initialize segment sizes */
487 htab_init_seg_sizes();
488
489 /* Initialize page sizes */
490 htab_init_page_sizes();
491
492 if (cpu_has_feature(CPU_FTR_1T_SEGMENT)) {
493 mmu_kernel_ssize = MMU_SEGSIZE_1T;
494 mmu_highuser_ssize = MMU_SEGSIZE_1T;
495 printk(KERN_INFO "Using 1TB segments\n");
496 }
497
498 /*
499 * Calculate the required size of the htab. We want the number of
500 * PTEGs to equal one half the number of real pages.
501 */
502 htab_size_bytes = htab_get_table_size();
503 pteg_count = htab_size_bytes >> 7;
504
505 htab_hash_mask = pteg_count - 1;
506
507 if (firmware_has_feature(FW_FEATURE_LPAR)) {
508 /* Using a hypervisor which owns the htab */
509 htab_address = NULL;
510 _SDR1 = 0;
511 } else {
512 /* Find storage for the HPT. Must be contiguous in
513 * the absolute address space.
514 */
515 table = lmb_alloc(htab_size_bytes, htab_size_bytes);
516
517 DBG("Hash table allocated at %lx, size: %lx\n", table,
518 htab_size_bytes);
519
520 htab_address = abs_to_virt(table);
521
522 /* htab absolute addr + encoded htabsize */
523 _SDR1 = table + __ilog2(pteg_count) - 11;
524
525 /* Initialize the HPT with no entries */
526 memset((void *)table, 0, htab_size_bytes);
527
528 /* Set SDR1 */
529 mtspr(SPRN_SDR1, _SDR1);
530 }
531
532 mode_rw = _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_COHERENT | PP_RWXX;
533
534 #ifdef CONFIG_DEBUG_PAGEALLOC
535 linear_map_hash_count = lmb_end_of_DRAM() >> PAGE_SHIFT;
536 linear_map_hash_slots = __va(lmb_alloc_base(linear_map_hash_count,
537 1, lmb.rmo_size));
538 memset(linear_map_hash_slots, 0, linear_map_hash_count);
539 #endif /* CONFIG_DEBUG_PAGEALLOC */
540
541 /* On U3 based machines, we need to reserve the DART area and
542 * _NOT_ map it to avoid cache paradoxes as it's remapped non
543 * cacheable later on
544 */
545
546 /* create bolted the linear mapping in the hash table */
547 for (i=0; i < lmb.memory.cnt; i++) {
548 base = (unsigned long)__va(lmb.memory.region[i].base);
549 size = lmb.memory.region[i].size;
550
551 DBG("creating mapping for region: %lx : %lx\n", base, size);
552
553 #ifdef CONFIG_U3_DART
554 /* Do not map the DART space. Fortunately, it will be aligned
555 * in such a way that it will not cross two lmb regions and
556 * will fit within a single 16Mb page.
557 * The DART space is assumed to be a full 16Mb region even if
558 * we only use 2Mb of that space. We will use more of it later
559 * for AGP GART. We have to use a full 16Mb large page.
560 */
561 DBG("DART base: %lx\n", dart_tablebase);
562
563 if (dart_tablebase != 0 && dart_tablebase >= base
564 && dart_tablebase < (base + size)) {
565 unsigned long dart_table_end = dart_tablebase + 16 * MB;
566 if (base != dart_tablebase)
567 BUG_ON(htab_bolt_mapping(base, dart_tablebase,
568 __pa(base), mode_rw,
569 mmu_linear_psize,
570 mmu_kernel_ssize));
571 if ((base + size) > dart_table_end)
572 BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB,
573 base + size,
574 __pa(dart_table_end),
575 mode_rw,
576 mmu_linear_psize,
577 mmu_kernel_ssize));
578 continue;
579 }
580 #endif /* CONFIG_U3_DART */
581 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
582 mode_rw, mmu_linear_psize, mmu_kernel_ssize));
583 }
584
585 /*
586 * If we have a memory_limit and we've allocated TCEs then we need to
587 * explicitly map the TCE area at the top of RAM. We also cope with the
588 * case that the TCEs start below memory_limit.
589 * tce_alloc_start/end are 16MB aligned so the mapping should work
590 * for either 4K or 16MB pages.
591 */
592 if (tce_alloc_start) {
593 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
594 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
595
596 if (base + size >= tce_alloc_start)
597 tce_alloc_start = base + size + 1;
598
599 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
600 __pa(tce_alloc_start), mode_rw,
601 mmu_linear_psize, mmu_kernel_ssize));
602 }
603
604 htab_finish_init();
605
606 DBG(" <- htab_initialize()\n");
607 }
608 #undef KB
609 #undef MB
610
611 void htab_initialize_secondary(void)
612 {
613 if (!firmware_has_feature(FW_FEATURE_LPAR))
614 mtspr(SPRN_SDR1, _SDR1);
615 }
616
617 /*
618 * Called by asm hashtable.S for doing lazy icache flush
619 */
620 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
621 {
622 struct page *page;
623
624 if (!pfn_valid(pte_pfn(pte)))
625 return pp;
626
627 page = pte_page(pte);
628
629 /* page is dirty */
630 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
631 if (trap == 0x400) {
632 __flush_dcache_icache(page_address(page));
633 set_bit(PG_arch_1, &page->flags);
634 } else
635 pp |= HPTE_R_N;
636 }
637 return pp;
638 }
639
640 /*
641 * Demote a segment to using 4k pages.
642 * For now this makes the whole process use 4k pages.
643 */
644 #ifdef CONFIG_PPC_64K_PAGES
645 static void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
646 {
647 if (mm->context.user_psize == MMU_PAGE_4K)
648 return;
649 slice_set_user_psize(mm, MMU_PAGE_4K);
650 #ifdef CONFIG_SPU_BASE
651 spu_flush_all_slbs(mm);
652 #endif
653 }
654 #endif /* CONFIG_PPC_64K_PAGES */
655
656 /* Result code is:
657 * 0 - handled
658 * 1 - normal page fault
659 * -1 - critical hash insertion error
660 */
661 int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
662 {
663 void *pgdir;
664 unsigned long vsid;
665 struct mm_struct *mm;
666 pte_t *ptep;
667 cpumask_t tmp;
668 int rc, user_region = 0, local = 0;
669 int psize, ssize;
670
671 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
672 ea, access, trap);
673
674 if ((ea & ~REGION_MASK) >= PGTABLE_RANGE) {
675 DBG_LOW(" out of pgtable range !\n");
676 return 1;
677 }
678
679 /* Get region & vsid */
680 switch (REGION_ID(ea)) {
681 case USER_REGION_ID:
682 user_region = 1;
683 mm = current->mm;
684 if (! mm) {
685 DBG_LOW(" user region with no mm !\n");
686 return 1;
687 }
688 #ifdef CONFIG_PPC_MM_SLICES
689 psize = get_slice_psize(mm, ea);
690 #else
691 psize = mm->context.user_psize;
692 #endif
693 ssize = user_segment_size(ea);
694 vsid = get_vsid(mm->context.id, ea, ssize);
695 break;
696 case VMALLOC_REGION_ID:
697 mm = &init_mm;
698 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
699 if (ea < VMALLOC_END)
700 psize = mmu_vmalloc_psize;
701 else
702 psize = mmu_io_psize;
703 ssize = mmu_kernel_ssize;
704 break;
705 default:
706 /* Not a valid range
707 * Send the problem up to do_page_fault
708 */
709 return 1;
710 }
711 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
712
713 /* Get pgdir */
714 pgdir = mm->pgd;
715 if (pgdir == NULL)
716 return 1;
717
718 /* Check CPU locality */
719 tmp = cpumask_of_cpu(smp_processor_id());
720 if (user_region && cpus_equal(mm->cpu_vm_mask, tmp))
721 local = 1;
722
723 #ifdef CONFIG_HUGETLB_PAGE
724 /* Handle hugepage regions */
725 if (HPAGE_SHIFT && psize == mmu_huge_psize) {
726 DBG_LOW(" -> huge page !\n");
727 return hash_huge_page(mm, access, ea, vsid, local, trap);
728 }
729 #endif /* CONFIG_HUGETLB_PAGE */
730
731 #ifndef CONFIG_PPC_64K_PAGES
732 /* If we use 4K pages and our psize is not 4K, then we are hitting
733 * a special driver mapping, we need to align the address before
734 * we fetch the PTE
735 */
736 if (psize != MMU_PAGE_4K)
737 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
738 #endif /* CONFIG_PPC_64K_PAGES */
739
740 /* Get PTE and page size from page tables */
741 ptep = find_linux_pte(pgdir, ea);
742 if (ptep == NULL || !pte_present(*ptep)) {
743 DBG_LOW(" no PTE !\n");
744 return 1;
745 }
746
747 #ifndef CONFIG_PPC_64K_PAGES
748 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
749 #else
750 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
751 pte_val(*(ptep + PTRS_PER_PTE)));
752 #endif
753 /* Pre-check access permissions (will be re-checked atomically
754 * in __hash_page_XX but this pre-check is a fast path
755 */
756 if (access & ~pte_val(*ptep)) {
757 DBG_LOW(" no access !\n");
758 return 1;
759 }
760
761 /* Do actual hashing */
762 #ifdef CONFIG_PPC_64K_PAGES
763 /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */
764 if (pte_val(*ptep) & _PAGE_4K_PFN) {
765 demote_segment_4k(mm, ea);
766 psize = MMU_PAGE_4K;
767 }
768
769 /* If this PTE is non-cacheable and we have restrictions on
770 * using non cacheable large pages, then we switch to 4k
771 */
772 if (mmu_ci_restrictions && psize == MMU_PAGE_64K &&
773 (pte_val(*ptep) & _PAGE_NO_CACHE)) {
774 if (user_region) {
775 demote_segment_4k(mm, ea);
776 psize = MMU_PAGE_4K;
777 } else if (ea < VMALLOC_END) {
778 /*
779 * some driver did a non-cacheable mapping
780 * in vmalloc space, so switch vmalloc
781 * to 4k pages
782 */
783 printk(KERN_ALERT "Reducing vmalloc segment "
784 "to 4kB pages because of "
785 "non-cacheable mapping\n");
786 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
787 #ifdef CONFIG_SPU_BASE
788 spu_flush_all_slbs(mm);
789 #endif
790 }
791 }
792 if (user_region) {
793 if (psize != get_paca()->context.user_psize) {
794 get_paca()->context.user_psize =
795 mm->context.user_psize;
796 slb_flush_and_rebolt();
797 }
798 } else if (get_paca()->vmalloc_sllp !=
799 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
800 get_paca()->vmalloc_sllp =
801 mmu_psize_defs[mmu_vmalloc_psize].sllp;
802 slb_vmalloc_update();
803 }
804 #endif /* CONFIG_PPC_64K_PAGES */
805
806 #ifdef CONFIG_PPC_HAS_HASH_64K
807 if (psize == MMU_PAGE_64K)
808 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
809 else
810 #endif /* CONFIG_PPC_HAS_HASH_64K */
811 rc = __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize);
812
813 #ifndef CONFIG_PPC_64K_PAGES
814 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
815 #else
816 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
817 pte_val(*(ptep + PTRS_PER_PTE)));
818 #endif
819 DBG_LOW(" -> rc=%d\n", rc);
820 return rc;
821 }
822 EXPORT_SYMBOL_GPL(hash_page);
823
824 void hash_preload(struct mm_struct *mm, unsigned long ea,
825 unsigned long access, unsigned long trap)
826 {
827 unsigned long vsid;
828 void *pgdir;
829 pte_t *ptep;
830 cpumask_t mask;
831 unsigned long flags;
832 int local = 0;
833 int ssize;
834
835 BUG_ON(REGION_ID(ea) != USER_REGION_ID);
836
837 #ifdef CONFIG_PPC_MM_SLICES
838 /* We only prefault standard pages for now */
839 if (unlikely(get_slice_psize(mm, ea) != mm->context.user_psize))
840 return;
841 #endif
842
843 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
844 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
845
846 /* Get Linux PTE if available */
847 pgdir = mm->pgd;
848 if (pgdir == NULL)
849 return;
850 ptep = find_linux_pte(pgdir, ea);
851 if (!ptep)
852 return;
853
854 #ifdef CONFIG_PPC_64K_PAGES
855 /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on
856 * a 64K kernel), then we don't preload, hash_page() will take
857 * care of it once we actually try to access the page.
858 * That way we don't have to duplicate all of the logic for segment
859 * page size demotion here
860 */
861 if (pte_val(*ptep) & (_PAGE_4K_PFN | _PAGE_NO_CACHE))
862 return;
863 #endif /* CONFIG_PPC_64K_PAGES */
864
865 /* Get VSID */
866 ssize = user_segment_size(ea);
867 vsid = get_vsid(mm->context.id, ea, ssize);
868
869 /* Hash doesn't like irqs */
870 local_irq_save(flags);
871
872 /* Is that local to this CPU ? */
873 mask = cpumask_of_cpu(smp_processor_id());
874 if (cpus_equal(mm->cpu_vm_mask, mask))
875 local = 1;
876
877 /* Hash it in */
878 #ifdef CONFIG_PPC_HAS_HASH_64K
879 if (mm->context.user_psize == MMU_PAGE_64K)
880 __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
881 else
882 #endif /* CONFIG_PPC_HAS_HASH_64K */
883 __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize);
884
885 local_irq_restore(flags);
886 }
887
888 void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int ssize,
889 int local)
890 {
891 unsigned long hash, index, shift, hidx, slot;
892
893 DBG_LOW("flush_hash_page(va=%016x)\n", va);
894 pte_iterate_hashed_subpages(pte, psize, va, index, shift) {
895 hash = hpt_hash(va, shift, ssize);
896 hidx = __rpte_to_hidx(pte, index);
897 if (hidx & _PTEIDX_SECONDARY)
898 hash = ~hash;
899 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
900 slot += hidx & _PTEIDX_GROUP_IX;
901 DBG_LOW(" sub %d: hash=%x, hidx=%x\n", index, slot, hidx);
902 ppc_md.hpte_invalidate(slot, va, psize, ssize, local);
903 } pte_iterate_hashed_end();
904 }
905
906 void flush_hash_range(unsigned long number, int local)
907 {
908 if (ppc_md.flush_hash_range)
909 ppc_md.flush_hash_range(number, local);
910 else {
911 int i;
912 struct ppc64_tlb_batch *batch =
913 &__get_cpu_var(ppc64_tlb_batch);
914
915 for (i = 0; i < number; i++)
916 flush_hash_page(batch->vaddr[i], batch->pte[i],
917 batch->psize, batch->ssize, local);
918 }
919 }
920
921 /*
922 * low_hash_fault is called when we the low level hash code failed
923 * to instert a PTE due to an hypervisor error
924 */
925 void low_hash_fault(struct pt_regs *regs, unsigned long address)
926 {
927 if (user_mode(regs)) {
928 siginfo_t info;
929
930 info.si_signo = SIGBUS;
931 info.si_errno = 0;
932 info.si_code = BUS_ADRERR;
933 info.si_addr = (void __user *)address;
934 force_sig_info(SIGBUS, &info, current);
935 return;
936 }
937 bad_page_fault(regs, address, SIGBUS);
938 }
939
940 #ifdef CONFIG_DEBUG_PAGEALLOC
941 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
942 {
943 unsigned long hash, hpteg;
944 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
945 unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
946 unsigned long mode = _PAGE_ACCESSED | _PAGE_DIRTY |
947 _PAGE_COHERENT | PP_RWXX | HPTE_R_N;
948 int ret;
949
950 hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
951 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
952
953 ret = ppc_md.hpte_insert(hpteg, va, __pa(vaddr),
954 mode, HPTE_V_BOLTED,
955 mmu_linear_psize, mmu_kernel_ssize);
956 BUG_ON (ret < 0);
957 spin_lock(&linear_map_hash_lock);
958 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
959 linear_map_hash_slots[lmi] = ret | 0x80;
960 spin_unlock(&linear_map_hash_lock);
961 }
962
963 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
964 {
965 unsigned long hash, hidx, slot;
966 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
967 unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
968
969 hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
970 spin_lock(&linear_map_hash_lock);
971 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
972 hidx = linear_map_hash_slots[lmi] & 0x7f;
973 linear_map_hash_slots[lmi] = 0;
974 spin_unlock(&linear_map_hash_lock);
975 if (hidx & _PTEIDX_SECONDARY)
976 hash = ~hash;
977 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
978 slot += hidx & _PTEIDX_GROUP_IX;
979 ppc_md.hpte_invalidate(slot, va, mmu_linear_psize, mmu_kernel_ssize, 0);
980 }
981
982 void kernel_map_pages(struct page *page, int numpages, int enable)
983 {
984 unsigned long flags, vaddr, lmi;
985 int i;
986
987 local_irq_save(flags);
988 for (i = 0; i < numpages; i++, page++) {
989 vaddr = (unsigned long)page_address(page);
990 lmi = __pa(vaddr) >> PAGE_SHIFT;
991 if (lmi >= linear_map_hash_count)
992 continue;
993 if (enable)
994 kernel_map_linear_page(vaddr, lmi);
995 else
996 kernel_unmap_linear_page(vaddr, lmi);
997 }
998 local_irq_restore(flags);
999 }
1000 #endif /* CONFIG_DEBUG_PAGEALLOC */
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