arch/ppc/syslib/gt64260_pic.c

   1 /*
   2  * Interrupt controller support for Galileo's GT64260.
   3  *
   4  * Author: Chris Zankel <source@mvista.com>
   5  * Modified by: Mark A. Greer <mgreer@mvista.com>
   6  *
   7  * Based on sources from Rabeeh Khoury / Galileo Technology
   8  *
   9  * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
  10  * the terms of the GNU General Public License version 2.  This program
  11  * is licensed "as is" without any warranty of any kind, whether express
  12  * or implied.
  13  */
  14
  15 /*
  16  * This file contains the specific functions to support the GT64260
  17  * interrupt controller.
  18  *
  19  * The GT64260 has two main interrupt registers (high and low) that
  20  * summarizes the interrupts generated by the units of the GT64260.
  21  * Each bit is assigned to an interrupt number, where the low register
  22  * are assigned from IRQ0 to IRQ31 and the high cause register
  23  * from IRQ32 to IRQ63
  24  * The GPP (General Purpose Port) interrupts are assigned from IRQ64 (GPP0)
  25  * to IRQ95 (GPP31).
  26  * get_irq() returns the lowest interrupt number that is currently asserted.
  27  *
  28  * Note:
  29  *  - This driver does not initialize the GPP when used as an interrupt
  30  *    input.
  31  */
  32
  33 #include <linux/stddef.h>
  34 #include <linux/init.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/sched.h>
  37 #include <linux/signal.h>
  38 #include <linux/stddef.h>
  39 #include <linux/delay.h>
  40 #include <linux/irq.h>
  41
  42 #include <asm/io.h>
  43 #include <asm/system.h>
  44 #include <asm/irq.h>
  45 #include <asm/mv64x60.h>
  46 #include <asm/machdep.h>
  47
  48 #define CPU_INTR_STR    "gt64260 cpu interface error"
  49 #define PCI0_INTR_STR   "gt64260 pci 0 error"
  50 #define PCI1_INTR_STR   "gt64260 pci 1 error"
  51
  52 /* ========================== forward declaration ========================== */
  53
  54 static void gt64260_unmask_irq(unsigned int);
  55 static void gt64260_mask_irq(unsigned int);
  56
  57 /* ========================== local declarations =========================== */
  58
  59 struct hw_interrupt_type gt64260_pic = {
  60         .typename = " gt64260_pic ",
  61         .enable   = gt64260_unmask_irq,
  62         .disable  = gt64260_mask_irq,
  63         .ack      = gt64260_mask_irq,
  64         .end      = gt64260_unmask_irq,
  65 };
  66
  67 u32 gt64260_irq_base = 0;       /* GT64260 handles the next 96 IRQs from here */
  68
  69 static struct mv64x60_handle bh;
  70
  71 /* gt64260_init_irq()
  72  *
  73  *  This function initializes the interrupt controller. It assigns
  74  *  all interrupts from IRQ0 to IRQ95 to the gt64260 interrupt controller.
  75  *
  76  * Note:
  77  *  We register all GPP inputs as interrupt source, but disable them.
  78  */
  79 void __init
  80 gt64260_init_irq(void)
  81 {
  82         int i;
  83
  84         if (ppc_md.progress)
  85                 ppc_md.progress("gt64260_init_irq: enter", 0x0);
  86
  87         bh.v_base = mv64x60_get_bridge_vbase();
  88
  89         ppc_cached_irq_mask[0] = 0;
  90         ppc_cached_irq_mask[1] = 0x0f000000;    /* Enable GPP intrs */
  91         ppc_cached_irq_mask[2] = 0;
  92
  93         /* disable all interrupts and clear current interrupts */
  94         mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, ppc_cached_irq_mask[2]);
  95         mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, 0);
  96         mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_LO, ppc_cached_irq_mask[0]);
  97         mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_HI, ppc_cached_irq_mask[1]);
  98
  99         /* use the gt64260 for all (possible) interrupt sources */
 100         for (i = gt64260_irq_base; i < (gt64260_irq_base + 96); i++)
 101                 irq_desc[i].chip = &gt64260_pic;
 102
 103         if (ppc_md.progress)
 104                 ppc_md.progress("gt64260_init_irq: exit", 0x0);
 105 }
 106
 107 /*
 108  * gt64260_get_irq()
 109  *
 110  *  This function returns the lowest interrupt number of all interrupts that
 111  *  are currently asserted.
 112  *
 113  * Output Variable(s):
 114  *  None.
 115  *
 116  * Returns:
 117  *  int <interrupt number> or -2 (bogus interrupt)
 118  */
 119 int
 120 gt64260_get_irq(void)
 121 {
 122         int irq;
 123         int irq_gpp;
 124
 125         irq = mv64x60_read(&bh, GT64260_IC_MAIN_CAUSE_LO);
 126         irq = __ilog2((irq & 0x3dfffffe) & ppc_cached_irq_mask[0]);
 127
 128         if (irq == -1) {
 129                 irq = mv64x60_read(&bh, GT64260_IC_MAIN_CAUSE_HI);
 130                 irq = __ilog2((irq & 0x0f000db7) & ppc_cached_irq_mask[1]);
 131
 132                 if (irq == -1)
 133                         irq = -2; /* bogus interrupt, should never happen */
 134                 else {
 135                         if (irq >= 24) {
 136                                 irq_gpp = mv64x60_read(&bh,
 137                                         MV64x60_GPP_INTR_CAUSE);
 138                                 irq_gpp = __ilog2(irq_gpp &
 139                                         ppc_cached_irq_mask[2]);
 140
 141                                 if (irq_gpp == -1)
 142                                         irq = -2;
 143                                 else {
 144                                         irq = irq_gpp + 64;
 145                                         mv64x60_write(&bh,
 146                                                 MV64x60_GPP_INTR_CAUSE,
 147                                                 ~(1 << (irq - 64)));
 148                                 }
 149                         } else
 150                                 irq += 32;
 151                 }
 152         }
 153
 154         (void)mv64x60_read(&bh, MV64x60_GPP_INTR_CAUSE);
 155
 156         if (irq < 0)
 157                 return (irq);
 158         else
 159                 return (gt64260_irq_base + irq);
 160 }
 161
 162 /* gt64260_unmask_irq()
 163  *
 164  *  This function enables an interrupt.
 165  *
 166  * Input Variable(s):
 167  *  unsigned int        interrupt number (IRQ0...IRQ95).
 168  *
 169  * Output Variable(s):
 170  *  None.
 171  *
 172  * Returns:
 173  *  void
 174  */
 175 static void
 176 gt64260_unmask_irq(unsigned int irq)
 177 {
 178         irq -= gt64260_irq_base;
 179
 180         if (irq > 31)
 181                 if (irq > 63) /* unmask GPP irq */
 182                         mv64x60_write(&bh, MV64x60_GPP_INTR_MASK,
 183                                 ppc_cached_irq_mask[2] |= (1 << (irq - 64)));
 184                 else /* mask high interrupt register */
 185                         mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_HI,
 186                                 ppc_cached_irq_mask[1] |= (1 << (irq - 32)));
 187         else /* mask low interrupt register */
 188                 mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_LO,
 189                         ppc_cached_irq_mask[0] |= (1 << irq));
 190
 191         (void)mv64x60_read(&bh, MV64x60_GPP_INTR_MASK);
 192         return;
 193 }
 194
 195 /* gt64260_mask_irq()
 196  *
 197  *  This function disables the requested interrupt.
 198  *
 199  * Input Variable(s):
 200  *  unsigned int        interrupt number (IRQ0...IRQ95).
 201  *
 202  * Output Variable(s):
 203  *  None.
 204  *
 205  * Returns:
 206  *  void
 207  */
 208 static void
 209 gt64260_mask_irq(unsigned int irq)
 210 {
 211         irq -= gt64260_irq_base;
 212
 213         if (irq > 31)
 214                 if (irq > 63) /* mask GPP irq */
 215                         mv64x60_write(&bh, MV64x60_GPP_INTR_MASK,
 216                                 ppc_cached_irq_mask[2] &= ~(1 << (irq - 64)));
 217                 else /* mask high interrupt register */
 218                         mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_HI,
 219                                 ppc_cached_irq_mask[1] &= ~(1 << (irq - 32)));
 220         else /* mask low interrupt register */
 221                 mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_LO,
 222                         ppc_cached_irq_mask[0] &= ~(1 << irq));
 223
 224         (void)mv64x60_read(&bh, MV64x60_GPP_INTR_MASK);
 225         return;
 226 }
 227
 228 static irqreturn_t
 229 gt64260_cpu_error_int_handler(int irq, void *dev_id)
 230 {
 231         printk(KERN_ERR "gt64260_cpu_error_int_handler: %s 0x%08x\n",
 232                 "Error on CPU interface - Cause regiser",
 233                 mv64x60_read(&bh, MV64x60_CPU_ERR_CAUSE));
 234         printk(KERN_ERR "\tCPU error register dump:\n");
 235         printk(KERN_ERR "\tAddress low  0x%08x\n",
 236                mv64x60_read(&bh, MV64x60_CPU_ERR_ADDR_LO));
 237         printk(KERN_ERR "\tAddress high 0x%08x\n",
 238                mv64x60_read(&bh, MV64x60_CPU_ERR_ADDR_HI));
 239         printk(KERN_ERR "\tData low     0x%08x\n",
 240                mv64x60_read(&bh, MV64x60_CPU_ERR_DATA_LO));
 241         printk(KERN_ERR "\tData high    0x%08x\n",
 242                mv64x60_read(&bh, MV64x60_CPU_ERR_DATA_HI));
 243         printk(KERN_ERR "\tParity       0x%08x\n",
 244                mv64x60_read(&bh, MV64x60_CPU_ERR_PARITY));
 245         mv64x60_write(&bh, MV64x60_CPU_ERR_CAUSE, 0);
 246         return IRQ_HANDLED;
 247 }
 248
 249 static irqreturn_t
 250 gt64260_pci_error_int_handler(int irq, void *dev_id)
 251 {
 252         u32 val;
 253         unsigned int pci_bus = (unsigned int)dev_id;
 254
 255         if (pci_bus == 0) {     /* Error on PCI 0 */
 256                 val = mv64x60_read(&bh, MV64x60_PCI0_ERR_CAUSE);
 257                 printk(KERN_ERR "%s: Error in PCI %d Interface\n",
 258                         "gt64260_pci_error_int_handler", pci_bus);
 259                 printk(KERN_ERR "\tPCI %d error register dump:\n", pci_bus);
 260                 printk(KERN_ERR "\tCause register 0x%08x\n", val);
 261                 printk(KERN_ERR "\tAddress Low    0x%08x\n",
 262                        mv64x60_read(&bh, MV64x60_PCI0_ERR_ADDR_LO));
 263                 printk(KERN_ERR "\tAddress High   0x%08x\n",
 264                        mv64x60_read(&bh, MV64x60_PCI0_ERR_ADDR_HI));
 265                 printk(KERN_ERR "\tAttribute      0x%08x\n",
 266                        mv64x60_read(&bh, MV64x60_PCI0_ERR_DATA_LO));
 267                 printk(KERN_ERR "\tCommand        0x%08x\n",
 268                        mv64x60_read(&bh, MV64x60_PCI0_ERR_CMD));
 269                 mv64x60_write(&bh, MV64x60_PCI0_ERR_CAUSE, ~val);
 270         }
 271         if (pci_bus == 1) {     /* Error on PCI 1 */
 272                 val = mv64x60_read(&bh, MV64x60_PCI1_ERR_CAUSE);
 273                 printk(KERN_ERR "%s: Error in PCI %d Interface\n",
 274                         "gt64260_pci_error_int_handler", pci_bus);
 275                 printk(KERN_ERR "\tPCI %d error register dump:\n", pci_bus);
 276                 printk(KERN_ERR "\tCause register 0x%08x\n", val);
 277                 printk(KERN_ERR "\tAddress Low    0x%08x\n",
 278                        mv64x60_read(&bh, MV64x60_PCI1_ERR_ADDR_LO));
 279                 printk(KERN_ERR "\tAddress High   0x%08x\n",
 280                        mv64x60_read(&bh, MV64x60_PCI1_ERR_ADDR_HI));
 281                 printk(KERN_ERR "\tAttribute      0x%08x\n",
 282                        mv64x60_read(&bh, MV64x60_PCI1_ERR_DATA_LO));
 283                 printk(KERN_ERR "\tCommand        0x%08x\n",
 284                        mv64x60_read(&bh, MV64x60_PCI1_ERR_CMD));
 285                 mv64x60_write(&bh, MV64x60_PCI1_ERR_CAUSE, ~val);
 286         }
 287         return IRQ_HANDLED;
 288 }
 289
 290 static int __init
 291 gt64260_register_hdlrs(void)
 292 {
 293         int rc;
 294
 295         /* Register CPU interface error interrupt handler */
 296         if ((rc = request_irq(MV64x60_IRQ_CPU_ERR,
 297                 gt64260_cpu_error_int_handler, IRQF_DISABLED, CPU_INTR_STR, 0)))
 298                 printk(KERN_WARNING "Can't register cpu error handler: %d", rc);
 299
 300         mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0);
 301         mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0x000000fe);
 302
 303         /* Register PCI 0 error interrupt handler */
 304         if ((rc = request_irq(MV64360_IRQ_PCI0, gt64260_pci_error_int_handler,
 305                     IRQF_DISABLED, PCI0_INTR_STR, (void *)0)))
 306                 printk(KERN_WARNING "Can't register pci 0 error handler: %d",
 307                         rc);
 308
 309         mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, 0);
 310         mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, 0x003c0c24);
 311
 312         /* Register PCI 1 error interrupt handler */
 313         if ((rc = request_irq(MV64360_IRQ_PCI1, gt64260_pci_error_int_handler,
 314                     IRQF_DISABLED, PCI1_INTR_STR, (void *)1)))
 315                 printk(KERN_WARNING "Can't register pci 1 error handler: %d",
 316                         rc);
 317
 318         mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, 0);
 319         mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, 0x003c0c24);
 320
 321         return 0;
 322 }
 323
 324 arch_initcall(gt64260_register_hdlrs);