2 * IPIC private definitions and structure.
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
6 * Copyright 2005 Freescale Semiconductor, Inc
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
18 #define MPC83xx_IPIC_SIZE (0x00100)
20 /* System Global Interrupt Configuration Register */
21 #define SICFR_IPSA 0x00010000
22 #define SICFR_IPSD 0x00080000
23 #define SICFR_MPSA 0x00200000
24 #define SICFR_MPSB 0x00400000
26 /* System External Interrupt Mask Register */
27 #define SEMSR_SIRQ0 0x00008000
29 /* System Error Control Register */
30 #define SERCR_MCPR 0x00000001
33 volatile u32 __iomem
*regs
;
34 unsigned int irq_offset
;
38 u8 pend
; /* pending register offset from base */
39 u8 mask
; /* mask register offset from base */
40 u8 prio
; /* priority register offset from base */
41 u8 force
; /* force register offset from base */
42 u8 bit
; /* register bit position (as per doc)
43 bit mask = 1 << (31 - bit) */
44 u8 prio_mask
; /* priority mask value */
47 #endif /* __IPIC_H__ */