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[SCSI] qla1280: convert to use the data buffer accessors
[linux-2.6/verdex.git] / arch / ppc / syslib / mv64x60.c
blob2744b8a6f66aee66daa87d9f97332f54afd2e6f2
1 /*
2 * Common routines for the Marvell/Galileo Discovery line of host bridges
3 * (gt64260, mv64360, mv64460, ...).
4 *
5 * Author: Mark A. Greer <mgreer@mvista.com>
6 *
7 * 2004 (c) MontaVista, Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/pci.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17 #include <linux/mutex.h>
18 #include <linux/string.h>
19 #include <linux/spinlock.h>
20 #include <linux/mv643xx.h>
21 #include <linux/platform_device.h>
22
23 #include <asm/byteorder.h>
24 #include <asm/io.h>
25 #include <asm/irq.h>
26 #include <asm/uaccess.h>
27 #include <asm/machdep.h>
28 #include <asm/pci-bridge.h>
29 #include <asm/delay.h>
30 #include <asm/mv64x60.h>
31
32
33 u8 mv64x60_pci_exclude_bridge = 1;
34 DEFINE_SPINLOCK(mv64x60_lock);
35
36 static phys_addr_t mv64x60_bridge_pbase;
37 static void __iomem *mv64x60_bridge_vbase;
38 static u32 mv64x60_bridge_type = MV64x60_TYPE_INVALID;
39 static u32 mv64x60_bridge_rev;
40 #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
41 static struct pci_controller sysfs_hose_a;
42 #endif
43
44 static u32 gt64260_translate_size(u32 base, u32 size, u32 num_bits);
45 static u32 gt64260_untranslate_size(u32 base, u32 size, u32 num_bits);
46 static void gt64260_set_pci2mem_window(struct pci_controller *hose, u32 bus,
47 u32 window, u32 base);
48 static void gt64260_set_pci2regs_window(struct mv64x60_handle *bh,
49 struct pci_controller *hose, u32 bus, u32 base);
50 static u32 gt64260_is_enabled_32bit(struct mv64x60_handle *bh, u32 window);
51 static void gt64260_enable_window_32bit(struct mv64x60_handle *bh, u32 window);
52 static void gt64260_disable_window_32bit(struct mv64x60_handle *bh, u32 window);
53 static void gt64260_enable_window_64bit(struct mv64x60_handle *bh, u32 window);
54 static void gt64260_disable_window_64bit(struct mv64x60_handle *bh, u32 window);
55 static void gt64260_disable_all_windows(struct mv64x60_handle *bh,
56 struct mv64x60_setup_info *si);
57 static void gt64260a_chip_specific_init(struct mv64x60_handle *bh,
58 struct mv64x60_setup_info *si);
59 static void gt64260b_chip_specific_init(struct mv64x60_handle *bh,
60 struct mv64x60_setup_info *si);
61
62 static u32 mv64360_translate_size(u32 base, u32 size, u32 num_bits);
63 static u32 mv64360_untranslate_size(u32 base, u32 size, u32 num_bits);
64 static void mv64360_set_pci2mem_window(struct pci_controller *hose, u32 bus,
65 u32 window, u32 base);
66 static void mv64360_set_pci2regs_window(struct mv64x60_handle *bh,
67 struct pci_controller *hose, u32 bus, u32 base);
68 static u32 mv64360_is_enabled_32bit(struct mv64x60_handle *bh, u32 window);
69 static void mv64360_enable_window_32bit(struct mv64x60_handle *bh, u32 window);
70 static void mv64360_disable_window_32bit(struct mv64x60_handle *bh, u32 window);
71 static void mv64360_enable_window_64bit(struct mv64x60_handle *bh, u32 window);
72 static void mv64360_disable_window_64bit(struct mv64x60_handle *bh, u32 window);
73 static void mv64360_disable_all_windows(struct mv64x60_handle *bh,
74 struct mv64x60_setup_info *si);
75 static void mv64360_config_io2mem_windows(struct mv64x60_handle *bh,
76 struct mv64x60_setup_info *si,
77 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
78 static void mv64360_set_mpsc2regs_window(struct mv64x60_handle *bh, u32 base);
79 static void mv64360_chip_specific_init(struct mv64x60_handle *bh,
80 struct mv64x60_setup_info *si);
81 static void mv64460_chip_specific_init(struct mv64x60_handle *bh,
82 struct mv64x60_setup_info *si);
83
84
85 /*
86 * Define tables that have the chip-specific info for each type of
87 * Marvell bridge chip.
88 */
89 static struct mv64x60_chip_info gt64260a_ci __initdata = { /* GT64260A */
90 .translate_size = gt64260_translate_size,
91 .untranslate_size = gt64260_untranslate_size,
92 .set_pci2mem_window = gt64260_set_pci2mem_window,
93 .set_pci2regs_window = gt64260_set_pci2regs_window,
94 .is_enabled_32bit = gt64260_is_enabled_32bit,
95 .enable_window_32bit = gt64260_enable_window_32bit,
96 .disable_window_32bit = gt64260_disable_window_32bit,
97 .enable_window_64bit = gt64260_enable_window_64bit,
98 .disable_window_64bit = gt64260_disable_window_64bit,
99 .disable_all_windows = gt64260_disable_all_windows,
100 .chip_specific_init = gt64260a_chip_specific_init,
101 .window_tab_32bit = gt64260_32bit_windows,
102 .window_tab_64bit = gt64260_64bit_windows,
103 };
104
105 static struct mv64x60_chip_info gt64260b_ci __initdata = { /* GT64260B */
106 .translate_size = gt64260_translate_size,
107 .untranslate_size = gt64260_untranslate_size,
108 .set_pci2mem_window = gt64260_set_pci2mem_window,
109 .set_pci2regs_window = gt64260_set_pci2regs_window,
110 .is_enabled_32bit = gt64260_is_enabled_32bit,
111 .enable_window_32bit = gt64260_enable_window_32bit,
112 .disable_window_32bit = gt64260_disable_window_32bit,
113 .enable_window_64bit = gt64260_enable_window_64bit,
114 .disable_window_64bit = gt64260_disable_window_64bit,
115 .disable_all_windows = gt64260_disable_all_windows,
116 .chip_specific_init = gt64260b_chip_specific_init,
117 .window_tab_32bit = gt64260_32bit_windows,
118 .window_tab_64bit = gt64260_64bit_windows,
119 };
120
121 static struct mv64x60_chip_info mv64360_ci __initdata = { /* MV64360 */
122 .translate_size = mv64360_translate_size,
123 .untranslate_size = mv64360_untranslate_size,
124 .set_pci2mem_window = mv64360_set_pci2mem_window,
125 .set_pci2regs_window = mv64360_set_pci2regs_window,
126 .is_enabled_32bit = mv64360_is_enabled_32bit,
127 .enable_window_32bit = mv64360_enable_window_32bit,
128 .disable_window_32bit = mv64360_disable_window_32bit,
129 .enable_window_64bit = mv64360_enable_window_64bit,
130 .disable_window_64bit = mv64360_disable_window_64bit,
131 .disable_all_windows = mv64360_disable_all_windows,
132 .config_io2mem_windows = mv64360_config_io2mem_windows,
133 .set_mpsc2regs_window = mv64360_set_mpsc2regs_window,
134 .chip_specific_init = mv64360_chip_specific_init,
135 .window_tab_32bit = mv64360_32bit_windows,
136 .window_tab_64bit = mv64360_64bit_windows,
137 };
138
139 static struct mv64x60_chip_info mv64460_ci __initdata = { /* MV64460 */
140 .translate_size = mv64360_translate_size,
141 .untranslate_size = mv64360_untranslate_size,
142 .set_pci2mem_window = mv64360_set_pci2mem_window,
143 .set_pci2regs_window = mv64360_set_pci2regs_window,
144 .is_enabled_32bit = mv64360_is_enabled_32bit,
145 .enable_window_32bit = mv64360_enable_window_32bit,
146 .disable_window_32bit = mv64360_disable_window_32bit,
147 .enable_window_64bit = mv64360_enable_window_64bit,
148 .disable_window_64bit = mv64360_disable_window_64bit,
149 .disable_all_windows = mv64360_disable_all_windows,
150 .config_io2mem_windows = mv64360_config_io2mem_windows,
151 .set_mpsc2regs_window = mv64360_set_mpsc2regs_window,
152 .chip_specific_init = mv64460_chip_specific_init,
153 .window_tab_32bit = mv64360_32bit_windows,
154 .window_tab_64bit = mv64360_64bit_windows,
155 };
156
157 /*
158 *****************************************************************************
159 *
160 * Platform Device Definitions
161 *
162 *****************************************************************************
163 */
164 #ifdef CONFIG_SERIAL_MPSC
165 static struct mpsc_shared_pdata mv64x60_mpsc_shared_pdata = {
166 .mrr_val = 0x3ffffe38,
167 .rcrr_val = 0,
168 .tcrr_val = 0,
169 .intr_cause_val = 0,
170 .intr_mask_val = 0,
171 };
172
173 static struct resource mv64x60_mpsc_shared_resources[] = {
174 /* Do not change the order of the IORESOURCE_MEM resources */
175 [0] = {
176 .name = "mpsc routing base",
177 .start = MV64x60_MPSC_ROUTING_OFFSET,
178 .end = MV64x60_MPSC_ROUTING_OFFSET +
179 MPSC_ROUTING_REG_BLOCK_SIZE - 1,
180 .flags = IORESOURCE_MEM,
181 },
182 [1] = {
183 .name = "sdma intr base",
184 .start = MV64x60_SDMA_INTR_OFFSET,
185 .end = MV64x60_SDMA_INTR_OFFSET +
186 MPSC_SDMA_INTR_REG_BLOCK_SIZE - 1,
187 .flags = IORESOURCE_MEM,
188 },
189 };
190
191 static struct platform_device mpsc_shared_device = { /* Shared device */
192 .name = MPSC_SHARED_NAME,
193 .id = 0,
194 .num_resources = ARRAY_SIZE(mv64x60_mpsc_shared_resources),
195 .resource = mv64x60_mpsc_shared_resources,
196 .dev = {
197 .platform_data = &mv64x60_mpsc_shared_pdata,
198 },
199 };
200
201 static struct mpsc_pdata mv64x60_mpsc0_pdata = {
202 .mirror_regs = 0,
203 .cache_mgmt = 0,
204 .max_idle = 0,
205 .default_baud = 9600,
206 .default_bits = 8,
207 .default_parity = 'n',
208 .default_flow = 'n',
209 .chr_1_val = 0x00000000,
210 .chr_2_val = 0x00000000,
211 .chr_10_val = 0x00000003,
212 .mpcr_val = 0,
213 .bcr_val = 0,
214 .brg_can_tune = 0,
215 .brg_clk_src = 8, /* Default to TCLK */
216 .brg_clk_freq = 100000000, /* Default to 100 MHz */
217 };
218
219 static struct resource mv64x60_mpsc0_resources[] = {
220 /* Do not change the order of the IORESOURCE_MEM resources */
221 [0] = {
222 .name = "mpsc 0 base",
223 .start = MV64x60_MPSC_0_OFFSET,
224 .end = MV64x60_MPSC_0_OFFSET + MPSC_REG_BLOCK_SIZE - 1,
225 .flags = IORESOURCE_MEM,
226 },
227 [1] = {
228 .name = "sdma 0 base",
229 .start = MV64x60_SDMA_0_OFFSET,
230 .end = MV64x60_SDMA_0_OFFSET + MPSC_SDMA_REG_BLOCK_SIZE - 1,
231 .flags = IORESOURCE_MEM,
232 },
233 [2] = {
234 .name = "brg 0 base",
235 .start = MV64x60_BRG_0_OFFSET,
236 .end = MV64x60_BRG_0_OFFSET + MPSC_BRG_REG_BLOCK_SIZE - 1,
237 .flags = IORESOURCE_MEM,
238 },
239 [3] = {
240 .name = "sdma 0 irq",
241 .start = MV64x60_IRQ_SDMA_0,
242 .end = MV64x60_IRQ_SDMA_0,
243 .flags = IORESOURCE_IRQ,
244 },
245 };
246
247 static struct platform_device mpsc0_device = {
248 .name = MPSC_CTLR_NAME,
249 .id = 0,
250 .num_resources = ARRAY_SIZE(mv64x60_mpsc0_resources),
251 .resource = mv64x60_mpsc0_resources,
252 .dev = {
253 .platform_data = &mv64x60_mpsc0_pdata,
254 },
255 };
256
257 static struct mpsc_pdata mv64x60_mpsc1_pdata = {
258 .mirror_regs = 0,
259 .cache_mgmt = 0,
260 .max_idle = 0,
261 .default_baud = 9600,
262 .default_bits = 8,
263 .default_parity = 'n',
264 .default_flow = 'n',
265 .chr_1_val = 0x00000000,
266 .chr_1_val = 0x00000000,
267 .chr_2_val = 0x00000000,
268 .chr_10_val = 0x00000003,
269 .mpcr_val = 0,
270 .bcr_val = 0,
271 .brg_can_tune = 0,
272 .brg_clk_src = 8, /* Default to TCLK */
273 .brg_clk_freq = 100000000, /* Default to 100 MHz */
274 };
275
276 static struct resource mv64x60_mpsc1_resources[] = {
277 /* Do not change the order of the IORESOURCE_MEM resources */
278 [0] = {
279 .name = "mpsc 1 base",
280 .start = MV64x60_MPSC_1_OFFSET,
281 .end = MV64x60_MPSC_1_OFFSET + MPSC_REG_BLOCK_SIZE - 1,
282 .flags = IORESOURCE_MEM,
283 },
284 [1] = {
285 .name = "sdma 1 base",
286 .start = MV64x60_SDMA_1_OFFSET,
287 .end = MV64x60_SDMA_1_OFFSET + MPSC_SDMA_REG_BLOCK_SIZE - 1,
288 .flags = IORESOURCE_MEM,
289 },
290 [2] = {
291 .name = "brg 1 base",
292 .start = MV64x60_BRG_1_OFFSET,
293 .end = MV64x60_BRG_1_OFFSET + MPSC_BRG_REG_BLOCK_SIZE - 1,
294 .flags = IORESOURCE_MEM,
295 },
296 [3] = {
297 .name = "sdma 1 irq",
298 .start = MV64360_IRQ_SDMA_1,
299 .end = MV64360_IRQ_SDMA_1,
300 .flags = IORESOURCE_IRQ,
301 },
302 };
303
304 static struct platform_device mpsc1_device = {
305 .name = MPSC_CTLR_NAME,
306 .id = 1,
307 .num_resources = ARRAY_SIZE(mv64x60_mpsc1_resources),
308 .resource = mv64x60_mpsc1_resources,
309 .dev = {
310 .platform_data = &mv64x60_mpsc1_pdata,
311 },
312 };
313 #endif
314
315 #if defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE)
316 static struct resource mv64x60_eth_shared_resources[] = {
317 [0] = {
318 .name = "ethernet shared base",
319 .start = MV643XX_ETH_SHARED_REGS,
320 .end = MV643XX_ETH_SHARED_REGS +
321 MV643XX_ETH_SHARED_REGS_SIZE - 1,
322 .flags = IORESOURCE_MEM,
323 },
324 };
325
326 static struct platform_device mv64x60_eth_shared_device = {
327 .name = MV643XX_ETH_SHARED_NAME,
328 .id = 0,
329 .num_resources = ARRAY_SIZE(mv64x60_eth_shared_resources),
330 .resource = mv64x60_eth_shared_resources,
331 };
332
333 #ifdef CONFIG_MV643XX_ETH_0
334 static struct resource mv64x60_eth0_resources[] = {
335 [0] = {
336 .name = "eth0 irq",
337 .start = MV64x60_IRQ_ETH_0,
338 .end = MV64x60_IRQ_ETH_0,
339 .flags = IORESOURCE_IRQ,
340 },
341 };
342
343 static struct mv643xx_eth_platform_data eth0_pd = {
344 .port_number = 0,
345 };
346
347 static struct platform_device eth0_device = {
348 .name = MV643XX_ETH_NAME,
349 .id = 0,
350 .num_resources = ARRAY_SIZE(mv64x60_eth0_resources),
351 .resource = mv64x60_eth0_resources,
352 .dev = {
353 .platform_data = &eth0_pd,
354 },
355 };
356 #endif
357
358 #ifdef CONFIG_MV643XX_ETH_1
359 static struct resource mv64x60_eth1_resources[] = {
360 [0] = {
361 .name = "eth1 irq",
362 .start = MV64x60_IRQ_ETH_1,
363 .end = MV64x60_IRQ_ETH_1,
364 .flags = IORESOURCE_IRQ,
365 },
366 };
367
368 static struct mv643xx_eth_platform_data eth1_pd = {
369 .port_number = 1,
370 };
371
372 static struct platform_device eth1_device = {
373 .name = MV643XX_ETH_NAME,
374 .id = 1,
375 .num_resources = ARRAY_SIZE(mv64x60_eth1_resources),
376 .resource = mv64x60_eth1_resources,
377 .dev = {
378 .platform_data = &eth1_pd,
379 },
380 };
381 #endif
382
383 #ifdef CONFIG_MV643XX_ETH_2
384 static struct resource mv64x60_eth2_resources[] = {
385 [0] = {
386 .name = "eth2 irq",
387 .start = MV64x60_IRQ_ETH_2,
388 .end = MV64x60_IRQ_ETH_2,
389 .flags = IORESOURCE_IRQ,
390 },
391 };
392
393 static struct mv643xx_eth_platform_data eth2_pd = {
394 .port_number = 2,
395 };
396
397 static struct platform_device eth2_device = {
398 .name = MV643XX_ETH_NAME,
399 .id = 2,
400 .num_resources = ARRAY_SIZE(mv64x60_eth2_resources),
401 .resource = mv64x60_eth2_resources,
402 .dev = {
403 .platform_data = &eth2_pd,
404 },
405 };
406 #endif
407 #endif
408
409 #ifdef CONFIG_I2C_MV64XXX
410 static struct mv64xxx_i2c_pdata mv64xxx_i2c_pdata = {
411 .freq_m = 8,
412 .freq_n = 3,
413 .timeout = 1000, /* Default timeout of 1 second */
414 .retries = 1,
415 };
416
417 static struct resource mv64xxx_i2c_resources[] = {
418 /* Do not change the order of the IORESOURCE_MEM resources */
419 [0] = {
420 .name = "mv64xxx i2c base",
421 .start = MV64XXX_I2C_OFFSET,
422 .end = MV64XXX_I2C_OFFSET + MV64XXX_I2C_REG_BLOCK_SIZE - 1,
423 .flags = IORESOURCE_MEM,
424 },
425 [1] = {
426 .name = "mv64xxx i2c irq",
427 .start = MV64x60_IRQ_I2C,
428 .end = MV64x60_IRQ_I2C,
429 .flags = IORESOURCE_IRQ,
430 },
431 };
432
433 static struct platform_device i2c_device = {
434 .name = MV64XXX_I2C_CTLR_NAME,
435 .id = 0,
436 .num_resources = ARRAY_SIZE(mv64xxx_i2c_resources),
437 .resource = mv64xxx_i2c_resources,
438 .dev = {
439 .platform_data = &mv64xxx_i2c_pdata,
440 },
441 };
442 #endif
443
444 #ifdef CONFIG_WATCHDOG
445 static struct mv64x60_wdt_pdata mv64x60_wdt_pdata = {
446 .timeout = 10, /* default watchdog expiry in seconds */
447 .bus_clk = 133, /* default bus clock in MHz */
448 };
449
450 static struct resource mv64x60_wdt_resources[] = {
451 [0] = {
452 .name = "mv64x60 wdt base",
453 .start = MV64x60_WDT_WDC,
454 .end = MV64x60_WDT_WDC + 8 - 1, /* two 32-bit registers */
455 .flags = IORESOURCE_MEM,
456 },
457 };
458
459 static struct platform_device wdt_device = {
460 .name = MV64x60_WDT_NAME,
461 .id = 0,
462 .num_resources = ARRAY_SIZE(mv64x60_wdt_resources),
463 .resource = mv64x60_wdt_resources,
464 .dev = {
465 .platform_data = &mv64x60_wdt_pdata,
466 },
467 };
468 #endif
469
470 #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
471 static struct mv64xxx_pdata mv64xxx_pdata = {
472 .hs_reg_valid = 0,
473 };
474
475 static struct platform_device mv64xxx_device = { /* general mv64x60 stuff */
476 .name = MV64XXX_DEV_NAME,
477 .id = 0,
478 .dev = {
479 .platform_data = &mv64xxx_pdata,
480 },
481 };
482 #endif
483
484 static struct platform_device *mv64x60_pd_devs[] __initdata = {
485 #ifdef CONFIG_SERIAL_MPSC
486 &mpsc_shared_device,
487 &mpsc0_device,
488 &mpsc1_device,
489 #endif
490 #if defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE)
491 &mv64x60_eth_shared_device,
492 #endif
493 #ifdef CONFIG_MV643XX_ETH_0
494 &eth0_device,
495 #endif
496 #ifdef CONFIG_MV643XX_ETH_1
497 &eth1_device,
498 #endif
499 #ifdef CONFIG_MV643XX_ETH_2
500 &eth2_device,
501 #endif
502 #ifdef CONFIG_I2C_MV64XXX
503 &i2c_device,
504 #endif
505 #ifdef CONFIG_MV64X60_WDT
506 &wdt_device,
507 #endif
508 #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
509 &mv64xxx_device,
510 #endif
511 };
512
513 /*
514 *****************************************************************************
515 *
516 * Bridge Initialization Routines
517 *
518 *****************************************************************************
519 */
520 /*
521 * mv64x60_init()
522 *
523 * Initialize the bridge based on setting passed in via 'si'. The bridge
524 * handle, 'bh', will be set so that it can be used to make subsequent
525 * calls to routines in this file.
526 */
527 int __init
528 mv64x60_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si)
529 {
530 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2];
531
532 if (ppc_md.progress)
533 ppc_md.progress("mv64x60 initialization", 0x0);
534
535 spin_lock_init(&mv64x60_lock);
536 mv64x60_early_init(bh, si);
537
538 if (mv64x60_get_type(bh) || mv64x60_setup_for_chip(bh)) {
539 iounmap(bh->v_base);
540 bh->v_base = 0;
541 if (ppc_md.progress)
542 ppc_md.progress("mv64x60_init: Can't determine chip",0);
543 return -1;
544 }
545
546 bh->ci->disable_all_windows(bh, si);
547 mv64x60_get_mem_windows(bh, mem_windows);
548 mv64x60_config_cpu2mem_windows(bh, si, mem_windows);
549
550 if (bh->ci->config_io2mem_windows)
551 bh->ci->config_io2mem_windows(bh, si, mem_windows);
552 if (bh->ci->set_mpsc2regs_window)
553 bh->ci->set_mpsc2regs_window(bh, si->phys_reg_base);
554
555 if (si->pci_1.enable_bus) {
556 bh->io_base_b = (u32)ioremap(si->pci_1.pci_io.cpu_base,
557 si->pci_1.pci_io.size);
558 isa_io_base = bh->io_base_b;
559 }
560
561 if (si->pci_0.enable_bus) {
562 bh->io_base_a = (u32)ioremap(si->pci_0.pci_io.cpu_base,
563 si->pci_0.pci_io.size);
564 isa_io_base = bh->io_base_a;
565
566 mv64x60_alloc_hose(bh, MV64x60_PCI0_CONFIG_ADDR,
567 MV64x60_PCI0_CONFIG_DATA, &bh->hose_a);
568 mv64x60_config_resources(bh->hose_a, &si->pci_0, bh->io_base_a);
569 mv64x60_config_pci_params(bh->hose_a, &si->pci_0);
570
571 mv64x60_config_cpu2pci_windows(bh, &si->pci_0, 0);
572 mv64x60_config_pci2mem_windows(bh, bh->hose_a, &si->pci_0, 0,
573 mem_windows);
574 bh->ci->set_pci2regs_window(bh, bh->hose_a, 0,
575 si->phys_reg_base);
576 }
577
578 if (si->pci_1.enable_bus) {
579 mv64x60_alloc_hose(bh, MV64x60_PCI1_CONFIG_ADDR,
580 MV64x60_PCI1_CONFIG_DATA, &bh->hose_b);
581 mv64x60_config_resources(bh->hose_b, &si->pci_1, bh->io_base_b);
582 mv64x60_config_pci_params(bh->hose_b, &si->pci_1);
583
584 mv64x60_config_cpu2pci_windows(bh, &si->pci_1, 1);
585 mv64x60_config_pci2mem_windows(bh, bh->hose_b, &si->pci_1, 1,
586 mem_windows);
587 bh->ci->set_pci2regs_window(bh, bh->hose_b, 1,
588 si->phys_reg_base);
589 }
590
591 bh->ci->chip_specific_init(bh, si);
592 mv64x60_pd_fixup(bh, mv64x60_pd_devs, ARRAY_SIZE(mv64x60_pd_devs));
593
594 return 0;
595 }
596
597 /*
598 * mv64x60_early_init()
599 *
600 * Do some bridge work that must take place before we start messing with
601 * the bridge for real.
602 */
603 void __init
604 mv64x60_early_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si)
605 {
606 struct pci_controller hose_a, hose_b;
607
608 memset(bh, 0, sizeof(*bh));
609
610 bh->p_base = si->phys_reg_base;
611 bh->v_base = ioremap(bh->p_base, MV64x60_INTERNAL_SPACE_SIZE);
612
613 mv64x60_bridge_pbase = bh->p_base;
614 mv64x60_bridge_vbase = bh->v_base;
615
616 /* Assuming pci mode [reserved] bits 4:5 on 64260 are 0 */
617 bh->pci_mode_a = mv64x60_read(bh, MV64x60_PCI0_MODE) &
618 MV64x60_PCIMODE_MASK;
619 bh->pci_mode_b = mv64x60_read(bh, MV64x60_PCI1_MODE) &
620 MV64x60_PCIMODE_MASK;
621
622 /* Need temporary hose structs to call mv64x60_set_bus() */
623 memset(&hose_a, 0, sizeof(hose_a));
624 memset(&hose_b, 0, sizeof(hose_b));
625 setup_indirect_pci_nomap(&hose_a, bh->v_base + MV64x60_PCI0_CONFIG_ADDR,
626 bh->v_base + MV64x60_PCI0_CONFIG_DATA);
627 setup_indirect_pci_nomap(&hose_b, bh->v_base + MV64x60_PCI1_CONFIG_ADDR,
628 bh->v_base + MV64x60_PCI1_CONFIG_DATA);
629 bh->hose_a = &hose_a;
630 bh->hose_b = &hose_b;
631
632 #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
633 /* Save a copy of hose_a for sysfs functions -- hack */
634 memcpy(&sysfs_hose_a, &hose_a, sizeof(hose_a));
635 #endif
636
637 mv64x60_set_bus(bh, 0, 0);
638 mv64x60_set_bus(bh, 1, 0);
639
640 bh->hose_a = NULL;
641 bh->hose_b = NULL;
642
643 /* Clear bit 0 of PCI addr decode control so PCI->CPU remap 1:1 */
644 mv64x60_clr_bits(bh, MV64x60_PCI0_PCI_DECODE_CNTL, 0x00000001);
645 mv64x60_clr_bits(bh, MV64x60_PCI1_PCI_DECODE_CNTL, 0x00000001);
646
647 /* Bit 12 MUST be 0; set bit 27--don't auto-update cpu remap regs */
648 mv64x60_clr_bits(bh, MV64x60_CPU_CONFIG, (1<<12));
649 mv64x60_set_bits(bh, MV64x60_CPU_CONFIG, (1<<27));
650
651 mv64x60_set_bits(bh, MV64x60_PCI0_TO_RETRY, 0xffff);
652 mv64x60_set_bits(bh, MV64x60_PCI1_TO_RETRY, 0xffff);
653 }
654
655 /*
656 *****************************************************************************
657 *
658 * Window Config Routines
659 *
660 *****************************************************************************
661 */
662 /*
663 * mv64x60_get_32bit_window()
664 *
665 * Determine the base address and size of a 32-bit window on the bridge.
666 */
667 void __init
668 mv64x60_get_32bit_window(struct mv64x60_handle *bh, u32 window,
669 u32 *base, u32 *size)
670 {
671 u32 val, base_reg, size_reg, base_bits, size_bits;
672 u32 (*get_from_field)(u32 val, u32 num_bits);
673
674 base_reg = bh->ci->window_tab_32bit[window].base_reg;
675
676 if (base_reg != 0) {
677 size_reg = bh->ci->window_tab_32bit[window].size_reg;
678 base_bits = bh->ci->window_tab_32bit[window].base_bits;
679 size_bits = bh->ci->window_tab_32bit[window].size_bits;
680 get_from_field= bh->ci->window_tab_32bit[window].get_from_field;
681
682 val = mv64x60_read(bh, base_reg);
683 *base = get_from_field(val, base_bits);
684
685 if (size_reg != 0) {
686 val = mv64x60_read(bh, size_reg);
687 val = get_from_field(val, size_bits);
688 *size = bh->ci->untranslate_size(*base, val, size_bits);
689 } else
690 *size = 0;
691 } else {
692 *base = 0;
693 *size = 0;
694 }
695
696 pr_debug("get 32bit window: %d, base: 0x%x, size: 0x%x\n",
697 window, *base, *size);
698 }
699
700 /*
701 * mv64x60_set_32bit_window()
702 *
703 * Set the base address and size of a 32-bit window on the bridge.
704 */
705 void __init
706 mv64x60_set_32bit_window(struct mv64x60_handle *bh, u32 window,
707 u32 base, u32 size, u32 other_bits)
708 {
709 u32 val, base_reg, size_reg, base_bits, size_bits;
710 u32 (*map_to_field)(u32 val, u32 num_bits);
711
712 pr_debug("set 32bit window: %d, base: 0x%x, size: 0x%x, other: 0x%x\n",
713 window, base, size, other_bits);
714
715 base_reg = bh->ci->window_tab_32bit[window].base_reg;
716
717 if (base_reg != 0) {
718 size_reg = bh->ci->window_tab_32bit[window].size_reg;
719 base_bits = bh->ci->window_tab_32bit[window].base_bits;
720 size_bits = bh->ci->window_tab_32bit[window].size_bits;
721 map_to_field = bh->ci->window_tab_32bit[window].map_to_field;
722
723 val = map_to_field(base, base_bits) | other_bits;
724 mv64x60_write(bh, base_reg, val);
725
726 if (size_reg != 0) {
727 val = bh->ci->translate_size(base, size, size_bits);
728 val = map_to_field(val, size_bits);
729 mv64x60_write(bh, size_reg, val);
730 }
731
732 (void)mv64x60_read(bh, base_reg); /* Flush FIFO */
733 }
734 }
735
736 /*
737 * mv64x60_get_64bit_window()
738 *
739 * Determine the base address and size of a 64-bit window on the bridge.
740 */
741 void __init
742 mv64x60_get_64bit_window(struct mv64x60_handle *bh, u32 window,
743 u32 *base_hi, u32 *base_lo, u32 *size)
744 {
745 u32 val, base_lo_reg, size_reg, base_lo_bits, size_bits;
746 u32 (*get_from_field)(u32 val, u32 num_bits);
747
748 base_lo_reg = bh->ci->window_tab_64bit[window].base_lo_reg;
749
750 if (base_lo_reg != 0) {
751 size_reg = bh->ci->window_tab_64bit[window].size_reg;
752 base_lo_bits = bh->ci->window_tab_64bit[window].base_lo_bits;
753 size_bits = bh->ci->window_tab_64bit[window].size_bits;
754 get_from_field= bh->ci->window_tab_64bit[window].get_from_field;
755
756 *base_hi = mv64x60_read(bh,
757 bh->ci->window_tab_64bit[window].base_hi_reg);
758
759 val = mv64x60_read(bh, base_lo_reg);
760 *base_lo = get_from_field(val, base_lo_bits);
761
762 if (size_reg != 0) {
763 val = mv64x60_read(bh, size_reg);
764 val = get_from_field(val, size_bits);
765 *size = bh->ci->untranslate_size(*base_lo, val,
766 size_bits);
767 } else
768 *size = 0;
769 } else {
770 *base_hi = 0;
771 *base_lo = 0;
772 *size = 0;
773 }
774
775 pr_debug("get 64bit window: %d, base hi: 0x%x, base lo: 0x%x, "
776 "size: 0x%x\n", window, *base_hi, *base_lo, *size);
777 }
778
779 /*
780 * mv64x60_set_64bit_window()
781 *
782 * Set the base address and size of a 64-bit window on the bridge.
783 */
784 void __init
785 mv64x60_set_64bit_window(struct mv64x60_handle *bh, u32 window,
786 u32 base_hi, u32 base_lo, u32 size, u32 other_bits)
787 {
788 u32 val, base_lo_reg, size_reg, base_lo_bits, size_bits;
789 u32 (*map_to_field)(u32 val, u32 num_bits);
790
791 pr_debug("set 64bit window: %d, base hi: 0x%x, base lo: 0x%x, "
792 "size: 0x%x, other: 0x%x\n",
793 window, base_hi, base_lo, size, other_bits);
794
795 base_lo_reg = bh->ci->window_tab_64bit[window].base_lo_reg;
796
797 if (base_lo_reg != 0) {
798 size_reg = bh->ci->window_tab_64bit[window].size_reg;
799 base_lo_bits = bh->ci->window_tab_64bit[window].base_lo_bits;
800 size_bits = bh->ci->window_tab_64bit[window].size_bits;
801 map_to_field = bh->ci->window_tab_64bit[window].map_to_field;
802
803 mv64x60_write(bh, bh->ci->window_tab_64bit[window].base_hi_reg,
804 base_hi);
805
806 val = map_to_field(base_lo, base_lo_bits) | other_bits;
807 mv64x60_write(bh, base_lo_reg, val);
808
809 if (size_reg != 0) {
810 val = bh->ci->translate_size(base_lo, size, size_bits);
811 val = map_to_field(val, size_bits);
812 mv64x60_write(bh, size_reg, val);
813 }
814
815 (void)mv64x60_read(bh, base_lo_reg); /* Flush FIFO */
816 }
817 }
818
819 /*
820 * mv64x60_mask()
821 *
822 * Take the high-order 'num_bits' of 'val' & mask off low bits.
823 */
824 u32 __init
825 mv64x60_mask(u32 val, u32 num_bits)
826 {
827 return val & (0xffffffff << (32 - num_bits));
828 }
829
830 /*
831 * mv64x60_shift_left()
832 *
833 * Take the low-order 'num_bits' of 'val', shift left to align at bit 31 (MSB).
834 */
835 u32 __init
836 mv64x60_shift_left(u32 val, u32 num_bits)
837 {
838 return val << (32 - num_bits);
839 }
840
841 /*
842 * mv64x60_shift_right()
843 *
844 * Take the high-order 'num_bits' of 'val', shift right to align at bit 0 (LSB).
845 */
846 u32 __init
847 mv64x60_shift_right(u32 val, u32 num_bits)
848 {
849 return val >> (32 - num_bits);
850 }
851
852 /*
853 *****************************************************************************
854 *
855 * Chip Identification Routines
856 *
857 *****************************************************************************
858 */
859 /*
860 * mv64x60_get_type()
861 *
862 * Determine the type of bridge chip we have.
863 */
864 int __init
865 mv64x60_get_type(struct mv64x60_handle *bh)
866 {
867 struct pci_controller hose;
868 u16 val;
869 u8 save_exclude;
870
871 memset(&hose, 0, sizeof(hose));
872 setup_indirect_pci_nomap(&hose, bh->v_base + MV64x60_PCI0_CONFIG_ADDR,
873 bh->v_base + MV64x60_PCI0_CONFIG_DATA);
874
875 save_exclude = mv64x60_pci_exclude_bridge;
876 mv64x60_pci_exclude_bridge = 0;
877 /* Sanity check of bridge's Vendor ID */
878 early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID, &val);
879
880 if (val != PCI_VENDOR_ID_MARVELL) {
881 mv64x60_pci_exclude_bridge = save_exclude;
882 return -1;
883 }
884
885 /* Get the revision of the chip */
886 early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_CLASS_REVISION,
887 &val);
888 bh->rev = (u32)(val & 0xff);
889
890 /* Figure out the type of Marvell bridge it is */
891 early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_DEVICE_ID, &val);
892 mv64x60_pci_exclude_bridge = save_exclude;
893
894 switch (val) {
895 case PCI_DEVICE_ID_MARVELL_GT64260:
896 switch (bh->rev) {
897 case GT64260_REV_A:
898 bh->type = MV64x60_TYPE_GT64260A;
899 break;
900
901 default:
902 printk(KERN_WARNING "Unsupported GT64260 rev %04x\n",
903 bh->rev);
904 /* Assume its similar to a 'B' rev and fallthru */
905 case GT64260_REV_B:
906 bh->type = MV64x60_TYPE_GT64260B;
907 break;
908 }
909 break;
910
911 case PCI_DEVICE_ID_MARVELL_MV64360:
912 /* Marvell won't tell me how to distinguish a 64361 & 64362 */
913 bh->type = MV64x60_TYPE_MV64360;
914 break;
915
916 case PCI_DEVICE_ID_MARVELL_MV64460:
917 bh->type = MV64x60_TYPE_MV64460;
918 break;
919
920 default:
921 printk(KERN_ERR "Unknown Marvell bridge type %04x\n", val);
922 return -1;
923 }
924
925 /* Hang onto bridge type & rev for PIC code */
926 mv64x60_bridge_type = bh->type;
927 mv64x60_bridge_rev = bh->rev;
928
929 return 0;
930 }
931
932 /*
933 * mv64x60_setup_for_chip()
934 *
935 * Set 'bh' to use the proper set of routine for the bridge chip that we have.
936 */
937 int __init
938 mv64x60_setup_for_chip(struct mv64x60_handle *bh)
939 {
940 int rc = 0;
941
942 /* Set up chip-specific info based on the chip/bridge type */
943 switch(bh->type) {
944 case MV64x60_TYPE_GT64260A:
945 bh->ci = &gt64260a_ci;
946 break;
947
948 case MV64x60_TYPE_GT64260B:
949 bh->ci = &gt64260b_ci;
950 break;
951
952 case MV64x60_TYPE_MV64360:
953 bh->ci = &mv64360_ci;
954 break;
955
956 case MV64x60_TYPE_MV64460:
957 bh->ci = &mv64460_ci;
958 break;
959
960 case MV64x60_TYPE_INVALID:
961 default:
962 if (ppc_md.progress)
963 ppc_md.progress("mv64x60: Unsupported bridge", 0x0);
964 printk(KERN_ERR "mv64x60: Unsupported bridge\n");
965 rc = -1;
966 }
967
968 return rc;
969 }
970
971 /*
972 * mv64x60_get_bridge_vbase()
973 *
974 * Return the virtual address of the bridge's registers.
975 */
976 void __iomem *
977 mv64x60_get_bridge_vbase(void)
978 {
979 return mv64x60_bridge_vbase;
980 }
981
982 /*
983 * mv64x60_get_bridge_type()
984 *
985 * Return the type of bridge on the platform.
986 */
987 u32
988 mv64x60_get_bridge_type(void)
989 {
990 return mv64x60_bridge_type;
991 }
992
993 /*
994 * mv64x60_get_bridge_rev()
995 *
996 * Return the revision of the bridge on the platform.
997 */
998 u32
999 mv64x60_get_bridge_rev(void)
1000 {
1001 return mv64x60_bridge_rev;
1002 }
1003
1004 /*
1005 *****************************************************************************
1006 *
1007 * System Memory Window Related Routines
1008 *
1009 *****************************************************************************
1010 */
1011 /*
1012 * mv64x60_get_mem_size()
1013 *
1014 * Calculate the amount of memory that the memory controller is set up for.
1015 * This should only be used by board-specific code if there is no other
1016 * way to determine the amount of memory in the system.
1017 */
1018 u32 __init
1019 mv64x60_get_mem_size(u32 bridge_base, u32 chip_type)
1020 {
1021 struct mv64x60_handle bh;
1022 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2];
1023 u32 rc = 0;
1024
1025 memset(&bh, 0, sizeof(bh));
1026
1027 bh.type = chip_type;
1028 bh.v_base = (void *)bridge_base;
1029
1030 if (!mv64x60_setup_for_chip(&bh)) {
1031 mv64x60_get_mem_windows(&bh, mem_windows);
1032 rc = mv64x60_calc_mem_size(&bh, mem_windows);
1033 }
1034
1035 return rc;
1036 }
1037
1038 /*
1039 * mv64x60_get_mem_windows()
1040 *
1041 * Get the values in the memory controller & return in the 'mem_windows' array.
1042 */
1043 void __init
1044 mv64x60_get_mem_windows(struct mv64x60_handle *bh,
1045 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
1046 {
1047 u32 i, win;
1048
1049 for (win=MV64x60_CPU2MEM_0_WIN,i=0;win<=MV64x60_CPU2MEM_3_WIN;win++,i++)
1050 if (bh->ci->is_enabled_32bit(bh, win))
1051 mv64x60_get_32bit_window(bh, win,
1052 &mem_windows[i][0], &mem_windows[i][1]);
1053 else {
1054 mem_windows[i][0] = 0;
1055 mem_windows[i][1] = 0;
1056 }
1057 }
1058
1059 /*
1060 * mv64x60_calc_mem_size()
1061 *
1062 * Using the memory controller register values in 'mem_windows', determine
1063 * how much memory it is set up for.
1064 */
1065 u32 __init
1066 mv64x60_calc_mem_size(struct mv64x60_handle *bh,
1067 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
1068 {
1069 u32 i, total = 0;
1070
1071 for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++)
1072 total += mem_windows[i][1];
1073
1074 return total;
1075 }
1076
1077 /*
1078 *****************************************************************************
1079 *
1080 * CPU->System MEM, PCI Config Routines
1081 *
1082 *****************************************************************************
1083 */
1084 /*
1085 * mv64x60_config_cpu2mem_windows()
1086 *
1087 * Configure CPU->Memory windows on the bridge.
1088 */
1089 static u32 prot_tab[] __initdata = {
1090 MV64x60_CPU_PROT_0_WIN, MV64x60_CPU_PROT_1_WIN,
1091 MV64x60_CPU_PROT_2_WIN, MV64x60_CPU_PROT_3_WIN
1092 };
1093
1094 static u32 cpu_snoop_tab[] __initdata = {
1095 MV64x60_CPU_SNOOP_0_WIN, MV64x60_CPU_SNOOP_1_WIN,
1096 MV64x60_CPU_SNOOP_2_WIN, MV64x60_CPU_SNOOP_3_WIN
1097 };
1098
1099 void __init
1100 mv64x60_config_cpu2mem_windows(struct mv64x60_handle *bh,
1101 struct mv64x60_setup_info *si,
1102 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
1103 {
1104 u32 i, win;
1105
1106 /* Set CPU protection & snoop windows */
1107 for (win=MV64x60_CPU2MEM_0_WIN,i=0;win<=MV64x60_CPU2MEM_3_WIN;win++,i++)
1108 if (bh->ci->is_enabled_32bit(bh, win)) {
1109 mv64x60_set_32bit_window(bh, prot_tab[i],
1110 mem_windows[i][0], mem_windows[i][1],
1111 si->cpu_prot_options[i]);
1112 bh->ci->enable_window_32bit(bh, prot_tab[i]);
1113
1114 if (bh->ci->window_tab_32bit[cpu_snoop_tab[i]].
1115 base_reg != 0) {
1116 mv64x60_set_32bit_window(bh, cpu_snoop_tab[i],
1117 mem_windows[i][0], mem_windows[i][1],
1118 si->cpu_snoop_options[i]);
1119 bh->ci->enable_window_32bit(bh,
1120 cpu_snoop_tab[i]);
1121 }
1122
1123 }
1124 }
1125
1126 /*
1127 * mv64x60_config_cpu2pci_windows()
1128 *
1129 * Configure the CPU->PCI windows for one of the PCI buses.
1130 */
1131 static u32 win_tab[2][4] __initdata = {
1132 { MV64x60_CPU2PCI0_IO_WIN, MV64x60_CPU2PCI0_MEM_0_WIN,
1133 MV64x60_CPU2PCI0_MEM_1_WIN, MV64x60_CPU2PCI0_MEM_2_WIN },
1134 { MV64x60_CPU2PCI1_IO_WIN, MV64x60_CPU2PCI1_MEM_0_WIN,
1135 MV64x60_CPU2PCI1_MEM_1_WIN, MV64x60_CPU2PCI1_MEM_2_WIN },
1136 };
1137
1138 static u32 remap_tab[2][4] __initdata = {
1139 { MV64x60_CPU2PCI0_IO_REMAP_WIN, MV64x60_CPU2PCI0_MEM_0_REMAP_WIN,
1140 MV64x60_CPU2PCI0_MEM_1_REMAP_WIN, MV64x60_CPU2PCI0_MEM_2_REMAP_WIN },
1141 { MV64x60_CPU2PCI1_IO_REMAP_WIN, MV64x60_CPU2PCI1_MEM_0_REMAP_WIN,
1142 MV64x60_CPU2PCI1_MEM_1_REMAP_WIN, MV64x60_CPU2PCI1_MEM_2_REMAP_WIN }
1143 };
1144
1145 void __init
1146 mv64x60_config_cpu2pci_windows(struct mv64x60_handle *bh,
1147 struct mv64x60_pci_info *pi, u32 bus)
1148 {
1149 int i;
1150
1151 if (pi->pci_io.size > 0) {
1152 mv64x60_set_32bit_window(bh, win_tab[bus][0],
1153 pi->pci_io.cpu_base, pi->pci_io.size, pi->pci_io.swap);
1154 mv64x60_set_32bit_window(bh, remap_tab[bus][0],
1155 pi->pci_io.pci_base_lo, 0, 0);
1156 bh->ci->enable_window_32bit(bh, win_tab[bus][0]);
1157 } else /* Actually, the window should already be disabled */
1158 bh->ci->disable_window_32bit(bh, win_tab[bus][0]);
1159
1160 for (i=0; i<3; i++)
1161 if (pi->pci_mem[i].size > 0) {
1162 mv64x60_set_32bit_window(bh, win_tab[bus][i+1],
1163 pi->pci_mem[i].cpu_base, pi->pci_mem[i].size,
1164 pi->pci_mem[i].swap);
1165 mv64x60_set_64bit_window(bh, remap_tab[bus][i+1],
1166 pi->pci_mem[i].pci_base_hi,
1167 pi->pci_mem[i].pci_base_lo, 0, 0);
1168 bh->ci->enable_window_32bit(bh, win_tab[bus][i+1]);
1169 } else /* Actually, the window should already be disabled */
1170 bh->ci->disable_window_32bit(bh, win_tab[bus][i+1]);
1171 }
1172
1173 /*
1174 *****************************************************************************
1175 *
1176 * PCI->System MEM Config Routines
1177 *
1178 *****************************************************************************
1179 */
1180 /*
1181 * mv64x60_config_pci2mem_windows()
1182 *
1183 * Configure the PCI->Memory windows on the bridge.
1184 */
1185 static u32 pci_acc_tab[2][4] __initdata = {
1186 { MV64x60_PCI02MEM_ACC_CNTL_0_WIN, MV64x60_PCI02MEM_ACC_CNTL_1_WIN,
1187 MV64x60_PCI02MEM_ACC_CNTL_2_WIN, MV64x60_PCI02MEM_ACC_CNTL_3_WIN },
1188 { MV64x60_PCI12MEM_ACC_CNTL_0_WIN, MV64x60_PCI12MEM_ACC_CNTL_1_WIN,
1189 MV64x60_PCI12MEM_ACC_CNTL_2_WIN, MV64x60_PCI12MEM_ACC_CNTL_3_WIN }
1190 };
1191
1192 static u32 pci_snoop_tab[2][4] __initdata = {
1193 { MV64x60_PCI02MEM_SNOOP_0_WIN, MV64x60_PCI02MEM_SNOOP_1_WIN,
1194 MV64x60_PCI02MEM_SNOOP_2_WIN, MV64x60_PCI02MEM_SNOOP_3_WIN },
1195 { MV64x60_PCI12MEM_SNOOP_0_WIN, MV64x60_PCI12MEM_SNOOP_1_WIN,
1196 MV64x60_PCI12MEM_SNOOP_2_WIN, MV64x60_PCI12MEM_SNOOP_3_WIN }
1197 };
1198
1199 static u32 pci_size_tab[2][4] __initdata = {
1200 { MV64x60_PCI0_MEM_0_SIZE, MV64x60_PCI0_MEM_1_SIZE,
1201 MV64x60_PCI0_MEM_2_SIZE, MV64x60_PCI0_MEM_3_SIZE },
1202 { MV64x60_PCI1_MEM_0_SIZE, MV64x60_PCI1_MEM_1_SIZE,
1203 MV64x60_PCI1_MEM_2_SIZE, MV64x60_PCI1_MEM_3_SIZE }
1204 };
1205
1206 void __init
1207 mv64x60_config_pci2mem_windows(struct mv64x60_handle *bh,
1208 struct pci_controller *hose, struct mv64x60_pci_info *pi,
1209 u32 bus, u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
1210 {
1211 u32 i, win;
1212
1213 /*
1214 * Set the access control, snoop, BAR size, and window base addresses.
1215 * PCI->MEM windows base addresses will match exactly what the
1216 * CPU->MEM windows are.
1217 */
1218 for (win=MV64x60_CPU2MEM_0_WIN,i=0;win<=MV64x60_CPU2MEM_3_WIN;win++,i++)
1219 if (bh->ci->is_enabled_32bit(bh, win)) {
1220 mv64x60_set_64bit_window(bh,
1221 pci_acc_tab[bus][i], 0,
1222 mem_windows[i][0], mem_windows[i][1],
1223 pi->acc_cntl_options[i]);
1224 bh->ci->enable_window_64bit(bh, pci_acc_tab[bus][i]);
1225
1226 if (bh->ci->window_tab_64bit[
1227 pci_snoop_tab[bus][i]].base_lo_reg != 0) {
1228
1229 mv64x60_set_64bit_window(bh,
1230 pci_snoop_tab[bus][i], 0,
1231 mem_windows[i][0], mem_windows[i][1],
1232 pi->snoop_options[i]);
1233 bh->ci->enable_window_64bit(bh,
1234 pci_snoop_tab[bus][i]);
1235 }
1236
1237 bh->ci->set_pci2mem_window(hose, bus, i,
1238 mem_windows[i][0]);
1239 mv64x60_write(bh, pci_size_tab[bus][i],
1240 mv64x60_mask(mem_windows[i][1] - 1, 20));
1241
1242 /* Enable the window */
1243 mv64x60_clr_bits(bh, ((bus == 0) ?
1244 MV64x60_PCI0_BAR_ENABLE :
1245 MV64x60_PCI1_BAR_ENABLE), (1 << i));
1246 }
1247 }
1248
1249 /*
1250 *****************************************************************************
1251 *
1252 * Hose & Resource Alloc/Init Routines
1253 *
1254 *****************************************************************************
1255 */
1256 /*
1257 * mv64x60_alloc_hoses()
1258 *
1259 * Allocate the PCI hose structures for the bridge's PCI buses.
1260 */
1261 void __init
1262 mv64x60_alloc_hose(struct mv64x60_handle *bh, u32 cfg_addr, u32 cfg_data,
1263 struct pci_controller **hose)
1264 {
1265 *hose = pcibios_alloc_controller();
1266 setup_indirect_pci_nomap(*hose, bh->v_base + cfg_addr,
1267 bh->v_base + cfg_data);
1268 }
1269
1270 /*
1271 * mv64x60_config_resources()
1272 *
1273 * Calculate the offsets, etc. for the hose structures to reflect all of
1274 * the address remapping that happens as you go from CPU->PCI and PCI->MEM.
1275 */
1276 void __init
1277 mv64x60_config_resources(struct pci_controller *hose,
1278 struct mv64x60_pci_info *pi, u32 io_base)
1279 {
1280 int i;
1281 /* 2 hoses; 4 resources/hose; string <= 64 bytes */
1282 static char s[2][4][64];
1283
1284 if (pi->pci_io.size != 0) {
1285 sprintf(s[hose->index][0], "PCI hose %d I/O Space",
1286 hose->index);
1287 pci_init_resource(&hose->io_resource, io_base - isa_io_base,
1288 io_base - isa_io_base + pi->pci_io.size - 1,
1289 IORESOURCE_IO, s[hose->index][0]);
1290 hose->io_space.start = pi->pci_io.pci_base_lo;
1291 hose->io_space.end = pi->pci_io.pci_base_lo + pi->pci_io.size-1;
1292 hose->io_base_phys = pi->pci_io.cpu_base;
1293 hose->io_base_virt = (void *)isa_io_base;
1294 }
1295
1296 for (i=0; i<3; i++)
1297 if (pi->pci_mem[i].size != 0) {
1298 sprintf(s[hose->index][i+1], "PCI hose %d MEM Space %d",
1299 hose->index, i);
1300 pci_init_resource(&hose->mem_resources[i],
1301 pi->pci_mem[i].cpu_base,
1302 pi->pci_mem[i].cpu_base + pi->pci_mem[i].size-1,
1303 IORESOURCE_MEM, s[hose->index][i+1]);
1304 }
1305
1306 hose->mem_space.end = pi->pci_mem[0].pci_base_lo +
1307 pi->pci_mem[0].size - 1;
1308 hose->pci_mem_offset = pi->pci_mem[0].cpu_base -
1309 pi->pci_mem[0].pci_base_lo;
1310 }
1311
1312 /*
1313 * mv64x60_config_pci_params()
1314 *
1315 * Configure a hose's PCI config space parameters.
1316 */
1317 void __init
1318 mv64x60_config_pci_params(struct pci_controller *hose,
1319 struct mv64x60_pci_info *pi)
1320 {
1321 u32 devfn;
1322 u16 u16_val;
1323 u8 save_exclude;
1324
1325 devfn = PCI_DEVFN(0,0);
1326
1327 save_exclude = mv64x60_pci_exclude_bridge;
1328 mv64x60_pci_exclude_bridge = 0;
1329
1330 /* Set class code to indicate host bridge */
1331 u16_val = PCI_CLASS_BRIDGE_HOST; /* 0x0600 (host bridge) */
1332 early_write_config_word(hose, 0, devfn, PCI_CLASS_DEVICE, u16_val);
1333
1334 /* Enable bridge to be PCI master & respond to PCI MEM cycles */
1335 early_read_config_word(hose, 0, devfn, PCI_COMMAND, &u16_val);
1336 u16_val &= ~(PCI_COMMAND_IO | PCI_COMMAND_INVALIDATE |
1337 PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK);
1338 u16_val |= pi->pci_cmd_bits | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
1339 early_write_config_word(hose, 0, devfn, PCI_COMMAND, u16_val);
1340
1341 /* Set latency timer, cache line size, clear BIST */
1342 u16_val = (pi->latency_timer << 8) | (L1_CACHE_BYTES >> 2);
1343 early_write_config_word(hose, 0, devfn, PCI_CACHE_LINE_SIZE, u16_val);
1344
1345 mv64x60_pci_exclude_bridge = save_exclude;
1346 }
1347
1348 /*
1349 *****************************************************************************
1350 *
1351 * PCI Related Routine
1352 *
1353 *****************************************************************************
1354 */
1355 /*
1356 * mv64x60_set_bus()
1357 *
1358 * Set the bus number for the hose directly under the bridge.
1359 */
1360 void __init
1361 mv64x60_set_bus(struct mv64x60_handle *bh, u32 bus, u32 child_bus)
1362 {
1363 struct pci_controller *hose;
1364 u32 pci_mode, p2p_cfg, pci_cfg_offset, val;
1365 u8 save_exclude;
1366
1367 if (bus == 0) {
1368 pci_mode = bh->pci_mode_a;
1369 p2p_cfg = MV64x60_PCI0_P2P_CONFIG;
1370 pci_cfg_offset = 0x64;
1371 hose = bh->hose_a;
1372 } else {
1373 pci_mode = bh->pci_mode_b;
1374 p2p_cfg = MV64x60_PCI1_P2P_CONFIG;
1375 pci_cfg_offset = 0xe4;
1376 hose = bh->hose_b;
1377 }
1378
1379 child_bus &= 0xff;
1380 val = mv64x60_read(bh, p2p_cfg);
1381
1382 if (pci_mode == MV64x60_PCIMODE_CONVENTIONAL) {
1383 val &= 0xe0000000; /* Force dev num to 0, turn off P2P bridge */
1384 val |= (child_bus << 16) | 0xff;
1385 mv64x60_write(bh, p2p_cfg, val);
1386 (void)mv64x60_read(bh, p2p_cfg); /* Flush FIFO */
1387 } else { /* PCI-X */
1388 /*
1389 * Need to use the current bus/dev number (that's in the
1390 * P2P CONFIG reg) to access the bridge's pci config space.
1391 */
1392 save_exclude = mv64x60_pci_exclude_bridge;
1393 mv64x60_pci_exclude_bridge = 0;
1394 early_write_config_dword(hose, (val & 0x00ff0000) >> 16,
1395 PCI_DEVFN(((val & 0x1f000000) >> 24), 0),
1396 pci_cfg_offset, child_bus << 8);
1397 mv64x60_pci_exclude_bridge = save_exclude;
1398 }
1399 }
1400
1401 /*
1402 * mv64x60_pci_exclude_device()
1403 *
1404 * This routine is used to make the bridge not appear when the
1405 * PCI subsystem is accessing PCI devices (in PCI config space).
1406 */
1407 int
1408 mv64x60_pci_exclude_device(u8 bus, u8 devfn)
1409 {
1410 struct pci_controller *hose;
1411
1412 hose = pci_bus_to_hose(bus);
1413
1414 /* Skip slot 0 on both hoses */
1415 if ((mv64x60_pci_exclude_bridge == 1) && (PCI_SLOT(devfn) == 0) &&
1416 (hose->first_busno == bus))
1417
1418 return PCIBIOS_DEVICE_NOT_FOUND;
1419 else
1420 return PCIBIOS_SUCCESSFUL;
1421 } /* mv64x60_pci_exclude_device() */
1422
1423 /*
1424 *****************************************************************************
1425 *
1426 * Platform Device Routines
1427 *
1428 *****************************************************************************
1429 */
1430
1431 /*
1432 * mv64x60_pd_fixup()
1433 *
1434 * Need to add the base addr of where the bridge's regs are mapped in the
1435 * physical addr space so drivers can ioremap() them.
1436 */
1437 void __init
1438 mv64x60_pd_fixup(struct mv64x60_handle *bh, struct platform_device *pd_devs[],
1439 u32 entries)
1440 {
1441 struct resource *r;
1442 u32 i, j;
1443
1444 for (i=0; i<entries; i++) {
1445 j = 0;
1446
1447 while ((r = platform_get_resource(pd_devs[i],IORESOURCE_MEM,j))
1448 != NULL) {
1449
1450 r->start += bh->p_base;
1451 r->end += bh->p_base;
1452 j++;
1453 }
1454 }
1455 }
1456
1457 /*
1458 * mv64x60_add_pds()
1459 *
1460 * Add the mv64x60 platform devices to the list of platform devices.
1461 */
1462 static int __init
1463 mv64x60_add_pds(void)
1464 {
1465 return platform_add_devices(mv64x60_pd_devs,
1466 ARRAY_SIZE(mv64x60_pd_devs));
1467 }
1468 arch_initcall(mv64x60_add_pds);
1469
1470 /*
1471 *****************************************************************************
1472 *
1473 * GT64260-Specific Routines
1474 *
1475 *****************************************************************************
1476 */
1477 /*
1478 * gt64260_translate_size()
1479 *
1480 * On the GT64260, the size register is really the "top" address of the window.
1481 */
1482 static u32 __init
1483 gt64260_translate_size(u32 base, u32 size, u32 num_bits)
1484 {
1485 return base + mv64x60_mask(size - 1, num_bits);
1486 }
1487
1488 /*
1489 * gt64260_untranslate_size()
1490 *
1491 * Translate the top address of a window into a window size.
1492 */
1493 static u32 __init
1494 gt64260_untranslate_size(u32 base, u32 size, u32 num_bits)
1495 {
1496 if (size >= base)
1497 size = size - base + (1 << (32 - num_bits));
1498 else
1499 size = 0;
1500
1501 return size;
1502 }
1503
1504 /*
1505 * gt64260_set_pci2mem_window()
1506 *
1507 * The PCI->MEM window registers are actually in PCI config space so need
1508 * to set them by setting the correct config space BARs.
1509 */
1510 static u32 gt64260_reg_addrs[2][4] __initdata = {
1511 { 0x10, 0x14, 0x18, 0x1c }, { 0x90, 0x94, 0x98, 0x9c }
1512 };
1513
1514 static void __init
1515 gt64260_set_pci2mem_window(struct pci_controller *hose, u32 bus, u32 window,
1516 u32 base)
1517 {
1518 u8 save_exclude;
1519
1520 pr_debug("set pci->mem window: %d, hose: %d, base: 0x%x\n", window,
1521 hose->index, base);
1522
1523 save_exclude = mv64x60_pci_exclude_bridge;
1524 mv64x60_pci_exclude_bridge = 0;
1525 early_write_config_dword(hose, 0, PCI_DEVFN(0, 0),
1526 gt64260_reg_addrs[bus][window], mv64x60_mask(base, 20) | 0x8);
1527 mv64x60_pci_exclude_bridge = save_exclude;
1528 }
1529
1530 /*
1531 * gt64260_set_pci2regs_window()
1532 *
1533 * Set where the bridge's registers appear in PCI MEM space.
1534 */
1535 static u32 gt64260_offset[2] __initdata = {0x20, 0xa0};
1536
1537 static void __init
1538 gt64260_set_pci2regs_window(struct mv64x60_handle *bh,
1539 struct pci_controller *hose, u32 bus, u32 base)
1540 {
1541 u8 save_exclude;
1542
1543 pr_debug("set pci->internal regs hose: %d, base: 0x%x\n", hose->index,
1544 base);
1545
1546 save_exclude = mv64x60_pci_exclude_bridge;
1547 mv64x60_pci_exclude_bridge = 0;
1548 early_write_config_dword(hose, 0, PCI_DEVFN(0,0), gt64260_offset[bus],
1549 (base << 16));
1550 mv64x60_pci_exclude_bridge = save_exclude;
1551 }
1552
1553 /*
1554 * gt64260_is_enabled_32bit()
1555 *
1556 * On a GT64260, a window is enabled iff its top address is >= to its base
1557 * address.
1558 */
1559 static u32 __init
1560 gt64260_is_enabled_32bit(struct mv64x60_handle *bh, u32 window)
1561 {
1562 u32 rc = 0;
1563
1564 if ((gt64260_32bit_windows[window].base_reg != 0) &&
1565 (gt64260_32bit_windows[window].size_reg != 0) &&
1566 ((mv64x60_read(bh, gt64260_32bit_windows[window].size_reg) &
1567 ((1 << gt64260_32bit_windows[window].size_bits) - 1)) >=
1568 (mv64x60_read(bh, gt64260_32bit_windows[window].base_reg) &
1569 ((1 << gt64260_32bit_windows[window].base_bits) - 1))))
1570
1571 rc = 1;
1572
1573 return rc;
1574 }
1575
1576 /*
1577 * gt64260_enable_window_32bit()
1578 *
1579 * On the GT64260, a window is enabled iff the top address is >= to the base
1580 * address of the window. Since the window has already been configured by
1581 * the time this routine is called, we have nothing to do here.
1582 */
1583 static void __init
1584 gt64260_enable_window_32bit(struct mv64x60_handle *bh, u32 window)
1585 {
1586 pr_debug("enable 32bit window: %d\n", window);
1587 }
1588
1589 /*
1590 * gt64260_disable_window_32bit()
1591 *
1592 * On a GT64260, you disable a window by setting its top address to be less
1593 * than its base address.
1594 */
1595 static void __init
1596 gt64260_disable_window_32bit(struct mv64x60_handle *bh, u32 window)
1597 {
1598 pr_debug("disable 32bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
1599 window, gt64260_32bit_windows[window].base_reg,
1600 gt64260_32bit_windows[window].size_reg);
1601
1602 if ((gt64260_32bit_windows[window].base_reg != 0) &&
1603 (gt64260_32bit_windows[window].size_reg != 0)) {
1604
1605 /* To disable, make bottom reg higher than top reg */
1606 mv64x60_write(bh, gt64260_32bit_windows[window].base_reg,0xfff);
1607 mv64x60_write(bh, gt64260_32bit_windows[window].size_reg, 0);
1608 }
1609 }
1610
1611 /*
1612 * gt64260_enable_window_64bit()
1613 *
1614 * On the GT64260, a window is enabled iff the top address is >= to the base
1615 * address of the window. Since the window has already been configured by
1616 * the time this routine is called, we have nothing to do here.
1617 */
1618 static void __init
1619 gt64260_enable_window_64bit(struct mv64x60_handle *bh, u32 window)
1620 {
1621 pr_debug("enable 64bit window: %d\n", window);
1622 }
1623
1624 /*
1625 * gt64260_disable_window_64bit()
1626 *
1627 * On a GT64260, you disable a window by setting its top address to be less
1628 * than its base address.
1629 */
1630 static void __init
1631 gt64260_disable_window_64bit(struct mv64x60_handle *bh, u32 window)
1632 {
1633 pr_debug("disable 64bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
1634 window, gt64260_64bit_windows[window].base_lo_reg,
1635 gt64260_64bit_windows[window].size_reg);
1636
1637 if ((gt64260_64bit_windows[window].base_lo_reg != 0) &&
1638 (gt64260_64bit_windows[window].size_reg != 0)) {
1639
1640 /* To disable, make bottom reg higher than top reg */
1641 mv64x60_write(bh, gt64260_64bit_windows[window].base_lo_reg,
1642 0xfff);
1643 mv64x60_write(bh, gt64260_64bit_windows[window].base_hi_reg, 0);
1644 mv64x60_write(bh, gt64260_64bit_windows[window].size_reg, 0);
1645 }
1646 }
1647
1648 /*
1649 * gt64260_disable_all_windows()
1650 *
1651 * The GT64260 has several windows that aren't represented in the table of
1652 * windows at the top of this file. This routine turns all of them off
1653 * except for the memory controller windows, of course.
1654 */
1655 static void __init
1656 gt64260_disable_all_windows(struct mv64x60_handle *bh,
1657 struct mv64x60_setup_info *si)
1658 {
1659 u32 i, preserve;
1660
1661 /* Disable 32bit windows (don't disable cpu->mem windows) */
1662 for (i=MV64x60_CPU2DEV_0_WIN; i<MV64x60_32BIT_WIN_COUNT; i++) {
1663 if (i < 32)
1664 preserve = si->window_preserve_mask_32_lo & (1 << i);
1665 else
1666 preserve = si->window_preserve_mask_32_hi & (1<<(i-32));
1667
1668 if (!preserve)
1669 gt64260_disable_window_32bit(bh, i);
1670 }
1671
1672 /* Disable 64bit windows */
1673 for (i=0; i<MV64x60_64BIT_WIN_COUNT; i++)
1674 if (!(si->window_preserve_mask_64 & (1<<i)))
1675 gt64260_disable_window_64bit(bh, i);
1676
1677 /* Turn off cpu protection windows not in gt64260_32bit_windows[] */
1678 mv64x60_write(bh, GT64260_CPU_PROT_BASE_4, 0xfff);
1679 mv64x60_write(bh, GT64260_CPU_PROT_SIZE_4, 0);
1680 mv64x60_write(bh, GT64260_CPU_PROT_BASE_5, 0xfff);
1681 mv64x60_write(bh, GT64260_CPU_PROT_SIZE_5, 0);
1682 mv64x60_write(bh, GT64260_CPU_PROT_BASE_6, 0xfff);
1683 mv64x60_write(bh, GT64260_CPU_PROT_SIZE_6, 0);
1684 mv64x60_write(bh, GT64260_CPU_PROT_BASE_7, 0xfff);
1685 mv64x60_write(bh, GT64260_CPU_PROT_SIZE_7, 0);
1686
1687 /* Turn off PCI->MEM access cntl wins not in gt64260_64bit_windows[] */
1688 mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_4_BASE_LO, 0xfff);
1689 mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_4_BASE_HI, 0);
1690 mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_4_SIZE, 0);
1691 mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_5_BASE_LO, 0xfff);
1692 mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_5_BASE_HI, 0);
1693 mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_5_SIZE, 0);
1694 mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_6_BASE_LO, 0xfff);
1695 mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_6_BASE_HI, 0);
1696 mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_6_SIZE, 0);
1697 mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_7_BASE_LO, 0xfff);
1698 mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_7_BASE_HI, 0);
1699 mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_7_SIZE, 0);
1700
1701 mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_4_BASE_LO, 0xfff);
1702 mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_4_BASE_HI, 0);
1703 mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_4_SIZE, 0);
1704 mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_5_BASE_LO, 0xfff);
1705 mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_5_BASE_HI, 0);
1706 mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_5_SIZE, 0);
1707 mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_6_BASE_LO, 0xfff);
1708 mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_6_BASE_HI, 0);
1709 mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_6_SIZE, 0);
1710 mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_7_BASE_LO, 0xfff);
1711 mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_7_BASE_HI, 0);
1712 mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_7_SIZE, 0);
1713
1714 /* Disable all PCI-><whatever> windows */
1715 mv64x60_set_bits(bh, MV64x60_PCI0_BAR_ENABLE, 0x07fffdff);
1716 mv64x60_set_bits(bh, MV64x60_PCI1_BAR_ENABLE, 0x07fffdff);
1717
1718 /*
1719 * Some firmwares enable a bunch of intr sources
1720 * for the PCI INT output pins.
1721 */
1722 mv64x60_write(bh, GT64260_IC_CPU_INTR_MASK_LO, 0);
1723 mv64x60_write(bh, GT64260_IC_CPU_INTR_MASK_HI, 0);
1724 mv64x60_write(bh, GT64260_IC_PCI0_INTR_MASK_LO, 0);
1725 mv64x60_write(bh, GT64260_IC_PCI0_INTR_MASK_HI, 0);
1726 mv64x60_write(bh, GT64260_IC_PCI1_INTR_MASK_LO, 0);
1727 mv64x60_write(bh, GT64260_IC_PCI1_INTR_MASK_HI, 0);
1728 mv64x60_write(bh, GT64260_IC_CPU_INT_0_MASK, 0);
1729 mv64x60_write(bh, GT64260_IC_CPU_INT_1_MASK, 0);
1730 mv64x60_write(bh, GT64260_IC_CPU_INT_2_MASK, 0);
1731 mv64x60_write(bh, GT64260_IC_CPU_INT_3_MASK, 0);
1732 }
1733
1734 /*
1735 * gt64260a_chip_specific_init()
1736 *
1737 * Implement errata workarounds for the GT64260A.
1738 */
1739 static void __init
1740 gt64260a_chip_specific_init(struct mv64x60_handle *bh,
1741 struct mv64x60_setup_info *si)
1742 {
1743 #ifdef CONFIG_SERIAL_MPSC
1744 struct resource *r;
1745 #endif
1746 #if !defined(CONFIG_NOT_COHERENT_CACHE)
1747 u32 val;
1748 u8 save_exclude;
1749 #endif
1750
1751 if (si->pci_0.enable_bus)
1752 mv64x60_set_bits(bh, MV64x60_PCI0_CMD,
1753 ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
1754
1755 if (si->pci_1.enable_bus)
1756 mv64x60_set_bits(bh, MV64x60_PCI1_CMD,
1757 ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
1758
1759 /*
1760 * Dave Wilhardt found that bit 4 in the PCI Command registers must
1761 * be set if you are using cache coherency.
1762 */
1763 #if !defined(CONFIG_NOT_COHERENT_CACHE)
1764 /* Res #MEM-4 -- cpu read buffer to buffer 1 */
1765 if ((mv64x60_read(bh, MV64x60_CPU_MODE) & 0xf0) == 0x40)
1766 mv64x60_set_bits(bh, GT64260_SDRAM_CONFIG, (1<<26));
1767
1768 save_exclude = mv64x60_pci_exclude_bridge;
1769 mv64x60_pci_exclude_bridge = 0;
1770 if (si->pci_0.enable_bus) {
1771 early_read_config_dword(bh->hose_a, 0, PCI_DEVFN(0,0),
1772 PCI_COMMAND, &val);
1773 val |= PCI_COMMAND_INVALIDATE;
1774 early_write_config_dword(bh->hose_a, 0, PCI_DEVFN(0,0),
1775 PCI_COMMAND, val);
1776 }
1777
1778 if (si->pci_1.enable_bus) {
1779 early_read_config_dword(bh->hose_b, 0, PCI_DEVFN(0,0),
1780 PCI_COMMAND, &val);
1781 val |= PCI_COMMAND_INVALIDATE;
1782 early_write_config_dword(bh->hose_b, 0, PCI_DEVFN(0,0),
1783 PCI_COMMAND, val);
1784 }
1785 mv64x60_pci_exclude_bridge = save_exclude;
1786 #endif
1787
1788 /* Disable buffer/descriptor snooping */
1789 mv64x60_clr_bits(bh, 0xf280, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
1790 mv64x60_clr_bits(bh, 0xf2c0, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
1791
1792 #ifdef CONFIG_SERIAL_MPSC
1793 mv64x60_mpsc0_pdata.mirror_regs = 1;
1794 mv64x60_mpsc0_pdata.cache_mgmt = 1;
1795 mv64x60_mpsc1_pdata.mirror_regs = 1;
1796 mv64x60_mpsc1_pdata.cache_mgmt = 1;
1797
1798 if ((r = platform_get_resource(&mpsc1_device, IORESOURCE_IRQ, 0))
1799 != NULL) {
1800 r->start = MV64x60_IRQ_SDMA_0;
1801 r->end = MV64x60_IRQ_SDMA_0;
1802 }
1803 #endif
1804 }
1805
1806 /*
1807 * gt64260b_chip_specific_init()
1808 *
1809 * Implement errata workarounds for the GT64260B.
1810 */
1811 static void __init
1812 gt64260b_chip_specific_init(struct mv64x60_handle *bh,
1813 struct mv64x60_setup_info *si)
1814 {
1815 #ifdef CONFIG_SERIAL_MPSC
1816 struct resource *r;
1817 #endif
1818 #if !defined(CONFIG_NOT_COHERENT_CACHE)
1819 u32 val;
1820 u8 save_exclude;
1821 #endif
1822
1823 if (si->pci_0.enable_bus)
1824 mv64x60_set_bits(bh, MV64x60_PCI0_CMD,
1825 ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
1826
1827 if (si->pci_1.enable_bus)
1828 mv64x60_set_bits(bh, MV64x60_PCI1_CMD,
1829 ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
1830
1831 /*
1832 * Dave Wilhardt found that bit 4 in the PCI Command registers must
1833 * be set if you are using cache coherency.
1834 */
1835 #if !defined(CONFIG_NOT_COHERENT_CACHE)
1836 mv64x60_set_bits(bh, GT64260_CPU_WB_PRIORITY_BUFFER_DEPTH, 0xf);
1837
1838 /* Res #MEM-4 -- cpu read buffer to buffer 1 */
1839 if ((mv64x60_read(bh, MV64x60_CPU_MODE) & 0xf0) == 0x40)
1840 mv64x60_set_bits(bh, GT64260_SDRAM_CONFIG, (1<<26));
1841
1842 save_exclude = mv64x60_pci_exclude_bridge;
1843 mv64x60_pci_exclude_bridge = 0;
1844 if (si->pci_0.enable_bus) {
1845 early_read_config_dword(bh->hose_a, 0, PCI_DEVFN(0,0),
1846 PCI_COMMAND, &val);
1847 val |= PCI_COMMAND_INVALIDATE;
1848 early_write_config_dword(bh->hose_a, 0, PCI_DEVFN(0,0),
1849 PCI_COMMAND, val);
1850 }
1851
1852 if (si->pci_1.enable_bus) {
1853 early_read_config_dword(bh->hose_b, 0, PCI_DEVFN(0,0),
1854 PCI_COMMAND, &val);
1855 val |= PCI_COMMAND_INVALIDATE;
1856 early_write_config_dword(bh->hose_b, 0, PCI_DEVFN(0,0),
1857 PCI_COMMAND, val);
1858 }
1859 mv64x60_pci_exclude_bridge = save_exclude;
1860 #endif
1861
1862 /* Disable buffer/descriptor snooping */
1863 mv64x60_clr_bits(bh, 0xf280, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
1864 mv64x60_clr_bits(bh, 0xf2c0, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
1865
1866 #ifdef CONFIG_SERIAL_MPSC
1867 /*
1868 * The 64260B is not supposed to have the bug where the MPSC & ENET
1869 * can't access cache coherent regions. However, testing has shown
1870 * that the MPSC, at least, still has this bug.
1871 */
1872 mv64x60_mpsc0_pdata.cache_mgmt = 1;
1873 mv64x60_mpsc1_pdata.cache_mgmt = 1;
1874
1875 if ((r = platform_get_resource(&mpsc1_device, IORESOURCE_IRQ, 0))
1876 != NULL) {
1877 r->start = MV64x60_IRQ_SDMA_0;
1878 r->end = MV64x60_IRQ_SDMA_0;
1879 }
1880 #endif
1881 }
1882
1883 /*
1884 *****************************************************************************
1885 *
1886 * MV64360-Specific Routines
1887 *
1888 *****************************************************************************
1889 */
1890 /*
1891 * mv64360_translate_size()
1892 *
1893 * On the MV64360, the size register is set similar to the size you get
1894 * from a pci config space BAR register. That is, programmed from LSB to MSB
1895 * as a sequence of 1's followed by a sequence of 0's. IOW, "size -1" with the
1896 * assumption that the size is a power of 2.
1897 */
1898 static u32 __init
1899 mv64360_translate_size(u32 base_addr, u32 size, u32 num_bits)
1900 {
1901 return mv64x60_mask(size - 1, num_bits);
1902 }
1903
1904 /*
1905 * mv64360_untranslate_size()
1906 *
1907 * Translate the size register value of a window into a window size.
1908 */
1909 static u32 __init
1910 mv64360_untranslate_size(u32 base_addr, u32 size, u32 num_bits)
1911 {
1912 if (size > 0) {
1913 size >>= (32 - num_bits);
1914 size++;
1915 size <<= (32 - num_bits);
1916 }
1917
1918 return size;
1919 }
1920
1921 /*
1922 * mv64360_set_pci2mem_window()
1923 *
1924 * The PCI->MEM window registers are actually in PCI config space so need
1925 * to set them by setting the correct config space BARs.
1926 */
1927 struct {
1928 u32 fcn;
1929 u32 base_hi_bar;
1930 u32 base_lo_bar;
1931 } static mv64360_reg_addrs[2][4] __initdata = {
1932 {{ 0, 0x14, 0x10 }, { 0, 0x1c, 0x18 },
1933 { 1, 0x14, 0x10 }, { 1, 0x1c, 0x18 }},
1934 {{ 0, 0x94, 0x90 }, { 0, 0x9c, 0x98 },
1935 { 1, 0x94, 0x90 }, { 1, 0x9c, 0x98 }}
1936 };
1937
1938 static void __init
1939 mv64360_set_pci2mem_window(struct pci_controller *hose, u32 bus, u32 window,
1940 u32 base)
1941 {
1942 u8 save_exclude;
1943
1944 pr_debug("set pci->mem window: %d, hose: %d, base: 0x%x\n", window,
1945 hose->index, base);
1946
1947 save_exclude = mv64x60_pci_exclude_bridge;
1948 mv64x60_pci_exclude_bridge = 0;
1949 early_write_config_dword(hose, 0,
1950 PCI_DEVFN(0, mv64360_reg_addrs[bus][window].fcn),
1951 mv64360_reg_addrs[bus][window].base_hi_bar, 0);
1952 early_write_config_dword(hose, 0,
1953 PCI_DEVFN(0, mv64360_reg_addrs[bus][window].fcn),
1954 mv64360_reg_addrs[bus][window].base_lo_bar,
1955 mv64x60_mask(base,20) | 0xc);
1956 mv64x60_pci_exclude_bridge = save_exclude;
1957 }
1958
1959 /*
1960 * mv64360_set_pci2regs_window()
1961 *
1962 * Set where the bridge's registers appear in PCI MEM space.
1963 */
1964 static u32 mv64360_offset[2][2] __initdata = {{0x20, 0x24}, {0xa0, 0xa4}};
1965
1966 static void __init
1967 mv64360_set_pci2regs_window(struct mv64x60_handle *bh,
1968 struct pci_controller *hose, u32 bus, u32 base)
1969 {
1970 u8 save_exclude;
1971
1972 pr_debug("set pci->internal regs hose: %d, base: 0x%x\n", hose->index,
1973 base);
1974
1975 save_exclude = mv64x60_pci_exclude_bridge;
1976 mv64x60_pci_exclude_bridge = 0;
1977 early_write_config_dword(hose, 0, PCI_DEVFN(0,0),
1978 mv64360_offset[bus][0], (base << 16));
1979 early_write_config_dword(hose, 0, PCI_DEVFN(0,0),
1980 mv64360_offset[bus][1], 0);
1981 mv64x60_pci_exclude_bridge = save_exclude;
1982 }
1983
1984 /*
1985 * mv64360_is_enabled_32bit()
1986 *
1987 * On a MV64360, a window is enabled by either clearing a bit in the
1988 * CPU BAR Enable reg or setting a bit in the window's base reg.
1989 * Note that this doesn't work for windows on the PCI slave side but we don't
1990 * check those so its okay.
1991 */
1992 static u32 __init
1993 mv64360_is_enabled_32bit(struct mv64x60_handle *bh, u32 window)
1994 {
1995 u32 extra, rc = 0;
1996
1997 if (((mv64360_32bit_windows[window].base_reg != 0) &&
1998 (mv64360_32bit_windows[window].size_reg != 0)) ||
1999 (window == MV64x60_CPU2SRAM_WIN)) {
2000
2001 extra = mv64360_32bit_windows[window].extra;
2002
2003 switch (extra & MV64x60_EXTRA_MASK) {
2004 case MV64x60_EXTRA_CPUWIN_ENAB:
2005 rc = (mv64x60_read(bh, MV64360_CPU_BAR_ENABLE) &
2006 (1 << (extra & 0x1f))) == 0;
2007 break;
2008
2009 case MV64x60_EXTRA_CPUPROT_ENAB:
2010 rc = (mv64x60_read(bh,
2011 mv64360_32bit_windows[window].base_reg) &
2012 (1 << (extra & 0x1f))) != 0;
2013 break;
2014
2015 case MV64x60_EXTRA_ENET_ENAB:
2016 rc = (mv64x60_read(bh, MV64360_ENET2MEM_BAR_ENABLE) &
2017 (1 << (extra & 0x7))) == 0;
2018 break;
2019
2020 case MV64x60_EXTRA_MPSC_ENAB:
2021 rc = (mv64x60_read(bh, MV64360_MPSC2MEM_BAR_ENABLE) &
2022 (1 << (extra & 0x3))) == 0;
2023 break;
2024
2025 case MV64x60_EXTRA_IDMA_ENAB:
2026 rc = (mv64x60_read(bh, MV64360_IDMA2MEM_BAR_ENABLE) &
2027 (1 << (extra & 0x7))) == 0;
2028 break;
2029
2030 default:
2031 printk(KERN_ERR "mv64360_is_enabled: %s\n",
2032 "32bit table corrupted");
2033 }
2034 }
2035
2036 return rc;
2037 }
2038
2039 /*
2040 * mv64360_enable_window_32bit()
2041 *
2042 * On a MV64360, a window is enabled by either clearing a bit in the
2043 * CPU BAR Enable reg or setting a bit in the window's base reg.
2044 */
2045 static void __init
2046 mv64360_enable_window_32bit(struct mv64x60_handle *bh, u32 window)
2047 {
2048 u32 extra;
2049
2050 pr_debug("enable 32bit window: %d\n", window);
2051
2052 if (((mv64360_32bit_windows[window].base_reg != 0) &&
2053 (mv64360_32bit_windows[window].size_reg != 0)) ||
2054 (window == MV64x60_CPU2SRAM_WIN)) {
2055
2056 extra = mv64360_32bit_windows[window].extra;
2057
2058 switch (extra & MV64x60_EXTRA_MASK) {
2059 case MV64x60_EXTRA_CPUWIN_ENAB:
2060 mv64x60_clr_bits(bh, MV64360_CPU_BAR_ENABLE,
2061 (1 << (extra & 0x1f)));
2062 break;
2063
2064 case MV64x60_EXTRA_CPUPROT_ENAB:
2065 mv64x60_set_bits(bh,
2066 mv64360_32bit_windows[window].base_reg,
2067 (1 << (extra & 0x1f)));
2068 break;
2069
2070 case MV64x60_EXTRA_ENET_ENAB:
2071 mv64x60_clr_bits(bh, MV64360_ENET2MEM_BAR_ENABLE,
2072 (1 << (extra & 0x7)));
2073 break;
2074
2075 case MV64x60_EXTRA_MPSC_ENAB:
2076 mv64x60_clr_bits(bh, MV64360_MPSC2MEM_BAR_ENABLE,
2077 (1 << (extra & 0x3)));
2078 break;
2079
2080 case MV64x60_EXTRA_IDMA_ENAB:
2081 mv64x60_clr_bits(bh, MV64360_IDMA2MEM_BAR_ENABLE,
2082 (1 << (extra & 0x7)));
2083 break;
2084
2085 default:
2086 printk(KERN_ERR "mv64360_enable: %s\n",
2087 "32bit table corrupted");
2088 }
2089 }
2090 }
2091
2092 /*
2093 * mv64360_disable_window_32bit()
2094 *
2095 * On a MV64360, a window is disabled by either setting a bit in the
2096 * CPU BAR Enable reg or clearing a bit in the window's base reg.
2097 */
2098 static void __init
2099 mv64360_disable_window_32bit(struct mv64x60_handle *bh, u32 window)
2100 {
2101 u32 extra;
2102
2103 pr_debug("disable 32bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
2104 window, mv64360_32bit_windows[window].base_reg,
2105 mv64360_32bit_windows[window].size_reg);
2106
2107 if (((mv64360_32bit_windows[window].base_reg != 0) &&
2108 (mv64360_32bit_windows[window].size_reg != 0)) ||
2109 (window == MV64x60_CPU2SRAM_WIN)) {
2110
2111 extra = mv64360_32bit_windows[window].extra;
2112
2113 switch (extra & MV64x60_EXTRA_MASK) {
2114 case MV64x60_EXTRA_CPUWIN_ENAB:
2115 mv64x60_set_bits(bh, MV64360_CPU_BAR_ENABLE,
2116 (1 << (extra & 0x1f)));
2117 break;
2118
2119 case MV64x60_EXTRA_CPUPROT_ENAB:
2120 mv64x60_clr_bits(bh,
2121 mv64360_32bit_windows[window].base_reg,
2122 (1 << (extra & 0x1f)));
2123 break;
2124
2125 case MV64x60_EXTRA_ENET_ENAB:
2126 mv64x60_set_bits(bh, MV64360_ENET2MEM_BAR_ENABLE,
2127 (1 << (extra & 0x7)));
2128 break;
2129
2130 case MV64x60_EXTRA_MPSC_ENAB:
2131 mv64x60_set_bits(bh, MV64360_MPSC2MEM_BAR_ENABLE,
2132 (1 << (extra & 0x3)));
2133 break;
2134
2135 case MV64x60_EXTRA_IDMA_ENAB:
2136 mv64x60_set_bits(bh, MV64360_IDMA2MEM_BAR_ENABLE,
2137 (1 << (extra & 0x7)));
2138 break;
2139
2140 default:
2141 printk(KERN_ERR "mv64360_disable: %s\n",
2142 "32bit table corrupted");
2143 }
2144 }
2145 }
2146
2147 /*
2148 * mv64360_enable_window_64bit()
2149 *
2150 * On the MV64360, a 64-bit window is enabled by setting a bit in the window's
2151 * base reg.
2152 */
2153 static void __init
2154 mv64360_enable_window_64bit(struct mv64x60_handle *bh, u32 window)
2155 {
2156 pr_debug("enable 64bit window: %d\n", window);
2157
2158 if ((mv64360_64bit_windows[window].base_lo_reg!= 0) &&
2159 (mv64360_64bit_windows[window].size_reg != 0)) {
2160
2161 if ((mv64360_64bit_windows[window].extra & MV64x60_EXTRA_MASK)
2162 == MV64x60_EXTRA_PCIACC_ENAB)
2163 mv64x60_set_bits(bh,
2164 mv64360_64bit_windows[window].base_lo_reg,
2165 (1 << (mv64360_64bit_windows[window].extra &
2166 0x1f)));
2167 else
2168 printk(KERN_ERR "mv64360_enable: %s\n",
2169 "64bit table corrupted");
2170 }
2171 }
2172
2173 /*
2174 * mv64360_disable_window_64bit()
2175 *
2176 * On a MV64360, a 64-bit window is disabled by clearing a bit in the window's
2177 * base reg.
2178 */
2179 static void __init
2180 mv64360_disable_window_64bit(struct mv64x60_handle *bh, u32 window)
2181 {
2182 pr_debug("disable 64bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
2183 window, mv64360_64bit_windows[window].base_lo_reg,
2184 mv64360_64bit_windows[window].size_reg);
2185
2186 if ((mv64360_64bit_windows[window].base_lo_reg != 0) &&
2187 (mv64360_64bit_windows[window].size_reg != 0)) {
2188 if ((mv64360_64bit_windows[window].extra & MV64x60_EXTRA_MASK)
2189 == MV64x60_EXTRA_PCIACC_ENAB)
2190 mv64x60_clr_bits(bh,
2191 mv64360_64bit_windows[window].base_lo_reg,
2192 (1 << (mv64360_64bit_windows[window].extra &
2193 0x1f)));
2194 else
2195 printk(KERN_ERR "mv64360_disable: %s\n",
2196 "64bit table corrupted");
2197 }
2198 }
2199
2200 /*
2201 * mv64360_disable_all_windows()
2202 *
2203 * The MV64360 has a few windows that aren't represented in the table of
2204 * windows at the top of this file. This routine turns all of them off
2205 * except for the memory controller windows, of course.
2206 */
2207 static void __init
2208 mv64360_disable_all_windows(struct mv64x60_handle *bh,
2209 struct mv64x60_setup_info *si)
2210 {
2211 u32 preserve, i;
2212
2213 /* Disable 32bit windows (don't disable cpu->mem windows) */
2214 for (i=MV64x60_CPU2DEV_0_WIN; i<MV64x60_32BIT_WIN_COUNT; i++) {
2215 if (i < 32)
2216 preserve = si->window_preserve_mask_32_lo & (1 << i);
2217 else
2218 preserve = si->window_preserve_mask_32_hi & (1<<(i-32));
2219
2220 if (!preserve)
2221 mv64360_disable_window_32bit(bh, i);
2222 }
2223
2224 /* Disable 64bit windows */
2225 for (i=0; i<MV64x60_64BIT_WIN_COUNT; i++)
2226 if (!(si->window_preserve_mask_64 & (1<<i)))
2227 mv64360_disable_window_64bit(bh, i);
2228
2229 /* Turn off PCI->MEM access cntl wins not in mv64360_64bit_windows[] */
2230 mv64x60_clr_bits(bh, MV64x60_PCI0_ACC_CNTL_4_BASE_LO, 0);
2231 mv64x60_clr_bits(bh, MV64x60_PCI0_ACC_CNTL_5_BASE_LO, 0);
2232 mv64x60_clr_bits(bh, MV64x60_PCI1_ACC_CNTL_4_BASE_LO, 0);
2233 mv64x60_clr_bits(bh, MV64x60_PCI1_ACC_CNTL_5_BASE_LO, 0);
2234
2235 /* Disable all PCI-><whatever> windows */
2236 mv64x60_set_bits(bh, MV64x60_PCI0_BAR_ENABLE, 0x0000f9ff);
2237 mv64x60_set_bits(bh, MV64x60_PCI1_BAR_ENABLE, 0x0000f9ff);
2238 }
2239
2240 /*
2241 * mv64360_config_io2mem_windows()
2242 *
2243 * ENET, MPSC, and IDMA ctlrs on the MV64[34]60 have separate windows that
2244 * must be set up so that the respective ctlr can access system memory.
2245 */
2246 static u32 enet_tab[MV64x60_CPU2MEM_WINDOWS] __initdata = {
2247 MV64x60_ENET2MEM_0_WIN, MV64x60_ENET2MEM_1_WIN,
2248 MV64x60_ENET2MEM_2_WIN, MV64x60_ENET2MEM_3_WIN,
2249 };
2250
2251 static u32 mpsc_tab[MV64x60_CPU2MEM_WINDOWS] __initdata = {
2252 MV64x60_MPSC2MEM_0_WIN, MV64x60_MPSC2MEM_1_WIN,
2253 MV64x60_MPSC2MEM_2_WIN, MV64x60_MPSC2MEM_3_WIN,
2254 };
2255
2256 static u32 idma_tab[MV64x60_CPU2MEM_WINDOWS] __initdata = {
2257 MV64x60_IDMA2MEM_0_WIN, MV64x60_IDMA2MEM_1_WIN,
2258 MV64x60_IDMA2MEM_2_WIN, MV64x60_IDMA2MEM_3_WIN,
2259 };
2260
2261 static u32 dram_selects[MV64x60_CPU2MEM_WINDOWS] __initdata =
2262 { 0xe, 0xd, 0xb, 0x7 };
2263
2264 static void __init
2265 mv64360_config_io2mem_windows(struct mv64x60_handle *bh,
2266 struct mv64x60_setup_info *si,
2267 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
2268 {
2269 u32 i, win;
2270
2271 pr_debug("config_io2regs_windows: enet, mpsc, idma -> bridge regs\n");
2272
2273 mv64x60_write(bh, MV64360_ENET2MEM_ACC_PROT_0, 0);
2274 mv64x60_write(bh, MV64360_ENET2MEM_ACC_PROT_1, 0);
2275 mv64x60_write(bh, MV64360_ENET2MEM_ACC_PROT_2, 0);
2276
2277 mv64x60_write(bh, MV64360_MPSC2MEM_ACC_PROT_0, 0);
2278 mv64x60_write(bh, MV64360_MPSC2MEM_ACC_PROT_1, 0);
2279
2280 mv64x60_write(bh, MV64360_IDMA2MEM_ACC_PROT_0, 0);
2281 mv64x60_write(bh, MV64360_IDMA2MEM_ACC_PROT_1, 0);
2282 mv64x60_write(bh, MV64360_IDMA2MEM_ACC_PROT_2, 0);
2283 mv64x60_write(bh, MV64360_IDMA2MEM_ACC_PROT_3, 0);
2284
2285 /* Assume that mem ctlr has no more windows than embedded I/O ctlr */
2286 for (win=MV64x60_CPU2MEM_0_WIN,i=0;win<=MV64x60_CPU2MEM_3_WIN;win++,i++)
2287 if (bh->ci->is_enabled_32bit(bh, win)) {
2288 mv64x60_set_32bit_window(bh, enet_tab[i],
2289 mem_windows[i][0], mem_windows[i][1],
2290 (dram_selects[i] << 8) |
2291 (si->enet_options[i] & 0x3000));
2292 bh->ci->enable_window_32bit(bh, enet_tab[i]);
2293
2294 /* Give enet r/w access to memory region */
2295 mv64x60_set_bits(bh, MV64360_ENET2MEM_ACC_PROT_0,
2296 (0x3 << (i << 1)));
2297 mv64x60_set_bits(bh, MV64360_ENET2MEM_ACC_PROT_1,
2298 (0x3 << (i << 1)));
2299 mv64x60_set_bits(bh, MV64360_ENET2MEM_ACC_PROT_2,
2300 (0x3 << (i << 1)));
2301
2302 mv64x60_set_32bit_window(bh, mpsc_tab[i],
2303 mem_windows[i][0], mem_windows[i][1],
2304 (dram_selects[i] << 8) |
2305 (si->mpsc_options[i] & 0x3000));
2306 bh->ci->enable_window_32bit(bh, mpsc_tab[i]);
2307
2308 /* Give mpsc r/w access to memory region */
2309 mv64x60_set_bits(bh, MV64360_MPSC2MEM_ACC_PROT_0,
2310 (0x3 << (i << 1)));
2311 mv64x60_set_bits(bh, MV64360_MPSC2MEM_ACC_PROT_1,
2312 (0x3 << (i << 1)));
2313
2314 mv64x60_set_32bit_window(bh, idma_tab[i],
2315 mem_windows[i][0], mem_windows[i][1],
2316 (dram_selects[i] << 8) |
2317 (si->idma_options[i] & 0x3000));
2318 bh->ci->enable_window_32bit(bh, idma_tab[i]);
2319
2320 /* Give idma r/w access to memory region */
2321 mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_0,
2322 (0x3 << (i << 1)));
2323 mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_1,
2324 (0x3 << (i << 1)));
2325 mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_2,
2326 (0x3 << (i << 1)));
2327 mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_3,
2328 (0x3 << (i << 1)));
2329 }
2330 }
2331
2332 /*
2333 * mv64360_set_mpsc2regs_window()
2334 *
2335 * MPSC has a window to the bridge's internal registers. Call this routine
2336 * to change that window so it doesn't conflict with the windows mapping the
2337 * mpsc to system memory.
2338 */
2339 static void __init
2340 mv64360_set_mpsc2regs_window(struct mv64x60_handle *bh, u32 base)
2341 {
2342 pr_debug("set mpsc->internal regs, base: 0x%x\n", base);
2343 mv64x60_write(bh, MV64360_MPSC2REGS_BASE, base & 0xffff0000);
2344 }
2345
2346 /*
2347 * mv64360_chip_specific_init()
2348 *
2349 * Implement errata workarounds for the MV64360.
2350 */
2351 static void __init
2352 mv64360_chip_specific_init(struct mv64x60_handle *bh,
2353 struct mv64x60_setup_info *si)
2354 {
2355 #if !defined(CONFIG_NOT_COHERENT_CACHE)
2356 mv64x60_set_bits(bh, MV64360_D_UNIT_CONTROL_HIGH, (1<<24));
2357 #endif
2358 #ifdef CONFIG_SERIAL_MPSC
2359 mv64x60_mpsc0_pdata.brg_can_tune = 1;
2360 mv64x60_mpsc0_pdata.cache_mgmt = 1;
2361 mv64x60_mpsc1_pdata.brg_can_tune = 1;
2362 mv64x60_mpsc1_pdata.cache_mgmt = 1;
2363 #endif
2364 }
2365
2366 /*
2367 * mv64460_chip_specific_init()
2368 *
2369 * Implement errata workarounds for the MV64460.
2370 */
2371 static void __init
2372 mv64460_chip_specific_init(struct mv64x60_handle *bh,
2373 struct mv64x60_setup_info *si)
2374 {
2375 #if !defined(CONFIG_NOT_COHERENT_CACHE)
2376 mv64x60_set_bits(bh, MV64360_D_UNIT_CONTROL_HIGH, (1<<24) | (1<<25));
2377 mv64x60_set_bits(bh, MV64460_D_UNIT_MMASK, (1<<1) | (1<<4));
2378 #endif
2379 #ifdef CONFIG_SERIAL_MPSC
2380 mv64x60_mpsc0_pdata.brg_can_tune = 1;
2381 mv64x60_mpsc0_pdata.cache_mgmt = 1;
2382 mv64x60_mpsc1_pdata.brg_can_tune = 1;
2383 mv64x60_mpsc1_pdata.cache_mgmt = 1;
2384 #endif
2385 }
2386
2387
2388 #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
2389 /* Export the hotswap register via sysfs for enum event monitoring */
2390 #define VAL_LEN_MAX 11 /* 32-bit hex or dec stringified number + '\n' */
2391
2392 static DEFINE_MUTEX(mv64xxx_hs_lock);
2393
2394 static ssize_t
2395 mv64xxx_hs_reg_read(struct kobject *kobj, char *buf, loff_t off, size_t count)
2396 {
2397 u32 v;
2398 u8 save_exclude;
2399
2400 if (off > 0)
2401 return 0;
2402 if (count < VAL_LEN_MAX)
2403 return -EINVAL;
2404
2405 if (mutex_lock_interruptible(&mv64xxx_hs_lock))
2406 return -ERESTARTSYS;
2407 save_exclude = mv64x60_pci_exclude_bridge;
2408 mv64x60_pci_exclude_bridge = 0;
2409 early_read_config_dword(&sysfs_hose_a, 0, PCI_DEVFN(0, 0),
2410 MV64360_PCICFG_CPCI_HOTSWAP, &v);
2411 mv64x60_pci_exclude_bridge = save_exclude;
2412 mutex_unlock(&mv64xxx_hs_lock);
2413
2414 return sprintf(buf, "0x%08x\n", v);
2415 }
2416
2417 static ssize_t
2418 mv64xxx_hs_reg_write(struct kobject *kobj, char *buf, loff_t off, size_t count)
2419 {
2420 u32 v;
2421 u8 save_exclude;
2422
2423 if (off > 0)
2424 return 0;
2425 if (count <= 0)
2426 return -EINVAL;
2427
2428 if (sscanf(buf, "%i", &v) == 1) {
2429 if (mutex_lock_interruptible(&mv64xxx_hs_lock))
2430 return -ERESTARTSYS;
2431 save_exclude = mv64x60_pci_exclude_bridge;
2432 mv64x60_pci_exclude_bridge = 0;
2433 early_write_config_dword(&sysfs_hose_a, 0, PCI_DEVFN(0, 0),
2434 MV64360_PCICFG_CPCI_HOTSWAP, v);
2435 mv64x60_pci_exclude_bridge = save_exclude;
2436 mutex_unlock(&mv64xxx_hs_lock);
2437 }
2438 else
2439 count = -EINVAL;
2440
2441 return count;
2442 }
2443
2444 static struct bin_attribute mv64xxx_hs_reg_attr = { /* Hotswap register */
2445 .attr = {
2446 .name = "hs_reg",
2447 .mode = S_IRUGO | S_IWUSR,
2448 },
2449 .size = VAL_LEN_MAX,
2450 .read = mv64xxx_hs_reg_read,
2451 .write = mv64xxx_hs_reg_write,
2452 };
2453
2454 /* Provide sysfs file indicating if this platform supports the hs_reg */
2455 static ssize_t
2456 mv64xxx_hs_reg_valid_show(struct device *dev, struct device_attribute *attr,
2457 char *buf)
2458 {
2459 struct platform_device *pdev;
2460 struct mv64xxx_pdata *pdp;
2461 u32 v;
2462
2463 pdev = container_of(dev, struct platform_device, dev);
2464 pdp = (struct mv64xxx_pdata *)pdev->dev.platform_data;
2465
2466 if (mutex_lock_interruptible(&mv64xxx_hs_lock))
2467 return -ERESTARTSYS;
2468 v = pdp->hs_reg_valid;
2469 mutex_unlock(&mv64xxx_hs_lock);
2470
2471 return sprintf(buf, "%i\n", v);
2472 }
2473 static DEVICE_ATTR(hs_reg_valid, S_IRUGO, mv64xxx_hs_reg_valid_show, NULL);
2474
2475 static int __init
2476 mv64xxx_sysfs_init(void)
2477 {
2478 sysfs_create_bin_file(&mv64xxx_device.dev.kobj, &mv64xxx_hs_reg_attr);
2479 sysfs_create_file(&mv64xxx_device.dev.kobj,&dev_attr_hs_reg_valid.attr);
2480 return 0;
2481 }
2482 subsys_initcall(mv64xxx_sysfs_init);
2483 #endif
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