arch/sparc64/kernel/iommu.c

   1 /* iommu.c: Generic sparc64 IOMMU support.
   2  *
   3  * Copyright (C) 1999, 2007 David S. Miller (davem@davemloft.net)
   4  * Copyright (C) 1999, 2000 Jakub Jelinek (jakub@redhat.com)
   5  */
   6
   7 #include <linux/kernel.h>
   8 #include <linux/module.h>
   9 #include <linux/delay.h>
  10 #include <linux/device.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/errno.h>
  13
  14 #ifdef CONFIG_PCI
  15 #include <linux/pci.h>
  16 #endif
  17
  18 #include <asm/iommu.h>
  19
  20 #include "iommu_common.h"
  21
  22 #define STC_CTXMATCH_ADDR(STC, CTX)     \
  23         ((STC)->strbuf_ctxmatch_base + ((CTX) << 3))
  24 #define STC_FLUSHFLAG_INIT(STC) \
  25         (*((STC)->strbuf_flushflag) = 0UL)
  26 #define STC_FLUSHFLAG_SET(STC) \
  27         (*((STC)->strbuf_flushflag) != 0UL)
  28
  29 #define iommu_read(__reg) \
  30 ({      u64 __ret; \
  31         __asm__ __volatile__("ldxa [%1] %2, %0" \
  32                              : "=r" (__ret) \
  33                              : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
  34                              : "memory"); \
  35         __ret; \
  36 })
  37 #define iommu_write(__reg, __val) \
  38         __asm__ __volatile__("stxa %0, [%1] %2" \
  39                              : /* no outputs */ \
  40                              : "r" (__val), "r" (__reg), \
  41                                "i" (ASI_PHYS_BYPASS_EC_E))
  42
  43 /* Must be invoked under the IOMMU lock. */
  44 static void __iommu_flushall(struct iommu *iommu)
  45 {
  46         if (iommu->iommu_flushinv) {
  47                 iommu_write(iommu->iommu_flushinv, ~(u64)0);
  48         } else {
  49                 unsigned long tag;
  50                 int entry;
  51
  52                 tag = iommu->iommu_tags;
  53                 for (entry = 0; entry < 16; entry++) {
  54                         iommu_write(tag, 0);
  55                         tag += 8;
  56                 }
  57
  58                 /* Ensure completion of previous PIO writes. */
  59                 (void) iommu_read(iommu->write_complete_reg);
  60         }
  61 }
  62
  63 #define IOPTE_CONSISTENT(CTX) \
  64         (IOPTE_VALID | IOPTE_CACHE | \
  65          (((CTX) << 47) & IOPTE_CONTEXT))
  66
  67 #define IOPTE_STREAMING(CTX) \
  68         (IOPTE_CONSISTENT(CTX) | IOPTE_STBUF)
  69
  70 /* Existing mappings are never marked invalid, instead they
  71  * are pointed to a dummy page.
  72  */
  73 #define IOPTE_IS_DUMMY(iommu, iopte)    \
  74         ((iopte_val(*iopte) & IOPTE_PAGE) == (iommu)->dummy_page_pa)
  75
  76 static inline void iopte_make_dummy(struct iommu *iommu, iopte_t *iopte)
  77 {
  78         unsigned long val = iopte_val(*iopte);
  79
  80         val &= ~IOPTE_PAGE;
  81         val |= iommu->dummy_page_pa;
  82
  83         iopte_val(*iopte) = val;
  84 }
  85
  86 /* Based largely upon the ppc64 iommu allocator.  */
  87 static long arena_alloc(struct iommu *iommu, unsigned long npages)
  88 {
  89         struct iommu_arena *arena = &iommu->arena;
  90         unsigned long n, i, start, end, limit;
  91         int pass;
  92
  93         limit = arena->limit;
  94         start = arena->hint;
  95         pass = 0;
  96
  97 again:
  98         n = find_next_zero_bit(arena->map, limit, start);
  99         end = n + npages;
 100         if (unlikely(end >= limit)) {
 101                 if (likely(pass < 1)) {
 102                         limit = start;
 103                         start = 0;
 104                         __iommu_flushall(iommu);
 105                         pass++;
 106                         goto again;
 107                 } else {
 108                         /* Scanned the whole thing, give up. */
 109                         return -1;
 110                 }
 111         }
 112
 113         for (i = n; i < end; i++) {
 114                 if (test_bit(i, arena->map)) {
 115                         start = i + 1;
 116                         goto again;
 117                 }
 118         }
 119
 120         for (i = n; i < end; i++)
 121                 __set_bit(i, arena->map);
 122
 123         arena->hint = end;
 124
 125         return n;
 126 }
 127
 128 static void arena_free(struct iommu_arena *arena, unsigned long base, unsigned long npages)
 129 {
 130         unsigned long i;
 131
 132         for (i = base; i < (base + npages); i++)
 133                 __clear_bit(i, arena->map);
 134 }
 135
 136 int iommu_table_init(struct iommu *iommu, int tsbsize,
 137                      u32 dma_offset, u32 dma_addr_mask)
 138 {
 139         unsigned long i, tsbbase, order, sz, num_tsb_entries;
 140
 141         num_tsb_entries = tsbsize / sizeof(iopte_t);
 142
 143         /* Setup initial software IOMMU state. */
 144         spin_lock_init(&iommu->lock);
 145         iommu->ctx_lowest_free = 1;
 146         iommu->page_table_map_base = dma_offset;
 147         iommu->dma_addr_mask = dma_addr_mask;
 148
 149         /* Allocate and initialize the free area map.  */
 150         sz = num_tsb_entries / 8;
 151         sz = (sz + 7UL) & ~7UL;
 152         iommu->arena.map = kzalloc(sz, GFP_KERNEL);
 153         if (!iommu->arena.map) {
 154                 printk(KERN_ERR "IOMMU: Error, kmalloc(arena.map) failed.\n");
 155                 return -ENOMEM;
 156         }
 157         iommu->arena.limit = num_tsb_entries;
 158
 159         /* Allocate and initialize the dummy page which we
 160          * set inactive IO PTEs to point to.
 161          */
 162         iommu->dummy_page = __get_free_pages(GFP_KERNEL, 0);
 163         if (!iommu->dummy_page) {
 164                 printk(KERN_ERR "IOMMU: Error, gfp(dummy_page) failed.\n");
 165                 goto out_free_map;
 166         }
 167         memset((void *)iommu->dummy_page, 0, PAGE_SIZE);
 168         iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page);
 169
 170         /* Now allocate and setup the IOMMU page table itself.  */
 171         order = get_order(tsbsize);
 172         tsbbase = __get_free_pages(GFP_KERNEL, order);
 173         if (!tsbbase) {
 174                 printk(KERN_ERR "IOMMU: Error, gfp(tsb) failed.\n");
 175                 goto out_free_dummy_page;
 176         }
 177         iommu->page_table = (iopte_t *)tsbbase;
 178
 179         for (i = 0; i < num_tsb_entries; i++)
 180                 iopte_make_dummy(iommu, &iommu->page_table[i]);
 181
 182         return 0;
 183
 184 out_free_dummy_page:
 185         free_page(iommu->dummy_page);
 186         iommu->dummy_page = 0UL;
 187
 188 out_free_map:
 189         kfree(iommu->arena.map);
 190         iommu->arena.map = NULL;
 191
 192         return -ENOMEM;
 193 }
 194
 195 static inline iopte_t *alloc_npages(struct iommu *iommu, unsigned long npages)
 196 {
 197         long entry;
 198
 199         entry = arena_alloc(iommu, npages);
 200         if (unlikely(entry < 0))
 201                 return NULL;
 202
 203         return iommu->page_table + entry;
 204 }
 205
 206 static inline void free_npages(struct iommu *iommu, dma_addr_t base, unsigned long npages)
 207 {
 208         arena_free(&iommu->arena, base >> IO_PAGE_SHIFT, npages);
 209 }
 210
 211 static int iommu_alloc_ctx(struct iommu *iommu)
 212 {
 213         int lowest = iommu->ctx_lowest_free;
 214         int sz = IOMMU_NUM_CTXS - lowest;
 215         int n = find_next_zero_bit(iommu->ctx_bitmap, sz, lowest);
 216
 217         if (unlikely(n == sz)) {
 218                 n = find_next_zero_bit(iommu->ctx_bitmap, lowest, 1);
 219                 if (unlikely(n == lowest)) {
 220                         printk(KERN_WARNING "IOMMU: Ran out of contexts.\n");
 221                         n = 0;
 222                 }
 223         }
 224         if (n)
 225                 __set_bit(n, iommu->ctx_bitmap);
 226
 227         return n;
 228 }
 229
 230 static inline void iommu_free_ctx(struct iommu *iommu, int ctx)
 231 {
 232         if (likely(ctx)) {
 233                 __clear_bit(ctx, iommu->ctx_bitmap);
 234                 if (ctx < iommu->ctx_lowest_free)
 235                         iommu->ctx_lowest_free = ctx;
 236         }
 237 }
 238
 239 static void *dma_4u_alloc_coherent(struct device *dev, size_t size,
 240                                    dma_addr_t *dma_addrp, gfp_t gfp)
 241 {
 242         struct iommu *iommu;
 243         iopte_t *iopte;
 244         unsigned long flags, order, first_page;
 245         void *ret;
 246         int npages;
 247
 248         size = IO_PAGE_ALIGN(size);
 249         order = get_order(size);
 250         if (order >= 10)
 251                 return NULL;
 252
 253         first_page = __get_free_pages(gfp, order);
 254         if (first_page == 0UL)
 255                 return NULL;
 256         memset((char *)first_page, 0, PAGE_SIZE << order);
 257
 258         iommu = dev->archdata.iommu;
 259
 260         spin_lock_irqsave(&iommu->lock, flags);
 261         iopte = alloc_npages(iommu, size >> IO_PAGE_SHIFT);
 262         spin_unlock_irqrestore(&iommu->lock, flags);
 263
 264         if (unlikely(iopte == NULL)) {
 265                 free_pages(first_page, order);
 266                 return NULL;
 267         }
 268
 269         *dma_addrp = (iommu->page_table_map_base +
 270                       ((iopte - iommu->page_table) << IO_PAGE_SHIFT));
 271         ret = (void *) first_page;
 272         npages = size >> IO_PAGE_SHIFT;
 273         first_page = __pa(first_page);
 274         while (npages--) {
 275                 iopte_val(*iopte) = (IOPTE_CONSISTENT(0UL) |
 276                                      IOPTE_WRITE |
 277                                      (first_page & IOPTE_PAGE));
 278                 iopte++;
 279                 first_page += IO_PAGE_SIZE;
 280         }
 281
 282         return ret;
 283 }
 284
 285 static void dma_4u_free_coherent(struct device *dev, size_t size,
 286                                  void *cpu, dma_addr_t dvma)
 287 {
 288         struct iommu *iommu;
 289         iopte_t *iopte;
 290         unsigned long flags, order, npages;
 291
 292         npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
 293         iommu = dev->archdata.iommu;
 294         iopte = iommu->page_table +
 295                 ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
 296
 297         spin_lock_irqsave(&iommu->lock, flags);
 298
 299         free_npages(iommu, dvma - iommu->page_table_map_base, npages);
 300
 301         spin_unlock_irqrestore(&iommu->lock, flags);
 302
 303         order = get_order(size);
 304         if (order < 10)
 305                 free_pages((unsigned long)cpu, order);
 306 }
 307
 308 static dma_addr_t dma_4u_map_single(struct device *dev, void *ptr, size_t sz,
 309                                     enum dma_data_direction direction)
 310 {
 311         struct iommu *iommu;
 312         struct strbuf *strbuf;
 313         iopte_t *base;
 314         unsigned long flags, npages, oaddr;
 315         unsigned long i, base_paddr, ctx;
 316         u32 bus_addr, ret;
 317         unsigned long iopte_protection;
 318
 319         iommu = dev->archdata.iommu;
 320         strbuf = dev->archdata.stc;
 321
 322         if (unlikely(direction == DMA_NONE))
 323                 goto bad_no_ctx;
 324
 325         oaddr = (unsigned long)ptr;
 326         npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
 327         npages >>= IO_PAGE_SHIFT;
 328
 329         spin_lock_irqsave(&iommu->lock, flags);
 330         base = alloc_npages(iommu, npages);
 331         ctx = 0;
 332         if (iommu->iommu_ctxflush)
 333                 ctx = iommu_alloc_ctx(iommu);
 334         spin_unlock_irqrestore(&iommu->lock, flags);
 335
 336         if (unlikely(!base))
 337                 goto bad;
 338
 339         bus_addr = (iommu->page_table_map_base +
 340                     ((base - iommu->page_table) << IO_PAGE_SHIFT));
 341         ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
 342         base_paddr = __pa(oaddr & IO_PAGE_MASK);
 343         if (strbuf->strbuf_enabled)
 344                 iopte_protection = IOPTE_STREAMING(ctx);
 345         else
 346                 iopte_protection = IOPTE_CONSISTENT(ctx);
 347         if (direction != DMA_TO_DEVICE)
 348                 iopte_protection |= IOPTE_WRITE;
 349
 350         for (i = 0; i < npages; i++, base++, base_paddr += IO_PAGE_SIZE)
 351                 iopte_val(*base) = iopte_protection | base_paddr;
 352
 353         return ret;
 354
 355 bad:
 356         iommu_free_ctx(iommu, ctx);
 357 bad_no_ctx:
 358         if (printk_ratelimit())
 359                 WARN_ON(1);
 360         return DMA_ERROR_CODE;
 361 }
 362
 363 static void strbuf_flush(struct strbuf *strbuf, struct iommu *iommu,
 364                          u32 vaddr, unsigned long ctx, unsigned long npages,
 365                          enum dma_data_direction direction)
 366 {
 367         int limit;
 368
 369         if (strbuf->strbuf_ctxflush &&
 370             iommu->iommu_ctxflush) {
 371                 unsigned long matchreg, flushreg;
 372                 u64 val;
 373
 374                 flushreg = strbuf->strbuf_ctxflush;
 375                 matchreg = STC_CTXMATCH_ADDR(strbuf, ctx);
 376
 377                 iommu_write(flushreg, ctx);
 378                 val = iommu_read(matchreg);
 379                 val &= 0xffff;
 380                 if (!val)
 381                         goto do_flush_sync;
 382
 383                 while (val) {
 384                         if (val & 0x1)
 385                                 iommu_write(flushreg, ctx);
 386                         val >>= 1;
 387                 }
 388                 val = iommu_read(matchreg);
 389                 if (unlikely(val)) {
 390                         printk(KERN_WARNING "strbuf_flush: ctx flush "
 391                                "timeout matchreg[%lx] ctx[%lx]\n",
 392                                val, ctx);
 393                         goto do_page_flush;
 394                 }
 395         } else {
 396                 unsigned long i;
 397
 398         do_page_flush:
 399                 for (i = 0; i < npages; i++, vaddr += IO_PAGE_SIZE)
 400                         iommu_write(strbuf->strbuf_pflush, vaddr);
 401         }
 402
 403 do_flush_sync:
 404         /* If the device could not have possibly put dirty data into
 405          * the streaming cache, no flush-flag synchronization needs
 406          * to be performed.
 407          */
 408         if (direction == DMA_TO_DEVICE)
 409                 return;
 410
 411         STC_FLUSHFLAG_INIT(strbuf);
 412         iommu_write(strbuf->strbuf_fsync, strbuf->strbuf_flushflag_pa);
 413         (void) iommu_read(iommu->write_complete_reg);
 414
 415         limit = 100000;
 416         while (!STC_FLUSHFLAG_SET(strbuf)) {
 417                 limit--;
 418                 if (!limit)
 419                         break;
 420                 udelay(1);
 421                 rmb();
 422         }
 423         if (!limit)
 424                 printk(KERN_WARNING "strbuf_flush: flushflag timeout "
 425                        "vaddr[%08x] ctx[%lx] npages[%ld]\n",
 426                        vaddr, ctx, npages);
 427 }
 428
 429 static void dma_4u_unmap_single(struct device *dev, dma_addr_t bus_addr,
 430                                 size_t sz, enum dma_data_direction direction)
 431 {
 432         struct iommu *iommu;
 433         struct strbuf *strbuf;
 434         iopte_t *base;
 435         unsigned long flags, npages, ctx, i;
 436
 437         if (unlikely(direction == DMA_NONE)) {
 438                 if (printk_ratelimit())
 439                         WARN_ON(1);
 440                 return;
 441         }
 442
 443         iommu = dev->archdata.iommu;
 444         strbuf = dev->archdata.stc;
 445
 446         npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
 447         npages >>= IO_PAGE_SHIFT;
 448         base = iommu->page_table +
 449                 ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
 450         bus_addr &= IO_PAGE_MASK;
 451
 452         spin_lock_irqsave(&iommu->lock, flags);
 453
 454         /* Record the context, if any. */
 455         ctx = 0;
 456         if (iommu->iommu_ctxflush)
 457                 ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
 458
 459         /* Step 1: Kick data out of streaming buffers if necessary. */
 460         if (strbuf->strbuf_enabled)
 461                 strbuf_flush(strbuf, iommu, bus_addr, ctx,
 462                              npages, direction);
 463
 464         /* Step 2: Clear out TSB entries. */
 465         for (i = 0; i < npages; i++)
 466                 iopte_make_dummy(iommu, base + i);
 467
 468         free_npages(iommu, bus_addr - iommu->page_table_map_base, npages);
 469
 470         iommu_free_ctx(iommu, ctx);
 471
 472         spin_unlock_irqrestore(&iommu->lock, flags);
 473 }
 474
 475 #define SG_ENT_PHYS_ADDRESS(SG) (__pa(sg_virt((SG))))
 476
 477 static void fill_sg(iopte_t *iopte, struct scatterlist *sg,
 478                     int nused, int nelems,
 479                     unsigned long iopte_protection)
 480 {
 481         struct scatterlist *dma_sg = sg;
 482         int i;
 483
 484         for (i = 0; i < nused; i++) {
 485                 unsigned long pteval = ~0UL;
 486                 u32 dma_npages;
 487
 488                 dma_npages = ((dma_sg->dma_address & (IO_PAGE_SIZE - 1UL)) +
 489                               dma_sg->dma_length +
 490                               ((IO_PAGE_SIZE - 1UL))) >> IO_PAGE_SHIFT;
 491                 do {
 492                         unsigned long offset;
 493                         signed int len;
 494
 495                         /* If we are here, we know we have at least one
 496                          * more page to map.  So walk forward until we
 497                          * hit a page crossing, and begin creating new
 498                          * mappings from that spot.
 499                          */
 500                         for (;;) {
 501                                 unsigned long tmp;
 502
 503                                 tmp = SG_ENT_PHYS_ADDRESS(sg);
 504                                 len = sg->length;
 505                                 if (((tmp ^ pteval) >> IO_PAGE_SHIFT) != 0UL) {
 506                                         pteval = tmp & IO_PAGE_MASK;
 507                                         offset = tmp & (IO_PAGE_SIZE - 1UL);
 508                                         break;
 509                                 }
 510                                 if (((tmp ^ (tmp + len - 1UL)) >> IO_PAGE_SHIFT) != 0UL) {
 511                                         pteval = (tmp + IO_PAGE_SIZE) & IO_PAGE_MASK;
 512                                         offset = 0UL;
 513                                         len -= (IO_PAGE_SIZE - (tmp & (IO_PAGE_SIZE - 1UL)));
 514                                         break;
 515                                 }
 516                                 sg = sg_next(sg);
 517                                 nelems--;
 518                         }
 519
 520                         pteval = iopte_protection | (pteval & IOPTE_PAGE);
 521                         while (len > 0) {
 522                                 *iopte++ = __iopte(pteval);
 523                                 pteval += IO_PAGE_SIZE;
 524                                 len -= (IO_PAGE_SIZE - offset);
 525                                 offset = 0;
 526                                 dma_npages--;
 527                         }
 528
 529                         pteval = (pteval & IOPTE_PAGE) + len;
 530                         sg = sg_next(sg);
 531                         nelems--;
 532
 533                         /* Skip over any tail mappings we've fully mapped,
 534                          * adjusting pteval along the way.  Stop when we
 535                          * detect a page crossing event.
 536                          */
 537                         while (nelems &&
 538                                (pteval << (64 - IO_PAGE_SHIFT)) != 0UL &&
 539                                (pteval == SG_ENT_PHYS_ADDRESS(sg)) &&
 540                                ((pteval ^
 541                                  (SG_ENT_PHYS_ADDRESS(sg) + sg->length - 1UL)) >> IO_PAGE_SHIFT) == 0UL) {
 542                                 pteval += sg->length;
 543                                 sg = sg_next(sg);
 544                                 nelems--;
 545                         }
 546                         if ((pteval << (64 - IO_PAGE_SHIFT)) == 0UL)
 547                                 pteval = ~0UL;
 548                 } while (dma_npages != 0);
 549                 dma_sg = sg_next(dma_sg);
 550         }
 551 }
 552
 553 static int dma_4u_map_sg(struct device *dev, struct scatterlist *sglist,
 554                          int nelems, enum dma_data_direction direction)
 555 {
 556         struct iommu *iommu;
 557         struct strbuf *strbuf;
 558         unsigned long flags, ctx, npages, iopte_protection;
 559         iopte_t *base;
 560         u32 dma_base;
 561         struct scatterlist *sgtmp;
 562         int used;
 563
 564         /* Fast path single entry scatterlists. */
 565         if (nelems == 1) {
 566                 sglist->dma_address =
 567                         dma_4u_map_single(dev, sg_virt(sglist),
 568                                           sglist->length, direction);
 569                 if (unlikely(sglist->dma_address == DMA_ERROR_CODE))
 570                         return 0;
 571                 sglist->dma_length = sglist->length;
 572                 return 1;
 573         }
 574
 575         iommu = dev->archdata.iommu;
 576         strbuf = dev->archdata.stc;
 577
 578         if (unlikely(direction == DMA_NONE))
 579                 goto bad_no_ctx;
 580
 581         /* Step 1: Prepare scatter list. */
 582
 583         npages = prepare_sg(sglist, nelems);
 584
 585         /* Step 2: Allocate a cluster and context, if necessary. */
 586
 587         spin_lock_irqsave(&iommu->lock, flags);
 588
 589         base = alloc_npages(iommu, npages);
 590         ctx = 0;
 591         if (iommu->iommu_ctxflush)
 592                 ctx = iommu_alloc_ctx(iommu);
 593
 594         spin_unlock_irqrestore(&iommu->lock, flags);
 595
 596         if (base == NULL)
 597                 goto bad;
 598
 599         dma_base = iommu->page_table_map_base +
 600                 ((base - iommu->page_table) << IO_PAGE_SHIFT);
 601
 602         /* Step 3: Normalize DMA addresses. */
 603         used = nelems;
 604
 605         sgtmp = sglist;
 606         while (used && sgtmp->dma_length) {
 607                 sgtmp->dma_address += dma_base;
 608                 sgtmp = sg_next(sgtmp);
 609                 used--;
 610         }
 611         used = nelems - used;
 612
 613         /* Step 4: Create the mappings. */
 614         if (strbuf->strbuf_enabled)
 615                 iopte_protection = IOPTE_STREAMING(ctx);
 616         else
 617                 iopte_protection = IOPTE_CONSISTENT(ctx);
 618         if (direction != DMA_TO_DEVICE)
 619                 iopte_protection |= IOPTE_WRITE;
 620
 621         fill_sg(base, sglist, used, nelems, iopte_protection);
 622
 623 #ifdef VERIFY_SG
 624         verify_sglist(sglist, nelems, base, npages);
 625 #endif
 626
 627         return used;
 628
 629 bad:
 630         iommu_free_ctx(iommu, ctx);
 631 bad_no_ctx:
 632         if (printk_ratelimit())
 633                 WARN_ON(1);
 634         return 0;
 635 }
 636
 637 static void dma_4u_unmap_sg(struct device *dev, struct scatterlist *sglist,
 638                             int nelems, enum dma_data_direction direction)
 639 {
 640         struct iommu *iommu;
 641         struct strbuf *strbuf;
 642         iopte_t *base;
 643         unsigned long flags, ctx, i, npages;
 644         struct scatterlist *sg, *sgprv;
 645         u32 bus_addr;
 646
 647         if (unlikely(direction == DMA_NONE)) {
 648                 if (printk_ratelimit())
 649                         WARN_ON(1);
 650         }
 651
 652         iommu = dev->archdata.iommu;
 653         strbuf = dev->archdata.stc;
 654
 655         bus_addr = sglist->dma_address & IO_PAGE_MASK;
 656
 657         sgprv = NULL;
 658         for_each_sg(sglist, sg, nelems, i) {
 659                 if (sg->dma_length == 0)
 660                         break;
 661                 sgprv = sg;
 662         }
 663
 664         npages = (IO_PAGE_ALIGN(sgprv->dma_address + sgprv->dma_length) -
 665                   bus_addr) >> IO_PAGE_SHIFT;
 666
 667         base = iommu->page_table +
 668                 ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
 669
 670         spin_lock_irqsave(&iommu->lock, flags);
 671
 672         /* Record the context, if any. */
 673         ctx = 0;
 674         if (iommu->iommu_ctxflush)
 675                 ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
 676
 677         /* Step 1: Kick data out of streaming buffers if necessary. */
 678         if (strbuf->strbuf_enabled)
 679                 strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
 680
 681         /* Step 2: Clear out the TSB entries. */
 682         for (i = 0; i < npages; i++)
 683                 iopte_make_dummy(iommu, base + i);
 684
 685         free_npages(iommu, bus_addr - iommu->page_table_map_base, npages);
 686
 687         iommu_free_ctx(iommu, ctx);
 688
 689         spin_unlock_irqrestore(&iommu->lock, flags);
 690 }
 691
 692 static void dma_4u_sync_single_for_cpu(struct device *dev,
 693                                        dma_addr_t bus_addr, size_t sz,
 694                                        enum dma_data_direction direction)
 695 {
 696         struct iommu *iommu;
 697         struct strbuf *strbuf;
 698         unsigned long flags, ctx, npages;
 699
 700         iommu = dev->archdata.iommu;
 701         strbuf = dev->archdata.stc;
 702
 703         if (!strbuf->strbuf_enabled)
 704                 return;
 705
 706         spin_lock_irqsave(&iommu->lock, flags);
 707
 708         npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
 709         npages >>= IO_PAGE_SHIFT;
 710         bus_addr &= IO_PAGE_MASK;
 711
 712         /* Step 1: Record the context, if any. */
 713         ctx = 0;
 714         if (iommu->iommu_ctxflush &&
 715             strbuf->strbuf_ctxflush) {
 716                 iopte_t *iopte;
 717
 718                 iopte = iommu->page_table +
 719                         ((bus_addr - iommu->page_table_map_base)>>IO_PAGE_SHIFT);
 720                 ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
 721         }
 722
 723         /* Step 2: Kick data out of streaming buffers. */
 724         strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
 725
 726         spin_unlock_irqrestore(&iommu->lock, flags);
 727 }
 728
 729 static void dma_4u_sync_sg_for_cpu(struct device *dev,
 730                                    struct scatterlist *sglist, int nelems,
 731                                    enum dma_data_direction direction)
 732 {
 733         struct iommu *iommu;
 734         struct strbuf *strbuf;
 735         unsigned long flags, ctx, npages, i;
 736         struct scatterlist *sg, *sgprv;
 737         u32 bus_addr;
 738
 739         iommu = dev->archdata.iommu;
 740         strbuf = dev->archdata.stc;
 741
 742         if (!strbuf->strbuf_enabled)
 743                 return;
 744
 745         spin_lock_irqsave(&iommu->lock, flags);
 746
 747         /* Step 1: Record the context, if any. */
 748         ctx = 0;
 749         if (iommu->iommu_ctxflush &&
 750             strbuf->strbuf_ctxflush) {
 751                 iopte_t *iopte;
 752
 753                 iopte = iommu->page_table +
 754                         ((sglist[0].dma_address - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
 755                 ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
 756         }
 757
 758         /* Step 2: Kick data out of streaming buffers. */
 759         bus_addr = sglist[0].dma_address & IO_PAGE_MASK;
 760         sgprv = NULL;
 761         for_each_sg(sglist, sg, nelems, i) {
 762                 if (sg->dma_length == 0)
 763                         break;
 764                 sgprv = sg;
 765         }
 766
 767         npages = (IO_PAGE_ALIGN(sgprv->dma_address + sgprv->dma_length)
 768                   - bus_addr) >> IO_PAGE_SHIFT;
 769         strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
 770
 771         spin_unlock_irqrestore(&iommu->lock, flags);
 772 }
 773
 774 const struct dma_ops sun4u_dma_ops = {
 775         .alloc_coherent         = dma_4u_alloc_coherent,
 776         .free_coherent          = dma_4u_free_coherent,
 777         .map_single             = dma_4u_map_single,
 778         .unmap_single           = dma_4u_unmap_single,
 779         .map_sg                 = dma_4u_map_sg,
 780         .unmap_sg               = dma_4u_unmap_sg,
 781         .sync_single_for_cpu    = dma_4u_sync_single_for_cpu,
 782         .sync_sg_for_cpu        = dma_4u_sync_sg_for_cpu,
 783 };
 784
 785 const struct dma_ops *dma_ops = &sun4u_dma_ops;
 786 EXPORT_SYMBOL(dma_ops);
 787
 788 int dma_supported(struct device *dev, u64 device_mask)
 789 {
 790         struct iommu *iommu = dev->archdata.iommu;
 791         u64 dma_addr_mask = iommu->dma_addr_mask;
 792
 793         if (device_mask >= (1UL << 32UL))
 794                 return 0;
 795
 796         if ((device_mask & dma_addr_mask) == dma_addr_mask)
 797                 return 1;
 798
 799 #ifdef CONFIG_PCI
 800         if (dev->bus == &pci_bus_type)
 801                 return pci_dma_supported(to_pci_dev(dev), device_mask);
 802 #endif
 803
 804         return 0;
 805 }
 806 EXPORT_SYMBOL(dma_supported);
 807
 808 int dma_set_mask(struct device *dev, u64 dma_mask)
 809 {
 810 #ifdef CONFIG_PCI
 811         if (dev->bus == &pci_bus_type)
 812                 return pci_set_dma_mask(to_pci_dev(dev), dma_mask);
 813 #endif
 814         return -EINVAL;
 815 }
 816 EXPORT_SYMBOL(dma_set_mask);