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[SCSI] qla1280: convert to use the data buffer accessors
[linux-2.6/verdex.git] / drivers / ata / sata_qstor.c
blob6d43ba79e154b70ba035e524f88b64ba9b846448
1 /*
2 * sata_qstor.c - Pacific Digital Corporation QStor SATA
3 *
4 * Maintained by: Mark Lord <mlord@pobox.com>
5 *
6 * Copyright 2005 Pacific Digital Corporation.
7 * (OSL/GPL code release authorized by Jalil Fadavi).
8 *
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2, or (at your option)
13 * any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; see the file COPYING. If not, write to
22 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
23 *
24 *
25 * libata documentation is available via 'make {ps|pdf}docs',
26 * as Documentation/DocBook/libata.*
27 *
28 */
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/init.h>
34 #include <linux/blkdev.h>
35 #include <linux/delay.h>
36 #include <linux/interrupt.h>
37 #include <linux/device.h>
38 #include <scsi/scsi_host.h>
39 #include <linux/libata.h>
40
41 #define DRV_NAME "sata_qstor"
42 #define DRV_VERSION "0.09"
43
44 enum {
45 QS_MMIO_BAR = 4,
46
47 QS_PORTS = 4,
48 QS_MAX_PRD = LIBATA_MAX_PRD,
49 QS_CPB_ORDER = 6,
50 QS_CPB_BYTES = (1 << QS_CPB_ORDER),
51 QS_PRD_BYTES = QS_MAX_PRD * 16,
52 QS_PKT_BYTES = QS_CPB_BYTES + QS_PRD_BYTES,
53
54 /* global register offsets */
55 QS_HCF_CNFG3 = 0x0003, /* host configuration offset */
56 QS_HID_HPHY = 0x0004, /* host physical interface info */
57 QS_HCT_CTRL = 0x00e4, /* global interrupt mask offset */
58 QS_HST_SFF = 0x0100, /* host status fifo offset */
59 QS_HVS_SERD3 = 0x0393, /* PHY enable offset */
60
61 /* global control bits */
62 QS_HPHY_64BIT = (1 << 1), /* 64-bit bus detected */
63 QS_CNFG3_GSRST = 0x01, /* global chip reset */
64 QS_SERD3_PHY_ENA = 0xf0, /* PHY detection ENAble*/
65
66 /* per-channel register offsets */
67 QS_CCF_CPBA = 0x0710, /* chan CPB base address */
68 QS_CCF_CSEP = 0x0718, /* chan CPB separation factor */
69 QS_CFC_HUFT = 0x0800, /* host upstream fifo threshold */
70 QS_CFC_HDFT = 0x0804, /* host downstream fifo threshold */
71 QS_CFC_DUFT = 0x0808, /* dev upstream fifo threshold */
72 QS_CFC_DDFT = 0x080c, /* dev downstream fifo threshold */
73 QS_CCT_CTR0 = 0x0900, /* chan control-0 offset */
74 QS_CCT_CTR1 = 0x0901, /* chan control-1 offset */
75 QS_CCT_CFF = 0x0a00, /* chan command fifo offset */
76
77 /* channel control bits */
78 QS_CTR0_REG = (1 << 1), /* register mode (vs. pkt mode) */
79 QS_CTR0_CLER = (1 << 2), /* clear channel errors */
80 QS_CTR1_RDEV = (1 << 1), /* sata phy/comms reset */
81 QS_CTR1_RCHN = (1 << 4), /* reset channel logic */
82 QS_CCF_RUN_PKT = 0x107, /* RUN a new dma PKT */
83
84 /* pkt sub-field headers */
85 QS_HCB_HDR = 0x01, /* Host Control Block header */
86 QS_DCB_HDR = 0x02, /* Device Control Block header */
87
88 /* pkt HCB flag bits */
89 QS_HF_DIRO = (1 << 0), /* data DIRection Out */
90 QS_HF_DAT = (1 << 3), /* DATa pkt */
91 QS_HF_IEN = (1 << 4), /* Interrupt ENable */
92 QS_HF_VLD = (1 << 5), /* VaLiD pkt */
93
94 /* pkt DCB flag bits */
95 QS_DF_PORD = (1 << 2), /* Pio OR Dma */
96 QS_DF_ELBA = (1 << 3), /* Extended LBA (lba48) */
97
98 /* PCI device IDs */
99 board_2068_idx = 0, /* QStor 4-port SATA/RAID */
100 };
101
102 enum {
103 QS_DMA_BOUNDARY = ~0UL
104 };
105
106 typedef enum { qs_state_idle, qs_state_pkt, qs_state_mmio } qs_state_t;
107
108 struct qs_port_priv {
109 u8 *pkt;
110 dma_addr_t pkt_dma;
111 qs_state_t state;
112 };
113
114 static int qs_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
115 static int qs_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
116 static int qs_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
117 static int qs_port_start(struct ata_port *ap);
118 static void qs_host_stop(struct ata_host *host);
119 static void qs_phy_reset(struct ata_port *ap);
120 static void qs_qc_prep(struct ata_queued_cmd *qc);
121 static unsigned int qs_qc_issue(struct ata_queued_cmd *qc);
122 static int qs_check_atapi_dma(struct ata_queued_cmd *qc);
123 static void qs_bmdma_stop(struct ata_queued_cmd *qc);
124 static u8 qs_bmdma_status(struct ata_port *ap);
125 static void qs_irq_clear(struct ata_port *ap);
126 static void qs_eng_timeout(struct ata_port *ap);
127
128 static struct scsi_host_template qs_ata_sht = {
129 .module = THIS_MODULE,
130 .name = DRV_NAME,
131 .ioctl = ata_scsi_ioctl,
132 .queuecommand = ata_scsi_queuecmd,
133 .can_queue = ATA_DEF_QUEUE,
134 .this_id = ATA_SHT_THIS_ID,
135 .sg_tablesize = QS_MAX_PRD,
136 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
137 .emulated = ATA_SHT_EMULATED,
138 .use_clustering = ENABLE_CLUSTERING,
139 .proc_name = DRV_NAME,
140 .dma_boundary = QS_DMA_BOUNDARY,
141 .slave_configure = ata_scsi_slave_config,
142 .slave_destroy = ata_scsi_slave_destroy,
143 .bios_param = ata_std_bios_param,
144 };
145
146 static const struct ata_port_operations qs_ata_ops = {
147 .tf_load = ata_tf_load,
148 .tf_read = ata_tf_read,
149 .check_status = ata_check_status,
150 .check_atapi_dma = qs_check_atapi_dma,
151 .exec_command = ata_exec_command,
152 .dev_select = ata_std_dev_select,
153 .phy_reset = qs_phy_reset,
154 .qc_prep = qs_qc_prep,
155 .qc_issue = qs_qc_issue,
156 .data_xfer = ata_data_xfer,
157 .eng_timeout = qs_eng_timeout,
158 .irq_clear = qs_irq_clear,
159 .irq_on = ata_irq_on,
160 .scr_read = qs_scr_read,
161 .scr_write = qs_scr_write,
162 .port_start = qs_port_start,
163 .host_stop = qs_host_stop,
164 .bmdma_stop = qs_bmdma_stop,
165 .bmdma_status = qs_bmdma_status,
166 };
167
168 static const struct ata_port_info qs_port_info[] = {
169 /* board_2068_idx */
170 {
171 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
172 ATA_FLAG_SATA_RESET |
173 //FIXME ATA_FLAG_SRST |
174 ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING,
175 .pio_mask = 0x10, /* pio4 */
176 .udma_mask = ATA_UDMA6,
177 .port_ops = &qs_ata_ops,
178 },
179 };
180
181 static const struct pci_device_id qs_ata_pci_tbl[] = {
182 { PCI_VDEVICE(PDC, 0x2068), board_2068_idx },
183
184 { } /* terminate list */
185 };
186
187 static struct pci_driver qs_ata_pci_driver = {
188 .name = DRV_NAME,
189 .id_table = qs_ata_pci_tbl,
190 .probe = qs_ata_init_one,
191 .remove = ata_pci_remove_one,
192 };
193
194 static void __iomem *qs_mmio_base(struct ata_host *host)
195 {
196 return host->iomap[QS_MMIO_BAR];
197 }
198
199 static int qs_check_atapi_dma(struct ata_queued_cmd *qc)
200 {
201 return 1; /* ATAPI DMA not supported */
202 }
203
204 static void qs_bmdma_stop(struct ata_queued_cmd *qc)
205 {
206 /* nothing */
207 }
208
209 static u8 qs_bmdma_status(struct ata_port *ap)
210 {
211 return 0;
212 }
213
214 static void qs_irq_clear(struct ata_port *ap)
215 {
216 /* nothing */
217 }
218
219 static inline void qs_enter_reg_mode(struct ata_port *ap)
220 {
221 u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
222
223 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
224 readb(chan + QS_CCT_CTR0); /* flush */
225 }
226
227 static inline void qs_reset_channel_logic(struct ata_port *ap)
228 {
229 u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
230
231 writeb(QS_CTR1_RCHN, chan + QS_CCT_CTR1);
232 readb(chan + QS_CCT_CTR0); /* flush */
233 qs_enter_reg_mode(ap);
234 }
235
236 static void qs_phy_reset(struct ata_port *ap)
237 {
238 struct qs_port_priv *pp = ap->private_data;
239
240 pp->state = qs_state_idle;
241 qs_reset_channel_logic(ap);
242 sata_phy_reset(ap);
243 }
244
245 static void qs_eng_timeout(struct ata_port *ap)
246 {
247 struct qs_port_priv *pp = ap->private_data;
248
249 if (pp->state != qs_state_idle) /* healthy paranoia */
250 pp->state = qs_state_mmio;
251 qs_reset_channel_logic(ap);
252 ata_eng_timeout(ap);
253 }
254
255 static int qs_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
256 {
257 if (sc_reg > SCR_CONTROL)
258 return -EINVAL;
259 *val = readl(ap->ioaddr.scr_addr + (sc_reg * 8));
260 return 0;
261 }
262
263 static int qs_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
264 {
265 if (sc_reg > SCR_CONTROL)
266 return -EINVAL;
267 writel(val, ap->ioaddr.scr_addr + (sc_reg * 8));
268 return 0;
269 }
270
271 static unsigned int qs_fill_sg(struct ata_queued_cmd *qc)
272 {
273 struct scatterlist *sg;
274 struct ata_port *ap = qc->ap;
275 struct qs_port_priv *pp = ap->private_data;
276 unsigned int nelem;
277 u8 *prd = pp->pkt + QS_CPB_BYTES;
278
279 WARN_ON(qc->__sg == NULL);
280 WARN_ON(qc->n_elem == 0 && qc->pad_len == 0);
281
282 nelem = 0;
283 ata_for_each_sg(sg, qc) {
284 u64 addr;
285 u32 len;
286
287 addr = sg_dma_address(sg);
288 *(__le64 *)prd = cpu_to_le64(addr);
289 prd += sizeof(u64);
290
291 len = sg_dma_len(sg);
292 *(__le32 *)prd = cpu_to_le32(len);
293 prd += sizeof(u64);
294
295 VPRINTK("PRD[%u] = (0x%llX, 0x%X)\n", nelem,
296 (unsigned long long)addr, len);
297 nelem++;
298 }
299
300 return nelem;
301 }
302
303 static void qs_qc_prep(struct ata_queued_cmd *qc)
304 {
305 struct qs_port_priv *pp = qc->ap->private_data;
306 u8 dflags = QS_DF_PORD, *buf = pp->pkt;
307 u8 hflags = QS_HF_DAT | QS_HF_IEN | QS_HF_VLD;
308 u64 addr;
309 unsigned int nelem;
310
311 VPRINTK("ENTER\n");
312
313 qs_enter_reg_mode(qc->ap);
314 if (qc->tf.protocol != ATA_PROT_DMA) {
315 ata_qc_prep(qc);
316 return;
317 }
318
319 nelem = qs_fill_sg(qc);
320
321 if ((qc->tf.flags & ATA_TFLAG_WRITE))
322 hflags |= QS_HF_DIRO;
323 if ((qc->tf.flags & ATA_TFLAG_LBA48))
324 dflags |= QS_DF_ELBA;
325
326 /* host control block (HCB) */
327 buf[ 0] = QS_HCB_HDR;
328 buf[ 1] = hflags;
329 *(__le32 *)(&buf[ 4]) = cpu_to_le32(qc->nbytes);
330 *(__le32 *)(&buf[ 8]) = cpu_to_le32(nelem);
331 addr = ((u64)pp->pkt_dma) + QS_CPB_BYTES;
332 *(__le64 *)(&buf[16]) = cpu_to_le64(addr);
333
334 /* device control block (DCB) */
335 buf[24] = QS_DCB_HDR;
336 buf[28] = dflags;
337
338 /* frame information structure (FIS) */
339 ata_tf_to_fis(&qc->tf, 0, 1, &buf[32]);
340 }
341
342 static inline void qs_packet_start(struct ata_queued_cmd *qc)
343 {
344 struct ata_port *ap = qc->ap;
345 u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
346
347 VPRINTK("ENTER, ap %p\n", ap);
348
349 writeb(QS_CTR0_CLER, chan + QS_CCT_CTR0);
350 wmb(); /* flush PRDs and pkt to memory */
351 writel(QS_CCF_RUN_PKT, chan + QS_CCT_CFF);
352 readl(chan + QS_CCT_CFF); /* flush */
353 }
354
355 static unsigned int qs_qc_issue(struct ata_queued_cmd *qc)
356 {
357 struct qs_port_priv *pp = qc->ap->private_data;
358
359 switch (qc->tf.protocol) {
360 case ATA_PROT_DMA:
361
362 pp->state = qs_state_pkt;
363 qs_packet_start(qc);
364 return 0;
365
366 case ATA_PROT_ATAPI_DMA:
367 BUG();
368 break;
369
370 default:
371 break;
372 }
373
374 pp->state = qs_state_mmio;
375 return ata_qc_issue_prot(qc);
376 }
377
378 static inline unsigned int qs_intr_pkt(struct ata_host *host)
379 {
380 unsigned int handled = 0;
381 u8 sFFE;
382 u8 __iomem *mmio_base = qs_mmio_base(host);
383
384 do {
385 u32 sff0 = readl(mmio_base + QS_HST_SFF);
386 u32 sff1 = readl(mmio_base + QS_HST_SFF + 4);
387 u8 sEVLD = (sff1 >> 30) & 0x01; /* valid flag */
388 sFFE = sff1 >> 31; /* empty flag */
389
390 if (sEVLD) {
391 u8 sDST = sff0 >> 16; /* dev status */
392 u8 sHST = sff1 & 0x3f; /* host status */
393 unsigned int port_no = (sff1 >> 8) & 0x03;
394 struct ata_port *ap = host->ports[port_no];
395
396 DPRINTK("SFF=%08x%08x: sCHAN=%u sHST=%d sDST=%02x\n",
397 sff1, sff0, port_no, sHST, sDST);
398 handled = 1;
399 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
400 struct ata_queued_cmd *qc;
401 struct qs_port_priv *pp = ap->private_data;
402 if (!pp || pp->state != qs_state_pkt)
403 continue;
404 qc = ata_qc_from_tag(ap, ap->link.active_tag);
405 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
406 switch (sHST) {
407 case 0: /* successful CPB */
408 case 3: /* device error */
409 pp->state = qs_state_idle;
410 qs_enter_reg_mode(qc->ap);
411 qc->err_mask |= ac_err_mask(sDST);
412 ata_qc_complete(qc);
413 break;
414 default:
415 break;
416 }
417 }
418 }
419 }
420 } while (!sFFE);
421 return handled;
422 }
423
424 static inline unsigned int qs_intr_mmio(struct ata_host *host)
425 {
426 unsigned int handled = 0, port_no;
427
428 for (port_no = 0; port_no < host->n_ports; ++port_no) {
429 struct ata_port *ap;
430 ap = host->ports[port_no];
431 if (ap &&
432 !(ap->flags & ATA_FLAG_DISABLED)) {
433 struct ata_queued_cmd *qc;
434 struct qs_port_priv *pp = ap->private_data;
435 if (!pp || pp->state != qs_state_mmio)
436 continue;
437 qc = ata_qc_from_tag(ap, ap->link.active_tag);
438 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
439
440 /* check main status, clearing INTRQ */
441 u8 status = ata_check_status(ap);
442 if ((status & ATA_BUSY))
443 continue;
444 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
445 ap->print_id, qc->tf.protocol, status);
446
447 /* complete taskfile transaction */
448 pp->state = qs_state_idle;
449 qc->err_mask |= ac_err_mask(status);
450 ata_qc_complete(qc);
451 handled = 1;
452 }
453 }
454 }
455 return handled;
456 }
457
458 static irqreturn_t qs_intr(int irq, void *dev_instance)
459 {
460 struct ata_host *host = dev_instance;
461 unsigned int handled = 0;
462
463 VPRINTK("ENTER\n");
464
465 spin_lock(&host->lock);
466 handled = qs_intr_pkt(host) | qs_intr_mmio(host);
467 spin_unlock(&host->lock);
468
469 VPRINTK("EXIT\n");
470
471 return IRQ_RETVAL(handled);
472 }
473
474 static void qs_ata_setup_port(struct ata_ioports *port, void __iomem *base)
475 {
476 port->cmd_addr =
477 port->data_addr = base + 0x400;
478 port->error_addr =
479 port->feature_addr = base + 0x408; /* hob_feature = 0x409 */
480 port->nsect_addr = base + 0x410; /* hob_nsect = 0x411 */
481 port->lbal_addr = base + 0x418; /* hob_lbal = 0x419 */
482 port->lbam_addr = base + 0x420; /* hob_lbam = 0x421 */
483 port->lbah_addr = base + 0x428; /* hob_lbah = 0x429 */
484 port->device_addr = base + 0x430;
485 port->status_addr =
486 port->command_addr = base + 0x438;
487 port->altstatus_addr =
488 port->ctl_addr = base + 0x440;
489 port->scr_addr = base + 0xc00;
490 }
491
492 static int qs_port_start(struct ata_port *ap)
493 {
494 struct device *dev = ap->host->dev;
495 struct qs_port_priv *pp;
496 void __iomem *mmio_base = qs_mmio_base(ap->host);
497 void __iomem *chan = mmio_base + (ap->port_no * 0x4000);
498 u64 addr;
499 int rc;
500
501 rc = ata_port_start(ap);
502 if (rc)
503 return rc;
504 qs_enter_reg_mode(ap);
505 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
506 if (!pp)
507 return -ENOMEM;
508 pp->pkt = dmam_alloc_coherent(dev, QS_PKT_BYTES, &pp->pkt_dma,
509 GFP_KERNEL);
510 if (!pp->pkt)
511 return -ENOMEM;
512 memset(pp->pkt, 0, QS_PKT_BYTES);
513 ap->private_data = pp;
514
515 addr = (u64)pp->pkt_dma;
516 writel((u32) addr, chan + QS_CCF_CPBA);
517 writel((u32)(addr >> 32), chan + QS_CCF_CPBA + 4);
518 return 0;
519 }
520
521 static void qs_host_stop(struct ata_host *host)
522 {
523 void __iomem *mmio_base = qs_mmio_base(host);
524
525 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
526 writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
527 }
528
529 static void qs_host_init(struct ata_host *host, unsigned int chip_id)
530 {
531 void __iomem *mmio_base = host->iomap[QS_MMIO_BAR];
532 unsigned int port_no;
533
534 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
535 writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
536
537 /* reset each channel in turn */
538 for (port_no = 0; port_no < host->n_ports; ++port_no) {
539 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
540 writeb(QS_CTR1_RDEV|QS_CTR1_RCHN, chan + QS_CCT_CTR1);
541 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
542 readb(chan + QS_CCT_CTR0); /* flush */
543 }
544 writeb(QS_SERD3_PHY_ENA, mmio_base + QS_HVS_SERD3); /* enable phy */
545
546 for (port_no = 0; port_no < host->n_ports; ++port_no) {
547 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
548 /* set FIFO depths to same settings as Windows driver */
549 writew(32, chan + QS_CFC_HUFT);
550 writew(32, chan + QS_CFC_HDFT);
551 writew(10, chan + QS_CFC_DUFT);
552 writew( 8, chan + QS_CFC_DDFT);
553 /* set CPB size in bytes, as a power of two */
554 writeb(QS_CPB_ORDER, chan + QS_CCF_CSEP);
555 }
556 writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
557 }
558
559 /*
560 * The QStor understands 64-bit buses, and uses 64-bit fields
561 * for DMA pointers regardless of bus width. We just have to
562 * make sure our DMA masks are set appropriately for whatever
563 * bridge lies between us and the QStor, and then the DMA mapping
564 * code will ensure we only ever "see" appropriate buffer addresses.
565 * If we're 32-bit limited somewhere, then our 64-bit fields will
566 * just end up with zeros in the upper 32-bits, without any special
567 * logic required outside of this routine (below).
568 */
569 static int qs_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
570 {
571 u32 bus_info = readl(mmio_base + QS_HID_HPHY);
572 int rc, have_64bit_bus = (bus_info & QS_HPHY_64BIT);
573
574 if (have_64bit_bus &&
575 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
576 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
577 if (rc) {
578 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
579 if (rc) {
580 dev_printk(KERN_ERR, &pdev->dev,
581 "64-bit DMA enable failed\n");
582 return rc;
583 }
584 }
585 } else {
586 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
587 if (rc) {
588 dev_printk(KERN_ERR, &pdev->dev,
589 "32-bit DMA enable failed\n");
590 return rc;
591 }
592 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
593 if (rc) {
594 dev_printk(KERN_ERR, &pdev->dev,
595 "32-bit consistent DMA enable failed\n");
596 return rc;
597 }
598 }
599 return 0;
600 }
601
602 static int qs_ata_init_one(struct pci_dev *pdev,
603 const struct pci_device_id *ent)
604 {
605 static int printed_version;
606 unsigned int board_idx = (unsigned int) ent->driver_data;
607 const struct ata_port_info *ppi[] = { &qs_port_info[board_idx], NULL };
608 struct ata_host *host;
609 int rc, port_no;
610
611 if (!printed_version++)
612 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
613
614 /* alloc host */
615 host = ata_host_alloc_pinfo(&pdev->dev, ppi, QS_PORTS);
616 if (!host)
617 return -ENOMEM;
618
619 /* acquire resources and fill host */
620 rc = pcim_enable_device(pdev);
621 if (rc)
622 return rc;
623
624 if ((pci_resource_flags(pdev, QS_MMIO_BAR) & IORESOURCE_MEM) == 0)
625 return -ENODEV;
626
627 rc = pcim_iomap_regions(pdev, 1 << QS_MMIO_BAR, DRV_NAME);
628 if (rc)
629 return rc;
630 host->iomap = pcim_iomap_table(pdev);
631
632 rc = qs_set_dma_masks(pdev, host->iomap[QS_MMIO_BAR]);
633 if (rc)
634 return rc;
635
636 for (port_no = 0; port_no < host->n_ports; ++port_no) {
637 struct ata_port *ap = host->ports[port_no];
638 unsigned int offset = port_no * 0x4000;
639 void __iomem *chan = host->iomap[QS_MMIO_BAR] + offset;
640
641 qs_ata_setup_port(&ap->ioaddr, chan);
642
643 ata_port_pbar_desc(ap, QS_MMIO_BAR, -1, "mmio");
644 ata_port_pbar_desc(ap, QS_MMIO_BAR, offset, "port");
645 }
646
647 /* initialize adapter */
648 qs_host_init(host, board_idx);
649
650 pci_set_master(pdev);
651 return ata_host_activate(host, pdev->irq, qs_intr, IRQF_SHARED,
652 &qs_ata_sht);
653 }
654
655 static int __init qs_ata_init(void)
656 {
657 return pci_register_driver(&qs_ata_pci_driver);
658 }
659
660 static void __exit qs_ata_exit(void)
661 {
662 pci_unregister_driver(&qs_ata_pci_driver);
663 }
664
665 MODULE_AUTHOR("Mark Lord");
666 MODULE_DESCRIPTION("Pacific Digital Corporation QStor SATA low-level driver");
667 MODULE_LICENSE("GPL");
668 MODULE_DEVICE_TABLE(pci, qs_ata_pci_tbl);
669 MODULE_VERSION(DRV_VERSION);
670
671 module_init(qs_ata_init);
672 module_exit(qs_ata_exit);
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