2 * Driver for C-Media CMI8338 and 8738 PCI soundcards.
3 * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 /* Does not work. Warning may block system in capture mode */
21 /* #define USE_VAR48KRATE */
23 #include <sound/driver.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27 #include <linux/init.h>
28 #include <linux/pci.h>
29 #include <linux/slab.h>
30 #include <linux/gameport.h>
31 #include <linux/moduleparam.h>
32 #include <linux/mutex.h>
33 #include <sound/core.h>
34 #include <sound/info.h>
35 #include <sound/control.h>
36 #include <sound/pcm.h>
37 #include <sound/rawmidi.h>
38 #include <sound/mpu401.h>
39 #include <sound/opl3.h>
41 #include <sound/asoundef.h>
42 #include <sound/initval.h>
44 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
45 MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
46 MODULE_LICENSE("GPL");
47 MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738},"
50 "{C-Media,CMI8338B}}");
52 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
53 #define SUPPORT_JOYSTICK 1
56 static int index
[SNDRV_CARDS
] = SNDRV_DEFAULT_IDX
; /* Index 0-MAX */
57 static char *id
[SNDRV_CARDS
] = SNDRV_DEFAULT_STR
; /* ID for this card */
58 static int enable
[SNDRV_CARDS
] = SNDRV_DEFAULT_ENABLE_PNP
; /* Enable switches */
59 static long mpu_port
[SNDRV_CARDS
];
60 static long fm_port
[SNDRV_CARDS
] = {[0 ... (SNDRV_CARDS
-1)]=1};
61 static int soft_ac3
[SNDRV_CARDS
] = {[0 ... (SNDRV_CARDS
-1)]=1};
62 #ifdef SUPPORT_JOYSTICK
63 static int joystick_port
[SNDRV_CARDS
];
66 module_param_array(index
, int, NULL
, 0444);
67 MODULE_PARM_DESC(index
, "Index value for C-Media PCI soundcard.");
68 module_param_array(id
, charp
, NULL
, 0444);
69 MODULE_PARM_DESC(id
, "ID string for C-Media PCI soundcard.");
70 module_param_array(enable
, bool, NULL
, 0444);
71 MODULE_PARM_DESC(enable
, "Enable C-Media PCI soundcard.");
72 module_param_array(mpu_port
, long, NULL
, 0444);
73 MODULE_PARM_DESC(mpu_port
, "MPU-401 port.");
74 module_param_array(fm_port
, long, NULL
, 0444);
75 MODULE_PARM_DESC(fm_port
, "FM port.");
76 module_param_array(soft_ac3
, bool, NULL
, 0444);
77 MODULE_PARM_DESC(soft_ac3
, "Sofware-conversion of raw SPDIF packets (model 033 only).");
78 #ifdef SUPPORT_JOYSTICK
79 module_param_array(joystick_port
, int, NULL
, 0444);
80 MODULE_PARM_DESC(joystick_port
, "Joystick port address.");
84 * CM8x38 registers definition
87 #define CM_REG_FUNCTRL0 0x00
88 #define CM_RST_CH1 0x00080000
89 #define CM_RST_CH0 0x00040000
90 #define CM_CHEN1 0x00020000 /* ch1: enable */
91 #define CM_CHEN0 0x00010000 /* ch0: enable */
92 #define CM_PAUSE1 0x00000008 /* ch1: pause */
93 #define CM_PAUSE0 0x00000004 /* ch0: pause */
94 #define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */
95 #define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */
97 #define CM_REG_FUNCTRL1 0x04
98 #define CM_DSFC_MASK 0x0000E000 /* channel 1 (DAC?) sampling frequency */
99 #define CM_DSFC_SHIFT 13
100 #define CM_ASFC_MASK 0x00001C00 /* channel 0 (ADC?) sampling frequency */
101 #define CM_ASFC_SHIFT 10
102 #define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */
103 #define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */
104 #define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/IN -> OUT loopback */
105 #define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */
106 #define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */
107 #define CM_BREQ 0x00000010 /* bus master enabled */
108 #define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */
109 #define CM_UART_EN 0x00000004 /* legacy UART */
110 #define CM_JYSTK_EN 0x00000002 /* legacy joystick */
111 #define CM_ZVPORT 0x00000001 /* ZVPORT */
113 #define CM_REG_CHFORMAT 0x08
115 #define CM_CHB3D5C 0x80000000 /* 5,6 channels */
116 #define CM_FMOFFSET2 0x40000000 /* initial FM PCM offset 2 when Fmute=1 */
117 #define CM_CHB3D 0x20000000 /* 4 channels */
119 #define CM_CHIP_MASK1 0x1f000000
120 #define CM_CHIP_037 0x01000000
121 #define CM_SETLAT48 0x00800000 /* set latency timer 48h */
122 #define CM_EDGEIRQ 0x00400000 /* emulated edge trigger legacy IRQ */
123 #define CM_SPD24SEL39 0x00200000 /* 24-bit spdif: model 039 */
124 #define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */
125 #define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */
126 #define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */
127 /* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */
129 #define CM_ADCBITLEN_MASK 0x0000C000
130 #define CM_ADCBITLEN_16 0x00000000
131 #define CM_ADCBITLEN_15 0x00004000
132 #define CM_ADCBITLEN_14 0x00008000
133 #define CM_ADCBITLEN_13 0x0000C000
135 #define CM_ADCDACLEN_MASK 0x00003000 /* model 037 */
136 #define CM_ADCDACLEN_060 0x00000000
137 #define CM_ADCDACLEN_066 0x00001000
138 #define CM_ADCDACLEN_130 0x00002000
139 #define CM_ADCDACLEN_280 0x00003000
141 #define CM_ADCDLEN_MASK 0x00003000 /* model 039 */
142 #define CM_ADCDLEN_ORIGINAL 0x00000000
143 #define CM_ADCDLEN_EXTRA 0x00001000
144 #define CM_ADCDLEN_24K 0x00002000
145 #define CM_ADCDLEN_WEIGHT 0x00003000
147 #define CM_CH1_SRATE_176K 0x00000800
148 #define CM_CH1_SRATE_96K 0x00000800 /* model 055? */
149 #define CM_CH1_SRATE_88K 0x00000400
150 #define CM_CH0_SRATE_176K 0x00000200
151 #define CM_CH0_SRATE_96K 0x00000200 /* model 055? */
152 #define CM_CH0_SRATE_88K 0x00000100
154 #define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */
155 #define CM_DBLSPDS 0x00000040 /* double SPDIF sample rate 88.2/96 */
156 #define CM_POLVALID 0x00000020 /* inverse SPDIF/IN valid bit */
157 #define CM_SPDLOCKED 0x00000010
159 #define CM_CH1FMT_MASK 0x0000000C /* bit 3: 16 bits, bit 2: stereo */
160 #define CM_CH1FMT_SHIFT 2
161 #define CM_CH0FMT_MASK 0x00000003 /* bit 1: 16 bits, bit 0: stereo */
162 #define CM_CH0FMT_SHIFT 0
164 #define CM_REG_INT_HLDCLR 0x0C
165 #define CM_CHIP_MASK2 0xff000000
166 #define CM_CHIP_8768 0x20000000
167 #define CM_CHIP_055 0x08000000
168 #define CM_CHIP_039 0x04000000
169 #define CM_CHIP_039_6CH 0x01000000
170 #define CM_UNKNOWN_INT_EN 0x00080000 /* ? */
171 #define CM_TDMA_INT_EN 0x00040000
172 #define CM_CH1_INT_EN 0x00020000
173 #define CM_CH0_INT_EN 0x00010000
175 #define CM_REG_INT_STATUS 0x10
176 #define CM_INTR 0x80000000
177 #define CM_VCO 0x08000000 /* Voice Control? CMI8738 */
178 #define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */
179 #define CM_UARTINT 0x00010000
180 #define CM_LTDMAINT 0x00008000
181 #define CM_HTDMAINT 0x00004000
182 #define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */
183 #define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */
184 #define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */
185 #define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */
186 #define CM_CH1BUSY 0x00000008
187 #define CM_CH0BUSY 0x00000004
188 #define CM_CHINT1 0x00000002
189 #define CM_CHINT0 0x00000001
191 #define CM_REG_LEGACY_CTRL 0x14
192 #define CM_NXCHG 0x80000000 /* don't map base reg dword->sample */
193 #define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */
194 #define CM_VMPU_330 0x00000000
195 #define CM_VMPU_320 0x20000000
196 #define CM_VMPU_310 0x40000000
197 #define CM_VMPU_300 0x60000000
198 #define CM_ENWR8237 0x10000000 /* enable bus master to write 8237 base reg */
199 #define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */
200 #define CM_VSBSEL_220 0x00000000
201 #define CM_VSBSEL_240 0x04000000
202 #define CM_VSBSEL_260 0x08000000
203 #define CM_VSBSEL_280 0x0C000000
204 #define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */
205 #define CM_FMSEL_388 0x00000000
206 #define CM_FMSEL_3C8 0x01000000
207 #define CM_FMSEL_3E0 0x02000000
208 #define CM_FMSEL_3E8 0x03000000
209 #define CM_ENSPDOUT 0x00800000 /* enable XSPDIF/OUT to I/O interface */
210 #define CM_SPDCOPYRHT 0x00400000 /* spdif in/out copyright bit */
211 #define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */
212 #define CM_INVIDWEN 0x00100000 /* internal vendor ID write enable, model 039? */
213 #define CM_SETRETRY 0x00100000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
214 #define CM_C_EEACCESS 0x00080000 /* direct programming eeprom regs */
215 #define CM_C_EECS 0x00040000
216 #define CM_C_EEDI46 0x00020000
217 #define CM_C_EECK46 0x00010000
218 #define CM_CHB3D6C 0x00008000 /* 5.1 channels support */
219 #define CM_CENTR2LIN 0x00004000 /* line-in as center out */
220 #define CM_BASE2LIN 0x00002000 /* line-in as bass out */
221 #define CM_EXBASEN 0x00001000 /* external bass input enable */
223 #define CM_REG_MISC_CTRL 0x18
224 #define CM_PWD 0x80000000 /* power down */
225 #define CM_RESET 0x40000000
226 #define CM_SFIL_MASK 0x30000000 /* filter control at front end DAC, model 037? */
227 #define CM_VMGAIN 0x10000000 /* analog master amp +6dB, model 039? */
228 #define CM_TXVX 0x08000000 /* model 037? */
229 #define CM_N4SPK3D 0x04000000 /* copy front to rear */
230 #define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */
231 #define CM_SPDIF48K 0x01000000 /* write */
232 #define CM_SPATUS48K 0x01000000 /* read */
233 #define CM_ENDBDAC 0x00800000 /* enable double dac */
234 #define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */
235 #define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */
236 #define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-OUT -> int. IN */
237 #define CM_FM_EN 0x00080000 /* enable legacy FM */
238 #define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */
239 #define CM_ENWRASID 0x00010000 /* choose writable internal SUBID (audio) */
240 #define CM_VIDWPDSB 0x00010000 /* model 037? */
241 #define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */
242 #define CM_MASK_EN 0x00004000 /* activate channel mask on legacy DMA */
243 #define CM_ENWRMSID 0x00002000 /* choose writable internal SUBID (modem) */
244 #define CM_VIDWPPRT 0x00002000 /* model 037? */
245 #define CM_SFILENB 0x00001000 /* filter stepping at front end DAC, model 037? */
246 #define CM_MMODE_MASK 0x00000E00 /* model DAA interface mode */
247 #define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */
248 #define CM_ENCENTER 0x00000080
249 #define CM_FLINKON 0x00000080 /* force modem link detection on, model 037 */
250 #define CM_MUTECH1 0x00000040 /* mute PCI ch1 to DAC */
251 #define CM_FLINKOFF 0x00000040 /* force modem link detection off, model 037 */
252 #define CM_UNKNOWN_18_5 0x00000020 /* ? */
253 #define CM_MIDSMP 0x00000010 /* 1/2 interpolation at front end DAC */
254 #define CM_UPDDMA_MASK 0x0000000C /* TDMA position update notification */
255 #define CM_UPDDMA_2048 0x00000000
256 #define CM_UPDDMA_1024 0x00000004
257 #define CM_UPDDMA_512 0x00000008
258 #define CM_UPDDMA_256 0x0000000C
259 #define CM_TWAIT_MASK 0x00000003 /* model 037 */
260 #define CM_TWAIT1 0x00000002 /* FM i/o cycle, 0: 48, 1: 64 PCICLKs */
261 #define CM_TWAIT0 0x00000001 /* i/o cycle, 0: 4, 1: 6 PCICLKs */
263 #define CM_REG_TDMA_POSITION 0x1C
264 #define CM_TDMA_CNT_MASK 0xFFFF0000 /* current byte/word count */
265 #define CM_TDMA_ADR_MASK 0x0000FFFF /* current address */
268 #define CM_REG_MIXER0 0x20
269 #define CM_REG_SBVR 0x20 /* write: sb16 version */
270 #define CM_REG_DEV 0x20 /* read: hardware device version */
272 #define CM_REG_MIXER21 0x21
273 #define CM_UNKNOWN_21_MASK 0x78 /* ? */
274 #define CM_X_ADPCM 0x04 /* SB16 ADPCM enable */
275 #define CM_PROINV 0x02 /* SBPro left/right channel switching */
276 #define CM_X_SB16 0x01 /* SB16 compatible */
278 #define CM_REG_SB16_DATA 0x22
279 #define CM_REG_SB16_ADDR 0x23
281 #define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */
282 #define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
283 #define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */
284 #define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */
286 #define CM_REG_MIXER1 0x24
287 #define CM_FMMUTE 0x80 /* mute FM */
288 #define CM_FMMUTE_SHIFT 7
289 #define CM_WSMUTE 0x40 /* mute PCM */
290 #define CM_WSMUTE_SHIFT 6
291 #define CM_REAR2LIN 0x20 /* lin-in -> rear line out */
292 #define CM_REAR2LIN_SHIFT 5
293 #define CM_REAR2FRONT 0x10 /* exchange rear/front */
294 #define CM_REAR2FRONT_SHIFT 4
295 #define CM_WAVEINL 0x08 /* digital wave rec. left chan */
296 #define CM_WAVEINL_SHIFT 3
297 #define CM_WAVEINR 0x04 /* digical wave rec. right */
298 #define CM_WAVEINR_SHIFT 2
299 #define CM_X3DEN 0x02 /* 3D surround enable */
300 #define CM_X3DEN_SHIFT 1
301 #define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */
302 #define CM_CDPLAY_SHIFT 0
304 #define CM_REG_MIXER2 0x25
305 #define CM_RAUXREN 0x80 /* AUX right capture */
306 #define CM_RAUXREN_SHIFT 7
307 #define CM_RAUXLEN 0x40 /* AUX left capture */
308 #define CM_RAUXLEN_SHIFT 6
309 #define CM_VAUXRM 0x20 /* AUX right mute */
310 #define CM_VAUXRM_SHIFT 5
311 #define CM_VAUXLM 0x10 /* AUX left mute */
312 #define CM_VAUXLM_SHIFT 4
313 #define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */
314 #define CM_VADMIC_SHIFT 1
315 #define CM_MICGAINZ 0x01 /* mic boost */
316 #define CM_MICGAINZ_SHIFT 0
318 #define CM_REG_MIXER3 0x24
319 #define CM_REG_AUX_VOL 0x26
320 #define CM_VAUXL_MASK 0xf0
321 #define CM_VAUXR_MASK 0x0f
323 #define CM_REG_MISC 0x27
324 #define CM_UNKNOWN_27_MASK 0xd8 /* ? */
325 #define CM_XGPO1 0x20
326 // #define CM_XGPBIO 0x04
327 #define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */
328 #define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */
329 #define CM_SPDVALID 0x02 /* spdif input valid check */
330 #define CM_DMAUTO 0x01 /* SB16 DMA auto detect */
332 #define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */
334 * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
335 * or identical with AC97 codec?
337 #define CM_REG_EXTERN_CODEC CM_REG_AC97
340 * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
342 #define CM_REG_MPU_PCI 0x40
345 * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
347 #define CM_REG_FM_PCI 0x50
350 * access from SB-mixer port
352 #define CM_REG_EXTENT_IND 0xf0
353 #define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */
354 #define CM_VPHONE_SHIFT 5
355 #define CM_VPHOM 0x10 /* Phone mute control */
356 #define CM_VSPKM 0x08 /* Speaker mute control, default high */
357 #define CM_RLOOPREN 0x04 /* Rec. R-channel enable */
358 #define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */
359 #define CM_VADMIC3 0x01 /* Mic record boost */
362 * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
363 * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
366 #define CM_REG_PLL 0xf8
371 #define CM_REG_CH0_FRAME1 0x80 /* write: base address */
372 #define CM_REG_CH0_FRAME2 0x84 /* read: current address */
373 #define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */
374 #define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */
376 #define CM_REG_EXT_MISC 0x90
377 #define CM_ADC48K44K 0x10000000 /* ADC parameters group, 0: 44k, 1: 48k */
378 #define CM_CHB3D8C 0x00200000 /* 7.1 channels support */
379 #define CM_SPD32FMT 0x00100000 /* SPDIF/IN 32k sample rate */
380 #define CM_ADC2SPDIF 0x00080000 /* ADC output to SPDIF/OUT */
381 #define CM_SHAREADC 0x00040000 /* DAC in ADC as Center/LFE */
382 #define CM_REALTCMP 0x00020000 /* monitor the CMPL/CMPR of ADC */
383 #define CM_INVLRCK 0x00010000 /* invert ZVPORT's LRCK */
384 #define CM_UNKNOWN_90_MASK 0x0000FFFF /* ? */
389 #define CM_EXTENT_CODEC 0x100
390 #define CM_EXTENT_MIDI 0x2
391 #define CM_EXTENT_SYNTH 0x4
395 * channels for playback / capture
401 * flags to check device open/close
403 #define CM_OPEN_NONE 0
404 #define CM_OPEN_CH_MASK 0x01
405 #define CM_OPEN_DAC 0x10
406 #define CM_OPEN_ADC 0x20
407 #define CM_OPEN_SPDIF 0x40
408 #define CM_OPEN_MCHAN 0x80
409 #define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC)
410 #define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC)
411 #define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
412 #define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC)
413 #define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
414 #define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
418 #define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K
419 #define CM_PLAYBACK_SPDF CM_SPDF_1
420 #define CM_CAPTURE_SPDF CM_SPDF_0
422 #define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
423 #define CM_PLAYBACK_SPDF CM_SPDF_0
424 #define CM_CAPTURE_SPDF CM_SPDF_1
433 struct snd_pcm_substream
*substream
;
434 u8 running
; /* dac/adc running? */
435 u8 fmt
; /* format bits */
438 unsigned int dma_size
; /* in frames */
440 unsigned int ch
; /* channel (0/1) */
441 unsigned int offset
; /* physical address of the buffer */
444 /* mixer elements toggled/resumed during ac3 playback */
445 struct cmipci_mixer_auto_switches
{
446 const char *name
; /* switch to toggle */
447 int toggle_on
; /* value to change when ac3 mode */
449 static const struct cmipci_mixer_auto_switches cm_saved_mixer
[] = {
450 {"PCM Playback Switch", 0},
451 {"IEC958 Output Switch", 1},
452 {"IEC958 Mix Analog", 0},
453 // {"IEC958 Out To DAC", 1}, // no longer used
456 #define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer)
459 struct snd_card
*card
;
462 unsigned int device
; /* device ID */
465 unsigned long iobase
;
466 unsigned int ctrl
; /* FUNCTRL0 current value */
468 struct snd_pcm
*pcm
; /* DAC/ADC PCM */
469 struct snd_pcm
*pcm2
; /* 2nd DAC */
470 struct snd_pcm
*pcm_spdif
; /* SPDIF */
474 unsigned int can_ac3_sw
: 1;
475 unsigned int can_ac3_hw
: 1;
476 unsigned int can_multi_ch
: 1;
477 unsigned int do_soft_ac3
: 1;
479 unsigned int spdif_playback_avail
: 1; /* spdif ready? */
480 unsigned int spdif_playback_enabled
: 1; /* spdif switch enabled? */
481 int spdif_counter
; /* for software AC3 */
483 unsigned int dig_status
;
484 unsigned int dig_pcm_status
;
486 struct snd_pcm_hardware
*hw_info
[3]; /* for playbacks */
488 int opened
[2]; /* open mode */
489 struct mutex open_mutex
;
491 unsigned int mixer_insensitive
: 1;
492 struct snd_kcontrol
*mixer_res_ctl
[CM_SAVED_MIXERS
];
493 int mixer_res_status
[CM_SAVED_MIXERS
];
495 struct cmipci_pcm channel
[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */
498 struct snd_rawmidi
*rmidi
;
500 #ifdef SUPPORT_JOYSTICK
501 struct gameport
*gameport
;
507 unsigned int saved_regs
[0x20];
508 unsigned char saved_mixers
[0x20];
513 /* read/write operations for dword register */
514 static inline void snd_cmipci_write(struct cmipci
*cm
, unsigned int cmd
, unsigned int data
)
516 outl(data
, cm
->iobase
+ cmd
);
519 static inline unsigned int snd_cmipci_read(struct cmipci
*cm
, unsigned int cmd
)
521 return inl(cm
->iobase
+ cmd
);
524 /* read/write operations for word register */
525 static inline void snd_cmipci_write_w(struct cmipci
*cm
, unsigned int cmd
, unsigned short data
)
527 outw(data
, cm
->iobase
+ cmd
);
530 static inline unsigned short snd_cmipci_read_w(struct cmipci
*cm
, unsigned int cmd
)
532 return inw(cm
->iobase
+ cmd
);
535 /* read/write operations for byte register */
536 static inline void snd_cmipci_write_b(struct cmipci
*cm
, unsigned int cmd
, unsigned char data
)
538 outb(data
, cm
->iobase
+ cmd
);
541 static inline unsigned char snd_cmipci_read_b(struct cmipci
*cm
, unsigned int cmd
)
543 return inb(cm
->iobase
+ cmd
);
546 /* bit operations for dword register */
547 static int snd_cmipci_set_bit(struct cmipci
*cm
, unsigned int cmd
, unsigned int flag
)
549 unsigned int val
, oval
;
550 val
= oval
= inl(cm
->iobase
+ cmd
);
554 outl(val
, cm
->iobase
+ cmd
);
558 static int snd_cmipci_clear_bit(struct cmipci
*cm
, unsigned int cmd
, unsigned int flag
)
560 unsigned int val
, oval
;
561 val
= oval
= inl(cm
->iobase
+ cmd
);
565 outl(val
, cm
->iobase
+ cmd
);
569 /* bit operations for byte register */
570 static int snd_cmipci_set_bit_b(struct cmipci
*cm
, unsigned int cmd
, unsigned char flag
)
572 unsigned char val
, oval
;
573 val
= oval
= inb(cm
->iobase
+ cmd
);
577 outb(val
, cm
->iobase
+ cmd
);
581 static int snd_cmipci_clear_bit_b(struct cmipci
*cm
, unsigned int cmd
, unsigned char flag
)
583 unsigned char val
, oval
;
584 val
= oval
= inb(cm
->iobase
+ cmd
);
588 outb(val
, cm
->iobase
+ cmd
);
598 * calculate frequency
601 static unsigned int rates
[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
603 static unsigned int snd_cmipci_rate_freq(unsigned int rate
)
609 for (i
= 0; i
< ARRAY_SIZE(rates
); i
++) {
610 if (rates
[i
] == rate
)
617 #ifdef USE_VAR48KRATE
619 * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
620 * does it this way .. maybe not. Never get any information from C-Media about
621 * that <werner@suse.de>.
623 static int snd_cmipci_pll_rmn(unsigned int rate
, unsigned int adcmult
, int *r
, int *m
, int *n
)
625 unsigned int delta
, tolerance
;
628 for (*r
= 0; rate
< CM_MAXIMUM_RATE
/adcmult
; *r
+= (1<<5))
633 tolerance
= rate
*CM_TOLERANCE_RATE
;
635 for (xn
= (1+2); xn
< (0x1f+2); xn
++) {
636 for (xm
= (1+2); xm
< (0xff+2); xm
++) {
637 xr
= ((CM_REFFREQ_XIN
/adcmult
) * xm
) / xn
;
645 * If we found one, remember this,
646 * and try to find a closer one
648 if (delta
< tolerance
) {
660 * Program pll register bits, I assume that the 8 registers 0xf8 upto 0xff
661 * are mapped onto the 8 ADC/DAC sampling frequency which can be choosen
662 * at the register CM_REG_FUNCTRL1 (0x04).
663 * Problem: other ways are also possible (any information about that?)
665 static void snd_cmipci_set_pll(struct cmipci
*cm
, unsigned int rate
, unsigned int slot
)
667 unsigned int reg
= CM_REG_PLL
+ slot
;
669 * Guess that this programs at reg. 0x04 the pos 15:13/12:10
670 * for DSFC/ASFC (000 upto 111).
673 /* FIXME: Init (Do we've to set an other register first before programming?) */
675 /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
676 snd_cmipci_write_b(cm
, reg
, rate
>>8);
677 snd_cmipci_write_b(cm
, reg
, rate
&0xff);
679 /* FIXME: Setup (Do we've to set an other register first to enable this?) */
681 #endif /* USE_VAR48KRATE */
683 static int snd_cmipci_hw_params(struct snd_pcm_substream
*substream
,
684 struct snd_pcm_hw_params
*hw_params
)
686 return snd_pcm_lib_malloc_pages(substream
, params_buffer_bytes(hw_params
));
689 static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream
*substream
,
690 struct snd_pcm_hw_params
*hw_params
)
692 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
693 if (params_channels(hw_params
) > 2) {
694 mutex_lock(&cm
->open_mutex
);
695 if (cm
->opened
[CM_CH_PLAY
]) {
696 mutex_unlock(&cm
->open_mutex
);
699 /* reserve the channel A */
700 cm
->opened
[CM_CH_PLAY
] = CM_OPEN_PLAYBACK_MULTI
;
701 mutex_unlock(&cm
->open_mutex
);
703 return snd_pcm_lib_malloc_pages(substream
, params_buffer_bytes(hw_params
));
706 static void snd_cmipci_ch_reset(struct cmipci
*cm
, int ch
)
708 int reset
= CM_RST_CH0
<< (cm
->channel
[ch
].ch
);
709 snd_cmipci_write(cm
, CM_REG_FUNCTRL0
, cm
->ctrl
| reset
);
710 snd_cmipci_write(cm
, CM_REG_FUNCTRL0
, cm
->ctrl
& ~reset
);
714 static int snd_cmipci_hw_free(struct snd_pcm_substream
*substream
)
716 return snd_pcm_lib_free_pages(substream
);
723 static unsigned int hw_channels
[] = {1, 2, 4, 6, 8};
724 static struct snd_pcm_hw_constraint_list hw_constraints_channels_4
= {
729 static struct snd_pcm_hw_constraint_list hw_constraints_channels_6
= {
734 static struct snd_pcm_hw_constraint_list hw_constraints_channels_8
= {
740 static int set_dac_channels(struct cmipci
*cm
, struct cmipci_pcm
*rec
, int channels
)
743 if (!cm
->can_multi_ch
|| !rec
->ch
)
745 if (rec
->fmt
!= 0x03) /* stereo 16bit only */
749 if (cm
->can_multi_ch
) {
750 spin_lock_irq(&cm
->reg_lock
);
752 snd_cmipci_set_bit(cm
, CM_REG_LEGACY_CTRL
, CM_NXCHG
);
753 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_XCHGDAC
);
755 snd_cmipci_clear_bit(cm
, CM_REG_LEGACY_CTRL
, CM_NXCHG
);
756 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL
, CM_XCHGDAC
);
759 snd_cmipci_set_bit(cm
, CM_REG_EXT_MISC
, CM_CHB3D8C
);
761 snd_cmipci_clear_bit(cm
, CM_REG_EXT_MISC
, CM_CHB3D8C
);
763 snd_cmipci_set_bit(cm
, CM_REG_CHFORMAT
, CM_CHB3D5C
);
764 snd_cmipci_set_bit(cm
, CM_REG_LEGACY_CTRL
, CM_CHB3D6C
);
766 snd_cmipci_clear_bit(cm
, CM_REG_CHFORMAT
, CM_CHB3D5C
);
767 snd_cmipci_clear_bit(cm
, CM_REG_LEGACY_CTRL
, CM_CHB3D6C
);
770 snd_cmipci_set_bit(cm
, CM_REG_CHFORMAT
, CM_CHB3D
);
772 snd_cmipci_clear_bit(cm
, CM_REG_CHFORMAT
, CM_CHB3D
);
773 spin_unlock_irq(&cm
->reg_lock
);
780 * prepare playback/capture channel
781 * channel to be used must have been set in rec->ch.
783 static int snd_cmipci_pcm_prepare(struct cmipci
*cm
, struct cmipci_pcm
*rec
,
784 struct snd_pcm_substream
*substream
)
786 unsigned int reg
, freq
, val
;
787 unsigned int period_size
;
788 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
792 if (snd_pcm_format_width(runtime
->format
) >= 16) {
794 if (snd_pcm_format_width(runtime
->format
) > 16)
795 rec
->shift
++; /* 24/32bit */
797 if (runtime
->channels
> 1)
799 if (rec
->is_dac
&& set_dac_channels(cm
, rec
, runtime
->channels
) < 0) {
800 snd_printd("cannot set dac channels\n");
804 rec
->offset
= runtime
->dma_addr
;
805 /* buffer and period sizes in frame */
806 rec
->dma_size
= runtime
->buffer_size
<< rec
->shift
;
807 period_size
= runtime
->period_size
<< rec
->shift
;
808 if (runtime
->channels
> 2) {
810 rec
->dma_size
= (rec
->dma_size
* runtime
->channels
) / 2;
811 period_size
= (period_size
* runtime
->channels
) / 2;
814 spin_lock_irq(&cm
->reg_lock
);
816 /* set buffer address */
817 reg
= rec
->ch
? CM_REG_CH1_FRAME1
: CM_REG_CH0_FRAME1
;
818 snd_cmipci_write(cm
, reg
, rec
->offset
);
819 /* program sample counts */
820 reg
= rec
->ch
? CM_REG_CH1_FRAME2
: CM_REG_CH0_FRAME2
;
821 snd_cmipci_write_w(cm
, reg
, rec
->dma_size
- 1);
822 snd_cmipci_write_w(cm
, reg
+ 2, period_size
- 1);
824 /* set adc/dac flag */
825 val
= rec
->ch
? CM_CHADC1
: CM_CHADC0
;
830 snd_cmipci_write(cm
, CM_REG_FUNCTRL0
, cm
->ctrl
);
831 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
833 /* set sample rate */
834 freq
= snd_cmipci_rate_freq(runtime
->rate
);
835 val
= snd_cmipci_read(cm
, CM_REG_FUNCTRL1
);
837 val
&= ~CM_DSFC_MASK
;
838 val
|= (freq
<< CM_DSFC_SHIFT
) & CM_DSFC_MASK
;
840 val
&= ~CM_ASFC_MASK
;
841 val
|= (freq
<< CM_ASFC_SHIFT
) & CM_ASFC_MASK
;
843 snd_cmipci_write(cm
, CM_REG_FUNCTRL1
, val
);
844 //snd_printd("cmipci: functrl1 = %08x\n", val);
847 val
= snd_cmipci_read(cm
, CM_REG_CHFORMAT
);
849 val
&= ~CM_CH1FMT_MASK
;
850 val
|= rec
->fmt
<< CM_CH1FMT_SHIFT
;
852 val
&= ~CM_CH0FMT_MASK
;
853 val
|= rec
->fmt
<< CM_CH0FMT_SHIFT
;
855 if (cm
->chip_version
== 68) {
856 if (runtime
->rate
== 88200)
857 val
|= CM_CH0_SRATE_88K
<< (rec
->ch
* 2);
859 val
&= ~(CM_CH0_SRATE_88K
<< (rec
->ch
* 2));
860 if (runtime
->rate
== 96000)
861 val
|= CM_CH0_SRATE_96K
<< (rec
->ch
* 2);
863 val
&= ~(CM_CH0_SRATE_96K
<< (rec
->ch
* 2));
865 snd_cmipci_write(cm
, CM_REG_CHFORMAT
, val
);
866 //snd_printd("cmipci: chformat = %08x\n", val);
869 spin_unlock_irq(&cm
->reg_lock
);
877 static int snd_cmipci_pcm_trigger(struct cmipci
*cm
, struct cmipci_pcm
*rec
,
880 unsigned int inthld
, chen
, reset
, pause
;
883 inthld
= CM_CH0_INT_EN
<< rec
->ch
;
884 chen
= CM_CHEN0
<< rec
->ch
;
885 reset
= CM_RST_CH0
<< rec
->ch
;
886 pause
= CM_PAUSE0
<< rec
->ch
;
888 spin_lock(&cm
->reg_lock
);
890 case SNDRV_PCM_TRIGGER_START
:
893 snd_cmipci_set_bit(cm
, CM_REG_INT_HLDCLR
, inthld
);
896 snd_cmipci_write(cm
, CM_REG_FUNCTRL0
, cm
->ctrl
);
897 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
899 case SNDRV_PCM_TRIGGER_STOP
:
901 /* disable interrupt */
902 snd_cmipci_clear_bit(cm
, CM_REG_INT_HLDCLR
, inthld
);
905 snd_cmipci_write(cm
, CM_REG_FUNCTRL0
, cm
->ctrl
| reset
);
906 snd_cmipci_write(cm
, CM_REG_FUNCTRL0
, cm
->ctrl
& ~reset
);
907 rec
->needs_silencing
= rec
->is_dac
;
909 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
910 case SNDRV_PCM_TRIGGER_SUSPEND
:
912 snd_cmipci_write(cm
, CM_REG_FUNCTRL0
, cm
->ctrl
);
914 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
915 case SNDRV_PCM_TRIGGER_RESUME
:
917 snd_cmipci_write(cm
, CM_REG_FUNCTRL0
, cm
->ctrl
);
923 spin_unlock(&cm
->reg_lock
);
928 * return the current pointer
930 static snd_pcm_uframes_t
snd_cmipci_pcm_pointer(struct cmipci
*cm
, struct cmipci_pcm
*rec
,
931 struct snd_pcm_substream
*substream
)
937 #if 1 // this seems better..
938 reg
= rec
->ch
? CM_REG_CH1_FRAME2
: CM_REG_CH0_FRAME2
;
939 ptr
= rec
->dma_size
- (snd_cmipci_read_w(cm
, reg
) + 1);
942 reg
= rec
->ch
? CM_REG_CH1_FRAME1
: CM_REG_CH0_FRAME1
;
943 ptr
= snd_cmipci_read(cm
, reg
) - rec
->offset
;
944 ptr
= bytes_to_frames(substream
->runtime
, ptr
);
946 if (substream
->runtime
->channels
> 2)
947 ptr
= (ptr
* 2) / substream
->runtime
->channels
;
955 static int snd_cmipci_playback_trigger(struct snd_pcm_substream
*substream
,
958 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
959 return snd_cmipci_pcm_trigger(cm
, &cm
->channel
[CM_CH_PLAY
], cmd
);
962 static snd_pcm_uframes_t
snd_cmipci_playback_pointer(struct snd_pcm_substream
*substream
)
964 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
965 return snd_cmipci_pcm_pointer(cm
, &cm
->channel
[CM_CH_PLAY
], substream
);
974 static int snd_cmipci_capture_trigger(struct snd_pcm_substream
*substream
,
977 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
978 return snd_cmipci_pcm_trigger(cm
, &cm
->channel
[CM_CH_CAPT
], cmd
);
981 static snd_pcm_uframes_t
snd_cmipci_capture_pointer(struct snd_pcm_substream
*substream
)
983 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
984 return snd_cmipci_pcm_pointer(cm
, &cm
->channel
[CM_CH_CAPT
], substream
);
989 * hw preparation for spdif
992 static int snd_cmipci_spdif_default_info(struct snd_kcontrol
*kcontrol
,
993 struct snd_ctl_elem_info
*uinfo
)
995 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_IEC958
;
1000 static int snd_cmipci_spdif_default_get(struct snd_kcontrol
*kcontrol
,
1001 struct snd_ctl_elem_value
*ucontrol
)
1003 struct cmipci
*chip
= snd_kcontrol_chip(kcontrol
);
1006 spin_lock_irq(&chip
->reg_lock
);
1007 for (i
= 0; i
< 4; i
++)
1008 ucontrol
->value
.iec958
.status
[i
] = (chip
->dig_status
>> (i
* 8)) & 0xff;
1009 spin_unlock_irq(&chip
->reg_lock
);
1013 static int snd_cmipci_spdif_default_put(struct snd_kcontrol
*kcontrol
,
1014 struct snd_ctl_elem_value
*ucontrol
)
1016 struct cmipci
*chip
= snd_kcontrol_chip(kcontrol
);
1021 spin_lock_irq(&chip
->reg_lock
);
1022 for (i
= 0; i
< 4; i
++)
1023 val
|= (unsigned int)ucontrol
->value
.iec958
.status
[i
] << (i
* 8);
1024 change
= val
!= chip
->dig_status
;
1025 chip
->dig_status
= val
;
1026 spin_unlock_irq(&chip
->reg_lock
);
1030 static struct snd_kcontrol_new snd_cmipci_spdif_default __devinitdata
=
1032 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
1033 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,DEFAULT
),
1034 .info
= snd_cmipci_spdif_default_info
,
1035 .get
= snd_cmipci_spdif_default_get
,
1036 .put
= snd_cmipci_spdif_default_put
1039 static int snd_cmipci_spdif_mask_info(struct snd_kcontrol
*kcontrol
,
1040 struct snd_ctl_elem_info
*uinfo
)
1042 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_IEC958
;
1047 static int snd_cmipci_spdif_mask_get(struct snd_kcontrol
*kcontrol
,
1048 struct snd_ctl_elem_value
*ucontrol
)
1050 ucontrol
->value
.iec958
.status
[0] = 0xff;
1051 ucontrol
->value
.iec958
.status
[1] = 0xff;
1052 ucontrol
->value
.iec958
.status
[2] = 0xff;
1053 ucontrol
->value
.iec958
.status
[3] = 0xff;
1057 static struct snd_kcontrol_new snd_cmipci_spdif_mask __devinitdata
=
1059 .access
= SNDRV_CTL_ELEM_ACCESS_READ
,
1060 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
1061 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,CON_MASK
),
1062 .info
= snd_cmipci_spdif_mask_info
,
1063 .get
= snd_cmipci_spdif_mask_get
,
1066 static int snd_cmipci_spdif_stream_info(struct snd_kcontrol
*kcontrol
,
1067 struct snd_ctl_elem_info
*uinfo
)
1069 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_IEC958
;
1074 static int snd_cmipci_spdif_stream_get(struct snd_kcontrol
*kcontrol
,
1075 struct snd_ctl_elem_value
*ucontrol
)
1077 struct cmipci
*chip
= snd_kcontrol_chip(kcontrol
);
1080 spin_lock_irq(&chip
->reg_lock
);
1081 for (i
= 0; i
< 4; i
++)
1082 ucontrol
->value
.iec958
.status
[i
] = (chip
->dig_pcm_status
>> (i
* 8)) & 0xff;
1083 spin_unlock_irq(&chip
->reg_lock
);
1087 static int snd_cmipci_spdif_stream_put(struct snd_kcontrol
*kcontrol
,
1088 struct snd_ctl_elem_value
*ucontrol
)
1090 struct cmipci
*chip
= snd_kcontrol_chip(kcontrol
);
1095 spin_lock_irq(&chip
->reg_lock
);
1096 for (i
= 0; i
< 4; i
++)
1097 val
|= (unsigned int)ucontrol
->value
.iec958
.status
[i
] << (i
* 8);
1098 change
= val
!= chip
->dig_pcm_status
;
1099 chip
->dig_pcm_status
= val
;
1100 spin_unlock_irq(&chip
->reg_lock
);
1104 static struct snd_kcontrol_new snd_cmipci_spdif_stream __devinitdata
=
1106 .access
= SNDRV_CTL_ELEM_ACCESS_READWRITE
| SNDRV_CTL_ELEM_ACCESS_INACTIVE
,
1107 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
1108 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,PCM_STREAM
),
1109 .info
= snd_cmipci_spdif_stream_info
,
1110 .get
= snd_cmipci_spdif_stream_get
,
1111 .put
= snd_cmipci_spdif_stream_put
1117 /* save mixer setting and mute for AC3 playback */
1118 static int save_mixer_state(struct cmipci
*cm
)
1120 if (! cm
->mixer_insensitive
) {
1121 struct snd_ctl_elem_value
*val
;
1124 val
= kmalloc(sizeof(*val
), GFP_ATOMIC
);
1127 for (i
= 0; i
< CM_SAVED_MIXERS
; i
++) {
1128 struct snd_kcontrol
*ctl
= cm
->mixer_res_ctl
[i
];
1131 memset(val
, 0, sizeof(*val
));
1133 cm
->mixer_res_status
[i
] = val
->value
.integer
.value
[0];
1134 val
->value
.integer
.value
[0] = cm_saved_mixer
[i
].toggle_on
;
1135 event
= SNDRV_CTL_EVENT_MASK_INFO
;
1136 if (cm
->mixer_res_status
[i
] != val
->value
.integer
.value
[0]) {
1137 ctl
->put(ctl
, val
); /* toggle */
1138 event
|= SNDRV_CTL_EVENT_MASK_VALUE
;
1140 ctl
->vd
[0].access
|= SNDRV_CTL_ELEM_ACCESS_INACTIVE
;
1141 snd_ctl_notify(cm
->card
, event
, &ctl
->id
);
1145 cm
->mixer_insensitive
= 1;
1151 /* restore the previously saved mixer status */
1152 static void restore_mixer_state(struct cmipci
*cm
)
1154 if (cm
->mixer_insensitive
) {
1155 struct snd_ctl_elem_value
*val
;
1158 val
= kmalloc(sizeof(*val
), GFP_KERNEL
);
1161 cm
->mixer_insensitive
= 0; /* at first clear this;
1162 otherwise the changes will be ignored */
1163 for (i
= 0; i
< CM_SAVED_MIXERS
; i
++) {
1164 struct snd_kcontrol
*ctl
= cm
->mixer_res_ctl
[i
];
1168 memset(val
, 0, sizeof(*val
));
1169 ctl
->vd
[0].access
&= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE
;
1171 event
= SNDRV_CTL_EVENT_MASK_INFO
;
1172 if (val
->value
.integer
.value
[0] != cm
->mixer_res_status
[i
]) {
1173 val
->value
.integer
.value
[0] = cm
->mixer_res_status
[i
];
1175 event
|= SNDRV_CTL_EVENT_MASK_VALUE
;
1177 snd_ctl_notify(cm
->card
, event
, &ctl
->id
);
1184 /* spinlock held! */
1185 static void setup_ac3(struct cmipci
*cm
, struct snd_pcm_substream
*subs
, int do_ac3
, int rate
)
1189 snd_cmipci_set_bit(cm
, CM_REG_CHFORMAT
, CM_AC3EN1
);
1191 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_AC3EN2
);
1193 if (cm
->can_ac3_hw
) {
1194 /* SPD24SEL for 037, 0x02 */
1195 /* SPD24SEL for 039, 0x20, but cannot be set */
1196 snd_cmipci_set_bit(cm
, CM_REG_CHFORMAT
, CM_SPD24SEL
);
1197 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL
, CM_SPD32SEL
);
1198 } else { /* can_ac3_sw */
1199 /* SPD32SEL for 037 & 039, 0x20 */
1200 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_SPD32SEL
);
1201 /* set 176K sample rate to fix 033 HW bug */
1202 if (cm
->chip_version
== 33) {
1203 if (rate
>= 48000) {
1204 snd_cmipci_set_bit(cm
, CM_REG_CHFORMAT
, CM_PLAYBACK_SRATE_176K
);
1206 snd_cmipci_clear_bit(cm
, CM_REG_CHFORMAT
, CM_PLAYBACK_SRATE_176K
);
1212 snd_cmipci_clear_bit(cm
, CM_REG_CHFORMAT
, CM_AC3EN1
);
1213 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL
, CM_AC3EN2
);
1215 if (cm
->can_ac3_hw
) {
1216 /* chip model >= 37 */
1217 if (snd_pcm_format_width(subs
->runtime
->format
) > 16) {
1218 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_SPD32SEL
);
1219 snd_cmipci_set_bit(cm
, CM_REG_CHFORMAT
, CM_SPD24SEL
);
1221 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL
, CM_SPD32SEL
);
1222 snd_cmipci_clear_bit(cm
, CM_REG_CHFORMAT
, CM_SPD24SEL
);
1225 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL
, CM_SPD32SEL
);
1226 snd_cmipci_clear_bit(cm
, CM_REG_CHFORMAT
, CM_SPD24SEL
);
1227 snd_cmipci_clear_bit(cm
, CM_REG_CHFORMAT
, CM_PLAYBACK_SRATE_176K
);
1232 static int setup_spdif_playback(struct cmipci
*cm
, struct snd_pcm_substream
*subs
, int up
, int do_ac3
)
1236 rate
= subs
->runtime
->rate
;
1239 if ((err
= save_mixer_state(cm
)) < 0)
1242 spin_lock_irq(&cm
->reg_lock
);
1243 cm
->spdif_playback_avail
= up
;
1245 /* they are controlled via "IEC958 Output Switch" */
1246 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1247 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1248 if (cm
->spdif_playback_enabled
)
1249 snd_cmipci_set_bit(cm
, CM_REG_FUNCTRL1
, CM_PLAYBACK_SPDF
);
1250 setup_ac3(cm
, subs
, do_ac3
, rate
);
1252 if (rate
== 48000 || rate
== 96000)
1253 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_SPDIF48K
| CM_SPDF_AC97
);
1255 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL
, CM_SPDIF48K
| CM_SPDF_AC97
);
1257 snd_cmipci_set_bit(cm
, CM_REG_CHFORMAT
, CM_DBLSPDS
);
1259 snd_cmipci_clear_bit(cm
, CM_REG_CHFORMAT
, CM_DBLSPDS
);
1261 /* they are controlled via "IEC958 Output Switch" */
1262 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1263 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1264 snd_cmipci_clear_bit(cm
, CM_REG_CHFORMAT
, CM_DBLSPDS
);
1265 snd_cmipci_clear_bit(cm
, CM_REG_FUNCTRL1
, CM_PLAYBACK_SPDF
);
1266 setup_ac3(cm
, subs
, 0, 0);
1268 spin_unlock_irq(&cm
->reg_lock
);
1277 /* playback - enable spdif only on the certain condition */
1278 static int snd_cmipci_playback_prepare(struct snd_pcm_substream
*substream
)
1280 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
1281 int rate
= substream
->runtime
->rate
;
1282 int err
, do_spdif
, do_ac3
= 0;
1284 do_spdif
= (rate
>= 44100 &&
1285 substream
->runtime
->format
== SNDRV_PCM_FORMAT_S16_LE
&&
1286 substream
->runtime
->channels
== 2);
1287 if (do_spdif
&& cm
->can_ac3_hw
)
1288 do_ac3
= cm
->dig_pcm_status
& IEC958_AES0_NONAUDIO
;
1289 if ((err
= setup_spdif_playback(cm
, substream
, do_spdif
, do_ac3
)) < 0)
1291 return snd_cmipci_pcm_prepare(cm
, &cm
->channel
[CM_CH_PLAY
], substream
);
1294 /* playback (via device #2) - enable spdif always */
1295 static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream
*substream
)
1297 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
1301 do_ac3
= cm
->dig_pcm_status
& IEC958_AES0_NONAUDIO
;
1303 do_ac3
= 1; /* doesn't matter */
1304 if ((err
= setup_spdif_playback(cm
, substream
, 1, do_ac3
)) < 0)
1306 return snd_cmipci_pcm_prepare(cm
, &cm
->channel
[CM_CH_PLAY
], substream
);
1310 * Apparently, the samples last played on channel A stay in some buffer, even
1311 * after the channel is reset, and get added to the data for the rear DACs when
1312 * playing a multichannel stream on channel B. This is likely to generate
1313 * wraparounds and thus distortions.
1314 * To avoid this, we play at least one zero sample after the actual stream has
1317 static void snd_cmipci_silence_hack(struct cmipci
*cm
, struct cmipci_pcm
*rec
)
1319 struct snd_pcm_runtime
*runtime
= rec
->substream
->runtime
;
1320 unsigned int reg
, val
;
1322 if (rec
->needs_silencing
&& runtime
&& runtime
->dma_area
) {
1323 /* set up a small silence buffer */
1324 memset(runtime
->dma_area
, 0, PAGE_SIZE
);
1325 reg
= rec
->ch
? CM_REG_CH1_FRAME2
: CM_REG_CH0_FRAME2
;
1326 val
= ((PAGE_SIZE
/ 4) - 1) | (((PAGE_SIZE
/ 4) / 2 - 1) << 16);
1327 snd_cmipci_write(cm
, reg
, val
);
1329 /* configure for 16 bits, 2 channels, 8 kHz */
1330 if (runtime
->channels
> 2)
1331 set_dac_channels(cm
, rec
, 2);
1332 spin_lock_irq(&cm
->reg_lock
);
1333 val
= snd_cmipci_read(cm
, CM_REG_FUNCTRL1
);
1334 val
&= ~(CM_ASFC_MASK
<< (rec
->ch
* 3));
1335 val
|= (4 << CM_ASFC_SHIFT
) << (rec
->ch
* 3);
1336 snd_cmipci_write(cm
, CM_REG_FUNCTRL1
, val
);
1337 val
= snd_cmipci_read(cm
, CM_REG_CHFORMAT
);
1338 val
&= ~(CM_CH0FMT_MASK
<< (rec
->ch
* 2));
1339 val
|= (3 << CM_CH0FMT_SHIFT
) << (rec
->ch
* 2);
1340 if (cm
->chip_version
== 68) {
1341 val
&= ~(CM_CH0_SRATE_88K
<< (rec
->ch
* 2));
1342 val
&= ~(CM_CH0_SRATE_96K
<< (rec
->ch
* 2));
1344 snd_cmipci_write(cm
, CM_REG_CHFORMAT
, val
);
1346 /* start stream (we don't need interrupts) */
1347 cm
->ctrl
|= CM_CHEN0
<< rec
->ch
;
1348 snd_cmipci_write(cm
, CM_REG_FUNCTRL0
, cm
->ctrl
);
1349 spin_unlock_irq(&cm
->reg_lock
);
1353 /* stop and reset stream */
1354 spin_lock_irq(&cm
->reg_lock
);
1355 cm
->ctrl
&= ~(CM_CHEN0
<< rec
->ch
);
1356 val
= CM_RST_CH0
<< rec
->ch
;
1357 snd_cmipci_write(cm
, CM_REG_FUNCTRL0
, cm
->ctrl
| val
);
1358 snd_cmipci_write(cm
, CM_REG_FUNCTRL0
, cm
->ctrl
& ~val
);
1359 spin_unlock_irq(&cm
->reg_lock
);
1361 rec
->needs_silencing
= 0;
1365 static int snd_cmipci_playback_hw_free(struct snd_pcm_substream
*substream
)
1367 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
1368 setup_spdif_playback(cm
, substream
, 0, 0);
1369 restore_mixer_state(cm
);
1370 snd_cmipci_silence_hack(cm
, &cm
->channel
[0]);
1371 return snd_cmipci_hw_free(substream
);
1374 static int snd_cmipci_playback2_hw_free(struct snd_pcm_substream
*substream
)
1376 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
1377 snd_cmipci_silence_hack(cm
, &cm
->channel
[1]);
1378 return snd_cmipci_hw_free(substream
);
1382 static int snd_cmipci_capture_prepare(struct snd_pcm_substream
*substream
)
1384 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
1385 return snd_cmipci_pcm_prepare(cm
, &cm
->channel
[CM_CH_CAPT
], substream
);
1388 /* capture with spdif (via device #2) */
1389 static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream
*substream
)
1391 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
1393 spin_lock_irq(&cm
->reg_lock
);
1394 snd_cmipci_set_bit(cm
, CM_REG_FUNCTRL1
, CM_CAPTURE_SPDF
);
1395 spin_unlock_irq(&cm
->reg_lock
);
1397 return snd_cmipci_pcm_prepare(cm
, &cm
->channel
[CM_CH_CAPT
], substream
);
1400 static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream
*subs
)
1402 struct cmipci
*cm
= snd_pcm_substream_chip(subs
);
1404 spin_lock_irq(&cm
->reg_lock
);
1405 snd_cmipci_clear_bit(cm
, CM_REG_FUNCTRL1
, CM_CAPTURE_SPDF
);
1406 spin_unlock_irq(&cm
->reg_lock
);
1408 return snd_cmipci_hw_free(subs
);
1415 static irqreturn_t
snd_cmipci_interrupt(int irq
, void *dev_id
)
1417 struct cmipci
*cm
= dev_id
;
1418 unsigned int status
, mask
= 0;
1420 /* fastpath out, to ease interrupt sharing */
1421 status
= snd_cmipci_read(cm
, CM_REG_INT_STATUS
);
1422 if (!(status
& CM_INTR
))
1425 /* acknowledge interrupt */
1426 spin_lock(&cm
->reg_lock
);
1427 if (status
& CM_CHINT0
)
1428 mask
|= CM_CH0_INT_EN
;
1429 if (status
& CM_CHINT1
)
1430 mask
|= CM_CH1_INT_EN
;
1431 snd_cmipci_clear_bit(cm
, CM_REG_INT_HLDCLR
, mask
);
1432 snd_cmipci_set_bit(cm
, CM_REG_INT_HLDCLR
, mask
);
1433 spin_unlock(&cm
->reg_lock
);
1435 if (cm
->rmidi
&& (status
& CM_UARTINT
))
1436 snd_mpu401_uart_interrupt(irq
, cm
->rmidi
->private_data
);
1439 if ((status
& CM_CHINT0
) && cm
->channel
[0].running
)
1440 snd_pcm_period_elapsed(cm
->channel
[0].substream
);
1441 if ((status
& CM_CHINT1
) && cm
->channel
[1].running
)
1442 snd_pcm_period_elapsed(cm
->channel
[1].substream
);
1451 /* playback on channel A */
1452 static struct snd_pcm_hardware snd_cmipci_playback
=
1454 .info
= (SNDRV_PCM_INFO_MMAP
| SNDRV_PCM_INFO_INTERLEAVED
|
1455 SNDRV_PCM_INFO_BLOCK_TRANSFER
| SNDRV_PCM_INFO_PAUSE
|
1456 SNDRV_PCM_INFO_RESUME
| SNDRV_PCM_INFO_MMAP_VALID
),
1457 .formats
= SNDRV_PCM_FMTBIT_U8
| SNDRV_PCM_FMTBIT_S16_LE
,
1458 .rates
= SNDRV_PCM_RATE_5512
| SNDRV_PCM_RATE_8000_48000
,
1463 .buffer_bytes_max
= (128*1024),
1464 .period_bytes_min
= 64,
1465 .period_bytes_max
= (128*1024),
1467 .periods_max
= 1024,
1471 /* capture on channel B */
1472 static struct snd_pcm_hardware snd_cmipci_capture
=
1474 .info
= (SNDRV_PCM_INFO_MMAP
| SNDRV_PCM_INFO_INTERLEAVED
|
1475 SNDRV_PCM_INFO_BLOCK_TRANSFER
| SNDRV_PCM_INFO_PAUSE
|
1476 SNDRV_PCM_INFO_RESUME
| SNDRV_PCM_INFO_MMAP_VALID
),
1477 .formats
= SNDRV_PCM_FMTBIT_U8
| SNDRV_PCM_FMTBIT_S16_LE
,
1478 .rates
= SNDRV_PCM_RATE_5512
| SNDRV_PCM_RATE_8000_48000
,
1483 .buffer_bytes_max
= (128*1024),
1484 .period_bytes_min
= 64,
1485 .period_bytes_max
= (128*1024),
1487 .periods_max
= 1024,
1491 /* playback on channel B - stereo 16bit only? */
1492 static struct snd_pcm_hardware snd_cmipci_playback2
=
1494 .info
= (SNDRV_PCM_INFO_MMAP
| SNDRV_PCM_INFO_INTERLEAVED
|
1495 SNDRV_PCM_INFO_BLOCK_TRANSFER
| SNDRV_PCM_INFO_PAUSE
|
1496 SNDRV_PCM_INFO_RESUME
| SNDRV_PCM_INFO_MMAP_VALID
),
1497 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
1498 .rates
= SNDRV_PCM_RATE_5512
| SNDRV_PCM_RATE_8000_48000
,
1503 .buffer_bytes_max
= (128*1024),
1504 .period_bytes_min
= 64,
1505 .period_bytes_max
= (128*1024),
1507 .periods_max
= 1024,
1511 /* spdif playback on channel A */
1512 static struct snd_pcm_hardware snd_cmipci_playback_spdif
=
1514 .info
= (SNDRV_PCM_INFO_MMAP
| SNDRV_PCM_INFO_INTERLEAVED
|
1515 SNDRV_PCM_INFO_BLOCK_TRANSFER
| SNDRV_PCM_INFO_PAUSE
|
1516 SNDRV_PCM_INFO_RESUME
| SNDRV_PCM_INFO_MMAP_VALID
),
1517 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
1518 .rates
= SNDRV_PCM_RATE_44100
| SNDRV_PCM_RATE_48000
,
1523 .buffer_bytes_max
= (128*1024),
1524 .period_bytes_min
= 64,
1525 .period_bytes_max
= (128*1024),
1527 .periods_max
= 1024,
1531 /* spdif playback on channel A (32bit, IEC958 subframes) */
1532 static struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe
=
1534 .info
= (SNDRV_PCM_INFO_MMAP
| SNDRV_PCM_INFO_INTERLEAVED
|
1535 SNDRV_PCM_INFO_BLOCK_TRANSFER
| SNDRV_PCM_INFO_PAUSE
|
1536 SNDRV_PCM_INFO_RESUME
| SNDRV_PCM_INFO_MMAP_VALID
),
1537 .formats
= SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE
,
1538 .rates
= SNDRV_PCM_RATE_44100
| SNDRV_PCM_RATE_48000
,
1543 .buffer_bytes_max
= (128*1024),
1544 .period_bytes_min
= 64,
1545 .period_bytes_max
= (128*1024),
1547 .periods_max
= 1024,
1551 /* spdif capture on channel B */
1552 static struct snd_pcm_hardware snd_cmipci_capture_spdif
=
1554 .info
= (SNDRV_PCM_INFO_MMAP
| SNDRV_PCM_INFO_INTERLEAVED
|
1555 SNDRV_PCM_INFO_BLOCK_TRANSFER
| SNDRV_PCM_INFO_PAUSE
|
1556 SNDRV_PCM_INFO_RESUME
| SNDRV_PCM_INFO_MMAP_VALID
),
1557 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
1558 .rates
= SNDRV_PCM_RATE_44100
| SNDRV_PCM_RATE_48000
,
1563 .buffer_bytes_max
= (128*1024),
1564 .period_bytes_min
= 64,
1565 .period_bytes_max
= (128*1024),
1567 .periods_max
= 1024,
1572 * check device open/close
1574 static int open_device_check(struct cmipci
*cm
, int mode
, struct snd_pcm_substream
*subs
)
1576 int ch
= mode
& CM_OPEN_CH_MASK
;
1578 /* FIXME: a file should wait until the device becomes free
1579 * when it's opened on blocking mode. however, since the current
1580 * pcm framework doesn't pass file pointer before actually opened,
1581 * we can't know whether blocking mode or not in open callback..
1583 mutex_lock(&cm
->open_mutex
);
1584 if (cm
->opened
[ch
]) {
1585 mutex_unlock(&cm
->open_mutex
);
1588 cm
->opened
[ch
] = mode
;
1589 cm
->channel
[ch
].substream
= subs
;
1590 if (! (mode
& CM_OPEN_DAC
)) {
1591 /* disable dual DAC mode */
1592 cm
->channel
[ch
].is_dac
= 0;
1593 spin_lock_irq(&cm
->reg_lock
);
1594 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL
, CM_ENDBDAC
);
1595 spin_unlock_irq(&cm
->reg_lock
);
1597 mutex_unlock(&cm
->open_mutex
);
1601 static void close_device_check(struct cmipci
*cm
, int mode
)
1603 int ch
= mode
& CM_OPEN_CH_MASK
;
1605 mutex_lock(&cm
->open_mutex
);
1606 if (cm
->opened
[ch
] == mode
) {
1607 if (cm
->channel
[ch
].substream
) {
1608 snd_cmipci_ch_reset(cm
, ch
);
1609 cm
->channel
[ch
].running
= 0;
1610 cm
->channel
[ch
].substream
= NULL
;
1613 if (! cm
->channel
[ch
].is_dac
) {
1614 /* enable dual DAC mode again */
1615 cm
->channel
[ch
].is_dac
= 1;
1616 spin_lock_irq(&cm
->reg_lock
);
1617 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_ENDBDAC
);
1618 spin_unlock_irq(&cm
->reg_lock
);
1621 mutex_unlock(&cm
->open_mutex
);
1627 static int snd_cmipci_playback_open(struct snd_pcm_substream
*substream
)
1629 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
1630 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1633 if ((err
= open_device_check(cm
, CM_OPEN_PLAYBACK
, substream
)) < 0)
1635 runtime
->hw
= snd_cmipci_playback
;
1636 if (cm
->chip_version
== 68) {
1637 runtime
->hw
.rates
|= SNDRV_PCM_RATE_88200
|
1638 SNDRV_PCM_RATE_96000
;
1639 runtime
->hw
.rate_max
= 96000;
1641 snd_pcm_hw_constraint_minmax(runtime
, SNDRV_PCM_HW_PARAM_BUFFER_SIZE
, 0, 0x10000);
1642 cm
->dig_pcm_status
= cm
->dig_status
;
1646 static int snd_cmipci_capture_open(struct snd_pcm_substream
*substream
)
1648 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
1649 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1652 if ((err
= open_device_check(cm
, CM_OPEN_CAPTURE
, substream
)) < 0)
1654 runtime
->hw
= snd_cmipci_capture
;
1655 if (cm
->chip_version
== 68) { // 8768 only supports 44k/48k recording
1656 runtime
->hw
.rate_min
= 41000;
1657 runtime
->hw
.rates
= SNDRV_PCM_RATE_44100
| SNDRV_PCM_RATE_48000
;
1659 snd_pcm_hw_constraint_minmax(runtime
, SNDRV_PCM_HW_PARAM_BUFFER_SIZE
, 0, 0x10000);
1663 static int snd_cmipci_playback2_open(struct snd_pcm_substream
*substream
)
1665 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
1666 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1669 if ((err
= open_device_check(cm
, CM_OPEN_PLAYBACK2
, substream
)) < 0) /* use channel B */
1671 runtime
->hw
= snd_cmipci_playback2
;
1672 mutex_lock(&cm
->open_mutex
);
1673 if (! cm
->opened
[CM_CH_PLAY
]) {
1674 if (cm
->can_multi_ch
) {
1675 runtime
->hw
.channels_max
= cm
->max_channels
;
1676 if (cm
->max_channels
== 4)
1677 snd_pcm_hw_constraint_list(runtime
, 0, SNDRV_PCM_HW_PARAM_CHANNELS
, &hw_constraints_channels_4
);
1678 else if (cm
->max_channels
== 6)
1679 snd_pcm_hw_constraint_list(runtime
, 0, SNDRV_PCM_HW_PARAM_CHANNELS
, &hw_constraints_channels_6
);
1680 else if (cm
->max_channels
== 8)
1681 snd_pcm_hw_constraint_list(runtime
, 0, SNDRV_PCM_HW_PARAM_CHANNELS
, &hw_constraints_channels_8
);
1684 mutex_unlock(&cm
->open_mutex
);
1685 if (cm
->chip_version
== 68) {
1686 runtime
->hw
.rates
|= SNDRV_PCM_RATE_88200
|
1687 SNDRV_PCM_RATE_96000
;
1688 runtime
->hw
.rate_max
= 96000;
1690 snd_pcm_hw_constraint_minmax(runtime
, SNDRV_PCM_HW_PARAM_BUFFER_SIZE
, 0, 0x10000);
1694 static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream
*substream
)
1696 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
1697 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1700 if ((err
= open_device_check(cm
, CM_OPEN_SPDIF_PLAYBACK
, substream
)) < 0) /* use channel A */
1702 if (cm
->can_ac3_hw
) {
1703 runtime
->hw
= snd_cmipci_playback_spdif
;
1704 if (cm
->chip_version
>= 37) {
1705 runtime
->hw
.formats
|= SNDRV_PCM_FMTBIT_S32_LE
;
1706 snd_pcm_hw_constraint_msbits(runtime
, 0, 32, 24);
1708 if (cm
->chip_version
== 68) {
1709 runtime
->hw
.rates
|= SNDRV_PCM_RATE_88200
|
1710 SNDRV_PCM_RATE_96000
;
1711 runtime
->hw
.rate_max
= 96000;
1714 runtime
->hw
= snd_cmipci_playback_iec958_subframe
;
1716 snd_pcm_hw_constraint_minmax(runtime
, SNDRV_PCM_HW_PARAM_BUFFER_SIZE
, 0, 0x40000);
1717 cm
->dig_pcm_status
= cm
->dig_status
;
1721 static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream
*substream
)
1723 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
1724 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1727 if ((err
= open_device_check(cm
, CM_OPEN_SPDIF_CAPTURE
, substream
)) < 0) /* use channel B */
1729 runtime
->hw
= snd_cmipci_capture_spdif
;
1730 snd_pcm_hw_constraint_minmax(runtime
, SNDRV_PCM_HW_PARAM_BUFFER_SIZE
, 0, 0x40000);
1738 static int snd_cmipci_playback_close(struct snd_pcm_substream
*substream
)
1740 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
1741 close_device_check(cm
, CM_OPEN_PLAYBACK
);
1745 static int snd_cmipci_capture_close(struct snd_pcm_substream
*substream
)
1747 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
1748 close_device_check(cm
, CM_OPEN_CAPTURE
);
1752 static int snd_cmipci_playback2_close(struct snd_pcm_substream
*substream
)
1754 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
1755 close_device_check(cm
, CM_OPEN_PLAYBACK2
);
1756 close_device_check(cm
, CM_OPEN_PLAYBACK_MULTI
);
1760 static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream
*substream
)
1762 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
1763 close_device_check(cm
, CM_OPEN_SPDIF_PLAYBACK
);
1767 static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream
*substream
)
1769 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
1770 close_device_check(cm
, CM_OPEN_SPDIF_CAPTURE
);
1778 static struct snd_pcm_ops snd_cmipci_playback_ops
= {
1779 .open
= snd_cmipci_playback_open
,
1780 .close
= snd_cmipci_playback_close
,
1781 .ioctl
= snd_pcm_lib_ioctl
,
1782 .hw_params
= snd_cmipci_hw_params
,
1783 .hw_free
= snd_cmipci_playback_hw_free
,
1784 .prepare
= snd_cmipci_playback_prepare
,
1785 .trigger
= snd_cmipci_playback_trigger
,
1786 .pointer
= snd_cmipci_playback_pointer
,
1789 static struct snd_pcm_ops snd_cmipci_capture_ops
= {
1790 .open
= snd_cmipci_capture_open
,
1791 .close
= snd_cmipci_capture_close
,
1792 .ioctl
= snd_pcm_lib_ioctl
,
1793 .hw_params
= snd_cmipci_hw_params
,
1794 .hw_free
= snd_cmipci_hw_free
,
1795 .prepare
= snd_cmipci_capture_prepare
,
1796 .trigger
= snd_cmipci_capture_trigger
,
1797 .pointer
= snd_cmipci_capture_pointer
,
1800 static struct snd_pcm_ops snd_cmipci_playback2_ops
= {
1801 .open
= snd_cmipci_playback2_open
,
1802 .close
= snd_cmipci_playback2_close
,
1803 .ioctl
= snd_pcm_lib_ioctl
,
1804 .hw_params
= snd_cmipci_playback2_hw_params
,
1805 .hw_free
= snd_cmipci_playback2_hw_free
,
1806 .prepare
= snd_cmipci_capture_prepare
, /* channel B */
1807 .trigger
= snd_cmipci_capture_trigger
, /* channel B */
1808 .pointer
= snd_cmipci_capture_pointer
, /* channel B */
1811 static struct snd_pcm_ops snd_cmipci_playback_spdif_ops
= {
1812 .open
= snd_cmipci_playback_spdif_open
,
1813 .close
= snd_cmipci_playback_spdif_close
,
1814 .ioctl
= snd_pcm_lib_ioctl
,
1815 .hw_params
= snd_cmipci_hw_params
,
1816 .hw_free
= snd_cmipci_playback_hw_free
,
1817 .prepare
= snd_cmipci_playback_spdif_prepare
, /* set up rate */
1818 .trigger
= snd_cmipci_playback_trigger
,
1819 .pointer
= snd_cmipci_playback_pointer
,
1822 static struct snd_pcm_ops snd_cmipci_capture_spdif_ops
= {
1823 .open
= snd_cmipci_capture_spdif_open
,
1824 .close
= snd_cmipci_capture_spdif_close
,
1825 .ioctl
= snd_pcm_lib_ioctl
,
1826 .hw_params
= snd_cmipci_hw_params
,
1827 .hw_free
= snd_cmipci_capture_spdif_hw_free
,
1828 .prepare
= snd_cmipci_capture_spdif_prepare
,
1829 .trigger
= snd_cmipci_capture_trigger
,
1830 .pointer
= snd_cmipci_capture_pointer
,
1837 static int __devinit
snd_cmipci_pcm_new(struct cmipci
*cm
, int device
)
1839 struct snd_pcm
*pcm
;
1842 err
= snd_pcm_new(cm
->card
, cm
->card
->driver
, device
, 1, 1, &pcm
);
1846 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &snd_cmipci_playback_ops
);
1847 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_CAPTURE
, &snd_cmipci_capture_ops
);
1849 pcm
->private_data
= cm
;
1850 pcm
->info_flags
= 0;
1851 strcpy(pcm
->name
, "C-Media PCI DAC/ADC");
1854 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV
,
1855 snd_dma_pci_data(cm
->pci
), 64*1024, 128*1024);
1860 static int __devinit
snd_cmipci_pcm2_new(struct cmipci
*cm
, int device
)
1862 struct snd_pcm
*pcm
;
1865 err
= snd_pcm_new(cm
->card
, cm
->card
->driver
, device
, 1, 0, &pcm
);
1869 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &snd_cmipci_playback2_ops
);
1871 pcm
->private_data
= cm
;
1872 pcm
->info_flags
= 0;
1873 strcpy(pcm
->name
, "C-Media PCI 2nd DAC");
1876 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV
,
1877 snd_dma_pci_data(cm
->pci
), 64*1024, 128*1024);
1882 static int __devinit
snd_cmipci_pcm_spdif_new(struct cmipci
*cm
, int device
)
1884 struct snd_pcm
*pcm
;
1887 err
= snd_pcm_new(cm
->card
, cm
->card
->driver
, device
, 1, 1, &pcm
);
1891 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &snd_cmipci_playback_spdif_ops
);
1892 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_CAPTURE
, &snd_cmipci_capture_spdif_ops
);
1894 pcm
->private_data
= cm
;
1895 pcm
->info_flags
= 0;
1896 strcpy(pcm
->name
, "C-Media PCI IEC958");
1897 cm
->pcm_spdif
= pcm
;
1899 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV
,
1900 snd_dma_pci_data(cm
->pci
), 64*1024, 128*1024);
1907 * - CM8338/8738 has a compatible mixer interface with SB16, but
1908 * lack of some elements like tone control, i/o gain and AGC.
1909 * - Access to native registers:
1911 * - Output mute switches
1914 static void snd_cmipci_mixer_write(struct cmipci
*s
, unsigned char idx
, unsigned char data
)
1916 outb(idx
, s
->iobase
+ CM_REG_SB16_ADDR
);
1917 outb(data
, s
->iobase
+ CM_REG_SB16_DATA
);
1920 static unsigned char snd_cmipci_mixer_read(struct cmipci
*s
, unsigned char idx
)
1924 outb(idx
, s
->iobase
+ CM_REG_SB16_ADDR
);
1925 v
= inb(s
->iobase
+ CM_REG_SB16_DATA
);
1930 * general mixer element
1932 struct cmipci_sb_reg
{
1933 unsigned int left_reg
, right_reg
;
1934 unsigned int left_shift
, right_shift
;
1936 unsigned int invert
: 1;
1937 unsigned int stereo
: 1;
1940 #define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
1941 ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
1943 #define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
1944 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1945 .info = snd_cmipci_info_volume, \
1946 .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
1947 .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
1950 #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
1951 #define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
1952 #define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
1953 #define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
1955 static void cmipci_sb_reg_decode(struct cmipci_sb_reg
*r
, unsigned long val
)
1957 r
->left_reg
= val
& 0xff;
1958 r
->right_reg
= (val
>> 8) & 0xff;
1959 r
->left_shift
= (val
>> 16) & 0x07;
1960 r
->right_shift
= (val
>> 19) & 0x07;
1961 r
->invert
= (val
>> 22) & 1;
1962 r
->stereo
= (val
>> 23) & 1;
1963 r
->mask
= (val
>> 24) & 0xff;
1966 static int snd_cmipci_info_volume(struct snd_kcontrol
*kcontrol
,
1967 struct snd_ctl_elem_info
*uinfo
)
1969 struct cmipci_sb_reg reg
;
1971 cmipci_sb_reg_decode(®
, kcontrol
->private_value
);
1972 uinfo
->type
= reg
.mask
== 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN
: SNDRV_CTL_ELEM_TYPE_INTEGER
;
1973 uinfo
->count
= reg
.stereo
+ 1;
1974 uinfo
->value
.integer
.min
= 0;
1975 uinfo
->value
.integer
.max
= reg
.mask
;
1979 static int snd_cmipci_get_volume(struct snd_kcontrol
*kcontrol
,
1980 struct snd_ctl_elem_value
*ucontrol
)
1982 struct cmipci
*cm
= snd_kcontrol_chip(kcontrol
);
1983 struct cmipci_sb_reg reg
;
1986 cmipci_sb_reg_decode(®
, kcontrol
->private_value
);
1987 spin_lock_irq(&cm
->reg_lock
);
1988 val
= (snd_cmipci_mixer_read(cm
, reg
.left_reg
) >> reg
.left_shift
) & reg
.mask
;
1990 val
= reg
.mask
- val
;
1991 ucontrol
->value
.integer
.value
[0] = val
;
1993 val
= (snd_cmipci_mixer_read(cm
, reg
.right_reg
) >> reg
.right_shift
) & reg
.mask
;
1995 val
= reg
.mask
- val
;
1996 ucontrol
->value
.integer
.value
[1] = val
;
1998 spin_unlock_irq(&cm
->reg_lock
);
2002 static int snd_cmipci_put_volume(struct snd_kcontrol
*kcontrol
,
2003 struct snd_ctl_elem_value
*ucontrol
)
2005 struct cmipci
*cm
= snd_kcontrol_chip(kcontrol
);
2006 struct cmipci_sb_reg reg
;
2008 int left
, right
, oleft
, oright
;
2010 cmipci_sb_reg_decode(®
, kcontrol
->private_value
);
2011 left
= ucontrol
->value
.integer
.value
[0] & reg
.mask
;
2013 left
= reg
.mask
- left
;
2014 left
<<= reg
.left_shift
;
2016 right
= ucontrol
->value
.integer
.value
[1] & reg
.mask
;
2018 right
= reg
.mask
- right
;
2019 right
<<= reg
.right_shift
;
2022 spin_lock_irq(&cm
->reg_lock
);
2023 oleft
= snd_cmipci_mixer_read(cm
, reg
.left_reg
);
2024 left
|= oleft
& ~(reg
.mask
<< reg
.left_shift
);
2025 change
= left
!= oleft
;
2027 if (reg
.left_reg
!= reg
.right_reg
) {
2028 snd_cmipci_mixer_write(cm
, reg
.left_reg
, left
);
2029 oright
= snd_cmipci_mixer_read(cm
, reg
.right_reg
);
2032 right
|= oright
& ~(reg
.mask
<< reg
.right_shift
);
2033 change
|= right
!= oright
;
2034 snd_cmipci_mixer_write(cm
, reg
.right_reg
, right
);
2036 snd_cmipci_mixer_write(cm
, reg
.left_reg
, left
);
2037 spin_unlock_irq(&cm
->reg_lock
);
2042 * input route (left,right) -> (left,right)
2044 #define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
2045 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2046 .info = snd_cmipci_info_input_sw, \
2047 .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
2048 .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
2051 static int snd_cmipci_info_input_sw(struct snd_kcontrol
*kcontrol
,
2052 struct snd_ctl_elem_info
*uinfo
)
2054 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_BOOLEAN
;
2056 uinfo
->value
.integer
.min
= 0;
2057 uinfo
->value
.integer
.max
= 1;
2061 static int snd_cmipci_get_input_sw(struct snd_kcontrol
*kcontrol
,
2062 struct snd_ctl_elem_value
*ucontrol
)
2064 struct cmipci
*cm
= snd_kcontrol_chip(kcontrol
);
2065 struct cmipci_sb_reg reg
;
2068 cmipci_sb_reg_decode(®
, kcontrol
->private_value
);
2069 spin_lock_irq(&cm
->reg_lock
);
2070 val1
= snd_cmipci_mixer_read(cm
, reg
.left_reg
);
2071 val2
= snd_cmipci_mixer_read(cm
, reg
.right_reg
);
2072 spin_unlock_irq(&cm
->reg_lock
);
2073 ucontrol
->value
.integer
.value
[0] = (val1
>> reg
.left_shift
) & 1;
2074 ucontrol
->value
.integer
.value
[1] = (val2
>> reg
.left_shift
) & 1;
2075 ucontrol
->value
.integer
.value
[2] = (val1
>> reg
.right_shift
) & 1;
2076 ucontrol
->value
.integer
.value
[3] = (val2
>> reg
.right_shift
) & 1;
2080 static int snd_cmipci_put_input_sw(struct snd_kcontrol
*kcontrol
,
2081 struct snd_ctl_elem_value
*ucontrol
)
2083 struct cmipci
*cm
= snd_kcontrol_chip(kcontrol
);
2084 struct cmipci_sb_reg reg
;
2086 int val1
, val2
, oval1
, oval2
;
2088 cmipci_sb_reg_decode(®
, kcontrol
->private_value
);
2089 spin_lock_irq(&cm
->reg_lock
);
2090 oval1
= snd_cmipci_mixer_read(cm
, reg
.left_reg
);
2091 oval2
= snd_cmipci_mixer_read(cm
, reg
.right_reg
);
2092 val1
= oval1
& ~((1 << reg
.left_shift
) | (1 << reg
.right_shift
));
2093 val2
= oval2
& ~((1 << reg
.left_shift
) | (1 << reg
.right_shift
));
2094 val1
|= (ucontrol
->value
.integer
.value
[0] & 1) << reg
.left_shift
;
2095 val2
|= (ucontrol
->value
.integer
.value
[1] & 1) << reg
.left_shift
;
2096 val1
|= (ucontrol
->value
.integer
.value
[2] & 1) << reg
.right_shift
;
2097 val2
|= (ucontrol
->value
.integer
.value
[3] & 1) << reg
.right_shift
;
2098 change
= val1
!= oval1
|| val2
!= oval2
;
2099 snd_cmipci_mixer_write(cm
, reg
.left_reg
, val1
);
2100 snd_cmipci_mixer_write(cm
, reg
.right_reg
, val2
);
2101 spin_unlock_irq(&cm
->reg_lock
);
2106 * native mixer switches/volumes
2109 #define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
2110 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2111 .info = snd_cmipci_info_native_mixer, \
2112 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2113 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
2116 #define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
2117 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2118 .info = snd_cmipci_info_native_mixer, \
2119 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2120 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
2123 #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
2124 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2125 .info = snd_cmipci_info_native_mixer, \
2126 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2127 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
2130 #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
2131 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2132 .info = snd_cmipci_info_native_mixer, \
2133 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2134 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
2137 static int snd_cmipci_info_native_mixer(struct snd_kcontrol
*kcontrol
,
2138 struct snd_ctl_elem_info
*uinfo
)
2140 struct cmipci_sb_reg reg
;
2142 cmipci_sb_reg_decode(®
, kcontrol
->private_value
);
2143 uinfo
->type
= reg
.mask
== 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN
: SNDRV_CTL_ELEM_TYPE_INTEGER
;
2144 uinfo
->count
= reg
.stereo
+ 1;
2145 uinfo
->value
.integer
.min
= 0;
2146 uinfo
->value
.integer
.max
= reg
.mask
;
2151 static int snd_cmipci_get_native_mixer(struct snd_kcontrol
*kcontrol
,
2152 struct snd_ctl_elem_value
*ucontrol
)
2154 struct cmipci
*cm
= snd_kcontrol_chip(kcontrol
);
2155 struct cmipci_sb_reg reg
;
2156 unsigned char oreg
, val
;
2158 cmipci_sb_reg_decode(®
, kcontrol
->private_value
);
2159 spin_lock_irq(&cm
->reg_lock
);
2160 oreg
= inb(cm
->iobase
+ reg
.left_reg
);
2161 val
= (oreg
>> reg
.left_shift
) & reg
.mask
;
2163 val
= reg
.mask
- val
;
2164 ucontrol
->value
.integer
.value
[0] = val
;
2166 val
= (oreg
>> reg
.right_shift
) & reg
.mask
;
2168 val
= reg
.mask
- val
;
2169 ucontrol
->value
.integer
.value
[1] = val
;
2171 spin_unlock_irq(&cm
->reg_lock
);
2175 static int snd_cmipci_put_native_mixer(struct snd_kcontrol
*kcontrol
,
2176 struct snd_ctl_elem_value
*ucontrol
)
2178 struct cmipci
*cm
= snd_kcontrol_chip(kcontrol
);
2179 struct cmipci_sb_reg reg
;
2180 unsigned char oreg
, nreg
, val
;
2182 cmipci_sb_reg_decode(®
, kcontrol
->private_value
);
2183 spin_lock_irq(&cm
->reg_lock
);
2184 oreg
= inb(cm
->iobase
+ reg
.left_reg
);
2185 val
= ucontrol
->value
.integer
.value
[0] & reg
.mask
;
2187 val
= reg
.mask
- val
;
2188 nreg
= oreg
& ~(reg
.mask
<< reg
.left_shift
);
2189 nreg
|= (val
<< reg
.left_shift
);
2191 val
= ucontrol
->value
.integer
.value
[1] & reg
.mask
;
2193 val
= reg
.mask
- val
;
2194 nreg
&= ~(reg
.mask
<< reg
.right_shift
);
2195 nreg
|= (val
<< reg
.right_shift
);
2197 outb(nreg
, cm
->iobase
+ reg
.left_reg
);
2198 spin_unlock_irq(&cm
->reg_lock
);
2199 return (nreg
!= oreg
);
2203 * special case - check mixer sensitivity
2205 static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol
*kcontrol
,
2206 struct snd_ctl_elem_value
*ucontrol
)
2208 //struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2209 return snd_cmipci_get_native_mixer(kcontrol
, ucontrol
);
2212 static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol
*kcontrol
,
2213 struct snd_ctl_elem_value
*ucontrol
)
2215 struct cmipci
*cm
= snd_kcontrol_chip(kcontrol
);
2216 if (cm
->mixer_insensitive
) {
2220 return snd_cmipci_put_native_mixer(kcontrol
, ucontrol
);
2224 static struct snd_kcontrol_new snd_cmipci_mixers
[] __devinitdata
= {
2225 CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV
, 3, 31),
2226 CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1
, CM_X3DEN_SHIFT
, 0),
2227 CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV
, 3, 31),
2228 //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2229 { /* switch with sensitivity */
2230 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2231 .name
= "PCM Playback Switch",
2232 .info
= snd_cmipci_info_native_mixer
,
2233 .get
= snd_cmipci_get_native_mixer_sensitive
,
2234 .put
= snd_cmipci_put_native_mixer_sensitive
,
2235 .private_value
= COMPOSE_SB_REG(CM_REG_MIXER1
, CM_REG_MIXER1
, CM_WSMUTE_SHIFT
, CM_WSMUTE_SHIFT
, 1, 1, 0),
2237 CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1
, CM_WAVEINL_SHIFT
, CM_WAVEINR_SHIFT
, 0),
2238 CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV
, 3, 31),
2239 CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1
, CM_FMMUTE_SHIFT
, 1),
2240 CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2241 CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV
, 3, 31),
2242 CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2243 CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2244 CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV
, 3, 31),
2245 CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2246 CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2247 CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV
, 3, 31),
2248 CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2249 CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT
, SB_DSP4_INPUT_RIGHT
, 0, 0, 1, 0, 0),
2250 CMIPCI_SB_VOL_MONO("PC Speaker Playback Volume", SB_DSP4_SPEAKER_DEV
, 6, 3),
2251 CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL
, 4, 0, 15),
2252 CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2
, CM_VAUXLM_SHIFT
, CM_VAUXRM_SHIFT
, 0),
2253 CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2
, CM_RAUXLEN_SHIFT
, CM_RAUXREN_SHIFT
, 0),
2254 CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2
, CM_MICGAINZ_SHIFT
, 1),
2255 CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2
, CM_VADMIC_SHIFT
, 7),
2256 CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND
, 5, 7),
2257 CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND
, CM_REG_EXTENT_IND
, 4, 4, 1, 0, 0),
2258 CMIPCI_DOUBLE("PC Speaker Playback Switch", CM_REG_EXTENT_IND
, CM_REG_EXTENT_IND
, 3, 3, 1, 0, 0),
2259 CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND
, CM_REG_EXTENT_IND
, 0, 0, 1, 0, 0),
2266 struct cmipci_switch_args
{
2267 int reg
; /* register index */
2268 unsigned int mask
; /* mask bits */
2269 unsigned int mask_on
; /* mask bits to turn on */
2270 unsigned int is_byte
: 1; /* byte access? */
2271 unsigned int ac3_sensitive
: 1; /* access forbidden during
2272 * non-audio operation?
2276 #define snd_cmipci_uswitch_info snd_ctl_boolean_mono_info
2278 static int _snd_cmipci_uswitch_get(struct snd_kcontrol
*kcontrol
,
2279 struct snd_ctl_elem_value
*ucontrol
,
2280 struct cmipci_switch_args
*args
)
2283 struct cmipci
*cm
= snd_kcontrol_chip(kcontrol
);
2285 spin_lock_irq(&cm
->reg_lock
);
2286 if (args
->ac3_sensitive
&& cm
->mixer_insensitive
) {
2287 ucontrol
->value
.integer
.value
[0] = 0;
2288 spin_unlock_irq(&cm
->reg_lock
);
2292 val
= inb(cm
->iobase
+ args
->reg
);
2294 val
= snd_cmipci_read(cm
, args
->reg
);
2295 ucontrol
->value
.integer
.value
[0] = ((val
& args
->mask
) == args
->mask_on
) ? 1 : 0;
2296 spin_unlock_irq(&cm
->reg_lock
);
2300 static int snd_cmipci_uswitch_get(struct snd_kcontrol
*kcontrol
,
2301 struct snd_ctl_elem_value
*ucontrol
)
2303 struct cmipci_switch_args
*args
;
2304 args
= (struct cmipci_switch_args
*)kcontrol
->private_value
;
2305 snd_assert(args
!= NULL
, return -EINVAL
);
2306 return _snd_cmipci_uswitch_get(kcontrol
, ucontrol
, args
);
2309 static int _snd_cmipci_uswitch_put(struct snd_kcontrol
*kcontrol
,
2310 struct snd_ctl_elem_value
*ucontrol
,
2311 struct cmipci_switch_args
*args
)
2315 struct cmipci
*cm
= snd_kcontrol_chip(kcontrol
);
2317 spin_lock_irq(&cm
->reg_lock
);
2318 if (args
->ac3_sensitive
&& cm
->mixer_insensitive
) {
2320 spin_unlock_irq(&cm
->reg_lock
);
2324 val
= inb(cm
->iobase
+ args
->reg
);
2326 val
= snd_cmipci_read(cm
, args
->reg
);
2327 change
= (val
& args
->mask
) != (ucontrol
->value
.integer
.value
[0] ?
2328 args
->mask_on
: (args
->mask
& ~args
->mask_on
));
2331 if (ucontrol
->value
.integer
.value
[0])
2332 val
|= args
->mask_on
;
2334 val
|= (args
->mask
& ~args
->mask_on
);
2336 outb((unsigned char)val
, cm
->iobase
+ args
->reg
);
2338 snd_cmipci_write(cm
, args
->reg
, val
);
2340 spin_unlock_irq(&cm
->reg_lock
);
2344 static int snd_cmipci_uswitch_put(struct snd_kcontrol
*kcontrol
,
2345 struct snd_ctl_elem_value
*ucontrol
)
2347 struct cmipci_switch_args
*args
;
2348 args
= (struct cmipci_switch_args
*)kcontrol
->private_value
;
2349 snd_assert(args
!= NULL
, return -EINVAL
);
2350 return _snd_cmipci_uswitch_put(kcontrol
, ucontrol
, args
);
2353 #define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2354 static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2357 .mask_on = xmask_on, \
2358 .is_byte = xis_byte, \
2359 .ac3_sensitive = xac3, \
2362 #define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2363 DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2365 #if 0 /* these will be controlled in pcm device */
2366 DEFINE_BIT_SWITCH_ARG(spdif_in
, CM_REG_FUNCTRL1
, CM_SPDF_1
, 0, 0);
2367 DEFINE_BIT_SWITCH_ARG(spdif_out
, CM_REG_FUNCTRL1
, CM_SPDF_0
, 0, 0);
2369 DEFINE_BIT_SWITCH_ARG(spdif_in_sel1
, CM_REG_CHFORMAT
, CM_SPDIF_SELECT1
, 0, 0);
2370 DEFINE_BIT_SWITCH_ARG(spdif_in_sel2
, CM_REG_MISC_CTRL
, CM_SPDIF_SELECT2
, 0, 0);
2371 DEFINE_BIT_SWITCH_ARG(spdif_enable
, CM_REG_LEGACY_CTRL
, CM_ENSPDOUT
, 0, 0);
2372 DEFINE_BIT_SWITCH_ARG(spdo2dac
, CM_REG_FUNCTRL1
, CM_SPDO2DAC
, 0, 1);
2373 DEFINE_BIT_SWITCH_ARG(spdi_valid
, CM_REG_MISC
, CM_SPDVALID
, 1, 0);
2374 DEFINE_BIT_SWITCH_ARG(spdif_copyright
, CM_REG_LEGACY_CTRL
, CM_SPDCOPYRHT
, 0, 0);
2375 DEFINE_BIT_SWITCH_ARG(spdif_dac_out
, CM_REG_LEGACY_CTRL
, CM_DAC2SPDO
, 0, 1);
2376 DEFINE_SWITCH_ARG(spdo_5v
, CM_REG_MISC_CTRL
, CM_SPDO5V
, 0, 0, 0); /* inverse: 0 = 5V */
2377 // DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2378 DEFINE_BIT_SWITCH_ARG(spdif_loop
, CM_REG_FUNCTRL1
, CM_SPDFLOOP
, 0, 1);
2379 DEFINE_BIT_SWITCH_ARG(spdi_monitor
, CM_REG_MIXER1
, CM_CDPLAY
, 1, 0);
2380 /* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2381 DEFINE_BIT_SWITCH_ARG(spdi_phase
, CM_REG_MISC
, CM_SPDIF_INVERSE
, 1, 0);
2382 DEFINE_BIT_SWITCH_ARG(spdi_phase2
, CM_REG_CHFORMAT
, CM_SPDIF_INVERSE2
, 0, 0);
2384 DEFINE_SWITCH_ARG(exchange_dac
, CM_REG_MISC_CTRL
, CM_XCHGDAC
, 0, 0, 0); /* reversed */
2386 DEFINE_SWITCH_ARG(exchange_dac
, CM_REG_MISC_CTRL
, CM_XCHGDAC
, CM_XCHGDAC
, 0, 0);
2388 DEFINE_BIT_SWITCH_ARG(fourch
, CM_REG_MISC_CTRL
, CM_N4SPK3D
, 0, 0);
2389 // DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_REAR2LIN, 1, 0);
2390 // DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_CENTR2LIN|CM_BASE2LIN, 0, 0);
2391 // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2392 DEFINE_SWITCH_ARG(modem
, CM_REG_MISC_CTRL
, CM_FLINKON
|CM_FLINKOFF
, CM_FLINKON
, 0, 0);
2394 #define DEFINE_SWITCH(sname, stype, sarg) \
2397 .info = snd_cmipci_uswitch_info, \
2398 .get = snd_cmipci_uswitch_get, \
2399 .put = snd_cmipci_uswitch_put, \
2400 .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2403 #define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2404 #define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2408 * callbacks for spdif output switch
2409 * needs toggle two registers..
2411 static int snd_cmipci_spdout_enable_get(struct snd_kcontrol
*kcontrol
,
2412 struct snd_ctl_elem_value
*ucontrol
)
2415 changed
= _snd_cmipci_uswitch_get(kcontrol
, ucontrol
, &cmipci_switch_arg_spdif_enable
);
2416 changed
|= _snd_cmipci_uswitch_get(kcontrol
, ucontrol
, &cmipci_switch_arg_spdo2dac
);
2420 static int snd_cmipci_spdout_enable_put(struct snd_kcontrol
*kcontrol
,
2421 struct snd_ctl_elem_value
*ucontrol
)
2423 struct cmipci
*chip
= snd_kcontrol_chip(kcontrol
);
2425 changed
= _snd_cmipci_uswitch_put(kcontrol
, ucontrol
, &cmipci_switch_arg_spdif_enable
);
2426 changed
|= _snd_cmipci_uswitch_put(kcontrol
, ucontrol
, &cmipci_switch_arg_spdo2dac
);
2428 if (ucontrol
->value
.integer
.value
[0]) {
2429 if (chip
->spdif_playback_avail
)
2430 snd_cmipci_set_bit(chip
, CM_REG_FUNCTRL1
, CM_PLAYBACK_SPDF
);
2432 if (chip
->spdif_playback_avail
)
2433 snd_cmipci_clear_bit(chip
, CM_REG_FUNCTRL1
, CM_PLAYBACK_SPDF
);
2436 chip
->spdif_playback_enabled
= ucontrol
->value
.integer
.value
[0];
2441 static int snd_cmipci_line_in_mode_info(struct snd_kcontrol
*kcontrol
,
2442 struct snd_ctl_elem_info
*uinfo
)
2444 struct cmipci
*cm
= snd_kcontrol_chip(kcontrol
);
2445 static char *texts
[3] = { "Line-In", "Rear Output", "Bass Output" };
2446 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_ENUMERATED
;
2448 uinfo
->value
.enumerated
.items
= cm
->chip_version
>= 39 ? 3 : 2;
2449 if (uinfo
->value
.enumerated
.item
>= uinfo
->value
.enumerated
.items
)
2450 uinfo
->value
.enumerated
.item
= uinfo
->value
.enumerated
.items
- 1;
2451 strcpy(uinfo
->value
.enumerated
.name
, texts
[uinfo
->value
.enumerated
.item
]);
2455 static inline unsigned int get_line_in_mode(struct cmipci
*cm
)
2458 if (cm
->chip_version
>= 39) {
2459 val
= snd_cmipci_read(cm
, CM_REG_LEGACY_CTRL
);
2460 if (val
& (CM_CENTR2LIN
| CM_BASE2LIN
))
2463 val
= snd_cmipci_read_b(cm
, CM_REG_MIXER1
);
2464 if (val
& CM_REAR2LIN
)
2469 static int snd_cmipci_line_in_mode_get(struct snd_kcontrol
*kcontrol
,
2470 struct snd_ctl_elem_value
*ucontrol
)
2472 struct cmipci
*cm
= snd_kcontrol_chip(kcontrol
);
2474 spin_lock_irq(&cm
->reg_lock
);
2475 ucontrol
->value
.enumerated
.item
[0] = get_line_in_mode(cm
);
2476 spin_unlock_irq(&cm
->reg_lock
);
2480 static int snd_cmipci_line_in_mode_put(struct snd_kcontrol
*kcontrol
,
2481 struct snd_ctl_elem_value
*ucontrol
)
2483 struct cmipci
*cm
= snd_kcontrol_chip(kcontrol
);
2486 spin_lock_irq(&cm
->reg_lock
);
2487 if (ucontrol
->value
.enumerated
.item
[0] == 2)
2488 change
= snd_cmipci_set_bit(cm
, CM_REG_LEGACY_CTRL
, CM_CENTR2LIN
| CM_BASE2LIN
);
2490 change
= snd_cmipci_clear_bit(cm
, CM_REG_LEGACY_CTRL
, CM_CENTR2LIN
| CM_BASE2LIN
);
2491 if (ucontrol
->value
.enumerated
.item
[0] == 1)
2492 change
|= snd_cmipci_set_bit_b(cm
, CM_REG_MIXER1
, CM_REAR2LIN
);
2494 change
|= snd_cmipci_clear_bit_b(cm
, CM_REG_MIXER1
, CM_REAR2LIN
);
2495 spin_unlock_irq(&cm
->reg_lock
);
2499 static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol
*kcontrol
,
2500 struct snd_ctl_elem_info
*uinfo
)
2502 static char *texts
[2] = { "Mic-In", "Center/LFE Output" };
2503 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_ENUMERATED
;
2505 uinfo
->value
.enumerated
.items
= 2;
2506 if (uinfo
->value
.enumerated
.item
>= uinfo
->value
.enumerated
.items
)
2507 uinfo
->value
.enumerated
.item
= uinfo
->value
.enumerated
.items
- 1;
2508 strcpy(uinfo
->value
.enumerated
.name
, texts
[uinfo
->value
.enumerated
.item
]);
2512 static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol
*kcontrol
,
2513 struct snd_ctl_elem_value
*ucontrol
)
2515 struct cmipci
*cm
= snd_kcontrol_chip(kcontrol
);
2516 /* same bit as spdi_phase */
2517 spin_lock_irq(&cm
->reg_lock
);
2518 ucontrol
->value
.enumerated
.item
[0] =
2519 (snd_cmipci_read_b(cm
, CM_REG_MISC
) & CM_SPDIF_INVERSE
) ? 1 : 0;
2520 spin_unlock_irq(&cm
->reg_lock
);
2524 static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol
*kcontrol
,
2525 struct snd_ctl_elem_value
*ucontrol
)
2527 struct cmipci
*cm
= snd_kcontrol_chip(kcontrol
);
2530 spin_lock_irq(&cm
->reg_lock
);
2531 if (ucontrol
->value
.enumerated
.item
[0])
2532 change
= snd_cmipci_set_bit_b(cm
, CM_REG_MISC
, CM_SPDIF_INVERSE
);
2534 change
= snd_cmipci_clear_bit_b(cm
, CM_REG_MISC
, CM_SPDIF_INVERSE
);
2535 spin_unlock_irq(&cm
->reg_lock
);
2539 /* both for CM8338/8738 */
2540 static struct snd_kcontrol_new snd_cmipci_mixer_switches
[] __devinitdata
= {
2541 DEFINE_MIXER_SWITCH("Four Channel Mode", fourch
),
2543 .name
= "Line-In Mode",
2544 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2545 .info
= snd_cmipci_line_in_mode_info
,
2546 .get
= snd_cmipci_line_in_mode_get
,
2547 .put
= snd_cmipci_line_in_mode_put
,
2551 /* for non-multichannel chips */
2552 static struct snd_kcontrol_new snd_cmipci_nomulti_switch __devinitdata
=
2553 DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac
);
2555 /* only for CM8738 */
2556 static struct snd_kcontrol_new snd_cmipci_8738_mixer_switches
[] __devinitdata
= {
2557 #if 0 /* controlled in pcm device */
2558 DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in
),
2559 DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out
),
2560 DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac
),
2562 // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2563 { .name
= "IEC958 Output Switch",
2564 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2565 .info
= snd_cmipci_uswitch_info
,
2566 .get
= snd_cmipci_spdout_enable_get
,
2567 .put
= snd_cmipci_spdout_enable_put
,
2569 DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid
),
2570 DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright
),
2571 DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v
),
2572 // DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2573 DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop
),
2574 DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor
),
2577 /* only for model 033/037 */
2578 static struct snd_kcontrol_new snd_cmipci_old_mixer_switches
[] __devinitdata
= {
2579 DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out
),
2580 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase
),
2581 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1
),
2584 /* only for model 039 or later */
2585 static struct snd_kcontrol_new snd_cmipci_extra_mixer_switches
[] __devinitdata
= {
2586 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2
),
2587 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2
),
2589 .name
= "Mic-In Mode",
2590 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2591 .info
= snd_cmipci_mic_in_mode_info
,
2592 .get
= snd_cmipci_mic_in_mode_get
,
2593 .put
= snd_cmipci_mic_in_mode_put
,
2597 /* card control switches */
2598 static struct snd_kcontrol_new snd_cmipci_control_switches
[] __devinitdata
= {
2599 // DEFINE_CARD_SWITCH("Joystick", joystick), /* now module option */
2600 DEFINE_CARD_SWITCH("Modem", modem
),
2604 static int __devinit
snd_cmipci_mixer_new(struct cmipci
*cm
, int pcm_spdif_device
)
2606 struct snd_card
*card
;
2607 struct snd_kcontrol_new
*sw
;
2608 struct snd_kcontrol
*kctl
;
2612 snd_assert(cm
!= NULL
&& cm
->card
!= NULL
, return -EINVAL
);
2616 strcpy(card
->mixername
, "CMedia PCI");
2618 spin_lock_irq(&cm
->reg_lock
);
2619 snd_cmipci_mixer_write(cm
, 0x00, 0x00); /* mixer reset */
2620 spin_unlock_irq(&cm
->reg_lock
);
2622 for (idx
= 0; idx
< ARRAY_SIZE(snd_cmipci_mixers
); idx
++) {
2623 if (cm
->chip_version
== 68) { // 8768 has no PCM volume
2624 if (!strcmp(snd_cmipci_mixers
[idx
].name
,
2625 "PCM Playback Volume"))
2628 if ((err
= snd_ctl_add(card
, snd_ctl_new1(&snd_cmipci_mixers
[idx
], cm
))) < 0)
2632 /* mixer switches */
2633 sw
= snd_cmipci_mixer_switches
;
2634 for (idx
= 0; idx
< ARRAY_SIZE(snd_cmipci_mixer_switches
); idx
++, sw
++) {
2635 err
= snd_ctl_add(cm
->card
, snd_ctl_new1(sw
, cm
));
2639 if (! cm
->can_multi_ch
) {
2640 err
= snd_ctl_add(cm
->card
, snd_ctl_new1(&snd_cmipci_nomulti_switch
, cm
));
2644 if (cm
->device
== PCI_DEVICE_ID_CMEDIA_CM8738
||
2645 cm
->device
== PCI_DEVICE_ID_CMEDIA_CM8738B
) {
2646 sw
= snd_cmipci_8738_mixer_switches
;
2647 for (idx
= 0; idx
< ARRAY_SIZE(snd_cmipci_8738_mixer_switches
); idx
++, sw
++) {
2648 err
= snd_ctl_add(cm
->card
, snd_ctl_new1(sw
, cm
));
2652 if (cm
->can_ac3_hw
) {
2653 if ((err
= snd_ctl_add(card
, kctl
= snd_ctl_new1(&snd_cmipci_spdif_default
, cm
))) < 0)
2655 kctl
->id
.device
= pcm_spdif_device
;
2656 if ((err
= snd_ctl_add(card
, kctl
= snd_ctl_new1(&snd_cmipci_spdif_mask
, cm
))) < 0)
2658 kctl
->id
.device
= pcm_spdif_device
;
2659 if ((err
= snd_ctl_add(card
, kctl
= snd_ctl_new1(&snd_cmipci_spdif_stream
, cm
))) < 0)
2661 kctl
->id
.device
= pcm_spdif_device
;
2663 if (cm
->chip_version
<= 37) {
2664 sw
= snd_cmipci_old_mixer_switches
;
2665 for (idx
= 0; idx
< ARRAY_SIZE(snd_cmipci_old_mixer_switches
); idx
++, sw
++) {
2666 err
= snd_ctl_add(cm
->card
, snd_ctl_new1(sw
, cm
));
2672 if (cm
->chip_version
>= 39) {
2673 sw
= snd_cmipci_extra_mixer_switches
;
2674 for (idx
= 0; idx
< ARRAY_SIZE(snd_cmipci_extra_mixer_switches
); idx
++, sw
++) {
2675 err
= snd_ctl_add(cm
->card
, snd_ctl_new1(sw
, cm
));
2682 sw
= snd_cmipci_control_switches
;
2683 for (idx
= 0; idx
< ARRAY_SIZE(snd_cmipci_control_switches
); idx
++, sw
++) {
2684 err
= snd_ctl_add(cm
->card
, snd_ctl_new1(sw
, cm
));
2689 for (idx
= 0; idx
< CM_SAVED_MIXERS
; idx
++) {
2690 struct snd_ctl_elem_id id
;
2691 struct snd_kcontrol
*ctl
;
2692 memset(&id
, 0, sizeof(id
));
2693 id
.iface
= SNDRV_CTL_ELEM_IFACE_MIXER
;
2694 strcpy(id
.name
, cm_saved_mixer
[idx
].name
);
2695 if ((ctl
= snd_ctl_find_id(cm
->card
, &id
)) != NULL
)
2696 cm
->mixer_res_ctl
[idx
] = ctl
;
2707 #ifdef CONFIG_PROC_FS
2708 static void snd_cmipci_proc_read(struct snd_info_entry
*entry
,
2709 struct snd_info_buffer
*buffer
)
2711 struct cmipci
*cm
= entry
->private_data
;
2714 snd_iprintf(buffer
, "%s\n", cm
->card
->longname
);
2715 for (i
= 0; i
< 0x94; i
++) {
2718 v
= inb(cm
->iobase
+ i
);
2720 snd_iprintf(buffer
, "\n%02x:", i
);
2721 snd_iprintf(buffer
, " %02x", v
);
2723 snd_iprintf(buffer
, "\n");
2726 static void __devinit
snd_cmipci_proc_init(struct cmipci
*cm
)
2728 struct snd_info_entry
*entry
;
2730 if (! snd_card_proc_new(cm
->card
, "cmipci", &entry
))
2731 snd_info_set_text_ops(entry
, cm
, snd_cmipci_proc_read
);
2733 #else /* !CONFIG_PROC_FS */
2734 static inline void snd_cmipci_proc_init(struct cmipci
*cm
) {}
2738 static struct pci_device_id snd_cmipci_ids
[] = {
2739 {PCI_VENDOR_ID_CMEDIA
, PCI_DEVICE_ID_CMEDIA_CM8338A
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
2740 {PCI_VENDOR_ID_CMEDIA
, PCI_DEVICE_ID_CMEDIA_CM8338B
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
2741 {PCI_VENDOR_ID_CMEDIA
, PCI_DEVICE_ID_CMEDIA_CM8738
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
2742 {PCI_VENDOR_ID_CMEDIA
, PCI_DEVICE_ID_CMEDIA_CM8738B
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
2743 {PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_CMEDIA_CM8738
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
2749 * check chip version and capabilities
2750 * driver name is modified according to the chip model
2752 static void __devinit
query_chip(struct cmipci
*cm
)
2754 unsigned int detect
;
2756 /* check reg 0Ch, bit 24-31 */
2757 detect
= snd_cmipci_read(cm
, CM_REG_INT_HLDCLR
) & CM_CHIP_MASK2
;
2759 /* check reg 08h, bit 24-28 */
2760 detect
= snd_cmipci_read(cm
, CM_REG_CHFORMAT
) & CM_CHIP_MASK1
;
2763 cm
->chip_version
= 33;
2764 if (cm
->do_soft_ac3
)
2770 cm
->chip_version
= 37;
2774 cm
->chip_version
= 39;
2778 cm
->max_channels
= 2;
2780 if (detect
& CM_CHIP_039
) {
2781 cm
->chip_version
= 39;
2782 if (detect
& CM_CHIP_039_6CH
) /* 4 or 6 channels */
2783 cm
->max_channels
= 6;
2785 cm
->max_channels
= 4;
2786 } else if (detect
& CM_CHIP_8768
) {
2787 cm
->chip_version
= 68;
2788 cm
->max_channels
= 8;
2790 cm
->chip_version
= 55;
2791 cm
->max_channels
= 6;
2794 cm
->can_multi_ch
= 1;
2798 #ifdef SUPPORT_JOYSTICK
2799 static int __devinit
snd_cmipci_create_gameport(struct cmipci
*cm
, int dev
)
2801 static int ports
[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2802 struct gameport
*gp
;
2803 struct resource
*r
= NULL
;
2806 if (joystick_port
[dev
] == 0)
2809 if (joystick_port
[dev
] == 1) { /* auto-detect */
2810 for (i
= 0; ports
[i
]; i
++) {
2812 r
= request_region(io_port
, 1, "CMIPCI gameport");
2817 io_port
= joystick_port
[dev
];
2818 r
= request_region(io_port
, 1, "CMIPCI gameport");
2822 printk(KERN_WARNING
"cmipci: cannot reserve joystick ports\n");
2826 cm
->gameport
= gp
= gameport_allocate_port();
2828 printk(KERN_ERR
"cmipci: cannot allocate memory for gameport\n");
2829 release_and_free_resource(r
);
2832 gameport_set_name(gp
, "C-Media Gameport");
2833 gameport_set_phys(gp
, "pci%s/gameport0", pci_name(cm
->pci
));
2834 gameport_set_dev_parent(gp
, &cm
->pci
->dev
);
2836 gameport_set_port_data(gp
, r
);
2838 snd_cmipci_set_bit(cm
, CM_REG_FUNCTRL1
, CM_JYSTK_EN
);
2840 gameport_register_port(cm
->gameport
);
2845 static void snd_cmipci_free_gameport(struct cmipci
*cm
)
2848 struct resource
*r
= gameport_get_port_data(cm
->gameport
);
2850 gameport_unregister_port(cm
->gameport
);
2851 cm
->gameport
= NULL
;
2853 snd_cmipci_clear_bit(cm
, CM_REG_FUNCTRL1
, CM_JYSTK_EN
);
2854 release_and_free_resource(r
);
2858 static inline int snd_cmipci_create_gameport(struct cmipci
*cm
, int dev
) { return -ENOSYS
; }
2859 static inline void snd_cmipci_free_gameport(struct cmipci
*cm
) { }
2862 static int snd_cmipci_free(struct cmipci
*cm
)
2865 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL
, CM_FM_EN
);
2866 snd_cmipci_clear_bit(cm
, CM_REG_LEGACY_CTRL
, CM_ENSPDOUT
);
2867 snd_cmipci_write(cm
, CM_REG_INT_HLDCLR
, 0); /* disable ints */
2868 snd_cmipci_ch_reset(cm
, CM_CH_PLAY
);
2869 snd_cmipci_ch_reset(cm
, CM_CH_CAPT
);
2870 snd_cmipci_write(cm
, CM_REG_FUNCTRL0
, 0); /* disable channels */
2871 snd_cmipci_write(cm
, CM_REG_FUNCTRL1
, 0);
2874 snd_cmipci_mixer_write(cm
, 0, 0);
2876 synchronize_irq(cm
->irq
);
2878 free_irq(cm
->irq
, cm
);
2881 snd_cmipci_free_gameport(cm
);
2882 pci_release_regions(cm
->pci
);
2883 pci_disable_device(cm
->pci
);
2888 static int snd_cmipci_dev_free(struct snd_device
*device
)
2890 struct cmipci
*cm
= device
->device_data
;
2891 return snd_cmipci_free(cm
);
2894 static int __devinit
snd_cmipci_create_fm(struct cmipci
*cm
, long fm_port
)
2898 struct snd_opl3
*opl3
;
2904 if (cm
->chip_version
>= 39) {
2905 /* first try FM regs in PCI port range */
2906 iosynth
= cm
->iobase
+ CM_REG_FM_PCI
;
2907 err
= snd_opl3_create(cm
->card
, iosynth
, iosynth
+ 2,
2908 OPL3_HW_OPL3
, 1, &opl3
);
2913 /* then try legacy ports */
2914 val
= snd_cmipci_read(cm
, CM_REG_LEGACY_CTRL
) & ~CM_FMSEL_MASK
;
2917 case 0x3E8: val
|= CM_FMSEL_3E8
; break;
2918 case 0x3E0: val
|= CM_FMSEL_3E0
; break;
2919 case 0x3C8: val
|= CM_FMSEL_3C8
; break;
2920 case 0x388: val
|= CM_FMSEL_388
; break;
2924 snd_cmipci_write(cm
, CM_REG_LEGACY_CTRL
, val
);
2926 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_FM_EN
);
2928 if (snd_opl3_create(cm
->card
, iosynth
, iosynth
+ 2,
2929 OPL3_HW_OPL3
, 0, &opl3
) < 0) {
2930 printk(KERN_ERR
"cmipci: no OPL device at %#lx, "
2931 "skipping...\n", iosynth
);
2935 if ((err
= snd_opl3_hwdep_new(opl3
, 0, 1, NULL
)) < 0) {
2936 printk(KERN_ERR
"cmipci: cannot create OPL3 hwdep\n");
2942 snd_cmipci_clear_bit(cm
, CM_REG_LEGACY_CTRL
, CM_FMSEL_MASK
);
2943 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL
, CM_FM_EN
);
2947 static int __devinit
snd_cmipci_create(struct snd_card
*card
, struct pci_dev
*pci
,
2948 int dev
, struct cmipci
**rcmipci
)
2952 static struct snd_device_ops ops
= {
2953 .dev_free
= snd_cmipci_dev_free
,
2957 int integrated_midi
= 0;
2959 int pcm_index
, pcm_spdif_index
;
2960 static struct pci_device_id intel_82437vx
[] = {
2961 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82437VX
) },
2967 if ((err
= pci_enable_device(pci
)) < 0)
2970 cm
= kzalloc(sizeof(*cm
), GFP_KERNEL
);
2972 pci_disable_device(pci
);
2976 spin_lock_init(&cm
->reg_lock
);
2977 mutex_init(&cm
->open_mutex
);
2978 cm
->device
= pci
->device
;
2982 cm
->channel
[0].ch
= 0;
2983 cm
->channel
[1].ch
= 1;
2984 cm
->channel
[0].is_dac
= cm
->channel
[1].is_dac
= 1; /* dual DAC mode */
2986 if ((err
= pci_request_regions(pci
, card
->driver
)) < 0) {
2988 pci_disable_device(pci
);
2991 cm
->iobase
= pci_resource_start(pci
, 0);
2993 if (request_irq(pci
->irq
, snd_cmipci_interrupt
,
2994 IRQF_SHARED
, card
->driver
, cm
)) {
2995 snd_printk(KERN_ERR
"unable to grab IRQ %d\n", pci
->irq
);
2996 snd_cmipci_free(cm
);
3001 pci_set_master(cm
->pci
);
3004 * check chip version, max channels and capabilities
3007 cm
->chip_version
= 0;
3008 cm
->max_channels
= 2;
3009 cm
->do_soft_ac3
= soft_ac3
[dev
];
3011 if (pci
->device
!= PCI_DEVICE_ID_CMEDIA_CM8338A
&&
3012 pci
->device
!= PCI_DEVICE_ID_CMEDIA_CM8338B
)
3014 /* added -MCx suffix for chip supporting multi-channels */
3015 if (cm
->can_multi_ch
)
3016 sprintf(cm
->card
->driver
+ strlen(cm
->card
->driver
),
3017 "-MC%d", cm
->max_channels
);
3018 else if (cm
->can_ac3_sw
)
3019 strcpy(cm
->card
->driver
+ strlen(cm
->card
->driver
), "-SWIEC");
3021 cm
->dig_status
= SNDRV_PCM_DEFAULT_CON_SPDIF
;
3022 cm
->dig_pcm_status
= SNDRV_PCM_DEFAULT_CON_SPDIF
;
3025 cm
->ctrl
= CM_CHADC0
; /* default FUNCNTRL0 */
3027 cm
->ctrl
= CM_CHADC1
; /* default FUNCNTRL0 */
3030 /* initialize codec registers */
3031 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_RESET
);
3032 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL
, CM_RESET
);
3033 snd_cmipci_write(cm
, CM_REG_INT_HLDCLR
, 0); /* disable ints */
3034 snd_cmipci_ch_reset(cm
, CM_CH_PLAY
);
3035 snd_cmipci_ch_reset(cm
, CM_CH_CAPT
);
3036 snd_cmipci_write(cm
, CM_REG_FUNCTRL0
, 0); /* disable channels */
3037 snd_cmipci_write(cm
, CM_REG_FUNCTRL1
, 0);
3039 snd_cmipci_write(cm
, CM_REG_CHFORMAT
, 0);
3040 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_ENDBDAC
|CM_N4SPK3D
);
3042 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_XCHGDAC
);
3044 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL
, CM_XCHGDAC
);
3046 if (cm
->chip_version
) {
3047 snd_cmipci_write_b(cm
, CM_REG_EXT_MISC
, 0x20); /* magic */
3048 snd_cmipci_write_b(cm
, CM_REG_EXT_MISC
+ 1, 0x09); /* more magic */
3050 /* Set Bus Master Request */
3051 snd_cmipci_set_bit(cm
, CM_REG_FUNCTRL1
, CM_BREQ
);
3053 /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
3054 switch (pci
->device
) {
3055 case PCI_DEVICE_ID_CMEDIA_CM8738
:
3056 case PCI_DEVICE_ID_CMEDIA_CM8738B
:
3057 if (!pci_dev_present(intel_82437vx
))
3058 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_TXVX
);
3064 if (cm
->chip_version
< 68) {
3065 val
= pci
->device
< 0x110 ? 8338 : 8738;
3067 switch (snd_cmipci_read_b(cm
, CM_REG_INT_HLDCLR
+ 3) & 0x03) {
3075 switch ((pci
->subsystem_vendor
<< 16) |
3076 pci
->subsystem_device
) {
3091 sprintf(card
->shortname
, "C-Media CMI%d", val
);
3092 if (cm
->chip_version
< 68)
3093 sprintf(modelstr
, " (model %d)", cm
->chip_version
);
3096 sprintf(card
->longname
, "%s%s at %#lx, irq %i",
3097 card
->shortname
, modelstr
, cm
->iobase
, cm
->irq
);
3099 if ((err
= snd_device_new(card
, SNDRV_DEV_LOWLEVEL
, cm
, &ops
)) < 0) {
3100 snd_cmipci_free(cm
);
3104 if (cm
->chip_version
>= 39) {
3105 val
= snd_cmipci_read_b(cm
, CM_REG_MPU_PCI
+ 1);
3106 if (val
!= 0x00 && val
!= 0xff) {
3107 iomidi
= cm
->iobase
+ CM_REG_MPU_PCI
;
3108 integrated_midi
= 1;
3111 if (!integrated_midi
) {
3113 iomidi
= mpu_port
[dev
];
3115 case 0x320: val
= CM_VMPU_320
; break;
3116 case 0x310: val
= CM_VMPU_310
; break;
3117 case 0x300: val
= CM_VMPU_300
; break;
3118 case 0x330: val
= CM_VMPU_330
; break;
3123 snd_cmipci_write(cm
, CM_REG_LEGACY_CTRL
, val
);
3125 snd_cmipci_set_bit(cm
, CM_REG_FUNCTRL1
, CM_UART_EN
);
3126 if (inb(iomidi
+ 1) == 0xff) {
3127 snd_printk(KERN_ERR
"cannot enable MPU-401 port"
3128 " at %#lx\n", iomidi
);
3129 snd_cmipci_clear_bit(cm
, CM_REG_FUNCTRL1
,
3136 if (cm
->chip_version
< 68) {
3137 err
= snd_cmipci_create_fm(cm
, fm_port
[dev
]);
3143 snd_cmipci_mixer_write(cm
, 0, 0);
3145 snd_cmipci_proc_init(cm
);
3147 /* create pcm devices */
3148 pcm_index
= pcm_spdif_index
= 0;
3149 if ((err
= snd_cmipci_pcm_new(cm
, pcm_index
)) < 0)
3152 if ((err
= snd_cmipci_pcm2_new(cm
, pcm_index
)) < 0)
3155 if (cm
->can_ac3_hw
|| cm
->can_ac3_sw
) {
3156 pcm_spdif_index
= pcm_index
;
3157 if ((err
= snd_cmipci_pcm_spdif_new(cm
, pcm_index
)) < 0)
3161 /* create mixer interface & switches */
3162 if ((err
= snd_cmipci_mixer_new(cm
, pcm_spdif_index
)) < 0)
3166 if ((err
= snd_mpu401_uart_new(card
, 0, MPU401_HW_CMIPCI
,
3169 MPU401_INFO_INTEGRATED
: 0),
3170 cm
->irq
, 0, &cm
->rmidi
)) < 0) {
3171 printk(KERN_ERR
"cmipci: no UART401 device at 0x%lx\n", iomidi
);
3175 #ifdef USE_VAR48KRATE
3176 for (val
= 0; val
< ARRAY_SIZE(rates
); val
++)
3177 snd_cmipci_set_pll(cm
, rates
[val
], val
);
3180 * (Re-)Enable external switch spdo_48k
3182 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_SPDIF48K
|CM_SPDF_AC97
);
3183 #endif /* USE_VAR48KRATE */
3185 if (snd_cmipci_create_gameport(cm
, dev
) < 0)
3186 snd_cmipci_clear_bit(cm
, CM_REG_FUNCTRL1
, CM_JYSTK_EN
);
3188 snd_card_set_dev(card
, &pci
->dev
);
3197 MODULE_DEVICE_TABLE(pci
, snd_cmipci_ids
);
3199 static int __devinit
snd_cmipci_probe(struct pci_dev
*pci
,
3200 const struct pci_device_id
*pci_id
)
3203 struct snd_card
*card
;
3207 if (dev
>= SNDRV_CARDS
)
3209 if (! enable
[dev
]) {
3214 card
= snd_card_new(index
[dev
], id
[dev
], THIS_MODULE
, 0);
3218 switch (pci
->device
) {
3219 case PCI_DEVICE_ID_CMEDIA_CM8738
:
3220 case PCI_DEVICE_ID_CMEDIA_CM8738B
:
3221 strcpy(card
->driver
, "CMI8738");
3223 case PCI_DEVICE_ID_CMEDIA_CM8338A
:
3224 case PCI_DEVICE_ID_CMEDIA_CM8338B
:
3225 strcpy(card
->driver
, "CMI8338");
3228 strcpy(card
->driver
, "CMIPCI");
3232 if ((err
= snd_cmipci_create(card
, pci
, dev
, &cm
)) < 0) {
3233 snd_card_free(card
);
3236 card
->private_data
= cm
;
3238 if ((err
= snd_card_register(card
)) < 0) {
3239 snd_card_free(card
);
3242 pci_set_drvdata(pci
, card
);
3248 static void __devexit
snd_cmipci_remove(struct pci_dev
*pci
)
3250 snd_card_free(pci_get_drvdata(pci
));
3251 pci_set_drvdata(pci
, NULL
);
3259 static unsigned char saved_regs
[] = {
3260 CM_REG_FUNCTRL1
, CM_REG_CHFORMAT
, CM_REG_LEGACY_CTRL
, CM_REG_MISC_CTRL
,
3261 CM_REG_MIXER0
, CM_REG_MIXER1
, CM_REG_MIXER2
, CM_REG_MIXER3
, CM_REG_PLL
,
3262 CM_REG_CH0_FRAME1
, CM_REG_CH0_FRAME2
,
3263 CM_REG_CH1_FRAME1
, CM_REG_CH1_FRAME2
, CM_REG_EXT_MISC
,
3264 CM_REG_INT_STATUS
, CM_REG_INT_HLDCLR
, CM_REG_FUNCTRL0
,
3267 static unsigned char saved_mixers
[] = {
3268 SB_DSP4_MASTER_DEV
, SB_DSP4_MASTER_DEV
+ 1,
3269 SB_DSP4_PCM_DEV
, SB_DSP4_PCM_DEV
+ 1,
3270 SB_DSP4_SYNTH_DEV
, SB_DSP4_SYNTH_DEV
+ 1,
3271 SB_DSP4_CD_DEV
, SB_DSP4_CD_DEV
+ 1,
3272 SB_DSP4_LINE_DEV
, SB_DSP4_LINE_DEV
+ 1,
3273 SB_DSP4_MIC_DEV
, SB_DSP4_SPEAKER_DEV
,
3274 CM_REG_EXTENT_IND
, SB_DSP4_OUTPUT_SW
,
3275 SB_DSP4_INPUT_LEFT
, SB_DSP4_INPUT_RIGHT
,
3278 static int snd_cmipci_suspend(struct pci_dev
*pci
, pm_message_t state
)
3280 struct snd_card
*card
= pci_get_drvdata(pci
);
3281 struct cmipci
*cm
= card
->private_data
;
3284 snd_power_change_state(card
, SNDRV_CTL_POWER_D3hot
);
3286 snd_pcm_suspend_all(cm
->pcm
);
3287 snd_pcm_suspend_all(cm
->pcm2
);
3288 snd_pcm_suspend_all(cm
->pcm_spdif
);
3290 /* save registers */
3291 for (i
= 0; i
< ARRAY_SIZE(saved_regs
); i
++)
3292 cm
->saved_regs
[i
] = snd_cmipci_read(cm
, saved_regs
[i
]);
3293 for (i
= 0; i
< ARRAY_SIZE(saved_mixers
); i
++)
3294 cm
->saved_mixers
[i
] = snd_cmipci_mixer_read(cm
, saved_mixers
[i
]);
3297 snd_cmipci_write(cm
, CM_REG_INT_HLDCLR
, 0);
3299 pci_disable_device(pci
);
3300 pci_save_state(pci
);
3301 pci_set_power_state(pci
, pci_choose_state(pci
, state
));
3305 static int snd_cmipci_resume(struct pci_dev
*pci
)
3307 struct snd_card
*card
= pci_get_drvdata(pci
);
3308 struct cmipci
*cm
= card
->private_data
;
3311 pci_set_power_state(pci
, PCI_D0
);
3312 pci_restore_state(pci
);
3313 if (pci_enable_device(pci
) < 0) {
3314 printk(KERN_ERR
"cmipci: pci_enable_device failed, "
3315 "disabling device\n");
3316 snd_card_disconnect(card
);
3319 pci_set_master(pci
);
3321 /* reset / initialize to a sane state */
3322 snd_cmipci_write(cm
, CM_REG_INT_HLDCLR
, 0);
3323 snd_cmipci_ch_reset(cm
, CM_CH_PLAY
);
3324 snd_cmipci_ch_reset(cm
, CM_CH_CAPT
);
3325 snd_cmipci_mixer_write(cm
, 0, 0);
3327 /* restore registers */
3328 for (i
= 0; i
< ARRAY_SIZE(saved_regs
); i
++)
3329 snd_cmipci_write(cm
, saved_regs
[i
], cm
->saved_regs
[i
]);
3330 for (i
= 0; i
< ARRAY_SIZE(saved_mixers
); i
++)
3331 snd_cmipci_mixer_write(cm
, saved_mixers
[i
], cm
->saved_mixers
[i
]);
3333 snd_power_change_state(card
, SNDRV_CTL_POWER_D0
);
3336 #endif /* CONFIG_PM */
3338 static struct pci_driver driver
= {
3339 .name
= "C-Media PCI",
3340 .id_table
= snd_cmipci_ids
,
3341 .probe
= snd_cmipci_probe
,
3342 .remove
= __devexit_p(snd_cmipci_remove
),
3344 .suspend
= snd_cmipci_suspend
,
3345 .resume
= snd_cmipci_resume
,
3349 static int __init
alsa_card_cmipci_init(void)
3351 return pci_register_driver(&driver
);
3354 static void __exit
alsa_card_cmipci_exit(void)
3356 pci_unregister_driver(&driver
);
3359 module_init(alsa_card_cmipci_init
)
3360 module_exit(alsa_card_cmipci_exit
)