2 * Prototypes, etc. for the Freescale MPC52xx embedded cpu chips
3 * May need to be cleaned as the port goes on ...
5 * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>
6 * Copyright (C) 2003 MontaVista, Software, Inc.
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 #ifndef __ASM_POWERPC_MPC52xx_H__
14 #define __ASM_POWERPC_MPC52xx_H__
17 #include <asm/types.h>
19 #endif /* __ASSEMBLY__ */
21 #include <linux/suspend.h>
23 /* Variants of the 5200(B) */
24 #define MPC5200_SVR 0x80110010
25 #define MPC5200_SVR_MASK 0xfffffff0
26 #define MPC5200B_SVR 0x80110020
27 #define MPC5200B_SVR_MASK 0xfffffff0
29 /* ======================================================================== */
30 /* Structures mapping of some unit register set */
31 /* ======================================================================== */
35 /* Memory Mapping Control */
36 struct mpc52xx_mmap_ctl
{
37 u32 mbar
; /* MMAP_CTRL + 0x00 */
39 u32 cs0_start
; /* MMAP_CTRL + 0x04 */
40 u32 cs0_stop
; /* MMAP_CTRL + 0x08 */
41 u32 cs1_start
; /* MMAP_CTRL + 0x0c */
42 u32 cs1_stop
; /* MMAP_CTRL + 0x10 */
43 u32 cs2_start
; /* MMAP_CTRL + 0x14 */
44 u32 cs2_stop
; /* MMAP_CTRL + 0x18 */
45 u32 cs3_start
; /* MMAP_CTRL + 0x1c */
46 u32 cs3_stop
; /* MMAP_CTRL + 0x20 */
47 u32 cs4_start
; /* MMAP_CTRL + 0x24 */
48 u32 cs4_stop
; /* MMAP_CTRL + 0x28 */
49 u32 cs5_start
; /* MMAP_CTRL + 0x2c */
50 u32 cs5_stop
; /* MMAP_CTRL + 0x30 */
52 u32 sdram0
; /* MMAP_CTRL + 0x34 */
53 u32 sdram1
; /* MMAP_CTRL + 0X38 */
55 u32 reserved
[4]; /* MMAP_CTRL + 0x3c .. 0x48 */
57 u32 boot_start
; /* MMAP_CTRL + 0x4c */
58 u32 boot_stop
; /* MMAP_CTRL + 0x50 */
60 u32 ipbi_ws_ctrl
; /* MMAP_CTRL + 0x54 */
62 u32 cs6_start
; /* MMAP_CTRL + 0x58 */
63 u32 cs6_stop
; /* MMAP_CTRL + 0x5c */
64 u32 cs7_start
; /* MMAP_CTRL + 0x60 */
65 u32 cs7_stop
; /* MMAP_CTRL + 0x64 */
69 struct mpc52xx_sdram
{
70 u32 mode
; /* SDRAM + 0x00 */
71 u32 ctrl
; /* SDRAM + 0x04 */
72 u32 config1
; /* SDRAM + 0x08 */
73 u32 config2
; /* SDRAM + 0x0c */
78 u32 taskBar
; /* SDMA + 0x00 */
79 u32 currentPointer
; /* SDMA + 0x04 */
80 u32 endPointer
; /* SDMA + 0x08 */
81 u32 variablePointer
; /* SDMA + 0x0c */
83 u8 IntVect1
; /* SDMA + 0x10 */
84 u8 IntVect2
; /* SDMA + 0x11 */
85 u16 PtdCntrl
; /* SDMA + 0x12 */
87 u32 IntPend
; /* SDMA + 0x14 */
88 u32 IntMask
; /* SDMA + 0x18 */
90 u16 tcr
[16]; /* SDMA + 0x1c .. 0x3a */
92 u8 ipr
[32]; /* SDMA + 0x3c .. 0x5b */
94 u32 cReqSelect
; /* SDMA + 0x5c */
95 u32 task_size0
; /* SDMA + 0x60 */
96 u32 task_size1
; /* SDMA + 0x64 */
97 u32 MDEDebug
; /* SDMA + 0x68 */
98 u32 ADSDebug
; /* SDMA + 0x6c */
99 u32 Value1
; /* SDMA + 0x70 */
100 u32 Value2
; /* SDMA + 0x74 */
101 u32 Control
; /* SDMA + 0x78 */
102 u32 Status
; /* SDMA + 0x7c */
103 u32 PTDDebug
; /* SDMA + 0x80 */
108 u32 mode
; /* GPTx + 0x00 */
109 u32 count
; /* GPTx + 0x04 */
110 u32 pwm
; /* GPTx + 0x08 */
111 u32 status
; /* GPTx + 0X0c */
115 struct mpc52xx_gpio
{
116 u32 port_config
; /* GPIO + 0x00 */
117 u32 simple_gpioe
; /* GPIO + 0x04 */
118 u32 simple_ode
; /* GPIO + 0x08 */
119 u32 simple_ddr
; /* GPIO + 0x0c */
120 u32 simple_dvo
; /* GPIO + 0x10 */
121 u32 simple_ival
; /* GPIO + 0x14 */
122 u8 outo_gpioe
; /* GPIO + 0x18 */
123 u8 reserved1
[3]; /* GPIO + 0x19 */
124 u8 outo_dvo
; /* GPIO + 0x1c */
125 u8 reserved2
[3]; /* GPIO + 0x1d */
126 u8 sint_gpioe
; /* GPIO + 0x20 */
127 u8 reserved3
[3]; /* GPIO + 0x21 */
128 u8 sint_ode
; /* GPIO + 0x24 */
129 u8 reserved4
[3]; /* GPIO + 0x25 */
130 u8 sint_ddr
; /* GPIO + 0x28 */
131 u8 reserved5
[3]; /* GPIO + 0x29 */
132 u8 sint_dvo
; /* GPIO + 0x2c */
133 u8 reserved6
[3]; /* GPIO + 0x2d */
134 u8 sint_inten
; /* GPIO + 0x30 */
135 u8 reserved7
[3]; /* GPIO + 0x31 */
136 u16 sint_itype
; /* GPIO + 0x34 */
137 u16 reserved8
; /* GPIO + 0x36 */
138 u8 gpio_control
; /* GPIO + 0x38 */
139 u8 reserved9
[3]; /* GPIO + 0x39 */
140 u8 sint_istat
; /* GPIO + 0x3c */
141 u8 sint_ival
; /* GPIO + 0x3d */
142 u8 bus_errs
; /* GPIO + 0x3e */
143 u8 reserved10
; /* GPIO + 0x3f */
146 #define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD 4
147 #define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD 5
148 #define MPC52xx_GPIO_PCI_DIS (1<<15)
150 /* GPIO with WakeUp*/
151 struct mpc52xx_gpio_wkup
{
152 u8 wkup_gpioe
; /* GPIO_WKUP + 0x00 */
153 u8 reserved1
[3]; /* GPIO_WKUP + 0x03 */
154 u8 wkup_ode
; /* GPIO_WKUP + 0x04 */
155 u8 reserved2
[3]; /* GPIO_WKUP + 0x05 */
156 u8 wkup_ddr
; /* GPIO_WKUP + 0x08 */
157 u8 reserved3
[3]; /* GPIO_WKUP + 0x09 */
158 u8 wkup_dvo
; /* GPIO_WKUP + 0x0C */
159 u8 reserved4
[3]; /* GPIO_WKUP + 0x0D */
160 u8 wkup_inten
; /* GPIO_WKUP + 0x10 */
161 u8 reserved5
[3]; /* GPIO_WKUP + 0x11 */
162 u8 wkup_iinten
; /* GPIO_WKUP + 0x14 */
163 u8 reserved6
[3]; /* GPIO_WKUP + 0x15 */
164 u16 wkup_itype
; /* GPIO_WKUP + 0x18 */
165 u8 reserved7
[2]; /* GPIO_WKUP + 0x1A */
166 u8 wkup_maste
; /* GPIO_WKUP + 0x1C */
167 u8 reserved8
[3]; /* GPIO_WKUP + 0x1D */
168 u8 wkup_ival
; /* GPIO_WKUP + 0x20 */
169 u8 reserved9
[3]; /* GPIO_WKUP + 0x21 */
170 u8 wkup_istat
; /* GPIO_WKUP + 0x24 */
171 u8 reserved10
[3]; /* GPIO_WKUP + 0x25 */
174 /* XLB Bus control */
177 u32 config
; /* XLB + 0x40 */
178 u32 version
; /* XLB + 0x44 */
179 u32 status
; /* XLB + 0x48 */
180 u32 int_enable
; /* XLB + 0x4c */
181 u32 addr_capture
; /* XLB + 0x50 */
182 u32 bus_sig_capture
; /* XLB + 0x54 */
183 u32 addr_timeout
; /* XLB + 0x58 */
184 u32 data_timeout
; /* XLB + 0x5c */
185 u32 bus_act_timeout
; /* XLB + 0x60 */
186 u32 master_pri_enable
; /* XLB + 0x64 */
187 u32 master_priority
; /* XLB + 0x68 */
188 u32 base_address
; /* XLB + 0x6c */
189 u32 snoop_window
; /* XLB + 0x70 */
192 #define MPC52xx_XLB_CFG_PLDIS (1 << 31)
193 #define MPC52xx_XLB_CFG_SNOOP (1 << 15)
195 /* Clock Distribution control */
197 u32 jtag_id
; /* CDM + 0x00 reg0 read only */
198 u32 rstcfg
; /* CDM + 0x04 reg1 read only */
199 u32 breadcrumb
; /* CDM + 0x08 reg2 */
201 u8 mem_clk_sel
; /* CDM + 0x0c reg3 byte0 */
202 u8 xlb_clk_sel
; /* CDM + 0x0d reg3 byte1 read only */
203 u8 ipb_clk_sel
; /* CDM + 0x0e reg3 byte2 */
204 u8 pci_clk_sel
; /* CDM + 0x0f reg3 byte3 */
206 u8 ext_48mhz_en
; /* CDM + 0x10 reg4 byte0 */
207 u8 fd_enable
; /* CDM + 0x11 reg4 byte1 */
208 u16 fd_counters
; /* CDM + 0x12 reg4 byte2,3 */
210 u32 clk_enables
; /* CDM + 0x14 reg5 */
212 u8 osc_disable
; /* CDM + 0x18 reg6 byte0 */
213 u8 reserved0
[3]; /* CDM + 0x19 reg6 byte1,2,3 */
215 u8 ccs_sleep_enable
; /* CDM + 0x1c reg7 byte0 */
216 u8 osc_sleep_enable
; /* CDM + 0x1d reg7 byte1 */
217 u8 reserved1
; /* CDM + 0x1e reg7 byte2 */
218 u8 ccs_qreq_test
; /* CDM + 0x1f reg7 byte3 */
220 u8 soft_reset
; /* CDM + 0x20 u8 byte0 */
221 u8 no_ckstp
; /* CDM + 0x21 u8 byte0 */
222 u8 reserved2
[2]; /* CDM + 0x22 u8 byte1,2,3 */
224 u8 pll_lock
; /* CDM + 0x24 reg9 byte0 */
225 u8 pll_looselock
; /* CDM + 0x25 reg9 byte1 */
226 u8 pll_sm_lockwin
; /* CDM + 0x26 reg9 byte2 */
227 u8 reserved3
; /* CDM + 0x27 reg9 byte3 */
229 u16 reserved4
; /* CDM + 0x28 reg10 byte0,1 */
230 u16 mclken_div_psc1
; /* CDM + 0x2a reg10 byte2,3 */
232 u16 reserved5
; /* CDM + 0x2c reg11 byte0,1 */
233 u16 mclken_div_psc2
; /* CDM + 0x2e reg11 byte2,3 */
235 u16 reserved6
; /* CDM + 0x30 reg12 byte0,1 */
236 u16 mclken_div_psc3
; /* CDM + 0x32 reg12 byte2,3 */
238 u16 reserved7
; /* CDM + 0x34 reg13 byte0,1 */
239 u16 mclken_div_psc6
; /* CDM + 0x36 reg13 byte2,3 */
242 #endif /* __ASSEMBLY__ */
245 /* ========================================================================= */
246 /* Prototypes for MPC52xx sysdev */
247 /* ========================================================================= */
251 extern void __iomem
* mpc52xx_find_and_map(const char *);
252 extern void __iomem
* mpc52xx_find_and_map_path(const char *path
);
253 extern unsigned int mpc52xx_find_ipb_freq(struct device_node
*node
);
254 extern void mpc5200_setup_xlb_arbiter(void);
255 extern void mpc52xx_declare_of_platform_devices(void);
257 extern void mpc52xx_init_irq(void);
258 extern unsigned int mpc52xx_get_irq(void);
260 extern int __init
mpc52xx_add_bridge(struct device_node
*node
);
262 extern void __init
mpc52xx_map_wdt(void);
263 extern void mpc52xx_restart(char *cmd
);
265 #endif /* __ASSEMBLY__ */
268 struct mpc52xx_suspend
{
269 void (*board_suspend_prepare
)(void __iomem
*mbar
);
270 void (*board_resume_finish
)(void __iomem
*mbar
);
273 extern struct mpc52xx_suspend mpc52xx_suspend
;
274 extern int __init
mpc52xx_pm_init(void);
275 extern int mpc52xx_set_wakeup_gpio(u8 pin
, u8 level
);
277 #ifdef CONFIG_PPC_LITE5200
278 extern int __init
lite5200_pm_init(void);
280 /* lite5200 calls mpc5200 suspend functions, so here they are */
281 extern int mpc52xx_pm_prepare(void);
282 extern int mpc52xx_pm_enter(suspend_state_t
);
283 extern void mpc52xx_pm_finish(void);
284 extern char saved_sram
[0x4000]; /* reuse buffer from mpc52xx suspend */
286 #endif /* CONFIG_PM */
288 #endif /* __ASM_POWERPC_MPC52xx_H__ */