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[PATCH] w1: Fixed 64bit compilation warning.
[linux-2.6/verdex.git] / drivers / net / irda / smsc-ircc2.c
blobdd89bda1f1315914349fe692029108b30dd6262a
1 /*********************************************************************
2 * $Id: smsc-ircc2.c,v 1.19.2.5 2002/10/27 11:34:26 dip Exp $
3 *
4 * Description: Driver for the SMC Infrared Communications Controller
5 * Status: Experimental.
6 * Author: Daniele Peri (peri@csai.unipa.it)
7 * Created at:
8 * Modified at:
9 * Modified by:
10 *
11 * Copyright (c) 2002 Daniele Peri
12 * All Rights Reserved.
13 * Copyright (c) 2002 Jean Tourrilhes
14 *
15 *
16 * Based on smc-ircc.c:
17 *
18 * Copyright (c) 2001 Stefani Seibold
19 * Copyright (c) 1999-2001 Dag Brattli
20 * Copyright (c) 1998-1999 Thomas Davis,
21 *
22 * and irport.c:
23 *
24 * Copyright (c) 1997, 1998, 1999-2000 Dag Brattli, All Rights Reserved.
25 *
26 *
27 * This program is free software; you can redistribute it and/or
28 * modify it under the terms of the GNU General Public License as
29 * published by the Free Software Foundation; either version 2 of
30 * the License, or (at your option) any later version.
31 *
32 * This program is distributed in the hope that it will be useful,
33 * but WITHOUT ANY WARRANTY; without even the implied warranty of
34 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
35 * GNU General Public License for more details.
36 *
37 * You should have received a copy of the GNU General Public License
38 * along with this program; if not, write to the Free Software
39 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
40 * MA 02111-1307 USA
41 *
42 ********************************************************************/
43
44 #include <linux/module.h>
45 #include <linux/kernel.h>
46 #include <linux/types.h>
47 #include <linux/skbuff.h>
48 #include <linux/netdevice.h>
49 #include <linux/ioport.h>
50 #include <linux/delay.h>
51 #include <linux/slab.h>
52 #include <linux/init.h>
53 #include <linux/rtnetlink.h>
54 #include <linux/serial_reg.h>
55 #include <linux/dma-mapping.h>
56
57 #include <asm/io.h>
58 #include <asm/dma.h>
59 #include <asm/byteorder.h>
60
61 #include <linux/spinlock.h>
62 #include <linux/pm.h>
63
64 #include <net/irda/wrapper.h>
65 #include <net/irda/irda.h>
66 #include <net/irda/irda_device.h>
67
68 #include "smsc-ircc2.h"
69 #include "smsc-sio.h"
70
71
72 MODULE_AUTHOR("Daniele Peri <peri@csai.unipa.it>");
73 MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver");
74 MODULE_LICENSE("GPL");
75
76 static int ircc_dma = 255;
77 module_param(ircc_dma, int, 0);
78 MODULE_PARM_DESC(ircc_dma, "DMA channel");
79
80 static int ircc_irq = 255;
81 module_param(ircc_irq, int, 0);
82 MODULE_PARM_DESC(ircc_irq, "IRQ line");
83
84 static int ircc_fir;
85 module_param(ircc_fir, int, 0);
86 MODULE_PARM_DESC(ircc_fir, "FIR Base Address");
87
88 static int ircc_sir;
89 module_param(ircc_sir, int, 0);
90 MODULE_PARM_DESC(ircc_sir, "SIR Base Address");
91
92 static int ircc_cfg;
93 module_param(ircc_cfg, int, 0);
94 MODULE_PARM_DESC(ircc_cfg, "Configuration register base address");
95
96 static int ircc_transceiver;
97 module_param(ircc_transceiver, int, 0);
98 MODULE_PARM_DESC(ircc_transceiver, "Transceiver type");
99
100 /* Types */
101
102 struct smsc_transceiver {
103 char *name;
104 void (*set_for_speed)(int fir_base, u32 speed);
105 int (*probe)(int fir_base);
106 };
107
108 struct smsc_chip {
109 char *name;
110 #if 0
111 u8 type;
112 #endif
113 u16 flags;
114 u8 devid;
115 u8 rev;
116 };
117
118 struct smsc_chip_address {
119 unsigned int cfg_base;
120 unsigned int type;
121 };
122
123 /* Private data for each instance */
124 struct smsc_ircc_cb {
125 struct net_device *netdev; /* Yes! we are some kind of netdevice */
126 struct net_device_stats stats;
127 struct irlap_cb *irlap; /* The link layer we are binded to */
128
129 chipio_t io; /* IrDA controller information */
130 iobuff_t tx_buff; /* Transmit buffer */
131 iobuff_t rx_buff; /* Receive buffer */
132 dma_addr_t tx_buff_dma;
133 dma_addr_t rx_buff_dma;
134
135 struct qos_info qos; /* QoS capabilities for this device */
136
137 spinlock_t lock; /* For serializing operations */
138
139 __u32 new_speed;
140 __u32 flags; /* Interface flags */
141
142 int tx_buff_offsets[10]; /* Offsets between frames in tx_buff */
143 int tx_len; /* Number of frames in tx_buff */
144
145 int transceiver;
146 struct platform_device *pldev;
147 };
148
149 /* Constants */
150
151 #define SMSC_IRCC2_DRIVER_NAME "smsc-ircc2"
152
153 #define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED 9600
154 #define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER 1
155 #define SMSC_IRCC2_C_NET_TIMEOUT 0
156 #define SMSC_IRCC2_C_SIR_STOP 0
157
158 static const char *driver_name = SMSC_IRCC2_DRIVER_NAME;
159
160 /* Prototypes */
161
162 static int smsc_ircc_open(unsigned int firbase, unsigned int sirbase, u8 dma, u8 irq);
163 static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base);
164 static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq);
165 static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self);
166 static void smsc_ircc_init_chip(struct smsc_ircc_cb *self);
167 static int __exit smsc_ircc_close(struct smsc_ircc_cb *self);
168 static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self);
169 static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self);
170 static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self);
171 static int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev);
172 static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev);
173 static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs);
174 static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self);
175 static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed);
176 static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, u32 speed);
177 static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id, struct pt_regs *regs);
178 static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev);
179 static void smsc_ircc_sir_start(struct smsc_ircc_cb *self);
180 #if SMSC_IRCC2_C_SIR_STOP
181 static void smsc_ircc_sir_stop(struct smsc_ircc_cb *self);
182 #endif
183 static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self);
184 static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
185 static int smsc_ircc_net_open(struct net_device *dev);
186 static int smsc_ircc_net_close(struct net_device *dev);
187 static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
188 #if SMSC_IRCC2_C_NET_TIMEOUT
189 static void smsc_ircc_timeout(struct net_device *dev);
190 #endif
191 static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev);
192 static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self);
193 static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self);
194 static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed);
195 static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self);
196
197 /* Probing */
198 static int __init smsc_ircc_look_for_chips(void);
199 static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type);
200 static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
201 static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
202 static int __init smsc_superio_fdc(unsigned short cfg_base);
203 static int __init smsc_superio_lpc(unsigned short cfg_base);
204
205 /* Transceivers specific functions */
206
207 static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed);
208 static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base);
209 static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed);
210 static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base);
211 static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed);
212 static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base);
213
214 /* Power Management */
215
216 static int smsc_ircc_suspend(struct device *dev, pm_message_t state, u32 level);
217 static int smsc_ircc_resume(struct device *dev, u32 level);
218
219 static struct device_driver smsc_ircc_driver = {
220 .name = SMSC_IRCC2_DRIVER_NAME,
221 .bus = &platform_bus_type,
222 .suspend = smsc_ircc_suspend,
223 .resume = smsc_ircc_resume,
224 };
225
226 /* Transceivers for SMSC-ircc */
227
228 static struct smsc_transceiver smsc_transceivers[] =
229 {
230 { "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800, smsc_ircc_probe_transceiver_toshiba_sat1800 },
231 { "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select },
232 { "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc, smsc_ircc_probe_transceiver_smsc_ircc_atc },
233 { NULL, NULL }
234 };
235 #define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (ARRAY_SIZE(smsc_transceivers) - 1)
236
237 /* SMC SuperIO chipsets definitions */
238
239 #define KEY55_1 0 /* SuperIO Configuration mode with Key <0x55> */
240 #define KEY55_2 1 /* SuperIO Configuration mode with Key <0x55,0x55> */
241 #define NoIRDA 2 /* SuperIO Chip has no IRDA Port */
242 #define SIR 0 /* SuperIO Chip has only slow IRDA */
243 #define FIR 4 /* SuperIO Chip has fast IRDA */
244 #define SERx4 8 /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */
245
246 static struct smsc_chip __initdata fdc_chips_flat[] =
247 {
248 /* Base address 0x3f0 or 0x370 */
249 { "37C44", KEY55_1|NoIRDA, 0x00, 0x00 }, /* This chip cannot be detected */
250 { "37C665GT", KEY55_2|NoIRDA, 0x65, 0x01 },
251 { "37C665GT", KEY55_2|NoIRDA, 0x66, 0x01 },
252 { "37C669", KEY55_2|SIR|SERx4, 0x03, 0x02 },
253 { "37C669", KEY55_2|SIR|SERx4, 0x04, 0x02 }, /* ID? */
254 { "37C78", KEY55_2|NoIRDA, 0x78, 0x00 },
255 { "37N769", KEY55_1|FIR|SERx4, 0x28, 0x00 },
256 { "37N869", KEY55_1|FIR|SERx4, 0x29, 0x00 },
257 { NULL }
258 };
259
260 static struct smsc_chip __initdata fdc_chips_paged[] =
261 {
262 /* Base address 0x3f0 or 0x370 */
263 { "37B72X", KEY55_1|SIR|SERx4, 0x4c, 0x00 },
264 { "37B77X", KEY55_1|SIR|SERx4, 0x43, 0x00 },
265 { "37B78X", KEY55_1|SIR|SERx4, 0x44, 0x00 },
266 { "37B80X", KEY55_1|SIR|SERx4, 0x42, 0x00 },
267 { "37C67X", KEY55_1|FIR|SERx4, 0x40, 0x00 },
268 { "37C93X", KEY55_2|SIR|SERx4, 0x02, 0x01 },
269 { "37C93XAPM", KEY55_1|SIR|SERx4, 0x30, 0x01 },
270 { "37C93XFR", KEY55_2|FIR|SERx4, 0x03, 0x01 },
271 { "37M707", KEY55_1|SIR|SERx4, 0x42, 0x00 },
272 { "37M81X", KEY55_1|SIR|SERx4, 0x4d, 0x00 },
273 { "37N958FR", KEY55_1|FIR|SERx4, 0x09, 0x04 },
274 { "37N971", KEY55_1|FIR|SERx4, 0x0a, 0x00 },
275 { "37N972", KEY55_1|FIR|SERx4, 0x0b, 0x00 },
276 { NULL }
277 };
278
279 static struct smsc_chip __initdata lpc_chips_flat[] =
280 {
281 /* Base address 0x2E or 0x4E */
282 { "47N227", KEY55_1|FIR|SERx4, 0x5a, 0x00 },
283 { "47N267", KEY55_1|FIR|SERx4, 0x5e, 0x00 },
284 { NULL }
285 };
286
287 static struct smsc_chip __initdata lpc_chips_paged[] =
288 {
289 /* Base address 0x2E or 0x4E */
290 { "47B27X", KEY55_1|SIR|SERx4, 0x51, 0x00 },
291 { "47B37X", KEY55_1|SIR|SERx4, 0x52, 0x00 },
292 { "47M10X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
293 { "47M120", KEY55_1|NoIRDA|SERx4, 0x5c, 0x00 },
294 { "47M13X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
295 { "47M14X", KEY55_1|SIR|SERx4, 0x5f, 0x00 },
296 { "47N252", KEY55_1|FIR|SERx4, 0x0e, 0x00 },
297 { "47S42X", KEY55_1|SIR|SERx4, 0x57, 0x00 },
298 { NULL }
299 };
300
301 #define SMSCSIO_TYPE_FDC 1
302 #define SMSCSIO_TYPE_LPC 2
303 #define SMSCSIO_TYPE_FLAT 4
304 #define SMSCSIO_TYPE_PAGED 8
305
306 static struct smsc_chip_address __initdata possible_addresses[] =
307 {
308 { 0x3f0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
309 { 0x370, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
310 { 0xe0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
311 { 0x2e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
312 { 0x4e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
313 { 0, 0 }
314 };
315
316 /* Globals */
317
318 static struct smsc_ircc_cb *dev_self[] = { NULL, NULL };
319 static unsigned short dev_count;
320
321 static inline void register_bank(int iobase, int bank)
322 {
323 outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)),
324 iobase + IRCC_MASTER);
325 }
326
327
328 /*******************************************************************************
329 *
330 *
331 * SMSC-ircc stuff
332 *
333 *
334 *******************************************************************************/
335
336 /*
337 * Function smsc_ircc_init ()
338 *
339 * Initialize chip. Just try to find out how many chips we are dealing with
340 * and where they are
341 */
342 static int __init smsc_ircc_init(void)
343 {
344 int ret;
345
346 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
347
348 ret = driver_register(&smsc_ircc_driver);
349 if (ret) {
350 IRDA_ERROR("%s, Can't register driver!\n", driver_name);
351 return ret;
352 }
353
354 dev_count = 0;
355
356 if (ircc_fir > 0 && ircc_sir > 0) {
357 IRDA_MESSAGE(" Overriding FIR address 0x%04x\n", ircc_fir);
358 IRDA_MESSAGE(" Overriding SIR address 0x%04x\n", ircc_sir);
359
360 if (smsc_ircc_open(ircc_fir, ircc_sir, ircc_dma, ircc_irq))
361 ret = -ENODEV;
362 } else {
363 ret = -ENODEV;
364
365 /* try user provided configuration register base address */
366 if (ircc_cfg > 0) {
367 IRDA_MESSAGE(" Overriding configuration address "
368 "0x%04x\n", ircc_cfg);
369 if (!smsc_superio_fdc(ircc_cfg))
370 ret = 0;
371 if (!smsc_superio_lpc(ircc_cfg))
372 ret = 0;
373 }
374
375 if (smsc_ircc_look_for_chips() > 0)
376 ret = 0;
377 }
378
379 if (ret)
380 driver_unregister(&smsc_ircc_driver);
381
382 return ret;
383 }
384
385 /*
386 * Function smsc_ircc_open (firbase, sirbase, dma, irq)
387 *
388 * Try to open driver instance
389 *
390 */
391 static int __init smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq)
392 {
393 struct smsc_ircc_cb *self;
394 struct net_device *dev;
395 int err;
396
397 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
398
399 err = smsc_ircc_present(fir_base, sir_base);
400 if (err)
401 goto err_out;
402
403 err = -ENOMEM;
404 if (dev_count >= ARRAY_SIZE(dev_self)) {
405 IRDA_WARNING("%s(), too many devices!\n", __FUNCTION__);
406 goto err_out1;
407 }
408
409 /*
410 * Allocate new instance of the driver
411 */
412 dev = alloc_irdadev(sizeof(struct smsc_ircc_cb));
413 if (!dev) {
414 IRDA_WARNING("%s() can't allocate net device\n", __FUNCTION__);
415 goto err_out1;
416 }
417
418 SET_MODULE_OWNER(dev);
419
420 dev->hard_start_xmit = smsc_ircc_hard_xmit_sir;
421 #if SMSC_IRCC2_C_NET_TIMEOUT
422 dev->tx_timeout = smsc_ircc_timeout;
423 dev->watchdog_timeo = HZ * 2; /* Allow enough time for speed change */
424 #endif
425 dev->open = smsc_ircc_net_open;
426 dev->stop = smsc_ircc_net_close;
427 dev->do_ioctl = smsc_ircc_net_ioctl;
428 dev->get_stats = smsc_ircc_net_get_stats;
429
430 self = netdev_priv(dev);
431 self->netdev = dev;
432
433 /* Make ifconfig display some details */
434 dev->base_addr = self->io.fir_base = fir_base;
435 dev->irq = self->io.irq = irq;
436
437 /* Need to store self somewhere */
438 dev_self[dev_count] = self;
439 spin_lock_init(&self->lock);
440
441 self->rx_buff.truesize = SMSC_IRCC2_RX_BUFF_TRUESIZE;
442 self->tx_buff.truesize = SMSC_IRCC2_TX_BUFF_TRUESIZE;
443
444 self->rx_buff.head =
445 dma_alloc_coherent(NULL, self->rx_buff.truesize,
446 &self->rx_buff_dma, GFP_KERNEL);
447 if (self->rx_buff.head == NULL) {
448 IRDA_ERROR("%s, Can't allocate memory for receive buffer!\n",
449 driver_name);
450 goto err_out2;
451 }
452
453 self->tx_buff.head =
454 dma_alloc_coherent(NULL, self->tx_buff.truesize,
455 &self->tx_buff_dma, GFP_KERNEL);
456 if (self->tx_buff.head == NULL) {
457 IRDA_ERROR("%s, Can't allocate memory for transmit buffer!\n",
458 driver_name);
459 goto err_out3;
460 }
461
462 memset(self->rx_buff.head, 0, self->rx_buff.truesize);
463 memset(self->tx_buff.head, 0, self->tx_buff.truesize);
464
465 self->rx_buff.in_frame = FALSE;
466 self->rx_buff.state = OUTSIDE_FRAME;
467 self->tx_buff.data = self->tx_buff.head;
468 self->rx_buff.data = self->rx_buff.head;
469
470 smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq);
471 smsc_ircc_setup_qos(self);
472 smsc_ircc_init_chip(self);
473
474 if (ircc_transceiver > 0 &&
475 ircc_transceiver < SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS)
476 self->transceiver = ircc_transceiver;
477 else
478 smsc_ircc_probe_transceiver(self);
479
480 err = register_netdev(self->netdev);
481 if (err) {
482 IRDA_ERROR("%s, Network device registration failed!\n",
483 driver_name);
484 goto err_out4;
485 }
486
487 self->pldev = platform_device_register_simple(SMSC_IRCC2_DRIVER_NAME,
488 dev_count, NULL, 0);
489 if (IS_ERR(self->pldev)) {
490 err = PTR_ERR(self->pldev);
491 goto err_out5;
492 }
493 dev_set_drvdata(&self->pldev->dev, self);
494
495 IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name);
496 dev_count++;
497
498 return 0;
499
500 err_out5:
501 unregister_netdev(self->netdev);
502
503 err_out4:
504 dma_free_coherent(NULL, self->tx_buff.truesize,
505 self->tx_buff.head, self->tx_buff_dma);
506 err_out3:
507 dma_free_coherent(NULL, self->rx_buff.truesize,
508 self->rx_buff.head, self->rx_buff_dma);
509 err_out2:
510 free_netdev(self->netdev);
511 dev_self[dev_count] = NULL;
512 err_out1:
513 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
514 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
515 err_out:
516 return err;
517 }
518
519 /*
520 * Function smsc_ircc_present(fir_base, sir_base)
521 *
522 * Check the smsc-ircc chip presence
523 *
524 */
525 static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base)
526 {
527 unsigned char low, high, chip, config, dma, irq, version;
528
529 if (!request_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT,
530 driver_name)) {
531 IRDA_WARNING("%s: can't get fir_base of 0x%03x\n",
532 __FUNCTION__, fir_base);
533 goto out1;
534 }
535
536 if (!request_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT,
537 driver_name)) {
538 IRDA_WARNING("%s: can't get sir_base of 0x%03x\n",
539 __FUNCTION__, sir_base);
540 goto out2;
541 }
542
543 register_bank(fir_base, 3);
544
545 high = inb(fir_base + IRCC_ID_HIGH);
546 low = inb(fir_base + IRCC_ID_LOW);
547 chip = inb(fir_base + IRCC_CHIP_ID);
548 version = inb(fir_base + IRCC_VERSION);
549 config = inb(fir_base + IRCC_INTERFACE);
550 dma = config & IRCC_INTERFACE_DMA_MASK;
551 irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
552
553 if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) {
554 IRDA_WARNING("%s(), addr 0x%04x - no device found!\n",
555 __FUNCTION__, fir_base);
556 goto out3;
557 }
558 IRDA_MESSAGE("SMsC IrDA Controller found\n IrCC version %d.%d, "
559 "firport 0x%03x, sirport 0x%03x dma=%d, irq=%d\n",
560 chip & 0x0f, version, fir_base, sir_base, dma, irq);
561
562 return 0;
563
564 out3:
565 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
566 out2:
567 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
568 out1:
569 return -ENODEV;
570 }
571
572 /*
573 * Function smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq)
574 *
575 * Setup I/O
576 *
577 */
578 static void smsc_ircc_setup_io(struct smsc_ircc_cb *self,
579 unsigned int fir_base, unsigned int sir_base,
580 u8 dma, u8 irq)
581 {
582 unsigned char config, chip_dma, chip_irq;
583
584 register_bank(fir_base, 3);
585 config = inb(fir_base + IRCC_INTERFACE);
586 chip_dma = config & IRCC_INTERFACE_DMA_MASK;
587 chip_irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
588
589 self->io.fir_base = fir_base;
590 self->io.sir_base = sir_base;
591 self->io.fir_ext = SMSC_IRCC2_FIR_CHIP_IO_EXTENT;
592 self->io.sir_ext = SMSC_IRCC2_SIR_CHIP_IO_EXTENT;
593 self->io.fifo_size = SMSC_IRCC2_FIFO_SIZE;
594 self->io.speed = SMSC_IRCC2_C_IRDA_FALLBACK_SPEED;
595
596 if (irq < 255) {
597 if (irq != chip_irq)
598 IRDA_MESSAGE("%s, Overriding IRQ - chip says %d, using %d\n",
599 driver_name, chip_irq, irq);
600 self->io.irq = irq;
601 } else
602 self->io.irq = chip_irq;
603
604 if (dma < 255) {
605 if (dma != chip_dma)
606 IRDA_MESSAGE("%s, Overriding DMA - chip says %d, using %d\n",
607 driver_name, chip_dma, dma);
608 self->io.dma = dma;
609 } else
610 self->io.dma = chip_dma;
611
612 }
613
614 /*
615 * Function smsc_ircc_setup_qos(self)
616 *
617 * Setup qos
618 *
619 */
620 static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self)
621 {
622 /* Initialize QoS for this device */
623 irda_init_max_qos_capabilies(&self->qos);
624
625 self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
626 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8);
627
628 self->qos.min_turn_time.bits = SMSC_IRCC2_MIN_TURN_TIME;
629 self->qos.window_size.bits = SMSC_IRCC2_WINDOW_SIZE;
630 irda_qos_bits_to_value(&self->qos);
631 }
632
633 /*
634 * Function smsc_ircc_init_chip(self)
635 *
636 * Init chip
637 *
638 */
639 static void smsc_ircc_init_chip(struct smsc_ircc_cb *self)
640 {
641 int iobase, ir_mode, ctrl, fast;
642
643 IRDA_ASSERT(self != NULL, return;);
644
645 iobase = self->io.fir_base;
646 ir_mode = IRCC_CFGA_IRDA_SIR_A;
647 ctrl = 0;
648 fast = 0;
649
650 register_bank(iobase, 0);
651 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
652 outb(0x00, iobase + IRCC_MASTER);
653
654 register_bank(iobase, 1);
655 outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | ir_mode),
656 iobase + IRCC_SCE_CFGA);
657
658 #ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */
659 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
660 iobase + IRCC_SCE_CFGB);
661 #else
662 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
663 iobase + IRCC_SCE_CFGB);
664 #endif
665 (void) inb(iobase + IRCC_FIFO_THRESHOLD);
666 outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase + IRCC_FIFO_THRESHOLD);
667
668 register_bank(iobase, 4);
669 outb((inb(iobase + IRCC_CONTROL) & 0x30) | ctrl, iobase + IRCC_CONTROL);
670
671 register_bank(iobase, 0);
672 outb(fast, iobase + IRCC_LCR_A);
673
674 smsc_ircc_set_sir_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
675
676 /* Power on device */
677 outb(0x00, iobase + IRCC_MASTER);
678 }
679
680 /*
681 * Function smsc_ircc_net_ioctl (dev, rq, cmd)
682 *
683 * Process IOCTL commands for this device
684 *
685 */
686 static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
687 {
688 struct if_irda_req *irq = (struct if_irda_req *) rq;
689 struct smsc_ircc_cb *self;
690 unsigned long flags;
691 int ret = 0;
692
693 IRDA_ASSERT(dev != NULL, return -1;);
694
695 self = netdev_priv(dev);
696
697 IRDA_ASSERT(self != NULL, return -1;);
698
699 IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __FUNCTION__, dev->name, cmd);
700
701 switch (cmd) {
702 case SIOCSBANDWIDTH: /* Set bandwidth */
703 if (!capable(CAP_NET_ADMIN))
704 ret = -EPERM;
705 else {
706 /* Make sure we are the only one touching
707 * self->io.speed and the hardware - Jean II */
708 spin_lock_irqsave(&self->lock, flags);
709 smsc_ircc_change_speed(self, irq->ifr_baudrate);
710 spin_unlock_irqrestore(&self->lock, flags);
711 }
712 break;
713 case SIOCSMEDIABUSY: /* Set media busy */
714 if (!capable(CAP_NET_ADMIN)) {
715 ret = -EPERM;
716 break;
717 }
718
719 irda_device_set_media_busy(self->netdev, TRUE);
720 break;
721 case SIOCGRECEIVING: /* Check if we are receiving right now */
722 irq->ifr_receiving = smsc_ircc_is_receiving(self);
723 break;
724 #if 0
725 case SIOCSDTRRTS:
726 if (!capable(CAP_NET_ADMIN)) {
727 ret = -EPERM;
728 break;
729 }
730 smsc_ircc_sir_set_dtr_rts(dev, irq->ifr_dtr, irq->ifr_rts);
731 break;
732 #endif
733 default:
734 ret = -EOPNOTSUPP;
735 }
736
737 return ret;
738 }
739
740 static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev)
741 {
742 struct smsc_ircc_cb *self = netdev_priv(dev);
743
744 return &self->stats;
745 }
746
747 #if SMSC_IRCC2_C_NET_TIMEOUT
748 /*
749 * Function smsc_ircc_timeout (struct net_device *dev)
750 *
751 * The networking timeout management.
752 *
753 */
754
755 static void smsc_ircc_timeout(struct net_device *dev)
756 {
757 struct smsc_ircc_cb *self = netdev_priv(dev);
758 unsigned long flags;
759
760 IRDA_WARNING("%s: transmit timed out, changing speed to: %d\n",
761 dev->name, self->io.speed);
762 spin_lock_irqsave(&self->lock, flags);
763 smsc_ircc_sir_start(self);
764 smsc_ircc_change_speed(self, self->io.speed);
765 dev->trans_start = jiffies;
766 netif_wake_queue(dev);
767 spin_unlock_irqrestore(&self->lock, flags);
768 }
769 #endif
770
771 /*
772 * Function smsc_ircc_hard_xmit_sir (struct sk_buff *skb, struct net_device *dev)
773 *
774 * Transmits the current frame until FIFO is full, then
775 * waits until the next transmit interrupt, and continues until the
776 * frame is transmitted.
777 */
778 int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev)
779 {
780 struct smsc_ircc_cb *self;
781 unsigned long flags;
782 s32 speed;
783
784 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
785
786 IRDA_ASSERT(dev != NULL, return 0;);
787
788 self = netdev_priv(dev);
789 IRDA_ASSERT(self != NULL, return 0;);
790
791 netif_stop_queue(dev);
792
793 /* Make sure test of self->io.speed & speed change are atomic */
794 spin_lock_irqsave(&self->lock, flags);
795
796 /* Check if we need to change the speed */
797 speed = irda_get_next_speed(skb);
798 if (speed != self->io.speed && speed != -1) {
799 /* Check for empty frame */
800 if (!skb->len) {
801 /*
802 * We send frames one by one in SIR mode (no
803 * pipelining), so at this point, if we were sending
804 * a previous frame, we just received the interrupt
805 * telling us it is finished (UART_IIR_THRI).
806 * Therefore, waiting for the transmitter to really
807 * finish draining the fifo won't take too long.
808 * And the interrupt handler is not expected to run.
809 * - Jean II */
810 smsc_ircc_sir_wait_hw_transmitter_finish(self);
811 smsc_ircc_change_speed(self, speed);
812 spin_unlock_irqrestore(&self->lock, flags);
813 dev_kfree_skb(skb);
814 return 0;
815 }
816 self->new_speed = speed;
817 }
818
819 /* Init tx buffer */
820 self->tx_buff.data = self->tx_buff.head;
821
822 /* Copy skb to tx_buff while wrapping, stuffing and making CRC */
823 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
824 self->tx_buff.truesize);
825
826 self->stats.tx_bytes += self->tx_buff.len;
827
828 /* Turn on transmit finished interrupt. Will fire immediately! */
829 outb(UART_IER_THRI, self->io.sir_base + UART_IER);
830
831 spin_unlock_irqrestore(&self->lock, flags);
832
833 dev_kfree_skb(skb);
834
835 return 0;
836 }
837
838 /*
839 * Function smsc_ircc_set_fir_speed (self, baud)
840 *
841 * Change the speed of the device
842 *
843 */
844 static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb *self, u32 speed)
845 {
846 int fir_base, ir_mode, ctrl, fast;
847
848 IRDA_ASSERT(self != NULL, return;);
849 fir_base = self->io.fir_base;
850
851 self->io.speed = speed;
852
853 switch (speed) {
854 default:
855 case 576000:
856 ir_mode = IRCC_CFGA_IRDA_HDLC;
857 ctrl = IRCC_CRC;
858 fast = 0;
859 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __FUNCTION__);
860 break;
861 case 1152000:
862 ir_mode = IRCC_CFGA_IRDA_HDLC;
863 ctrl = IRCC_1152 | IRCC_CRC;
864 fast = IRCC_LCR_A_FAST | IRCC_LCR_A_GP_DATA;
865 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n",
866 __FUNCTION__);
867 break;
868 case 4000000:
869 ir_mode = IRCC_CFGA_IRDA_4PPM;
870 ctrl = IRCC_CRC;
871 fast = IRCC_LCR_A_FAST;
872 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n",
873 __FUNCTION__);
874 break;
875 }
876 #if 0
877 Now in tranceiver!
878 /* This causes an interrupt */
879 register_bank(fir_base, 0);
880 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast, fir_base + IRCC_LCR_A);
881 #endif
882
883 register_bank(fir_base, 1);
884 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base + IRCC_SCE_CFGA);
885
886 register_bank(fir_base, 4);
887 outb((inb(fir_base + IRCC_CONTROL) & 0x30) | ctrl, fir_base + IRCC_CONTROL);
888 }
889
890 /*
891 * Function smsc_ircc_fir_start(self)
892 *
893 * Change the speed of the device
894 *
895 */
896 static void smsc_ircc_fir_start(struct smsc_ircc_cb *self)
897 {
898 struct net_device *dev;
899 int fir_base;
900
901 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
902
903 IRDA_ASSERT(self != NULL, return;);
904 dev = self->netdev;
905 IRDA_ASSERT(dev != NULL, return;);
906
907 fir_base = self->io.fir_base;
908
909 /* Reset everything */
910
911 /* Install FIR transmit handler */
912 dev->hard_start_xmit = smsc_ircc_hard_xmit_fir;
913
914 /* Clear FIFO */
915 outb(inb(fir_base + IRCC_LCR_A) | IRCC_LCR_A_FIFO_RESET, fir_base + IRCC_LCR_A);
916
917 /* Enable interrupt */
918 /*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base + IRCC_IER);*/
919
920 register_bank(fir_base, 1);
921
922 /* Select the TX/RX interface */
923 #ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */
924 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
925 fir_base + IRCC_SCE_CFGB);
926 #else
927 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
928 fir_base + IRCC_SCE_CFGB);
929 #endif
930 (void) inb(fir_base + IRCC_FIFO_THRESHOLD);
931
932 /* Enable SCE interrupts */
933 outb(0, fir_base + IRCC_MASTER);
934 register_bank(fir_base, 0);
935 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, fir_base + IRCC_IER);
936 outb(IRCC_MASTER_INT_EN, fir_base + IRCC_MASTER);
937 }
938
939 /*
940 * Function smsc_ircc_fir_stop(self, baud)
941 *
942 * Change the speed of the device
943 *
944 */
945 static void smsc_ircc_fir_stop(struct smsc_ircc_cb *self)
946 {
947 int fir_base;
948
949 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
950
951 IRDA_ASSERT(self != NULL, return;);
952
953 fir_base = self->io.fir_base;
954 register_bank(fir_base, 0);
955 /*outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);*/
956 outb(inb(fir_base + IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base + IRCC_LCR_B);
957 }
958
959
960 /*
961 * Function smsc_ircc_change_speed(self, baud)
962 *
963 * Change the speed of the device
964 *
965 * This function *must* be called with spinlock held, because it may
966 * be called from the irq handler. - Jean II
967 */
968 static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed)
969 {
970 struct net_device *dev;
971 int last_speed_was_sir;
972
973 IRDA_DEBUG(0, "%s() changing speed to: %d\n", __FUNCTION__, speed);
974
975 IRDA_ASSERT(self != NULL, return;);
976 dev = self->netdev;
977
978 last_speed_was_sir = self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED;
979
980 #if 0
981 /* Temp Hack */
982 speed= 1152000;
983 self->io.speed = speed;
984 last_speed_was_sir = 0;
985 smsc_ircc_fir_start(self);
986 #endif
987
988 if (self->io.speed == 0)
989 smsc_ircc_sir_start(self);
990
991 #if 0
992 if (!last_speed_was_sir) speed = self->io.speed;
993 #endif
994
995 if (self->io.speed != speed)
996 smsc_ircc_set_transceiver_for_speed(self, speed);
997
998 self->io.speed = speed;
999
1000 if (speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1001 if (!last_speed_was_sir) {
1002 smsc_ircc_fir_stop(self);
1003 smsc_ircc_sir_start(self);
1004 }
1005 smsc_ircc_set_sir_speed(self, speed);
1006 } else {
1007 if (last_speed_was_sir) {
1008 #if SMSC_IRCC2_C_SIR_STOP
1009 smsc_ircc_sir_stop(self);
1010 #endif
1011 smsc_ircc_fir_start(self);
1012 }
1013 smsc_ircc_set_fir_speed(self, speed);
1014
1015 #if 0
1016 self->tx_buff.len = 10;
1017 self->tx_buff.data = self->tx_buff.head;
1018
1019 smsc_ircc_dma_xmit(self, 4000);
1020 #endif
1021 /* Be ready for incoming frames */
1022 smsc_ircc_dma_receive(self);
1023 }
1024
1025 netif_wake_queue(dev);
1026 }
1027
1028 /*
1029 * Function smsc_ircc_set_sir_speed (self, speed)
1030 *
1031 * Set speed of IrDA port to specified baudrate
1032 *
1033 */
1034 void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, __u32 speed)
1035 {
1036 int iobase;
1037 int fcr; /* FIFO control reg */
1038 int lcr; /* Line control reg */
1039 int divisor;
1040
1041 IRDA_DEBUG(0, "%s(), Setting speed to: %d\n", __FUNCTION__, speed);
1042
1043 IRDA_ASSERT(self != NULL, return;);
1044 iobase = self->io.sir_base;
1045
1046 /* Update accounting for new speed */
1047 self->io.speed = speed;
1048
1049 /* Turn off interrupts */
1050 outb(0, iobase + UART_IER);
1051
1052 divisor = SMSC_IRCC2_MAX_SIR_SPEED / speed;
1053
1054 fcr = UART_FCR_ENABLE_FIFO;
1055
1056 /*
1057 * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and
1058 * almost 1,7 ms at 19200 bps. At speeds above that we can just forget
1059 * about this timeout since it will always be fast enough.
1060 */
1061 fcr |= self->io.speed < 38400 ?
1062 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
1063
1064 /* IrDA ports use 8N1 */
1065 lcr = UART_LCR_WLEN8;
1066
1067 outb(UART_LCR_DLAB | lcr, iobase + UART_LCR); /* Set DLAB */
1068 outb(divisor & 0xff, iobase + UART_DLL); /* Set speed */
1069 outb(divisor >> 8, iobase + UART_DLM);
1070 outb(lcr, iobase + UART_LCR); /* Set 8N1 */
1071 outb(fcr, iobase + UART_FCR); /* Enable FIFO's */
1072
1073 /* Turn on interrups */
1074 outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER);
1075
1076 IRDA_DEBUG(2, "%s() speed changed to: %d\n", __FUNCTION__, speed);
1077 }
1078
1079
1080 /*
1081 * Function smsc_ircc_hard_xmit_fir (skb, dev)
1082 *
1083 * Transmit the frame!
1084 *
1085 */
1086 static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev)
1087 {
1088 struct smsc_ircc_cb *self;
1089 unsigned long flags;
1090 s32 speed;
1091 int mtt;
1092
1093 IRDA_ASSERT(dev != NULL, return 0;);
1094 self = netdev_priv(dev);
1095 IRDA_ASSERT(self != NULL, return 0;);
1096
1097 netif_stop_queue(dev);
1098
1099 /* Make sure test of self->io.speed & speed change are atomic */
1100 spin_lock_irqsave(&self->lock, flags);
1101
1102 /* Check if we need to change the speed after this frame */
1103 speed = irda_get_next_speed(skb);
1104 if (speed != self->io.speed && speed != -1) {
1105 /* Check for empty frame */
1106 if (!skb->len) {
1107 /* Note : you should make sure that speed changes
1108 * are not going to corrupt any outgoing frame.
1109 * Look at nsc-ircc for the gory details - Jean II */
1110 smsc_ircc_change_speed(self, speed);
1111 spin_unlock_irqrestore(&self->lock, flags);
1112 dev_kfree_skb(skb);
1113 return 0;
1114 }
1115
1116 self->new_speed = speed;
1117 }
1118
1119 memcpy(self->tx_buff.head, skb->data, skb->len);
1120
1121 self->tx_buff.len = skb->len;
1122 self->tx_buff.data = self->tx_buff.head;
1123
1124 mtt = irda_get_mtt(skb);
1125 if (mtt) {
1126 int bofs;
1127
1128 /*
1129 * Compute how many BOFs (STA or PA's) we need to waste the
1130 * min turn time given the speed of the link.
1131 */
1132 bofs = mtt * (self->io.speed / 1000) / 8000;
1133 if (bofs > 4095)
1134 bofs = 4095;
1135
1136 smsc_ircc_dma_xmit(self, bofs);
1137 } else {
1138 /* Transmit frame */
1139 smsc_ircc_dma_xmit(self, 0);
1140 }
1141
1142 spin_unlock_irqrestore(&self->lock, flags);
1143 dev_kfree_skb(skb);
1144
1145 return 0;
1146 }
1147
1148 /*
1149 * Function smsc_ircc_dma_xmit (self, bofs)
1150 *
1151 * Transmit data using DMA
1152 *
1153 */
1154 static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs)
1155 {
1156 int iobase = self->io.fir_base;
1157 u8 ctrl;
1158
1159 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1160 #if 1
1161 /* Disable Rx */
1162 register_bank(iobase, 0);
1163 outb(0x00, iobase + IRCC_LCR_B);
1164 #endif
1165 register_bank(iobase, 1);
1166 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1167 iobase + IRCC_SCE_CFGB);
1168
1169 self->io.direction = IO_XMIT;
1170
1171 /* Set BOF additional count for generating the min turn time */
1172 register_bank(iobase, 4);
1173 outb(bofs & 0xff, iobase + IRCC_BOF_COUNT_LO);
1174 ctrl = inb(iobase + IRCC_CONTROL) & 0xf0;
1175 outb(ctrl | ((bofs >> 8) & 0x0f), iobase + IRCC_BOF_COUNT_HI);
1176
1177 /* Set max Tx frame size */
1178 outb(self->tx_buff.len >> 8, iobase + IRCC_TX_SIZE_HI);
1179 outb(self->tx_buff.len & 0xff, iobase + IRCC_TX_SIZE_LO);
1180
1181 /*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/
1182
1183 /* Enable burst mode chip Tx DMA */
1184 register_bank(iobase, 1);
1185 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1186 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1187
1188 /* Setup DMA controller (must be done after enabling chip DMA) */
1189 irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
1190 DMA_TX_MODE);
1191
1192 /* Enable interrupt */
1193
1194 register_bank(iobase, 0);
1195 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1196 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1197
1198 /* Enable transmit */
1199 outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B);
1200 }
1201
1202 /*
1203 * Function smsc_ircc_dma_xmit_complete (self)
1204 *
1205 * The transfer of a frame in finished. This function will only be called
1206 * by the interrupt handler
1207 *
1208 */
1209 static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self)
1210 {
1211 int iobase = self->io.fir_base;
1212
1213 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1214 #if 0
1215 /* Disable Tx */
1216 register_bank(iobase, 0);
1217 outb(0x00, iobase + IRCC_LCR_B);
1218 #endif
1219 register_bank(iobase, 1);
1220 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1221 iobase + IRCC_SCE_CFGB);
1222
1223 /* Check for underrun! */
1224 register_bank(iobase, 0);
1225 if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) {
1226 self->stats.tx_errors++;
1227 self->stats.tx_fifo_errors++;
1228
1229 /* Reset error condition */
1230 register_bank(iobase, 0);
1231 outb(IRCC_MASTER_ERROR_RESET, iobase + IRCC_MASTER);
1232 outb(0x00, iobase + IRCC_MASTER);
1233 } else {
1234 self->stats.tx_packets++;
1235 self->stats.tx_bytes += self->tx_buff.len;
1236 }
1237
1238 /* Check if it's time to change the speed */
1239 if (self->new_speed) {
1240 smsc_ircc_change_speed(self, self->new_speed);
1241 self->new_speed = 0;
1242 }
1243
1244 netif_wake_queue(self->netdev);
1245 }
1246
1247 /*
1248 * Function smsc_ircc_dma_receive(self)
1249 *
1250 * Get ready for receiving a frame. The device will initiate a DMA
1251 * if it starts to receive a frame.
1252 *
1253 */
1254 static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self)
1255 {
1256 int iobase = self->io.fir_base;
1257 #if 0
1258 /* Turn off chip DMA */
1259 register_bank(iobase, 1);
1260 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1261 iobase + IRCC_SCE_CFGB);
1262 #endif
1263
1264 /* Disable Tx */
1265 register_bank(iobase, 0);
1266 outb(0x00, iobase + IRCC_LCR_B);
1267
1268 /* Turn off chip DMA */
1269 register_bank(iobase, 1);
1270 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1271 iobase + IRCC_SCE_CFGB);
1272
1273 self->io.direction = IO_RECV;
1274 self->rx_buff.data = self->rx_buff.head;
1275
1276 /* Set max Rx frame size */
1277 register_bank(iobase, 4);
1278 outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI);
1279 outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO);
1280
1281 /* Setup DMA controller */
1282 irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
1283 DMA_RX_MODE);
1284
1285 /* Enable burst mode chip Rx DMA */
1286 register_bank(iobase, 1);
1287 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1288 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1289
1290 /* Enable interrupt */
1291 register_bank(iobase, 0);
1292 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1293 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1294
1295 /* Enable receiver */
1296 register_bank(iobase, 0);
1297 outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE,
1298 iobase + IRCC_LCR_B);
1299
1300 return 0;
1301 }
1302
1303 /*
1304 * Function smsc_ircc_dma_receive_complete(self)
1305 *
1306 * Finished with receiving frames
1307 *
1308 */
1309 static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self)
1310 {
1311 struct sk_buff *skb;
1312 int len, msgcnt, lsr;
1313 int iobase = self->io.fir_base;
1314
1315 register_bank(iobase, 0);
1316
1317 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1318 #if 0
1319 /* Disable Rx */
1320 register_bank(iobase, 0);
1321 outb(0x00, iobase + IRCC_LCR_B);
1322 #endif
1323 register_bank(iobase, 0);
1324 outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR);
1325 lsr= inb(iobase + IRCC_LSR);
1326 msgcnt = inb(iobase + IRCC_LCR_B) & 0x08;
1327
1328 IRDA_DEBUG(2, "%s: dma count = %d\n", __FUNCTION__,
1329 get_dma_residue(self->io.dma));
1330
1331 len = self->rx_buff.truesize - get_dma_residue(self->io.dma);
1332
1333 /* Look for errors */
1334 if (lsr & (IRCC_LSR_FRAME_ERROR | IRCC_LSR_CRC_ERROR | IRCC_LSR_SIZE_ERROR)) {
1335 self->stats.rx_errors++;
1336 if (lsr & IRCC_LSR_FRAME_ERROR)
1337 self->stats.rx_frame_errors++;
1338 if (lsr & IRCC_LSR_CRC_ERROR)
1339 self->stats.rx_crc_errors++;
1340 if (lsr & IRCC_LSR_SIZE_ERROR)
1341 self->stats.rx_length_errors++;
1342 if (lsr & (IRCC_LSR_UNDERRUN | IRCC_LSR_OVERRUN))
1343 self->stats.rx_length_errors++;
1344 return;
1345 }
1346
1347 /* Remove CRC */
1348 len -= self->io.speed < 4000000 ? 2 : 4;
1349
1350 if (len < 2 || len > 2050) {
1351 IRDA_WARNING("%s(), bogus len=%d\n", __FUNCTION__, len);
1352 return;
1353 }
1354 IRDA_DEBUG(2, "%s: msgcnt = %d, len=%d\n", __FUNCTION__, msgcnt, len);
1355
1356 skb = dev_alloc_skb(len + 1);
1357 if (!skb) {
1358 IRDA_WARNING("%s(), memory squeeze, dropping frame.\n",
1359 __FUNCTION__);
1360 return;
1361 }
1362 /* Make sure IP header gets aligned */
1363 skb_reserve(skb, 1);
1364
1365 memcpy(skb_put(skb, len), self->rx_buff.data, len);
1366 self->stats.rx_packets++;
1367 self->stats.rx_bytes += len;
1368
1369 skb->dev = self->netdev;
1370 skb->mac.raw = skb->data;
1371 skb->protocol = htons(ETH_P_IRDA);
1372 netif_rx(skb);
1373 }
1374
1375 /*
1376 * Function smsc_ircc_sir_receive (self)
1377 *
1378 * Receive one frame from the infrared port
1379 *
1380 */
1381 static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self)
1382 {
1383 int boguscount = 0;
1384 int iobase;
1385
1386 IRDA_ASSERT(self != NULL, return;);
1387
1388 iobase = self->io.sir_base;
1389
1390 /*
1391 * Receive all characters in Rx FIFO, unwrap and unstuff them.
1392 * async_unwrap_char will deliver all found frames
1393 */
1394 do {
1395 async_unwrap_char(self->netdev, &self->stats, &self->rx_buff,
1396 inb(iobase + UART_RX));
1397
1398 /* Make sure we don't stay here to long */
1399 if (boguscount++ > 32) {
1400 IRDA_DEBUG(2, "%s(), breaking!\n", __FUNCTION__);
1401 break;
1402 }
1403 } while (inb(iobase + UART_LSR) & UART_LSR_DR);
1404 }
1405
1406
1407 /*
1408 * Function smsc_ircc_interrupt (irq, dev_id, regs)
1409 *
1410 * An interrupt from the chip has arrived. Time to do some work
1411 *
1412 */
1413 static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1414 {
1415 struct net_device *dev = (struct net_device *) dev_id;
1416 struct smsc_ircc_cb *self;
1417 int iobase, iir, lcra, lsr;
1418 irqreturn_t ret = IRQ_NONE;
1419
1420 if (dev == NULL) {
1421 printk(KERN_WARNING "%s: irq %d for unknown device.\n",
1422 driver_name, irq);
1423 goto irq_ret;
1424 }
1425
1426 self = netdev_priv(dev);
1427 IRDA_ASSERT(self != NULL, return IRQ_NONE;);
1428
1429 /* Serialise the interrupt handler in various CPUs, stop Tx path */
1430 spin_lock(&self->lock);
1431
1432 /* Check if we should use the SIR interrupt handler */
1433 if (self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1434 ret = smsc_ircc_interrupt_sir(dev);
1435 goto irq_ret_unlock;
1436 }
1437
1438 iobase = self->io.fir_base;
1439
1440 register_bank(iobase, 0);
1441 iir = inb(iobase + IRCC_IIR);
1442 if (iir == 0)
1443 goto irq_ret_unlock;
1444 ret = IRQ_HANDLED;
1445
1446 /* Disable interrupts */
1447 outb(0, iobase + IRCC_IER);
1448 lcra = inb(iobase + IRCC_LCR_A);
1449 lsr = inb(iobase + IRCC_LSR);
1450
1451 IRDA_DEBUG(2, "%s(), iir = 0x%02x\n", __FUNCTION__, iir);
1452
1453 if (iir & IRCC_IIR_EOM) {
1454 if (self->io.direction == IO_RECV)
1455 smsc_ircc_dma_receive_complete(self);
1456 else
1457 smsc_ircc_dma_xmit_complete(self);
1458
1459 smsc_ircc_dma_receive(self);
1460 }
1461
1462 if (iir & IRCC_IIR_ACTIVE_FRAME) {
1463 /*printk(KERN_WARNING "%s(): Active Frame\n", __FUNCTION__);*/
1464 }
1465
1466 /* Enable interrupts again */
1467
1468 register_bank(iobase, 0);
1469 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1470
1471 irq_ret_unlock:
1472 spin_unlock(&self->lock);
1473 irq_ret:
1474 return ret;
1475 }
1476
1477 /*
1478 * Function irport_interrupt_sir (irq, dev_id, regs)
1479 *
1480 * Interrupt handler for SIR modes
1481 */
1482 static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev)
1483 {
1484 struct smsc_ircc_cb *self = netdev_priv(dev);
1485 int boguscount = 0;
1486 int iobase;
1487 int iir, lsr;
1488
1489 /* Already locked comming here in smsc_ircc_interrupt() */
1490 /*spin_lock(&self->lock);*/
1491
1492 iobase = self->io.sir_base;
1493
1494 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1495 if (iir == 0)
1496 return IRQ_NONE;
1497 while (iir) {
1498 /* Clear interrupt */
1499 lsr = inb(iobase + UART_LSR);
1500
1501 IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n",
1502 __FUNCTION__, iir, lsr, iobase);
1503
1504 switch (iir) {
1505 case UART_IIR_RLSI:
1506 IRDA_DEBUG(2, "%s(), RLSI\n", __FUNCTION__);
1507 break;
1508 case UART_IIR_RDI:
1509 /* Receive interrupt */
1510 smsc_ircc_sir_receive(self);
1511 break;
1512 case UART_IIR_THRI:
1513 if (lsr & UART_LSR_THRE)
1514 /* Transmitter ready for data */
1515 smsc_ircc_sir_write_wakeup(self);
1516 break;
1517 default:
1518 IRDA_DEBUG(0, "%s(), unhandled IIR=%#x\n",
1519 __FUNCTION__, iir);
1520 break;
1521 }
1522
1523 /* Make sure we don't stay here to long */
1524 if (boguscount++ > 100)
1525 break;
1526
1527 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1528 }
1529 /*spin_unlock(&self->lock);*/
1530 return IRQ_HANDLED;
1531 }
1532
1533
1534 #if 0 /* unused */
1535 /*
1536 * Function ircc_is_receiving (self)
1537 *
1538 * Return TRUE is we are currently receiving a frame
1539 *
1540 */
1541 static int ircc_is_receiving(struct smsc_ircc_cb *self)
1542 {
1543 int status = FALSE;
1544 /* int iobase; */
1545
1546 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1547
1548 IRDA_ASSERT(self != NULL, return FALSE;);
1549
1550 IRDA_DEBUG(0, "%s: dma count = %d\n", __FUNCTION__,
1551 get_dma_residue(self->io.dma));
1552
1553 status = (self->rx_buff.state != OUTSIDE_FRAME);
1554
1555 return status;
1556 }
1557 #endif /* unused */
1558
1559
1560 /*
1561 * Function smsc_ircc_net_open (dev)
1562 *
1563 * Start the device
1564 *
1565 */
1566 static int smsc_ircc_net_open(struct net_device *dev)
1567 {
1568 struct smsc_ircc_cb *self;
1569 char hwname[16];
1570 unsigned long flags;
1571
1572 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1573
1574 IRDA_ASSERT(dev != NULL, return -1;);
1575 self = netdev_priv(dev);
1576 IRDA_ASSERT(self != NULL, return 0;);
1577
1578 if (request_irq(self->io.irq, smsc_ircc_interrupt, 0, dev->name,
1579 (void *) dev)) {
1580 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d\n",
1581 __FUNCTION__, self->io.irq);
1582 return -EAGAIN;
1583 }
1584
1585 spin_lock_irqsave(&self->lock, flags);
1586 /*smsc_ircc_sir_start(self);*/
1587 self->io.speed = 0;
1588 smsc_ircc_change_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
1589 spin_unlock_irqrestore(&self->lock, flags);
1590
1591 /* Give self a hardware name */
1592 /* It would be cool to offer the chip revision here - Jean II */
1593 sprintf(hwname, "SMSC @ 0x%03x", self->io.fir_base);
1594
1595 /*
1596 * Open new IrLAP layer instance, now that everything should be
1597 * initialized properly
1598 */
1599 self->irlap = irlap_open(dev, &self->qos, hwname);
1600
1601 /*
1602 * Always allocate the DMA channel after the IRQ,
1603 * and clean up on failure.
1604 */
1605 if (request_dma(self->io.dma, dev->name)) {
1606 smsc_ircc_net_close(dev);
1607
1608 IRDA_WARNING("%s(), unable to allocate DMA=%d\n",
1609 __FUNCTION__, self->io.dma);
1610 return -EAGAIN;
1611 }
1612
1613 netif_start_queue(dev);
1614
1615 return 0;
1616 }
1617
1618 /*
1619 * Function smsc_ircc_net_close (dev)
1620 *
1621 * Stop the device
1622 *
1623 */
1624 static int smsc_ircc_net_close(struct net_device *dev)
1625 {
1626 struct smsc_ircc_cb *self;
1627
1628 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1629
1630 IRDA_ASSERT(dev != NULL, return -1;);
1631 self = netdev_priv(dev);
1632 IRDA_ASSERT(self != NULL, return 0;);
1633
1634 /* Stop device */
1635 netif_stop_queue(dev);
1636
1637 /* Stop and remove instance of IrLAP */
1638 if (self->irlap)
1639 irlap_close(self->irlap);
1640 self->irlap = NULL;
1641
1642 free_irq(self->io.irq, dev);
1643 disable_dma(self->io.dma);
1644 free_dma(self->io.dma);
1645
1646 return 0;
1647 }
1648
1649 static int smsc_ircc_suspend(struct device *dev, pm_message_t state, u32 level)
1650 {
1651 struct smsc_ircc_cb *self = dev_get_drvdata(dev);
1652
1653 IRDA_MESSAGE("%s, Suspending\n", driver_name);
1654
1655 if (level == SUSPEND_DISABLE && !self->io.suspended) {
1656 smsc_ircc_net_close(self->netdev);
1657 self->io.suspended = 1;
1658 }
1659
1660 return 0;
1661 }
1662
1663 static int smsc_ircc_resume(struct device *dev, u32 level)
1664 {
1665 struct smsc_ircc_cb *self = dev_get_drvdata(dev);
1666
1667 if (level == RESUME_ENABLE && self->io.suspended) {
1668
1669 smsc_ircc_net_open(self->netdev);
1670 self->io.suspended = 0;
1671
1672 IRDA_MESSAGE("%s, Waking up\n", driver_name);
1673 }
1674 return 0;
1675 }
1676
1677 /*
1678 * Function smsc_ircc_close (self)
1679 *
1680 * Close driver instance
1681 *
1682 */
1683 static int __exit smsc_ircc_close(struct smsc_ircc_cb *self)
1684 {
1685 int iobase;
1686 unsigned long flags;
1687
1688 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1689
1690 IRDA_ASSERT(self != NULL, return -1;);
1691
1692 platform_device_unregister(self->pldev);
1693
1694 /* Remove netdevice */
1695 unregister_netdev(self->netdev);
1696
1697 /* Make sure the irq handler is not exectuting */
1698 spin_lock_irqsave(&self->lock, flags);
1699
1700 /* Stop interrupts */
1701 iobase = self->io.fir_base;
1702 register_bank(iobase, 0);
1703 outb(0, iobase + IRCC_IER);
1704 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
1705 outb(0x00, iobase + IRCC_MASTER);
1706 #if 0
1707 /* Reset to SIR mode */
1708 register_bank(iobase, 1);
1709 outb(IRCC_CFGA_IRDA_SIR_A|IRCC_CFGA_TX_POLARITY, iobase + IRCC_SCE_CFGA);
1710 outb(IRCC_CFGB_IR, iobase + IRCC_SCE_CFGB);
1711 #endif
1712 spin_unlock_irqrestore(&self->lock, flags);
1713
1714 /* Release the PORTS that this driver is using */
1715 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __FUNCTION__,
1716 self->io.fir_base);
1717
1718 release_region(self->io.fir_base, self->io.fir_ext);
1719
1720 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __FUNCTION__,
1721 self->io.sir_base);
1722
1723 release_region(self->io.sir_base, self->io.sir_ext);
1724
1725 if (self->tx_buff.head)
1726 dma_free_coherent(NULL, self->tx_buff.truesize,
1727 self->tx_buff.head, self->tx_buff_dma);
1728
1729 if (self->rx_buff.head)
1730 dma_free_coherent(NULL, self->rx_buff.truesize,
1731 self->rx_buff.head, self->rx_buff_dma);
1732
1733 free_netdev(self->netdev);
1734
1735 return 0;
1736 }
1737
1738 static void __exit smsc_ircc_cleanup(void)
1739 {
1740 int i;
1741
1742 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1743
1744 for (i = 0; i < 2; i++) {
1745 if (dev_self[i])
1746 smsc_ircc_close(dev_self[i]);
1747 }
1748
1749 driver_unregister(&smsc_ircc_driver);
1750 }
1751
1752 /*
1753 * Start SIR operations
1754 *
1755 * This function *must* be called with spinlock held, because it may
1756 * be called from the irq handler (via smsc_ircc_change_speed()). - Jean II
1757 */
1758 void smsc_ircc_sir_start(struct smsc_ircc_cb *self)
1759 {
1760 struct net_device *dev;
1761 int fir_base, sir_base;
1762
1763 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1764
1765 IRDA_ASSERT(self != NULL, return;);
1766 dev = self->netdev;
1767 IRDA_ASSERT(dev != NULL, return;);
1768 dev->hard_start_xmit = &smsc_ircc_hard_xmit_sir;
1769
1770 fir_base = self->io.fir_base;
1771 sir_base = self->io.sir_base;
1772
1773 /* Reset everything */
1774 outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);
1775
1776 #if SMSC_IRCC2_C_SIR_STOP
1777 /*smsc_ircc_sir_stop(self);*/
1778 #endif
1779
1780 register_bank(fir_base, 1);
1781 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base + IRCC_SCE_CFGA);
1782
1783 /* Initialize UART */
1784 outb(UART_LCR_WLEN8, sir_base + UART_LCR); /* Reset DLAB */
1785 outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base + UART_MCR);
1786
1787 /* Turn on interrups */
1788 outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base + UART_IER);
1789
1790 IRDA_DEBUG(3, "%s() - exit\n", __FUNCTION__);
1791
1792 outb(0x00, fir_base + IRCC_MASTER);
1793 }
1794
1795 #if SMSC_IRCC2_C_SIR_STOP
1796 void smsc_ircc_sir_stop(struct smsc_ircc_cb *self)
1797 {
1798 int iobase;
1799
1800 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1801 iobase = self->io.sir_base;
1802
1803 /* Reset UART */
1804 outb(0, iobase + UART_MCR);
1805
1806 /* Turn off interrupts */
1807 outb(0, iobase + UART_IER);
1808 }
1809 #endif
1810
1811 /*
1812 * Function smsc_sir_write_wakeup (self)
1813 *
1814 * Called by the SIR interrupt handler when there's room for more data.
1815 * If we have more packets to send, we send them here.
1816 *
1817 */
1818 static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self)
1819 {
1820 int actual = 0;
1821 int iobase;
1822 int fcr;
1823
1824 IRDA_ASSERT(self != NULL, return;);
1825
1826 IRDA_DEBUG(4, "%s\n", __FUNCTION__);
1827
1828 iobase = self->io.sir_base;
1829
1830 /* Finished with frame? */
1831 if (self->tx_buff.len > 0) {
1832 /* Write data left in transmit buffer */
1833 actual = smsc_ircc_sir_write(iobase, self->io.fifo_size,
1834 self->tx_buff.data, self->tx_buff.len);
1835 self->tx_buff.data += actual;
1836 self->tx_buff.len -= actual;
1837 } else {
1838
1839 /*if (self->tx_buff.len ==0) {*/
1840
1841 /*
1842 * Now serial buffer is almost free & we can start
1843 * transmission of another packet. But first we must check
1844 * if we need to change the speed of the hardware
1845 */
1846 if (self->new_speed) {
1847 IRDA_DEBUG(5, "%s(), Changing speed to %d.\n",
1848 __FUNCTION__, self->new_speed);
1849 smsc_ircc_sir_wait_hw_transmitter_finish(self);
1850 smsc_ircc_change_speed(self, self->new_speed);
1851 self->new_speed = 0;
1852 } else {
1853 /* Tell network layer that we want more frames */
1854 netif_wake_queue(self->netdev);
1855 }
1856 self->stats.tx_packets++;
1857
1858 if (self->io.speed <= 115200) {
1859 /*
1860 * Reset Rx FIFO to make sure that all reflected transmit data
1861 * is discarded. This is needed for half duplex operation
1862 */
1863 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR;
1864 fcr |= self->io.speed < 38400 ?
1865 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
1866
1867 outb(fcr, iobase + UART_FCR);
1868
1869 /* Turn on receive interrupts */
1870 outb(UART_IER_RDI, iobase + UART_IER);
1871 }
1872 }
1873 }
1874
1875 /*
1876 * Function smsc_ircc_sir_write (iobase, fifo_size, buf, len)
1877 *
1878 * Fill Tx FIFO with transmit data
1879 *
1880 */
1881 static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len)
1882 {
1883 int actual = 0;
1884
1885 /* Tx FIFO should be empty! */
1886 if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) {
1887 IRDA_WARNING("%s(), failed, fifo not empty!\n", __FUNCTION__);
1888 return 0;
1889 }
1890
1891 /* Fill FIFO with current frame */
1892 while (fifo_size-- > 0 && actual < len) {
1893 /* Transmit next byte */
1894 outb(buf[actual], iobase + UART_TX);
1895 actual++;
1896 }
1897 return actual;
1898 }
1899
1900 /*
1901 * Function smsc_ircc_is_receiving (self)
1902 *
1903 * Returns true is we are currently receiving data
1904 *
1905 */
1906 static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self)
1907 {
1908 return (self->rx_buff.state != OUTSIDE_FRAME);
1909 }
1910
1911
1912 /*
1913 * Function smsc_ircc_probe_transceiver(self)
1914 *
1915 * Tries to find the used Transceiver
1916 *
1917 */
1918 static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self)
1919 {
1920 unsigned int i;
1921
1922 IRDA_ASSERT(self != NULL, return;);
1923
1924 for (i = 0; smsc_transceivers[i].name != NULL; i++)
1925 if (smsc_transceivers[i].probe(self->io.fir_base)) {
1926 IRDA_MESSAGE(" %s transceiver found\n",
1927 smsc_transceivers[i].name);
1928 self->transceiver= i + 1;
1929 return;
1930 }
1931
1932 IRDA_MESSAGE("No transceiver found. Defaulting to %s\n",
1933 smsc_transceivers[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER].name);
1934
1935 self->transceiver = SMSC_IRCC2_C_DEFAULT_TRANSCEIVER;
1936 }
1937
1938
1939 /*
1940 * Function smsc_ircc_set_transceiver_for_speed(self, speed)
1941 *
1942 * Set the transceiver according to the speed
1943 *
1944 */
1945 static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed)
1946 {
1947 unsigned int trx;
1948
1949 trx = self->transceiver;
1950 if (trx > 0)
1951 smsc_transceivers[trx - 1].set_for_speed(self->io.fir_base, speed);
1952 }
1953
1954 /*
1955 * Function smsc_ircc_wait_hw_transmitter_finish ()
1956 *
1957 * Wait for the real end of HW transmission
1958 *
1959 * The UART is a strict FIFO, and we get called only when we have finished
1960 * pushing data to the FIFO, so the maximum amount of time we must wait
1961 * is only for the FIFO to drain out.
1962 *
1963 * We use a simple calibrated loop. We may need to adjust the loop
1964 * delay (udelay) to balance I/O traffic and latency. And we also need to
1965 * adjust the maximum timeout.
1966 * It would probably be better to wait for the proper interrupt,
1967 * but it doesn't seem to be available.
1968 *
1969 * We can't use jiffies or kernel timers because :
1970 * 1) We are called from the interrupt handler, which disable softirqs,
1971 * so jiffies won't be increased
1972 * 2) Jiffies granularity is usually very coarse (10ms), and we don't
1973 * want to wait that long to detect stuck hardware.
1974 * Jean II
1975 */
1976
1977 static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self)
1978 {
1979 int iobase = self->io.sir_base;
1980 int count = SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US;
1981
1982 /* Calibrated busy loop */
1983 while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT))
1984 udelay(1);
1985
1986 if (count == 0)
1987 IRDA_DEBUG(0, "%s(): stuck transmitter\n", __FUNCTION__);
1988 }
1989
1990
1991 /* PROBING
1992 *
1993 *
1994 */
1995
1996 static int __init smsc_ircc_look_for_chips(void)
1997 {
1998 struct smsc_chip_address *address;
1999 char *type;
2000 unsigned int cfg_base, found;
2001
2002 found = 0;
2003 address = possible_addresses;
2004
2005 while (address->cfg_base) {
2006 cfg_base = address->cfg_base;
2007
2008 /*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __FUNCTION__, cfg_base, address->type);*/
2009
2010 if (address->type & SMSCSIO_TYPE_FDC) {
2011 type = "FDC";
2012 if (address->type & SMSCSIO_TYPE_FLAT)
2013 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, type))
2014 found++;
2015
2016 if (address->type & SMSCSIO_TYPE_PAGED)
2017 if (!smsc_superio_paged(fdc_chips_paged, cfg_base, type))
2018 found++;
2019 }
2020 if (address->type & SMSCSIO_TYPE_LPC) {
2021 type = "LPC";
2022 if (address->type & SMSCSIO_TYPE_FLAT)
2023 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, type))
2024 found++;
2025
2026 if (address->type & SMSCSIO_TYPE_PAGED)
2027 if (!smsc_superio_paged(lpc_chips_paged, cfg_base, type))
2028 found++;
2029 }
2030 address++;
2031 }
2032 return found;
2033 }
2034
2035 /*
2036 * Function smsc_superio_flat (chip, base, type)
2037 *
2038 * Try to get configuration of a smc SuperIO chip with flat register model
2039 *
2040 */
2041 static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfgbase, char *type)
2042 {
2043 unsigned short firbase, sirbase;
2044 u8 mode, dma, irq;
2045 int ret = -ENODEV;
2046
2047 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2048
2049 if (smsc_ircc_probe(cfgbase, SMSCSIOFLAT_DEVICEID_REG, chips, type) == NULL)
2050 return ret;
2051
2052 outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase);
2053 mode = inb(cfgbase + 1);
2054
2055 /*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __FUNCTION__, mode);*/
2056
2057 if (!(mode & SMSCSIOFLAT_UART2MODE_VAL_IRDA))
2058 IRDA_WARNING("%s(): IrDA not enabled\n", __FUNCTION__);
2059
2060 outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase);
2061 sirbase = inb(cfgbase + 1) << 2;
2062
2063 /* FIR iobase */
2064 outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase);
2065 firbase = inb(cfgbase + 1) << 3;
2066
2067 /* DMA */
2068 outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase);
2069 dma = inb(cfgbase + 1) & SMSCSIOFLAT_FIRDMASELECT_MASK;
2070
2071 /* IRQ */
2072 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase);
2073 irq = inb(cfgbase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2074
2075 IRDA_MESSAGE("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n", __FUNCTION__, firbase, sirbase, dma, irq, mode);
2076
2077 if (firbase && smsc_ircc_open(firbase, sirbase, dma, irq) == 0)
2078 ret = 0;
2079
2080 /* Exit configuration */
2081 outb(SMSCSIO_CFGEXITKEY, cfgbase);
2082
2083 return ret;
2084 }
2085
2086 /*
2087 * Function smsc_superio_paged (chip, base, type)
2088 *
2089 * Try to get configuration of a smc SuperIO chip with paged register model
2090 *
2091 */
2092 static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type)
2093 {
2094 unsigned short fir_io, sir_io;
2095 int ret = -ENODEV;
2096
2097 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2098
2099 if (smsc_ircc_probe(cfg_base, 0x20, chips, type) == NULL)
2100 return ret;
2101
2102 /* Select logical device (UART2) */
2103 outb(0x07, cfg_base);
2104 outb(0x05, cfg_base + 1);
2105
2106 /* SIR iobase */
2107 outb(0x60, cfg_base);
2108 sir_io = inb(cfg_base + 1) << 8;
2109 outb(0x61, cfg_base);
2110 sir_io |= inb(cfg_base + 1);
2111
2112 /* Read FIR base */
2113 outb(0x62, cfg_base);
2114 fir_io = inb(cfg_base + 1) << 8;
2115 outb(0x63, cfg_base);
2116 fir_io |= inb(cfg_base + 1);
2117 outb(0x2b, cfg_base); /* ??? */
2118
2119 if (fir_io && smsc_ircc_open(fir_io, sir_io, ircc_dma, ircc_irq) == 0)
2120 ret = 0;
2121
2122 /* Exit configuration */
2123 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2124
2125 return ret;
2126 }
2127
2128
2129 static int __init smsc_access(unsigned short cfg_base, unsigned char reg)
2130 {
2131 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2132
2133 outb(reg, cfg_base);
2134 return inb(cfg_base) != reg ? -1 : 0;
2135 }
2136
2137 static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type)
2138 {
2139 u8 devid, xdevid, rev;
2140
2141 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2142
2143 /* Leave configuration */
2144
2145 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2146
2147 if (inb(cfg_base) == SMSCSIO_CFGEXITKEY) /* not a smc superio chip */
2148 return NULL;
2149
2150 outb(reg, cfg_base);
2151
2152 xdevid = inb(cfg_base + 1);
2153
2154 /* Enter configuration */
2155
2156 outb(SMSCSIO_CFGACCESSKEY, cfg_base);
2157
2158 #if 0
2159 if (smsc_access(cfg_base,0x55)) /* send second key and check */
2160 return NULL;
2161 #endif
2162
2163 /* probe device ID */
2164
2165 if (smsc_access(cfg_base, reg))
2166 return NULL;
2167
2168 devid = inb(cfg_base + 1);
2169
2170 if (devid == 0 || devid == 0xff) /* typical values for unused port */
2171 return NULL;
2172
2173 /* probe revision ID */
2174
2175 if (smsc_access(cfg_base, reg + 1))
2176 return NULL;
2177
2178 rev = inb(cfg_base + 1);
2179
2180 if (rev >= 128) /* i think this will make no sense */
2181 return NULL;
2182
2183 if (devid == xdevid) /* protection against false positives */
2184 return NULL;
2185
2186 /* Check for expected device ID; are there others? */
2187
2188 while (chip->devid != devid) {
2189
2190 chip++;
2191
2192 if (chip->name == NULL)
2193 return NULL;
2194 }
2195
2196 IRDA_MESSAGE("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n",
2197 devid, rev, cfg_base, type, chip->name);
2198
2199 if (chip->rev > rev) {
2200 IRDA_MESSAGE("Revision higher than expected\n");
2201 return NULL;
2202 }
2203
2204 if (chip->flags & NoIRDA)
2205 IRDA_MESSAGE("chipset does not support IRDA\n");
2206
2207 return chip;
2208 }
2209
2210 static int __init smsc_superio_fdc(unsigned short cfg_base)
2211 {
2212 int ret = -1;
2213
2214 if (!request_region(cfg_base, 2, driver_name)) {
2215 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2216 __FUNCTION__, cfg_base);
2217 } else {
2218 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, "FDC") ||
2219 !smsc_superio_paged(fdc_chips_paged, cfg_base, "FDC"))
2220 ret = 0;
2221
2222 release_region(cfg_base, 2);
2223 }
2224
2225 return ret;
2226 }
2227
2228 static int __init smsc_superio_lpc(unsigned short cfg_base)
2229 {
2230 int ret = -1;
2231
2232 if (!request_region(cfg_base, 2, driver_name)) {
2233 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2234 __FUNCTION__, cfg_base);
2235 } else {
2236 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, "LPC") ||
2237 !smsc_superio_paged(lpc_chips_paged, cfg_base, "LPC"))
2238 ret = 0;
2239
2240 release_region(cfg_base, 2);
2241 }
2242 return ret;
2243 }
2244
2245 /************************************************
2246 *
2247 * Transceivers specific functions
2248 *
2249 ************************************************/
2250
2251
2252 /*
2253 * Function smsc_ircc_set_transceiver_smsc_ircc_atc(fir_base, speed)
2254 *
2255 * Program transceiver through smsc-ircc ATC circuitry
2256 *
2257 */
2258
2259 static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed)
2260 {
2261 unsigned long jiffies_now, jiffies_timeout;
2262 u8 val;
2263
2264 jiffies_now = jiffies;
2265 jiffies_timeout = jiffies + SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES;
2266
2267 /* ATC */
2268 register_bank(fir_base, 4);
2269 outb((inb(fir_base + IRCC_ATC) & IRCC_ATC_MASK) | IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE,
2270 fir_base + IRCC_ATC);
2271
2272 while ((val = (inb(fir_base + IRCC_ATC) & IRCC_ATC_nPROGREADY)) &&
2273 !time_after(jiffies, jiffies_timeout))
2274 /* empty */;
2275
2276 if (val)
2277 IRDA_WARNING("%s(): ATC: 0x%02x\n", __FUNCTION__,
2278 inb(fir_base + IRCC_ATC));
2279 }
2280
2281 /*
2282 * Function smsc_ircc_probe_transceiver_smsc_ircc_atc(fir_base)
2283 *
2284 * Probe transceiver smsc-ircc ATC circuitry
2285 *
2286 */
2287
2288 static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base)
2289 {
2290 return 0;
2291 }
2292
2293 /*
2294 * Function smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(self, speed)
2295 *
2296 * Set transceiver
2297 *
2298 */
2299
2300 static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed)
2301 {
2302 u8 fast_mode;
2303
2304 switch (speed) {
2305 default:
2306 case 576000 :
2307 fast_mode = 0;
2308 break;
2309 case 1152000 :
2310 case 4000000 :
2311 fast_mode = IRCC_LCR_A_FAST;
2312 break;
2313 }
2314 register_bank(fir_base, 0);
2315 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
2316 }
2317
2318 /*
2319 * Function smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(fir_base)
2320 *
2321 * Probe transceiver
2322 *
2323 */
2324
2325 static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base)
2326 {
2327 return 0;
2328 }
2329
2330 /*
2331 * Function smsc_ircc_set_transceiver_toshiba_sat1800(fir_base, speed)
2332 *
2333 * Set transceiver
2334 *
2335 */
2336
2337 static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed)
2338 {
2339 u8 fast_mode;
2340
2341 switch (speed) {
2342 default:
2343 case 576000 :
2344 fast_mode = 0;
2345 break;
2346 case 1152000 :
2347 case 4000000 :
2348 fast_mode = /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA;
2349 break;
2350
2351 }
2352 /* This causes an interrupt */
2353 register_bank(fir_base, 0);
2354 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
2355 }
2356
2357 /*
2358 * Function smsc_ircc_probe_transceiver_toshiba_sat1800(fir_base)
2359 *
2360 * Probe transceiver
2361 *
2362 */
2363
2364 static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base)
2365 {
2366 return 0;
2367 }
2368
2369
2370 module_init(smsc_ircc_init);
2371 module_exit(smsc_ircc_cleanup);
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