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[PATCH] w1: Fixed 64bit compilation warning.
[linux-2.6/verdex.git] / drivers / pci / probe.c
blob93e8a878ea951d379c2c1af147193928c728c480
1 /*
2 * probe.c - PCI detection and setup code
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include "pci.h"
13
14 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
15 #define CARDBUS_RESERVE_BUSNR 3
16 #define PCI_CFG_SPACE_SIZE 256
17 #define PCI_CFG_SPACE_EXP_SIZE 4096
18
19 /* Ugh. Need to stop exporting this to modules. */
20 LIST_HEAD(pci_root_buses);
21 EXPORT_SYMBOL(pci_root_buses);
22
23 LIST_HEAD(pci_devices);
24
25 #ifdef HAVE_PCI_LEGACY
26 /**
27 * pci_create_legacy_files - create legacy I/O port and memory files
28 * @b: bus to create files under
29 *
30 * Some platforms allow access to legacy I/O port and ISA memory space on
31 * a per-bus basis. This routine creates the files and ties them into
32 * their associated read, write and mmap files from pci-sysfs.c
33 */
34 static void pci_create_legacy_files(struct pci_bus *b)
35 {
36 b->legacy_io = kmalloc(sizeof(struct bin_attribute) * 2,
37 GFP_ATOMIC);
38 if (b->legacy_io) {
39 memset(b->legacy_io, 0, sizeof(struct bin_attribute) * 2);
40 b->legacy_io->attr.name = "legacy_io";
41 b->legacy_io->size = 0xffff;
42 b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
43 b->legacy_io->attr.owner = THIS_MODULE;
44 b->legacy_io->read = pci_read_legacy_io;
45 b->legacy_io->write = pci_write_legacy_io;
46 class_device_create_bin_file(&b->class_dev, b->legacy_io);
47
48 /* Allocated above after the legacy_io struct */
49 b->legacy_mem = b->legacy_io + 1;
50 b->legacy_mem->attr.name = "legacy_mem";
51 b->legacy_mem->size = 1024*1024;
52 b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
53 b->legacy_mem->attr.owner = THIS_MODULE;
54 b->legacy_mem->mmap = pci_mmap_legacy_mem;
55 class_device_create_bin_file(&b->class_dev, b->legacy_mem);
56 }
57 }
58
59 void pci_remove_legacy_files(struct pci_bus *b)
60 {
61 if (b->legacy_io) {
62 class_device_remove_bin_file(&b->class_dev, b->legacy_io);
63 class_device_remove_bin_file(&b->class_dev, b->legacy_mem);
64 kfree(b->legacy_io); /* both are allocated here */
65 }
66 }
67 #else /* !HAVE_PCI_LEGACY */
68 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
69 void pci_remove_legacy_files(struct pci_bus *bus) { return; }
70 #endif /* HAVE_PCI_LEGACY */
71
72 /*
73 * PCI Bus Class Devices
74 */
75 static ssize_t pci_bus_show_cpuaffinity(struct class_device *class_dev, char *buf)
76 {
77 cpumask_t cpumask = pcibus_to_cpumask(to_pci_bus(class_dev));
78 int ret;
79
80 ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask);
81 if (ret < PAGE_SIZE)
82 buf[ret++] = '\n';
83 return ret;
84 }
85 CLASS_DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL);
86
87 /*
88 * PCI Bus Class
89 */
90 static void release_pcibus_dev(struct class_device *class_dev)
91 {
92 struct pci_bus *pci_bus = to_pci_bus(class_dev);
93
94 if (pci_bus->bridge)
95 put_device(pci_bus->bridge);
96 kfree(pci_bus);
97 }
98
99 static struct class pcibus_class = {
100 .name = "pci_bus",
101 .release = &release_pcibus_dev,
102 };
103
104 static int __init pcibus_class_init(void)
105 {
106 return class_register(&pcibus_class);
107 }
108 postcore_initcall(pcibus_class_init);
109
110 /*
111 * Translate the low bits of the PCI base
112 * to the resource type
113 */
114 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
115 {
116 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
117 return IORESOURCE_IO;
118
119 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
120 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
121
122 return IORESOURCE_MEM;
123 }
124
125 /*
126 * Find the extent of a PCI decode..
127 */
128 static u32 pci_size(u32 base, u32 maxbase, u32 mask)
129 {
130 u32 size = mask & maxbase; /* Find the significant bits */
131 if (!size)
132 return 0;
133
134 /* Get the lowest of them to find the decode size, and
135 from that the extent. */
136 size = (size & ~(size-1)) - 1;
137
138 /* base == maxbase can be valid only if the BAR has
139 already been programmed with all 1s. */
140 if (base == maxbase && ((base | size) & mask) != mask)
141 return 0;
142
143 return size;
144 }
145
146 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
147 {
148 unsigned int pos, reg, next;
149 u32 l, sz;
150 struct resource *res;
151
152 for(pos=0; pos<howmany; pos = next) {
153 next = pos+1;
154 res = &dev->resource[pos];
155 res->name = pci_name(dev);
156 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
157 pci_read_config_dword(dev, reg, &l);
158 pci_write_config_dword(dev, reg, ~0);
159 pci_read_config_dword(dev, reg, &sz);
160 pci_write_config_dword(dev, reg, l);
161 if (!sz || sz == 0xffffffff)
162 continue;
163 if (l == 0xffffffff)
164 l = 0;
165 if ((l & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) {
166 sz = pci_size(l, sz, PCI_BASE_ADDRESS_MEM_MASK);
167 if (!sz)
168 continue;
169 res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
170 res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
171 } else {
172 sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
173 if (!sz)
174 continue;
175 res->start = l & PCI_BASE_ADDRESS_IO_MASK;
176 res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
177 }
178 res->end = res->start + (unsigned long) sz;
179 res->flags |= pci_calc_resource_flags(l);
180 if ((l & (PCI_BASE_ADDRESS_SPACE | PCI_BASE_ADDRESS_MEM_TYPE_MASK))
181 == (PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64)) {
182 pci_read_config_dword(dev, reg+4, &l);
183 next++;
184 #if BITS_PER_LONG == 64
185 res->start |= ((unsigned long) l) << 32;
186 res->end = res->start + sz;
187 pci_write_config_dword(dev, reg+4, ~0);
188 pci_read_config_dword(dev, reg+4, &sz);
189 pci_write_config_dword(dev, reg+4, l);
190 sz = pci_size(l, sz, 0xffffffff);
191 if (sz) {
192 /* This BAR needs > 4GB? Wow. */
193 res->end |= (unsigned long)sz<<32;
194 }
195 #else
196 if (l) {
197 printk(KERN_ERR "PCI: Unable to handle 64-bit address for device %s\n", pci_name(dev));
198 res->start = 0;
199 res->flags = 0;
200 continue;
201 }
202 #endif
203 }
204 }
205 if (rom) {
206 dev->rom_base_reg = rom;
207 res = &dev->resource[PCI_ROM_RESOURCE];
208 res->name = pci_name(dev);
209 pci_read_config_dword(dev, rom, &l);
210 pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
211 pci_read_config_dword(dev, rom, &sz);
212 pci_write_config_dword(dev, rom, l);
213 if (l == 0xffffffff)
214 l = 0;
215 if (sz && sz != 0xffffffff) {
216 sz = pci_size(l, sz, PCI_ROM_ADDRESS_MASK);
217 if (sz) {
218 res->flags = (l & IORESOURCE_ROM_ENABLE) |
219 IORESOURCE_MEM | IORESOURCE_PREFETCH |
220 IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
221 res->start = l & PCI_ROM_ADDRESS_MASK;
222 res->end = res->start + (unsigned long) sz;
223 }
224 }
225 }
226 }
227
228 void __devinit pci_read_bridge_bases(struct pci_bus *child)
229 {
230 struct pci_dev *dev = child->self;
231 u8 io_base_lo, io_limit_lo;
232 u16 mem_base_lo, mem_limit_lo;
233 unsigned long base, limit;
234 struct resource *res;
235 int i;
236
237 if (!dev) /* It's a host bus, nothing to read */
238 return;
239
240 if (dev->transparent) {
241 printk(KERN_INFO "PCI: Transparent bridge - %s\n", pci_name(dev));
242 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
243 child->resource[i] = child->parent->resource[i - 3];
244 }
245
246 for(i=0; i<3; i++)
247 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
248
249 res = child->resource[0];
250 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
251 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
252 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
253 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
254
255 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
256 u16 io_base_hi, io_limit_hi;
257 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
258 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
259 base |= (io_base_hi << 16);
260 limit |= (io_limit_hi << 16);
261 }
262
263 if (base <= limit) {
264 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
265 res->start = base;
266 res->end = limit + 0xfff;
267 }
268
269 res = child->resource[1];
270 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
271 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
272 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
273 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
274 if (base <= limit) {
275 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
276 res->start = base;
277 res->end = limit + 0xfffff;
278 }
279
280 res = child->resource[2];
281 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
282 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
283 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
284 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
285
286 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
287 u32 mem_base_hi, mem_limit_hi;
288 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
289 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
290
291 /*
292 * Some bridges set the base > limit by default, and some
293 * (broken) BIOSes do not initialize them. If we find
294 * this, just assume they are not being used.
295 */
296 if (mem_base_hi <= mem_limit_hi) {
297 #if BITS_PER_LONG == 64
298 base |= ((long) mem_base_hi) << 32;
299 limit |= ((long) mem_limit_hi) << 32;
300 #else
301 if (mem_base_hi || mem_limit_hi) {
302 printk(KERN_ERR "PCI: Unable to handle 64-bit address space for bridge %s\n", pci_name(dev));
303 return;
304 }
305 #endif
306 }
307 }
308 if (base <= limit) {
309 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
310 res->start = base;
311 res->end = limit + 0xfffff;
312 }
313 }
314
315 static struct pci_bus * __devinit pci_alloc_bus(void)
316 {
317 struct pci_bus *b;
318
319 b = kmalloc(sizeof(*b), GFP_KERNEL);
320 if (b) {
321 memset(b, 0, sizeof(*b));
322 INIT_LIST_HEAD(&b->node);
323 INIT_LIST_HEAD(&b->children);
324 INIT_LIST_HEAD(&b->devices);
325 }
326 return b;
327 }
328
329 static struct pci_bus * __devinit
330 pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr)
331 {
332 struct pci_bus *child;
333 int i;
334
335 /*
336 * Allocate a new bus, and inherit stuff from the parent..
337 */
338 child = pci_alloc_bus();
339 if (!child)
340 return NULL;
341
342 child->self = bridge;
343 child->parent = parent;
344 child->ops = parent->ops;
345 child->sysdata = parent->sysdata;
346 child->bridge = get_device(&bridge->dev);
347
348 child->class_dev.class = &pcibus_class;
349 sprintf(child->class_dev.class_id, "%04x:%02x", pci_domain_nr(child), busnr);
350 class_device_register(&child->class_dev);
351 class_device_create_file(&child->class_dev, &class_device_attr_cpuaffinity);
352
353 /*
354 * Set up the primary, secondary and subordinate
355 * bus numbers.
356 */
357 child->number = child->secondary = busnr;
358 child->primary = parent->secondary;
359 child->subordinate = 0xff;
360
361 /* Set up default resource pointers and names.. */
362 for (i = 0; i < 4; i++) {
363 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
364 child->resource[i]->name = child->name;
365 }
366 bridge->subordinate = child;
367
368 return child;
369 }
370
371 struct pci_bus * __devinit pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
372 {
373 struct pci_bus *child;
374
375 child = pci_alloc_child_bus(parent, dev, busnr);
376 if (child) {
377 spin_lock(&pci_bus_lock);
378 list_add_tail(&child->node, &parent->children);
379 spin_unlock(&pci_bus_lock);
380 }
381 return child;
382 }
383
384 static void pci_enable_crs(struct pci_dev *dev)
385 {
386 u16 cap, rpctl;
387 int rpcap = pci_find_capability(dev, PCI_CAP_ID_EXP);
388 if (!rpcap)
389 return;
390
391 pci_read_config_word(dev, rpcap + PCI_CAP_FLAGS, &cap);
392 if (((cap & PCI_EXP_FLAGS_TYPE) >> 4) != PCI_EXP_TYPE_ROOT_PORT)
393 return;
394
395 pci_read_config_word(dev, rpcap + PCI_EXP_RTCTL, &rpctl);
396 rpctl |= PCI_EXP_RTCTL_CRSSVE;
397 pci_write_config_word(dev, rpcap + PCI_EXP_RTCTL, rpctl);
398 }
399
400 static void __devinit pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
401 {
402 struct pci_bus *parent = child->parent;
403 while (parent->parent && parent->subordinate < max) {
404 parent->subordinate = max;
405 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
406 parent = parent->parent;
407 }
408 }
409
410 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus);
411
412 /*
413 * If it's a bridge, configure it and scan the bus behind it.
414 * For CardBus bridges, we don't scan behind as the devices will
415 * be handled by the bridge driver itself.
416 *
417 * We need to process bridges in two passes -- first we scan those
418 * already configured by the BIOS and after we are done with all of
419 * them, we proceed to assigning numbers to the remaining buses in
420 * order to avoid overlaps between old and new bus numbers.
421 */
422 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass)
423 {
424 struct pci_bus *child;
425 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
426 u32 buses, i;
427 u16 bctl;
428
429 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
430
431 pr_debug("PCI: Scanning behind PCI bridge %s, config %06x, pass %d\n",
432 pci_name(dev), buses & 0xffffff, pass);
433
434 /* Disable MasterAbortMode during probing to avoid reporting
435 of bus errors (in some architectures) */
436 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
437 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
438 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
439
440 pci_enable_crs(dev);
441
442 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
443 unsigned int cmax, busnr;
444 /*
445 * Bus already configured by firmware, process it in the first
446 * pass and just note the configuration.
447 */
448 if (pass)
449 return max;
450 busnr = (buses >> 8) & 0xFF;
451
452 /*
453 * If we already got to this bus through a different bridge,
454 * ignore it. This can happen with the i450NX chipset.
455 */
456 if (pci_find_bus(pci_domain_nr(bus), busnr)) {
457 printk(KERN_INFO "PCI: Bus %04x:%02x already known\n",
458 pci_domain_nr(bus), busnr);
459 return max;
460 }
461
462 child = pci_add_new_bus(bus, dev, busnr);
463 if (!child)
464 return max;
465 child->primary = buses & 0xFF;
466 child->subordinate = (buses >> 16) & 0xFF;
467 child->bridge_ctl = bctl;
468
469 cmax = pci_scan_child_bus(child);
470 if (cmax > max)
471 max = cmax;
472 if (child->subordinate > max)
473 max = child->subordinate;
474 } else {
475 /*
476 * We need to assign a number to this bus which we always
477 * do in the second pass.
478 */
479 if (!pass)
480 return max;
481
482 /* Clear errors */
483 pci_write_config_word(dev, PCI_STATUS, 0xffff);
484
485 /* Prevent assigning a bus number that already exists.
486 * This can happen when a bridge is hot-plugged */
487 if (pci_find_bus(pci_domain_nr(bus), max+1))
488 return max;
489 child = pci_add_new_bus(bus, dev, ++max);
490 buses = (buses & 0xff000000)
491 | ((unsigned int)(child->primary) << 0)
492 | ((unsigned int)(child->secondary) << 8)
493 | ((unsigned int)(child->subordinate) << 16);
494
495 /*
496 * yenta.c forces a secondary latency timer of 176.
497 * Copy that behaviour here.
498 */
499 if (is_cardbus) {
500 buses &= ~0xff000000;
501 buses |= CARDBUS_LATENCY_TIMER << 24;
502 }
503
504 /*
505 * We need to blast all three values with a single write.
506 */
507 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
508
509 if (!is_cardbus) {
510 child->bridge_ctl = bctl | PCI_BRIDGE_CTL_NO_ISA;
511 /*
512 * Adjust subordinate busnr in parent buses.
513 * We do this before scanning for children because
514 * some devices may not be detected if the bios
515 * was lazy.
516 */
517 pci_fixup_parent_subordinate_busnr(child, max);
518 /* Now we can scan all subordinate buses... */
519 max = pci_scan_child_bus(child);
520 } else {
521 /*
522 * For CardBus bridges, we leave 4 bus numbers
523 * as cards with a PCI-to-PCI bridge can be
524 * inserted later.
525 */
526 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++)
527 if (pci_find_bus(pci_domain_nr(bus),
528 max+i+1))
529 break;
530 max += i;
531 pci_fixup_parent_subordinate_busnr(child, max);
532 }
533 /*
534 * Set the subordinate bus number to its real value.
535 */
536 child->subordinate = max;
537 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
538 }
539
540 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
541
542 sprintf(child->name, (is_cardbus ? "PCI CardBus #%02x" : "PCI Bus #%02x"), child->number);
543
544 return max;
545 }
546
547 /*
548 * Read interrupt line and base address registers.
549 * The architecture-dependent code can tweak these, of course.
550 */
551 static void pci_read_irq(struct pci_dev *dev)
552 {
553 unsigned char irq;
554
555 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
556 if (irq)
557 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
558 dev->irq = irq;
559 }
560
561 /**
562 * pci_setup_device - fill in class and map information of a device
563 * @dev: the device structure to fill
564 *
565 * Initialize the device structure with information about the device's
566 * vendor,class,memory and IO-space addresses,IRQ lines etc.
567 * Called at initialisation of the PCI subsystem and by CardBus services.
568 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
569 * or CardBus).
570 */
571 static int pci_setup_device(struct pci_dev * dev)
572 {
573 u32 class;
574
575 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
576 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
577
578 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
579 class >>= 8; /* upper 3 bytes */
580 dev->class = class;
581 class >>= 8;
582
583 pr_debug("PCI: Found %s [%04x/%04x] %06x %02x\n", pci_name(dev),
584 dev->vendor, dev->device, class, dev->hdr_type);
585
586 /* "Unknown power state" */
587 dev->current_state = 4;
588
589 /* Early fixups, before probing the BARs */
590 pci_fixup_device(pci_fixup_early, dev);
591 class = dev->class >> 8;
592
593 switch (dev->hdr_type) { /* header type */
594 case PCI_HEADER_TYPE_NORMAL: /* standard header */
595 if (class == PCI_CLASS_BRIDGE_PCI)
596 goto bad;
597 pci_read_irq(dev);
598 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
599 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
600 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
601 break;
602
603 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
604 if (class != PCI_CLASS_BRIDGE_PCI)
605 goto bad;
606 /* The PCI-to-PCI bridge spec requires that subtractive
607 decoding (i.e. transparent) bridge must have programming
608 interface code of 0x01. */
609 dev->transparent = ((dev->class & 0xff) == 1);
610 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
611 break;
612
613 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
614 if (class != PCI_CLASS_BRIDGE_CARDBUS)
615 goto bad;
616 pci_read_irq(dev);
617 pci_read_bases(dev, 1, 0);
618 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
619 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
620 break;
621
622 default: /* unknown header */
623 printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
624 pci_name(dev), dev->hdr_type);
625 return -1;
626
627 bad:
628 printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
629 pci_name(dev), class, dev->hdr_type);
630 dev->class = PCI_CLASS_NOT_DEFINED;
631 }
632
633 /* We found a fine healthy device, go go go... */
634 return 0;
635 }
636
637 /**
638 * pci_release_dev - free a pci device structure when all users of it are finished.
639 * @dev: device that's been disconnected
640 *
641 * Will be called only by the device core when all users of this pci device are
642 * done.
643 */
644 static void pci_release_dev(struct device *dev)
645 {
646 struct pci_dev *pci_dev;
647
648 pci_dev = to_pci_dev(dev);
649 kfree(pci_dev);
650 }
651
652 /**
653 * pci_cfg_space_size - get the configuration space size of the PCI device.
654 *
655 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
656 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
657 * access it. Maybe we don't have a way to generate extended config space
658 * accesses, or the device is behind a reverse Express bridge. So we try
659 * reading the dword at 0x100 which must either be 0 or a valid extended
660 * capability header.
661 */
662 static int pci_cfg_space_size(struct pci_dev *dev)
663 {
664 int pos;
665 u32 status;
666
667 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
668 if (!pos) {
669 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
670 if (!pos)
671 goto fail;
672
673 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
674 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
675 goto fail;
676 }
677
678 if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
679 goto fail;
680 if (status == 0xffffffff)
681 goto fail;
682
683 return PCI_CFG_SPACE_EXP_SIZE;
684
685 fail:
686 return PCI_CFG_SPACE_SIZE;
687 }
688
689 static void pci_release_bus_bridge_dev(struct device *dev)
690 {
691 kfree(dev);
692 }
693
694 /*
695 * Read the config data for a PCI device, sanity-check it
696 * and fill in the dev structure...
697 */
698 static struct pci_dev * __devinit
699 pci_scan_device(struct pci_bus *bus, int devfn)
700 {
701 struct pci_dev *dev;
702 u32 l;
703 u8 hdr_type;
704 int delay = 1;
705
706 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
707 return NULL;
708
709 /* some broken boards return 0 or ~0 if a slot is empty: */
710 if (l == 0xffffffff || l == 0x00000000 ||
711 l == 0x0000ffff || l == 0xffff0000)
712 return NULL;
713
714 /* Configuration request Retry Status */
715 while (l == 0xffff0001) {
716 msleep(delay);
717 delay *= 2;
718 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
719 return NULL;
720 /* Card hasn't responded in 60 seconds? Must be stuck. */
721 if (delay > 60 * 1000) {
722 printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
723 "responding\n", pci_domain_nr(bus),
724 bus->number, PCI_SLOT(devfn),
725 PCI_FUNC(devfn));
726 return NULL;
727 }
728 }
729
730 if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
731 return NULL;
732
733 dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL);
734 if (!dev)
735 return NULL;
736
737 memset(dev, 0, sizeof(struct pci_dev));
738 dev->bus = bus;
739 dev->sysdata = bus->sysdata;
740 dev->dev.parent = bus->bridge;
741 dev->dev.bus = &pci_bus_type;
742 dev->devfn = devfn;
743 dev->hdr_type = hdr_type & 0x7f;
744 dev->multifunction = !!(hdr_type & 0x80);
745 dev->vendor = l & 0xffff;
746 dev->device = (l >> 16) & 0xffff;
747 dev->cfg_size = pci_cfg_space_size(dev);
748
749 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
750 set this higher, assuming the system even supports it. */
751 dev->dma_mask = 0xffffffff;
752 if (pci_setup_device(dev) < 0) {
753 kfree(dev);
754 return NULL;
755 }
756 device_initialize(&dev->dev);
757 dev->dev.release = pci_release_dev;
758 pci_dev_get(dev);
759
760 pci_name_device(dev);
761
762 dev->dev.dma_mask = &dev->dma_mask;
763 dev->dev.coherent_dma_mask = 0xffffffffull;
764
765 return dev;
766 }
767
768 struct pci_dev * __devinit
769 pci_scan_single_device(struct pci_bus *bus, int devfn)
770 {
771 struct pci_dev *dev;
772
773 dev = pci_scan_device(bus, devfn);
774 pci_scan_msi_device(dev);
775
776 if (!dev)
777 return NULL;
778
779 /* Fix up broken headers */
780 pci_fixup_device(pci_fixup_header, dev);
781
782 /*
783 * Add the device to our list of discovered devices
784 * and the bus list for fixup functions, etc.
785 */
786 INIT_LIST_HEAD(&dev->global_list);
787 spin_lock(&pci_bus_lock);
788 list_add_tail(&dev->bus_list, &bus->devices);
789 spin_unlock(&pci_bus_lock);
790
791 return dev;
792 }
793
794 /**
795 * pci_scan_slot - scan a PCI slot on a bus for devices.
796 * @bus: PCI bus to scan
797 * @devfn: slot number to scan (must have zero function.)
798 *
799 * Scan a PCI slot on the specified PCI bus for devices, adding
800 * discovered devices to the @bus->devices list. New devices
801 * will have an empty dev->global_list head.
802 */
803 int __devinit pci_scan_slot(struct pci_bus *bus, int devfn)
804 {
805 int func, nr = 0;
806 int scan_all_fns;
807
808 scan_all_fns = pcibios_scan_all_fns(bus, devfn);
809
810 for (func = 0; func < 8; func++, devfn++) {
811 struct pci_dev *dev;
812
813 dev = pci_scan_single_device(bus, devfn);
814 if (dev) {
815 nr++;
816
817 /*
818 * If this is a single function device,
819 * don't scan past the first function.
820 */
821 if (!dev->multifunction) {
822 if (func > 0) {
823 dev->multifunction = 1;
824 } else {
825 break;
826 }
827 }
828 } else {
829 if (func == 0 && !scan_all_fns)
830 break;
831 }
832 }
833 return nr;
834 }
835
836 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
837 {
838 unsigned int devfn, pass, max = bus->secondary;
839 struct pci_dev *dev;
840
841 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
842
843 /* Go find them, Rover! */
844 for (devfn = 0; devfn < 0x100; devfn += 8)
845 pci_scan_slot(bus, devfn);
846
847 /*
848 * After performing arch-dependent fixup of the bus, look behind
849 * all PCI-to-PCI bridges on this bus.
850 */
851 pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
852 pcibios_fixup_bus(bus);
853 for (pass=0; pass < 2; pass++)
854 list_for_each_entry(dev, &bus->devices, bus_list) {
855 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
856 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
857 max = pci_scan_bridge(bus, dev, max, pass);
858 }
859
860 /*
861 * We've scanned the bus and so we know all about what's on
862 * the other side of any bridges that may be on this bus plus
863 * any devices.
864 *
865 * Return how far we've got finding sub-buses.
866 */
867 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
868 pci_domain_nr(bus), bus->number, max);
869 return max;
870 }
871
872 unsigned int __devinit pci_do_scan_bus(struct pci_bus *bus)
873 {
874 unsigned int max;
875
876 max = pci_scan_child_bus(bus);
877
878 /*
879 * Make the discovered devices available.
880 */
881 pci_bus_add_devices(bus);
882
883 return max;
884 }
885
886 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent, int bus, struct pci_ops *ops, void *sysdata)
887 {
888 int error;
889 struct pci_bus *b;
890 struct device *dev;
891
892 b = pci_alloc_bus();
893 if (!b)
894 return NULL;
895
896 dev = kmalloc(sizeof(*dev), GFP_KERNEL);
897 if (!dev){
898 kfree(b);
899 return NULL;
900 }
901
902 b->sysdata = sysdata;
903 b->ops = ops;
904
905 if (pci_find_bus(pci_domain_nr(b), bus)) {
906 /* If we already got to this bus through a different bridge, ignore it */
907 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
908 goto err_out;
909 }
910 spin_lock(&pci_bus_lock);
911 list_add_tail(&b->node, &pci_root_buses);
912 spin_unlock(&pci_bus_lock);
913
914 memset(dev, 0, sizeof(*dev));
915 dev->parent = parent;
916 dev->release = pci_release_bus_bridge_dev;
917 sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus);
918 error = device_register(dev);
919 if (error)
920 goto dev_reg_err;
921 b->bridge = get_device(dev);
922
923 b->class_dev.class = &pcibus_class;
924 sprintf(b->class_dev.class_id, "%04x:%02x", pci_domain_nr(b), bus);
925 error = class_device_register(&b->class_dev);
926 if (error)
927 goto class_dev_reg_err;
928 error = class_device_create_file(&b->class_dev, &class_device_attr_cpuaffinity);
929 if (error)
930 goto class_dev_create_file_err;
931
932 /* Create legacy_io and legacy_mem files for this bus */
933 pci_create_legacy_files(b);
934
935 error = sysfs_create_link(&b->class_dev.kobj, &b->bridge->kobj, "bridge");
936 if (error)
937 goto sys_create_link_err;
938
939 b->number = b->secondary = bus;
940 b->resource[0] = &ioport_resource;
941 b->resource[1] = &iomem_resource;
942
943 b->subordinate = pci_scan_child_bus(b);
944
945 return b;
946
947 sys_create_link_err:
948 class_device_remove_file(&b->class_dev, &class_device_attr_cpuaffinity);
949 class_dev_create_file_err:
950 class_device_unregister(&b->class_dev);
951 class_dev_reg_err:
952 device_unregister(dev);
953 dev_reg_err:
954 spin_lock(&pci_bus_lock);
955 list_del(&b->node);
956 spin_unlock(&pci_bus_lock);
957 err_out:
958 kfree(dev);
959 kfree(b);
960 return NULL;
961 }
962 EXPORT_SYMBOL(pci_scan_bus_parented);
963
964 #ifdef CONFIG_HOTPLUG
965 EXPORT_SYMBOL(pci_add_new_bus);
966 EXPORT_SYMBOL(pci_do_scan_bus);
967 EXPORT_SYMBOL(pci_scan_slot);
968 EXPORT_SYMBOL(pci_scan_bridge);
969 EXPORT_SYMBOL(pci_scan_single_device);
970 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
971 #endif
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