2 * linux/drivers/char/synclink.c
4 * $Id: synclink.c,v 4.37 2005/09/07 13:13:19 paulkf Exp $
6 * Device driver for Microgate SyncLink ISA and PCI
7 * high speed multiprotocol serial adapters.
9 * written by Paul Fulghum for Microgate Corporation
10 * paulkf@microgate.com
12 * Microgate and SyncLink are trademarks of Microgate Corporation
14 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
16 * Original release 01/11/99
18 * This code is released under the GNU General Public License (GPL)
20 * This driver is primarily intended for use in synchronous
21 * HDLC mode. Asynchronous mode is also provided.
23 * When operating in synchronous mode, each call to mgsl_write()
24 * contains exactly one complete HDLC frame. Calling mgsl_put_char
25 * will start assembling an HDLC frame that will not be sent until
26 * mgsl_flush_chars or mgsl_write is called.
28 * Synchronous receive data is reported as complete frames. To accomplish
29 * this, the TTY flip buffer is bypassed (too small to hold largest
30 * frame and may fragment frames) and the line discipline
31 * receive entry point is called directly.
33 * This driver has been tested with a slightly modified ppp.c driver
34 * for synchronous PPP.
37 * Added interface for syncppp.c driver (an alternate synchronous PPP
38 * implementation that also supports Cisco HDLC). Each device instance
39 * registers as a tty device AND a network device (if dosyncppp option
40 * is set for the device). The functionality is determined by which
41 * device interface is opened.
43 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
44 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
45 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
46 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
47 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
48 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
49 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
50 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
51 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
53 * OF THE POSSIBILITY OF SUCH DAMAGE.
57 # define BREAKPOINT() asm(" int $3");
59 # define BREAKPOINT() { }
62 #define MAX_ISA_DEVICES 10
63 #define MAX_PCI_DEVICES 10
64 #define MAX_TOTAL_DEVICES 20
66 #include <linux/config.h>
67 #include <linux/module.h>
68 #include <linux/errno.h>
69 #include <linux/signal.h>
70 #include <linux/sched.h>
71 #include <linux/timer.h>
72 #include <linux/interrupt.h>
73 #include <linux/pci.h>
74 #include <linux/tty.h>
75 #include <linux/tty_flip.h>
76 #include <linux/serial.h>
77 #include <linux/major.h>
78 #include <linux/string.h>
79 #include <linux/fcntl.h>
80 #include <linux/ptrace.h>
81 #include <linux/ioport.h>
83 #include <linux/slab.h>
84 #include <linux/delay.h>
86 #include <linux/netdevice.h>
88 #include <linux/vmalloc.h>
89 #include <linux/init.h>
90 #include <asm/serial.h>
92 #include <linux/delay.h>
93 #include <linux/ioctl.h>
95 #include <asm/system.h>
99 #include <linux/bitops.h>
100 #include <asm/types.h>
101 #include <linux/termios.h>
102 #include <linux/workqueue.h>
103 #include <linux/hdlc.h>
105 #ifdef CONFIG_HDLC_MODULE
106 #define CONFIG_HDLC 1
109 #define GET_USER(error,value,addr) error = get_user(value,addr)
110 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
111 #define PUT_USER(error,value,addr) error = put_user(value,addr)
112 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
114 #include <asm/uaccess.h>
116 #include "linux/synclink.h"
118 #define RCLRVALUE 0xffff
120 static MGSL_PARAMS default_params
= {
121 MGSL_MODE_HDLC
, /* unsigned long mode */
122 0, /* unsigned char loopback; */
123 HDLC_FLAG_UNDERRUN_ABORT15
, /* unsigned short flags; */
124 HDLC_ENCODING_NRZI_SPACE
, /* unsigned char encoding; */
125 0, /* unsigned long clock_speed; */
126 0xff, /* unsigned char addr_filter; */
127 HDLC_CRC_16_CCITT
, /* unsigned short crc_type; */
128 HDLC_PREAMBLE_LENGTH_8BITS
, /* unsigned char preamble_length; */
129 HDLC_PREAMBLE_PATTERN_NONE
, /* unsigned char preamble; */
130 9600, /* unsigned long data_rate; */
131 8, /* unsigned char data_bits; */
132 1, /* unsigned char stop_bits; */
133 ASYNC_PARITY_NONE
/* unsigned char parity; */
136 #define SHARED_MEM_ADDRESS_SIZE 0x40000
137 #define BUFFERLISTSIZE (PAGE_SIZE)
138 #define DMABUFFERSIZE (PAGE_SIZE)
139 #define MAXRXFRAMES 7
141 typedef struct _DMABUFFERENTRY
143 u32 phys_addr
; /* 32-bit flat physical address of data buffer */
144 volatile u16 count
; /* buffer size/data count */
145 volatile u16 status
; /* Control/status field */
146 volatile u16 rcc
; /* character count field */
147 u16 reserved
; /* padding required by 16C32 */
148 u32 link
; /* 32-bit flat link to next buffer entry */
149 char *virt_addr
; /* virtual address of data buffer */
150 u32 phys_entry
; /* physical address of this buffer entry */
151 } DMABUFFERENTRY
, *DMAPBUFFERENTRY
;
153 /* The queue of BH actions to be performed */
156 #define BH_TRANSMIT 2
159 #define IO_PIN_SHUTDOWN_LIMIT 100
161 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
163 struct _input_signal_events
{
174 /* transmit holding buffer definitions*/
175 #define MAX_TX_HOLDING_BUFFERS 5
176 struct tx_holding_buffer
{
178 unsigned char * buffer
;
183 * Device instance data structure
189 int count
; /* count of opens */
192 unsigned short close_delay
;
193 unsigned short closing_wait
; /* time to wait before closing */
195 struct mgsl_icount icount
;
197 struct tty_struct
*tty
;
199 int x_char
; /* xon/xoff character */
200 int blocked_open
; /* # of blocked opens */
201 u16 read_status_mask
;
202 u16 ignore_status_mask
;
203 unsigned char *xmit_buf
;
208 wait_queue_head_t open_wait
;
209 wait_queue_head_t close_wait
;
211 wait_queue_head_t status_event_wait_q
;
212 wait_queue_head_t event_wait_q
;
213 struct timer_list tx_timer
; /* HDLC transmit timeout timer */
214 struct mgsl_struct
*next_device
; /* device list link */
216 spinlock_t irq_spinlock
; /* spinlock for synchronizing with ISR */
217 struct work_struct task
; /* task structure for scheduling bh */
219 u32 EventMask
; /* event trigger mask */
220 u32 RecordedEvents
; /* pending events */
222 u32 max_frame_size
; /* as set by device config */
226 int bh_running
; /* Protection from multiple */
230 int dcd_chkcount
; /* check counts to prevent */
231 int cts_chkcount
; /* too many IRQs if a signal */
232 int dsr_chkcount
; /* is floating */
235 char *buffer_list
; /* virtual address of Rx & Tx buffer lists */
236 unsigned long buffer_list_phys
;
238 unsigned int rx_buffer_count
; /* count of total allocated Rx buffers */
239 DMABUFFERENTRY
*rx_buffer_list
; /* list of receive buffer entries */
240 unsigned int current_rx_buffer
;
242 int num_tx_dma_buffers
; /* number of tx dma frames required */
243 int tx_dma_buffers_used
;
244 unsigned int tx_buffer_count
; /* count of total allocated Tx buffers */
245 DMABUFFERENTRY
*tx_buffer_list
; /* list of transmit buffer entries */
246 int start_tx_dma_buffer
; /* tx dma buffer to start tx dma operation */
247 int current_tx_buffer
; /* next tx dma buffer to be loaded */
249 unsigned char *intermediate_rxbuffer
;
251 int num_tx_holding_buffers
; /* number of tx holding buffer allocated */
252 int get_tx_holding_index
; /* next tx holding buffer for adapter to load */
253 int put_tx_holding_index
; /* next tx holding buffer to store user request */
254 int tx_holding_count
; /* number of tx holding buffers waiting */
255 struct tx_holding_buffer tx_holding_buffers
[MAX_TX_HOLDING_BUFFERS
];
268 char device_name
[25]; /* device instance name */
270 unsigned int bus_type
; /* expansion bus type (ISA,EISA,PCI) */
271 unsigned char bus
; /* expansion bus number (zero based) */
272 unsigned char function
; /* PCI device number */
274 unsigned int io_base
; /* base I/O address of adapter */
275 unsigned int io_addr_size
; /* size of the I/O address range */
276 int io_addr_requested
; /* nonzero if I/O address requested */
278 unsigned int irq_level
; /* interrupt level */
279 unsigned long irq_flags
;
280 int irq_requested
; /* nonzero if IRQ requested */
282 unsigned int dma_level
; /* DMA channel */
283 int dma_requested
; /* nonzero if dma channel requested */
289 MGSL_PARAMS params
; /* communications parameters */
291 unsigned char serial_signals
; /* current serial signal states */
293 int irq_occurred
; /* for diagnostics use */
294 unsigned int init_error
; /* Initialization startup error (DIAGS) */
295 int fDiagnosticsmode
; /* Driver in Diagnostic mode? (DIAGS) */
298 unsigned char* memory_base
; /* shared memory address (PCI only) */
299 u32 phys_memory_base
;
300 int shared_mem_requested
;
302 unsigned char* lcr_base
; /* local config registers (PCI only) */
305 int lcr_mem_requested
;
308 char flag_buf
[MAX_ASYNC_BUFFER_SIZE
];
309 char char_buf
[MAX_ASYNC_BUFFER_SIZE
];
310 BOOLEAN drop_rts_on_tx_done
;
312 BOOLEAN loopmode_insert_requested
;
313 BOOLEAN loopmode_send_done_requested
;
315 struct _input_signal_events input_signal_events
;
317 /* generic HDLC device parts */
323 struct net_device
*netdev
;
327 #define MGSL_MAGIC 0x5401
330 * The size of the serial xmit buffer is 1 page, or 4096 bytes
332 #ifndef SERIAL_XMIT_SIZE
333 #define SERIAL_XMIT_SIZE 4096
337 * These macros define the offsets used in calculating the
338 * I/O address of the specified USC registers.
342 #define DCPIN 2 /* Bit 1 of I/O address */
343 #define SDPIN 4 /* Bit 2 of I/O address */
345 #define DCAR 0 /* DMA command/address register */
346 #define CCAR SDPIN /* channel command/address register */
347 #define DATAREG DCPIN + SDPIN /* serial data register */
352 * These macros define the register address (ordinal number)
353 * used for writing address/value pairs to the USC.
356 #define CMR 0x02 /* Channel mode Register */
357 #define CCSR 0x04 /* Channel Command/status Register */
358 #define CCR 0x06 /* Channel Control Register */
359 #define PSR 0x08 /* Port status Register */
360 #define PCR 0x0a /* Port Control Register */
361 #define TMDR 0x0c /* Test mode Data Register */
362 #define TMCR 0x0e /* Test mode Control Register */
363 #define CMCR 0x10 /* Clock mode Control Register */
364 #define HCR 0x12 /* Hardware Configuration Register */
365 #define IVR 0x14 /* Interrupt Vector Register */
366 #define IOCR 0x16 /* Input/Output Control Register */
367 #define ICR 0x18 /* Interrupt Control Register */
368 #define DCCR 0x1a /* Daisy Chain Control Register */
369 #define MISR 0x1c /* Misc Interrupt status Register */
370 #define SICR 0x1e /* status Interrupt Control Register */
371 #define RDR 0x20 /* Receive Data Register */
372 #define RMR 0x22 /* Receive mode Register */
373 #define RCSR 0x24 /* Receive Command/status Register */
374 #define RICR 0x26 /* Receive Interrupt Control Register */
375 #define RSR 0x28 /* Receive Sync Register */
376 #define RCLR 0x2a /* Receive count Limit Register */
377 #define RCCR 0x2c /* Receive Character count Register */
378 #define TC0R 0x2e /* Time Constant 0 Register */
379 #define TDR 0x30 /* Transmit Data Register */
380 #define TMR 0x32 /* Transmit mode Register */
381 #define TCSR 0x34 /* Transmit Command/status Register */
382 #define TICR 0x36 /* Transmit Interrupt Control Register */
383 #define TSR 0x38 /* Transmit Sync Register */
384 #define TCLR 0x3a /* Transmit count Limit Register */
385 #define TCCR 0x3c /* Transmit Character count Register */
386 #define TC1R 0x3e /* Time Constant 1 Register */
390 * MACRO DEFINITIONS FOR DMA REGISTERS
393 #define DCR 0x06 /* DMA Control Register (shared) */
394 #define DACR 0x08 /* DMA Array count Register (shared) */
395 #define BDCR 0x12 /* Burst/Dwell Control Register (shared) */
396 #define DIVR 0x14 /* DMA Interrupt Vector Register (shared) */
397 #define DICR 0x18 /* DMA Interrupt Control Register (shared) */
398 #define CDIR 0x1a /* Clear DMA Interrupt Register (shared) */
399 #define SDIR 0x1c /* Set DMA Interrupt Register (shared) */
401 #define TDMR 0x02 /* Transmit DMA mode Register */
402 #define TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */
403 #define TBCR 0x2a /* Transmit Byte count Register */
404 #define TARL 0x2c /* Transmit Address Register (low) */
405 #define TARU 0x2e /* Transmit Address Register (high) */
406 #define NTBCR 0x3a /* Next Transmit Byte count Register */
407 #define NTARL 0x3c /* Next Transmit Address Register (low) */
408 #define NTARU 0x3e /* Next Transmit Address Register (high) */
410 #define RDMR 0x82 /* Receive DMA mode Register (non-shared) */
411 #define RDIAR 0x9e /* Receive DMA Interrupt Arm Register */
412 #define RBCR 0xaa /* Receive Byte count Register */
413 #define RARL 0xac /* Receive Address Register (low) */
414 #define RARU 0xae /* Receive Address Register (high) */
415 #define NRBCR 0xba /* Next Receive Byte count Register */
416 #define NRARL 0xbc /* Next Receive Address Register (low) */
417 #define NRARU 0xbe /* Next Receive Address Register (high) */
421 * MACRO DEFINITIONS FOR MODEM STATUS BITS
424 #define MODEMSTATUS_DTR 0x80
425 #define MODEMSTATUS_DSR 0x40
426 #define MODEMSTATUS_RTS 0x20
427 #define MODEMSTATUS_CTS 0x10
428 #define MODEMSTATUS_RI 0x04
429 #define MODEMSTATUS_DCD 0x01
433 * Channel Command/Address Register (CCAR) Command Codes
436 #define RTCmd_Null 0x0000
437 #define RTCmd_ResetHighestIus 0x1000
438 #define RTCmd_TriggerChannelLoadDma 0x2000
439 #define RTCmd_TriggerRxDma 0x2800
440 #define RTCmd_TriggerTxDma 0x3000
441 #define RTCmd_TriggerRxAndTxDma 0x3800
442 #define RTCmd_PurgeRxFifo 0x4800
443 #define RTCmd_PurgeTxFifo 0x5000
444 #define RTCmd_PurgeRxAndTxFifo 0x5800
445 #define RTCmd_LoadRcc 0x6800
446 #define RTCmd_LoadTcc 0x7000
447 #define RTCmd_LoadRccAndTcc 0x7800
448 #define RTCmd_LoadTC0 0x8800
449 #define RTCmd_LoadTC1 0x9000
450 #define RTCmd_LoadTC0AndTC1 0x9800
451 #define RTCmd_SerialDataLSBFirst 0xa000
452 #define RTCmd_SerialDataMSBFirst 0xa800
453 #define RTCmd_SelectBigEndian 0xb000
454 #define RTCmd_SelectLittleEndian 0xb800
458 * DMA Command/Address Register (DCAR) Command Codes
461 #define DmaCmd_Null 0x0000
462 #define DmaCmd_ResetTxChannel 0x1000
463 #define DmaCmd_ResetRxChannel 0x1200
464 #define DmaCmd_StartTxChannel 0x2000
465 #define DmaCmd_StartRxChannel 0x2200
466 #define DmaCmd_ContinueTxChannel 0x3000
467 #define DmaCmd_ContinueRxChannel 0x3200
468 #define DmaCmd_PauseTxChannel 0x4000
469 #define DmaCmd_PauseRxChannel 0x4200
470 #define DmaCmd_AbortTxChannel 0x5000
471 #define DmaCmd_AbortRxChannel 0x5200
472 #define DmaCmd_InitTxChannel 0x7000
473 #define DmaCmd_InitRxChannel 0x7200
474 #define DmaCmd_ResetHighestDmaIus 0x8000
475 #define DmaCmd_ResetAllChannels 0x9000
476 #define DmaCmd_StartAllChannels 0xa000
477 #define DmaCmd_ContinueAllChannels 0xb000
478 #define DmaCmd_PauseAllChannels 0xc000
479 #define DmaCmd_AbortAllChannels 0xd000
480 #define DmaCmd_InitAllChannels 0xf000
482 #define TCmd_Null 0x0000
483 #define TCmd_ClearTxCRC 0x2000
484 #define TCmd_SelectTicrTtsaData 0x4000
485 #define TCmd_SelectTicrTxFifostatus 0x5000
486 #define TCmd_SelectTicrIntLevel 0x6000
487 #define TCmd_SelectTicrdma_level 0x7000
488 #define TCmd_SendFrame 0x8000
489 #define TCmd_SendAbort 0x9000
490 #define TCmd_EnableDleInsertion 0xc000
491 #define TCmd_DisableDleInsertion 0xd000
492 #define TCmd_ClearEofEom 0xe000
493 #define TCmd_SetEofEom 0xf000
495 #define RCmd_Null 0x0000
496 #define RCmd_ClearRxCRC 0x2000
497 #define RCmd_EnterHuntmode 0x3000
498 #define RCmd_SelectRicrRtsaData 0x4000
499 #define RCmd_SelectRicrRxFifostatus 0x5000
500 #define RCmd_SelectRicrIntLevel 0x6000
501 #define RCmd_SelectRicrdma_level 0x7000
504 * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
507 #define RECEIVE_STATUS BIT5
508 #define RECEIVE_DATA BIT4
509 #define TRANSMIT_STATUS BIT3
510 #define TRANSMIT_DATA BIT2
516 * Receive status Bits in Receive Command/status Register RCSR
519 #define RXSTATUS_SHORT_FRAME BIT8
520 #define RXSTATUS_CODE_VIOLATION BIT8
521 #define RXSTATUS_EXITED_HUNT BIT7
522 #define RXSTATUS_IDLE_RECEIVED BIT6
523 #define RXSTATUS_BREAK_RECEIVED BIT5
524 #define RXSTATUS_ABORT_RECEIVED BIT5
525 #define RXSTATUS_RXBOUND BIT4
526 #define RXSTATUS_CRC_ERROR BIT3
527 #define RXSTATUS_FRAMING_ERROR BIT3
528 #define RXSTATUS_ABORT BIT2
529 #define RXSTATUS_PARITY_ERROR BIT2
530 #define RXSTATUS_OVERRUN BIT1
531 #define RXSTATUS_DATA_AVAILABLE BIT0
532 #define RXSTATUS_ALL 0x01f6
533 #define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
536 * Values for setting transmit idle mode in
537 * Transmit Control/status Register (TCSR)
539 #define IDLEMODE_FLAGS 0x0000
540 #define IDLEMODE_ALT_ONE_ZERO 0x0100
541 #define IDLEMODE_ZERO 0x0200
542 #define IDLEMODE_ONE 0x0300
543 #define IDLEMODE_ALT_MARK_SPACE 0x0500
544 #define IDLEMODE_SPACE 0x0600
545 #define IDLEMODE_MARK 0x0700
546 #define IDLEMODE_MASK 0x0700
549 * IUSC revision identifiers
551 #define IUSC_SL1660 0x4d44
552 #define IUSC_PRE_SL1660 0x4553
555 * Transmit status Bits in Transmit Command/status Register (TCSR)
558 #define TCSR_PRESERVE 0x0F00
560 #define TCSR_UNDERWAIT BIT11
561 #define TXSTATUS_PREAMBLE_SENT BIT7
562 #define TXSTATUS_IDLE_SENT BIT6
563 #define TXSTATUS_ABORT_SENT BIT5
564 #define TXSTATUS_EOF_SENT BIT4
565 #define TXSTATUS_EOM_SENT BIT4
566 #define TXSTATUS_CRC_SENT BIT3
567 #define TXSTATUS_ALL_SENT BIT2
568 #define TXSTATUS_UNDERRUN BIT1
569 #define TXSTATUS_FIFO_EMPTY BIT0
570 #define TXSTATUS_ALL 0x00fa
571 #define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
574 #define MISCSTATUS_RXC_LATCHED BIT15
575 #define MISCSTATUS_RXC BIT14
576 #define MISCSTATUS_TXC_LATCHED BIT13
577 #define MISCSTATUS_TXC BIT12
578 #define MISCSTATUS_RI_LATCHED BIT11
579 #define MISCSTATUS_RI BIT10
580 #define MISCSTATUS_DSR_LATCHED BIT9
581 #define MISCSTATUS_DSR BIT8
582 #define MISCSTATUS_DCD_LATCHED BIT7
583 #define MISCSTATUS_DCD BIT6
584 #define MISCSTATUS_CTS_LATCHED BIT5
585 #define MISCSTATUS_CTS BIT4
586 #define MISCSTATUS_RCC_UNDERRUN BIT3
587 #define MISCSTATUS_DPLL_NO_SYNC BIT2
588 #define MISCSTATUS_BRG1_ZERO BIT1
589 #define MISCSTATUS_BRG0_ZERO BIT0
591 #define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
592 #define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
594 #define SICR_RXC_ACTIVE BIT15
595 #define SICR_RXC_INACTIVE BIT14
596 #define SICR_RXC (BIT15+BIT14)
597 #define SICR_TXC_ACTIVE BIT13
598 #define SICR_TXC_INACTIVE BIT12
599 #define SICR_TXC (BIT13+BIT12)
600 #define SICR_RI_ACTIVE BIT11
601 #define SICR_RI_INACTIVE BIT10
602 #define SICR_RI (BIT11+BIT10)
603 #define SICR_DSR_ACTIVE BIT9
604 #define SICR_DSR_INACTIVE BIT8
605 #define SICR_DSR (BIT9+BIT8)
606 #define SICR_DCD_ACTIVE BIT7
607 #define SICR_DCD_INACTIVE BIT6
608 #define SICR_DCD (BIT7+BIT6)
609 #define SICR_CTS_ACTIVE BIT5
610 #define SICR_CTS_INACTIVE BIT4
611 #define SICR_CTS (BIT5+BIT4)
612 #define SICR_RCC_UNDERFLOW BIT3
613 #define SICR_DPLL_NO_SYNC BIT2
614 #define SICR_BRG1_ZERO BIT1
615 #define SICR_BRG0_ZERO BIT0
617 void usc_DisableMasterIrqBit( struct mgsl_struct
*info
);
618 void usc_EnableMasterIrqBit( struct mgsl_struct
*info
);
619 void usc_EnableInterrupts( struct mgsl_struct
*info
, u16 IrqMask
);
620 void usc_DisableInterrupts( struct mgsl_struct
*info
, u16 IrqMask
);
621 void usc_ClearIrqPendingBits( struct mgsl_struct
*info
, u16 IrqMask
);
623 #define usc_EnableInterrupts( a, b ) \
624 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
626 #define usc_DisableInterrupts( a, b ) \
627 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
629 #define usc_EnableMasterIrqBit(a) \
630 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
632 #define usc_DisableMasterIrqBit(a) \
633 usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
635 #define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
638 * Transmit status Bits in Transmit Control status Register (TCSR)
639 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
642 #define TXSTATUS_PREAMBLE_SENT BIT7
643 #define TXSTATUS_IDLE_SENT BIT6
644 #define TXSTATUS_ABORT_SENT BIT5
645 #define TXSTATUS_EOF BIT4
646 #define TXSTATUS_CRC_SENT BIT3
647 #define TXSTATUS_ALL_SENT BIT2
648 #define TXSTATUS_UNDERRUN BIT1
649 #define TXSTATUS_FIFO_EMPTY BIT0
651 #define DICR_MASTER BIT15
652 #define DICR_TRANSMIT BIT0
653 #define DICR_RECEIVE BIT1
655 #define usc_EnableDmaInterrupts(a,b) \
656 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
658 #define usc_DisableDmaInterrupts(a,b) \
659 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
661 #define usc_EnableStatusIrqs(a,b) \
662 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
664 #define usc_DisablestatusIrqs(a,b) \
665 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
667 /* Transmit status Bits in Transmit Control status Register (TCSR) */
668 /* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
671 #define DISABLE_UNCONDITIONAL 0
672 #define DISABLE_END_OF_FRAME 1
673 #define ENABLE_UNCONDITIONAL 2
674 #define ENABLE_AUTO_CTS 3
675 #define ENABLE_AUTO_DCD 3
676 #define usc_EnableTransmitter(a,b) \
677 usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
678 #define usc_EnableReceiver(a,b) \
679 usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
681 static u16
usc_InDmaReg( struct mgsl_struct
*info
, u16 Port
);
682 static void usc_OutDmaReg( struct mgsl_struct
*info
, u16 Port
, u16 Value
);
683 static void usc_DmaCmd( struct mgsl_struct
*info
, u16 Cmd
);
685 static u16
usc_InReg( struct mgsl_struct
*info
, u16 Port
);
686 static void usc_OutReg( struct mgsl_struct
*info
, u16 Port
, u16 Value
);
687 static void usc_RTCmd( struct mgsl_struct
*info
, u16 Cmd
);
688 void usc_RCmd( struct mgsl_struct
*info
, u16 Cmd
);
689 void usc_TCmd( struct mgsl_struct
*info
, u16 Cmd
);
691 #define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
692 #define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
694 #define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
696 static void usc_process_rxoverrun_sync( struct mgsl_struct
*info
);
697 static void usc_start_receiver( struct mgsl_struct
*info
);
698 static void usc_stop_receiver( struct mgsl_struct
*info
);
700 static void usc_start_transmitter( struct mgsl_struct
*info
);
701 static void usc_stop_transmitter( struct mgsl_struct
*info
);
702 static void usc_set_txidle( struct mgsl_struct
*info
);
703 static void usc_load_txfifo( struct mgsl_struct
*info
);
705 static void usc_enable_aux_clock( struct mgsl_struct
*info
, u32 DataRate
);
706 static void usc_enable_loopback( struct mgsl_struct
*info
, int enable
);
708 static void usc_get_serial_signals( struct mgsl_struct
*info
);
709 static void usc_set_serial_signals( struct mgsl_struct
*info
);
711 static void usc_reset( struct mgsl_struct
*info
);
713 static void usc_set_sync_mode( struct mgsl_struct
*info
);
714 static void usc_set_sdlc_mode( struct mgsl_struct
*info
);
715 static void usc_set_async_mode( struct mgsl_struct
*info
);
716 static void usc_enable_async_clock( struct mgsl_struct
*info
, u32 DataRate
);
718 static void usc_loopback_frame( struct mgsl_struct
*info
);
720 static void mgsl_tx_timeout(unsigned long context
);
723 static void usc_loopmode_cancel_transmit( struct mgsl_struct
* info
);
724 static void usc_loopmode_insert_request( struct mgsl_struct
* info
);
725 static int usc_loopmode_active( struct mgsl_struct
* info
);
726 static void usc_loopmode_send_done( struct mgsl_struct
* info
);
728 static int mgsl_ioctl_common(struct mgsl_struct
*info
, unsigned int cmd
, unsigned long arg
);
731 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
732 static void hdlcdev_tx_done(struct mgsl_struct
*info
);
733 static void hdlcdev_rx(struct mgsl_struct
*info
, char *buf
, int size
);
734 static int hdlcdev_init(struct mgsl_struct
*info
);
735 static void hdlcdev_exit(struct mgsl_struct
*info
);
739 * Defines a BUS descriptor value for the PCI adapter
740 * local bus address ranges.
743 #define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
754 static void mgsl_trace_block(struct mgsl_struct
*info
,const char* data
, int count
, int xmit
);
757 * Adapter diagnostic routines
759 static BOOLEAN
mgsl_register_test( struct mgsl_struct
*info
);
760 static BOOLEAN
mgsl_irq_test( struct mgsl_struct
*info
);
761 static BOOLEAN
mgsl_dma_test( struct mgsl_struct
*info
);
762 static BOOLEAN
mgsl_memory_test( struct mgsl_struct
*info
);
763 static int mgsl_adapter_test( struct mgsl_struct
*info
);
766 * device and resource management routines
768 static int mgsl_claim_resources(struct mgsl_struct
*info
);
769 static void mgsl_release_resources(struct mgsl_struct
*info
);
770 static void mgsl_add_device(struct mgsl_struct
*info
);
771 static struct mgsl_struct
* mgsl_allocate_device(void);
774 * DMA buffer manupulation functions.
776 static void mgsl_free_rx_frame_buffers( struct mgsl_struct
*info
, unsigned int StartIndex
, unsigned int EndIndex
);
777 static int mgsl_get_rx_frame( struct mgsl_struct
*info
);
778 static int mgsl_get_raw_rx_frame( struct mgsl_struct
*info
);
779 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct
*info
);
780 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct
*info
);
781 static int num_free_tx_dma_buffers(struct mgsl_struct
*info
);
782 static void mgsl_load_tx_dma_buffer( struct mgsl_struct
*info
, const char *Buffer
, unsigned int BufferSize
);
783 static void mgsl_load_pci_memory(char* TargetPtr
, const char* SourcePtr
, unsigned short count
);
786 * DMA and Shared Memory buffer allocation and formatting
788 static int mgsl_allocate_dma_buffers(struct mgsl_struct
*info
);
789 static void mgsl_free_dma_buffers(struct mgsl_struct
*info
);
790 static int mgsl_alloc_frame_memory(struct mgsl_struct
*info
, DMABUFFERENTRY
*BufferList
,int Buffercount
);
791 static void mgsl_free_frame_memory(struct mgsl_struct
*info
, DMABUFFERENTRY
*BufferList
,int Buffercount
);
792 static int mgsl_alloc_buffer_list_memory(struct mgsl_struct
*info
);
793 static void mgsl_free_buffer_list_memory(struct mgsl_struct
*info
);
794 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct
*info
);
795 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct
*info
);
796 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct
*info
);
797 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct
*info
);
798 static int load_next_tx_holding_buffer(struct mgsl_struct
*info
);
799 static int save_tx_buffer_request(struct mgsl_struct
*info
,const char *Buffer
, unsigned int BufferSize
);
802 * Bottom half interrupt handlers
804 static void mgsl_bh_handler(void* Context
);
805 static void mgsl_bh_receive(struct mgsl_struct
*info
);
806 static void mgsl_bh_transmit(struct mgsl_struct
*info
);
807 static void mgsl_bh_status(struct mgsl_struct
*info
);
810 * Interrupt handler routines and dispatch table.
812 static void mgsl_isr_null( struct mgsl_struct
*info
);
813 static void mgsl_isr_transmit_data( struct mgsl_struct
*info
);
814 static void mgsl_isr_receive_data( struct mgsl_struct
*info
);
815 static void mgsl_isr_receive_status( struct mgsl_struct
*info
);
816 static void mgsl_isr_transmit_status( struct mgsl_struct
*info
);
817 static void mgsl_isr_io_pin( struct mgsl_struct
*info
);
818 static void mgsl_isr_misc( struct mgsl_struct
*info
);
819 static void mgsl_isr_receive_dma( struct mgsl_struct
*info
);
820 static void mgsl_isr_transmit_dma( struct mgsl_struct
*info
);
822 typedef void (*isr_dispatch_func
)(struct mgsl_struct
*);
824 static isr_dispatch_func UscIsrTable
[7] =
829 mgsl_isr_transmit_data
,
830 mgsl_isr_transmit_status
,
831 mgsl_isr_receive_data
,
832 mgsl_isr_receive_status
836 * ioctl call handlers
838 static int tiocmget(struct tty_struct
*tty
, struct file
*file
);
839 static int tiocmset(struct tty_struct
*tty
, struct file
*file
,
840 unsigned int set
, unsigned int clear
);
841 static int mgsl_get_stats(struct mgsl_struct
* info
, struct mgsl_icount
842 __user
*user_icount
);
843 static int mgsl_get_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*user_params
);
844 static int mgsl_set_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*new_params
);
845 static int mgsl_get_txidle(struct mgsl_struct
* info
, int __user
*idle_mode
);
846 static int mgsl_set_txidle(struct mgsl_struct
* info
, int idle_mode
);
847 static int mgsl_txenable(struct mgsl_struct
* info
, int enable
);
848 static int mgsl_txabort(struct mgsl_struct
* info
);
849 static int mgsl_rxenable(struct mgsl_struct
* info
, int enable
);
850 static int mgsl_wait_event(struct mgsl_struct
* info
, int __user
*mask
);
851 static int mgsl_loopmode_send_done( struct mgsl_struct
* info
);
853 /* set non-zero on successful registration with PCI subsystem */
854 static int pci_registered
;
857 * Global linked list of SyncLink devices
859 static struct mgsl_struct
*mgsl_device_list
;
860 static int mgsl_device_count
;
863 * Set this param to non-zero to load eax with the
864 * .text section address and breakpoint on module load.
865 * This is useful for use with gdb and add-symbol-file command.
867 static int break_on_load
;
870 * Driver major number, defaults to zero to get auto
871 * assigned major number. May be forced as module parameter.
876 * Array of user specified options for ISA adapters.
878 static int io
[MAX_ISA_DEVICES
];
879 static int irq
[MAX_ISA_DEVICES
];
880 static int dma
[MAX_ISA_DEVICES
];
881 static int debug_level
;
882 static int maxframe
[MAX_TOTAL_DEVICES
];
883 static int dosyncppp
[MAX_TOTAL_DEVICES
];
884 static int txdmabufs
[MAX_TOTAL_DEVICES
];
885 static int txholdbufs
[MAX_TOTAL_DEVICES
];
887 module_param(break_on_load
, bool, 0);
888 module_param(ttymajor
, int, 0);
889 module_param_array(io
, int, NULL
, 0);
890 module_param_array(irq
, int, NULL
, 0);
891 module_param_array(dma
, int, NULL
, 0);
892 module_param(debug_level
, int, 0);
893 module_param_array(maxframe
, int, NULL
, 0);
894 module_param_array(dosyncppp
, int, NULL
, 0);
895 module_param_array(txdmabufs
, int, NULL
, 0);
896 module_param_array(txholdbufs
, int, NULL
, 0);
898 static char *driver_name
= "SyncLink serial driver";
899 static char *driver_version
= "$Revision: 4.37 $";
901 static int synclink_init_one (struct pci_dev
*dev
,
902 const struct pci_device_id
*ent
);
903 static void synclink_remove_one (struct pci_dev
*dev
);
905 static struct pci_device_id synclink_pci_tbl
[] = {
906 { PCI_VENDOR_ID_MICROGATE
, PCI_DEVICE_ID_MICROGATE_USC
, PCI_ANY_ID
, PCI_ANY_ID
, },
907 { PCI_VENDOR_ID_MICROGATE
, 0x0210, PCI_ANY_ID
, PCI_ANY_ID
, },
908 { 0, }, /* terminate list */
910 MODULE_DEVICE_TABLE(pci
, synclink_pci_tbl
);
912 MODULE_LICENSE("GPL");
914 static struct pci_driver synclink_pci_driver
= {
915 .owner
= THIS_MODULE
,
917 .id_table
= synclink_pci_tbl
,
918 .probe
= synclink_init_one
,
919 .remove
= __devexit_p(synclink_remove_one
),
922 static struct tty_driver
*serial_driver
;
924 /* number of characters left in xmit buffer before we ask for more */
925 #define WAKEUP_CHARS 256
928 static void mgsl_change_params(struct mgsl_struct
*info
);
929 static void mgsl_wait_until_sent(struct tty_struct
*tty
, int timeout
);
932 * 1st function defined in .text section. Calling this function in
933 * init_module() followed by a breakpoint allows a remote debugger
934 * (gdb) to get the .text address for the add-symbol-file command.
935 * This allows remote debugging of dynamically loadable modules.
937 static void* mgsl_get_text_ptr(void)
939 return mgsl_get_text_ptr
;
943 * tmp_buf is used as a temporary buffer by mgsl_write. We need to
944 * lock it in case the COPY_FROM_USER blocks while swapping in a page,
945 * and some other program tries to do a serial write at the same time.
946 * Since the lock will only come under contention when the system is
947 * swapping and available memory is low, it makes sense to share one
948 * buffer across all the serial ioports, since it significantly saves
949 * memory if large numbers of serial ports are open.
951 static unsigned char *tmp_buf
;
952 static DECLARE_MUTEX(tmp_buf_sem
);
954 static inline int mgsl_paranoia_check(struct mgsl_struct
*info
,
955 char *name
, const char *routine
)
957 #ifdef MGSL_PARANOIA_CHECK
958 static const char *badmagic
=
959 "Warning: bad magic number for mgsl struct (%s) in %s\n";
960 static const char *badinfo
=
961 "Warning: null mgsl_struct for (%s) in %s\n";
964 printk(badinfo
, name
, routine
);
967 if (info
->magic
!= MGSL_MAGIC
) {
968 printk(badmagic
, name
, routine
);
979 * line discipline callback wrappers
981 * The wrappers maintain line discipline references
982 * while calling into the line discipline.
984 * ldisc_receive_buf - pass receive data to line discipline
987 static void ldisc_receive_buf(struct tty_struct
*tty
,
988 const __u8
*data
, char *flags
, int count
)
990 struct tty_ldisc
*ld
;
993 ld
= tty_ldisc_ref(tty
);
996 ld
->receive_buf(tty
, data
, flags
, count
);
1001 /* mgsl_stop() throttle (stop) transmitter
1003 * Arguments: tty pointer to tty info structure
1004 * Return Value: None
1006 static void mgsl_stop(struct tty_struct
*tty
)
1008 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
1009 unsigned long flags
;
1011 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_stop"))
1014 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1015 printk("mgsl_stop(%s)\n",info
->device_name
);
1017 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1018 if (info
->tx_enabled
)
1019 usc_stop_transmitter(info
);
1020 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1022 } /* end of mgsl_stop() */
1024 /* mgsl_start() release (start) transmitter
1026 * Arguments: tty pointer to tty info structure
1027 * Return Value: None
1029 static void mgsl_start(struct tty_struct
*tty
)
1031 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
1032 unsigned long flags
;
1034 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_start"))
1037 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1038 printk("mgsl_start(%s)\n",info
->device_name
);
1040 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1041 if (!info
->tx_enabled
)
1042 usc_start_transmitter(info
);
1043 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1045 } /* end of mgsl_start() */
1048 * Bottom half work queue access functions
1051 /* mgsl_bh_action() Return next bottom half action to perform.
1052 * Return Value: BH action code or 0 if nothing to do.
1054 static int mgsl_bh_action(struct mgsl_struct
*info
)
1056 unsigned long flags
;
1059 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1061 if (info
->pending_bh
& BH_RECEIVE
) {
1062 info
->pending_bh
&= ~BH_RECEIVE
;
1064 } else if (info
->pending_bh
& BH_TRANSMIT
) {
1065 info
->pending_bh
&= ~BH_TRANSMIT
;
1067 } else if (info
->pending_bh
& BH_STATUS
) {
1068 info
->pending_bh
&= ~BH_STATUS
;
1073 /* Mark BH routine as complete */
1074 info
->bh_running
= 0;
1075 info
->bh_requested
= 0;
1078 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1084 * Perform bottom half processing of work items queued by ISR.
1086 static void mgsl_bh_handler(void* Context
)
1088 struct mgsl_struct
*info
= (struct mgsl_struct
*)Context
;
1094 if ( debug_level
>= DEBUG_LEVEL_BH
)
1095 printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1096 __FILE__
,__LINE__
,info
->device_name
);
1098 info
->bh_running
= 1;
1100 while((action
= mgsl_bh_action(info
)) != 0) {
1102 /* Process work item */
1103 if ( debug_level
>= DEBUG_LEVEL_BH
)
1104 printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1105 __FILE__
,__LINE__
,action
);
1110 mgsl_bh_receive(info
);
1113 mgsl_bh_transmit(info
);
1116 mgsl_bh_status(info
);
1119 /* unknown work item ID */
1120 printk("Unknown work item ID=%08X!\n", action
);
1125 if ( debug_level
>= DEBUG_LEVEL_BH
)
1126 printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1127 __FILE__
,__LINE__
,info
->device_name
);
1130 static void mgsl_bh_receive(struct mgsl_struct
*info
)
1132 int (*get_rx_frame
)(struct mgsl_struct
*info
) =
1133 (info
->params
.mode
== MGSL_MODE_HDLC
? mgsl_get_rx_frame
: mgsl_get_raw_rx_frame
);
1135 if ( debug_level
>= DEBUG_LEVEL_BH
)
1136 printk( "%s(%d):mgsl_bh_receive(%s)\n",
1137 __FILE__
,__LINE__
,info
->device_name
);
1141 if (info
->rx_rcc_underrun
) {
1142 unsigned long flags
;
1143 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1144 usc_start_receiver(info
);
1145 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1148 } while(get_rx_frame(info
));
1151 static void mgsl_bh_transmit(struct mgsl_struct
*info
)
1153 struct tty_struct
*tty
= info
->tty
;
1154 unsigned long flags
;
1156 if ( debug_level
>= DEBUG_LEVEL_BH
)
1157 printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1158 __FILE__
,__LINE__
,info
->device_name
);
1162 wake_up_interruptible(&tty
->write_wait
);
1165 /* if transmitter idle and loopmode_send_done_requested
1166 * then start echoing RxD to TxD
1168 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1169 if ( !info
->tx_active
&& info
->loopmode_send_done_requested
)
1170 usc_loopmode_send_done( info
);
1171 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1174 static void mgsl_bh_status(struct mgsl_struct
*info
)
1176 if ( debug_level
>= DEBUG_LEVEL_BH
)
1177 printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1178 __FILE__
,__LINE__
,info
->device_name
);
1180 info
->ri_chkcount
= 0;
1181 info
->dsr_chkcount
= 0;
1182 info
->dcd_chkcount
= 0;
1183 info
->cts_chkcount
= 0;
1186 /* mgsl_isr_receive_status()
1188 * Service a receive status interrupt. The type of status
1189 * interrupt is indicated by the state of the RCSR.
1190 * This is only used for HDLC mode.
1192 * Arguments: info pointer to device instance data
1193 * Return Value: None
1195 static void mgsl_isr_receive_status( struct mgsl_struct
*info
)
1197 u16 status
= usc_InReg( info
, RCSR
);
1199 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1200 printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1201 __FILE__
,__LINE__
,status
);
1203 if ( (status
& RXSTATUS_ABORT_RECEIVED
) &&
1204 info
->loopmode_insert_requested
&&
1205 usc_loopmode_active(info
) )
1207 ++info
->icount
.rxabort
;
1208 info
->loopmode_insert_requested
= FALSE
;
1210 /* clear CMR:13 to start echoing RxD to TxD */
1211 info
->cmr_value
&= ~BIT13
;
1212 usc_OutReg(info
, CMR
, info
->cmr_value
);
1214 /* disable received abort irq (no longer required) */
1215 usc_OutReg(info
, RICR
,
1216 (usc_InReg(info
, RICR
) & ~RXSTATUS_ABORT_RECEIVED
));
1219 if (status
& (RXSTATUS_EXITED_HUNT
+ RXSTATUS_IDLE_RECEIVED
)) {
1220 if (status
& RXSTATUS_EXITED_HUNT
)
1221 info
->icount
.exithunt
++;
1222 if (status
& RXSTATUS_IDLE_RECEIVED
)
1223 info
->icount
.rxidle
++;
1224 wake_up_interruptible(&info
->event_wait_q
);
1227 if (status
& RXSTATUS_OVERRUN
){
1228 info
->icount
.rxover
++;
1229 usc_process_rxoverrun_sync( info
);
1232 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
);
1233 usc_UnlatchRxstatusBits( info
, status
);
1235 } /* end of mgsl_isr_receive_status() */
1237 /* mgsl_isr_transmit_status()
1239 * Service a transmit status interrupt
1240 * HDLC mode :end of transmit frame
1241 * Async mode:all data is sent
1242 * transmit status is indicated by bits in the TCSR.
1244 * Arguments: info pointer to device instance data
1245 * Return Value: None
1247 static void mgsl_isr_transmit_status( struct mgsl_struct
*info
)
1249 u16 status
= usc_InReg( info
, TCSR
);
1251 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1252 printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1253 __FILE__
,__LINE__
,status
);
1255 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
1256 usc_UnlatchTxstatusBits( info
, status
);
1258 if ( status
& (TXSTATUS_UNDERRUN
| TXSTATUS_ABORT_SENT
) )
1260 /* finished sending HDLC abort. This may leave */
1261 /* the TxFifo with data from the aborted frame */
1262 /* so purge the TxFifo. Also shutdown the DMA */
1263 /* channel in case there is data remaining in */
1264 /* the DMA buffer */
1265 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
1266 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
1269 if ( status
& TXSTATUS_EOF_SENT
)
1270 info
->icount
.txok
++;
1271 else if ( status
& TXSTATUS_UNDERRUN
)
1272 info
->icount
.txunder
++;
1273 else if ( status
& TXSTATUS_ABORT_SENT
)
1274 info
->icount
.txabort
++;
1276 info
->icount
.txunder
++;
1278 info
->tx_active
= 0;
1279 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
1280 del_timer(&info
->tx_timer
);
1282 if ( info
->drop_rts_on_tx_done
) {
1283 usc_get_serial_signals( info
);
1284 if ( info
->serial_signals
& SerialSignal_RTS
) {
1285 info
->serial_signals
&= ~SerialSignal_RTS
;
1286 usc_set_serial_signals( info
);
1288 info
->drop_rts_on_tx_done
= 0;
1293 hdlcdev_tx_done(info
);
1297 if (info
->tty
->stopped
|| info
->tty
->hw_stopped
) {
1298 usc_stop_transmitter(info
);
1301 info
->pending_bh
|= BH_TRANSMIT
;
1304 } /* end of mgsl_isr_transmit_status() */
1306 /* mgsl_isr_io_pin()
1308 * Service an Input/Output pin interrupt. The type of
1309 * interrupt is indicated by bits in the MISR
1311 * Arguments: info pointer to device instance data
1312 * Return Value: None
1314 static void mgsl_isr_io_pin( struct mgsl_struct
*info
)
1316 struct mgsl_icount
*icount
;
1317 u16 status
= usc_InReg( info
, MISR
);
1319 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1320 printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1321 __FILE__
,__LINE__
,status
);
1323 usc_ClearIrqPendingBits( info
, IO_PIN
);
1324 usc_UnlatchIostatusBits( info
, status
);
1326 if (status
& (MISCSTATUS_CTS_LATCHED
| MISCSTATUS_DCD_LATCHED
|
1327 MISCSTATUS_DSR_LATCHED
| MISCSTATUS_RI_LATCHED
) ) {
1328 icount
= &info
->icount
;
1329 /* update input line counters */
1330 if (status
& MISCSTATUS_RI_LATCHED
) {
1331 if ((info
->ri_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1332 usc_DisablestatusIrqs(info
,SICR_RI
);
1334 if ( status
& MISCSTATUS_RI
)
1335 info
->input_signal_events
.ri_up
++;
1337 info
->input_signal_events
.ri_down
++;
1339 if (status
& MISCSTATUS_DSR_LATCHED
) {
1340 if ((info
->dsr_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1341 usc_DisablestatusIrqs(info
,SICR_DSR
);
1343 if ( status
& MISCSTATUS_DSR
)
1344 info
->input_signal_events
.dsr_up
++;
1346 info
->input_signal_events
.dsr_down
++;
1348 if (status
& MISCSTATUS_DCD_LATCHED
) {
1349 if ((info
->dcd_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1350 usc_DisablestatusIrqs(info
,SICR_DCD
);
1352 if (status
& MISCSTATUS_DCD
) {
1353 info
->input_signal_events
.dcd_up
++;
1355 info
->input_signal_events
.dcd_down
++;
1358 hdlc_set_carrier(status
& MISCSTATUS_DCD
, info
->netdev
);
1361 if (status
& MISCSTATUS_CTS_LATCHED
)
1363 if ((info
->cts_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1364 usc_DisablestatusIrqs(info
,SICR_CTS
);
1366 if ( status
& MISCSTATUS_CTS
)
1367 info
->input_signal_events
.cts_up
++;
1369 info
->input_signal_events
.cts_down
++;
1371 wake_up_interruptible(&info
->status_event_wait_q
);
1372 wake_up_interruptible(&info
->event_wait_q
);
1374 if ( (info
->flags
& ASYNC_CHECK_CD
) &&
1375 (status
& MISCSTATUS_DCD_LATCHED
) ) {
1376 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1377 printk("%s CD now %s...", info
->device_name
,
1378 (status
& MISCSTATUS_DCD
) ? "on" : "off");
1379 if (status
& MISCSTATUS_DCD
)
1380 wake_up_interruptible(&info
->open_wait
);
1382 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1383 printk("doing serial hangup...");
1385 tty_hangup(info
->tty
);
1389 if ( (info
->flags
& ASYNC_CTS_FLOW
) &&
1390 (status
& MISCSTATUS_CTS_LATCHED
) ) {
1391 if (info
->tty
->hw_stopped
) {
1392 if (status
& MISCSTATUS_CTS
) {
1393 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1394 printk("CTS tx start...");
1396 info
->tty
->hw_stopped
= 0;
1397 usc_start_transmitter(info
);
1398 info
->pending_bh
|= BH_TRANSMIT
;
1402 if (!(status
& MISCSTATUS_CTS
)) {
1403 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1404 printk("CTS tx stop...");
1406 info
->tty
->hw_stopped
= 1;
1407 usc_stop_transmitter(info
);
1413 info
->pending_bh
|= BH_STATUS
;
1415 /* for diagnostics set IRQ flag */
1416 if ( status
& MISCSTATUS_TXC_LATCHED
){
1417 usc_OutReg( info
, SICR
,
1418 (unsigned short)(usc_InReg(info
,SICR
) & ~(SICR_TXC_ACTIVE
+SICR_TXC_INACTIVE
)) );
1419 usc_UnlatchIostatusBits( info
, MISCSTATUS_TXC_LATCHED
);
1420 info
->irq_occurred
= 1;
1423 } /* end of mgsl_isr_io_pin() */
1425 /* mgsl_isr_transmit_data()
1427 * Service a transmit data interrupt (async mode only).
1429 * Arguments: info pointer to device instance data
1430 * Return Value: None
1432 static void mgsl_isr_transmit_data( struct mgsl_struct
*info
)
1434 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1435 printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1436 __FILE__
,__LINE__
,info
->xmit_cnt
);
1438 usc_ClearIrqPendingBits( info
, TRANSMIT_DATA
);
1440 if (info
->tty
->stopped
|| info
->tty
->hw_stopped
) {
1441 usc_stop_transmitter(info
);
1445 if ( info
->xmit_cnt
)
1446 usc_load_txfifo( info
);
1448 info
->tx_active
= 0;
1450 if (info
->xmit_cnt
< WAKEUP_CHARS
)
1451 info
->pending_bh
|= BH_TRANSMIT
;
1453 } /* end of mgsl_isr_transmit_data() */
1455 /* mgsl_isr_receive_data()
1457 * Service a receive data interrupt. This occurs
1458 * when operating in asynchronous interrupt transfer mode.
1459 * The receive data FIFO is flushed to the receive data buffers.
1461 * Arguments: info pointer to device instance data
1462 * Return Value: None
1464 static void mgsl_isr_receive_data( struct mgsl_struct
*info
)
1468 unsigned char DataByte
;
1469 struct tty_struct
*tty
= info
->tty
;
1470 struct mgsl_icount
*icount
= &info
->icount
;
1472 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1473 printk("%s(%d):mgsl_isr_receive_data\n",
1476 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
);
1478 /* select FIFO status for RICR readback */
1479 usc_RCmd( info
, RCmd_SelectRicrRxFifostatus
);
1481 /* clear the Wordstatus bit so that status readback */
1482 /* only reflects the status of this byte */
1483 usc_OutReg( info
, RICR
+LSBONLY
, (u16
)(usc_InReg(info
, RICR
+LSBONLY
) & ~BIT3
));
1485 /* flush the receive FIFO */
1487 while( (Fifocount
= (usc_InReg(info
,RICR
) >> 8)) ) {
1488 /* read one byte from RxFIFO */
1489 outw( (inw(info
->io_base
+ CCAR
) & 0x0780) | (RDR
+LSBONLY
),
1490 info
->io_base
+ CCAR
);
1491 DataByte
= inb( info
->io_base
+ CCAR
);
1493 /* get the status of the received byte */
1494 status
= usc_InReg(info
, RCSR
);
1495 if ( status
& (RXSTATUS_FRAMING_ERROR
+ RXSTATUS_PARITY_ERROR
+
1496 RXSTATUS_OVERRUN
+ RXSTATUS_BREAK_RECEIVED
) )
1497 usc_UnlatchRxstatusBits(info
,RXSTATUS_ALL
);
1499 if (tty
->flip
.count
>= TTY_FLIPBUF_SIZE
)
1502 *tty
->flip
.char_buf_ptr
= DataByte
;
1505 *tty
->flip
.flag_buf_ptr
= 0;
1506 if ( status
& (RXSTATUS_FRAMING_ERROR
+ RXSTATUS_PARITY_ERROR
+
1507 RXSTATUS_OVERRUN
+ RXSTATUS_BREAK_RECEIVED
) ) {
1508 printk("rxerr=%04X\n",status
);
1509 /* update error statistics */
1510 if ( status
& RXSTATUS_BREAK_RECEIVED
) {
1511 status
&= ~(RXSTATUS_FRAMING_ERROR
+ RXSTATUS_PARITY_ERROR
);
1513 } else if (status
& RXSTATUS_PARITY_ERROR
)
1515 else if (status
& RXSTATUS_FRAMING_ERROR
)
1517 else if (status
& RXSTATUS_OVERRUN
) {
1518 /* must issue purge fifo cmd before */
1519 /* 16C32 accepts more receive chars */
1520 usc_RTCmd(info
,RTCmd_PurgeRxFifo
);
1524 /* discard char if tty control flags say so */
1525 if (status
& info
->ignore_status_mask
)
1528 status
&= info
->read_status_mask
;
1530 if (status
& RXSTATUS_BREAK_RECEIVED
) {
1531 *tty
->flip
.flag_buf_ptr
= TTY_BREAK
;
1532 if (info
->flags
& ASYNC_SAK
)
1534 } else if (status
& RXSTATUS_PARITY_ERROR
)
1535 *tty
->flip
.flag_buf_ptr
= TTY_PARITY
;
1536 else if (status
& RXSTATUS_FRAMING_ERROR
)
1537 *tty
->flip
.flag_buf_ptr
= TTY_FRAME
;
1538 if (status
& RXSTATUS_OVERRUN
) {
1539 /* Overrun is special, since it's
1540 * reported immediately, and doesn't
1541 * affect the current character
1543 if (tty
->flip
.count
< TTY_FLIPBUF_SIZE
) {
1545 tty
->flip
.flag_buf_ptr
++;
1546 tty
->flip
.char_buf_ptr
++;
1547 *tty
->flip
.flag_buf_ptr
= TTY_OVERRUN
;
1550 } /* end of if (error) */
1552 tty
->flip
.flag_buf_ptr
++;
1553 tty
->flip
.char_buf_ptr
++;
1557 if ( debug_level
>= DEBUG_LEVEL_ISR
) {
1558 printk("%s(%d):mgsl_isr_receive_data flip count=%d\n",
1559 __FILE__
,__LINE__
,tty
->flip
.count
);
1560 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1561 __FILE__
,__LINE__
,icount
->rx
,icount
->brk
,
1562 icount
->parity
,icount
->frame
,icount
->overrun
);
1565 if ( tty
->flip
.count
)
1566 tty_flip_buffer_push(tty
);
1571 * Service a miscellaneos interrupt source.
1573 * Arguments: info pointer to device extension (instance data)
1574 * Return Value: None
1576 static void mgsl_isr_misc( struct mgsl_struct
*info
)
1578 u16 status
= usc_InReg( info
, MISR
);
1580 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1581 printk("%s(%d):mgsl_isr_misc status=%04X\n",
1582 __FILE__
,__LINE__
,status
);
1584 if ((status
& MISCSTATUS_RCC_UNDERRUN
) &&
1585 (info
->params
.mode
== MGSL_MODE_HDLC
)) {
1587 /* turn off receiver and rx DMA */
1588 usc_EnableReceiver(info
,DISABLE_UNCONDITIONAL
);
1589 usc_DmaCmd(info
, DmaCmd_ResetRxChannel
);
1590 usc_UnlatchRxstatusBits(info
, RXSTATUS_ALL
);
1591 usc_ClearIrqPendingBits(info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
1592 usc_DisableInterrupts(info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
1594 /* schedule BH handler to restart receiver */
1595 info
->pending_bh
|= BH_RECEIVE
;
1596 info
->rx_rcc_underrun
= 1;
1599 usc_ClearIrqPendingBits( info
, MISC
);
1600 usc_UnlatchMiscstatusBits( info
, status
);
1602 } /* end of mgsl_isr_misc() */
1606 * Services undefined interrupt vectors from the
1607 * USC. (hence this function SHOULD never be called)
1609 * Arguments: info pointer to device extension (instance data)
1610 * Return Value: None
1612 static void mgsl_isr_null( struct mgsl_struct
*info
)
1615 } /* end of mgsl_isr_null() */
1617 /* mgsl_isr_receive_dma()
1619 * Service a receive DMA channel interrupt.
1620 * For this driver there are two sources of receive DMA interrupts
1621 * as identified in the Receive DMA mode Register (RDMR):
1623 * BIT3 EOA/EOL End of List, all receive buffers in receive
1624 * buffer list have been filled (no more free buffers
1625 * available). The DMA controller has shut down.
1627 * BIT2 EOB End of Buffer. This interrupt occurs when a receive
1628 * DMA buffer is terminated in response to completion
1629 * of a good frame or a frame with errors. The status
1630 * of the frame is stored in the buffer entry in the
1631 * list of receive buffer entries.
1633 * Arguments: info pointer to device instance data
1634 * Return Value: None
1636 static void mgsl_isr_receive_dma( struct mgsl_struct
*info
)
1640 /* clear interrupt pending and IUS bit for Rx DMA IRQ */
1641 usc_OutDmaReg( info
, CDIR
, BIT9
+BIT1
);
1643 /* Read the receive DMA status to identify interrupt type. */
1644 /* This also clears the status bits. */
1645 status
= usc_InDmaReg( info
, RDMR
);
1647 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1648 printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1649 __FILE__
,__LINE__
,info
->device_name
,status
);
1651 info
->pending_bh
|= BH_RECEIVE
;
1653 if ( status
& BIT3
) {
1654 info
->rx_overflow
= 1;
1655 info
->icount
.buf_overrun
++;
1658 } /* end of mgsl_isr_receive_dma() */
1660 /* mgsl_isr_transmit_dma()
1662 * This function services a transmit DMA channel interrupt.
1664 * For this driver there is one source of transmit DMA interrupts
1665 * as identified in the Transmit DMA Mode Register (TDMR):
1667 * BIT2 EOB End of Buffer. This interrupt occurs when a
1668 * transmit DMA buffer has been emptied.
1670 * The driver maintains enough transmit DMA buffers to hold at least
1671 * one max frame size transmit frame. When operating in a buffered
1672 * transmit mode, there may be enough transmit DMA buffers to hold at
1673 * least two or more max frame size frames. On an EOB condition,
1674 * determine if there are any queued transmit buffers and copy into
1675 * transmit DMA buffers if we have room.
1677 * Arguments: info pointer to device instance data
1678 * Return Value: None
1680 static void mgsl_isr_transmit_dma( struct mgsl_struct
*info
)
1684 /* clear interrupt pending and IUS bit for Tx DMA IRQ */
1685 usc_OutDmaReg(info
, CDIR
, BIT8
+BIT0
);
1687 /* Read the transmit DMA status to identify interrupt type. */
1688 /* This also clears the status bits. */
1690 status
= usc_InDmaReg( info
, TDMR
);
1692 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1693 printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
1694 __FILE__
,__LINE__
,info
->device_name
,status
);
1696 if ( status
& BIT2
) {
1697 --info
->tx_dma_buffers_used
;
1699 /* if there are transmit frames queued,
1700 * try to load the next one
1702 if ( load_next_tx_holding_buffer(info
) ) {
1703 /* if call returns non-zero value, we have
1704 * at least one free tx holding buffer
1706 info
->pending_bh
|= BH_TRANSMIT
;
1710 } /* end of mgsl_isr_transmit_dma() */
1714 * Interrupt service routine entry point.
1718 * irq interrupt number that caused interrupt
1719 * dev_id device ID supplied during interrupt registration
1720 * regs interrupted processor context
1722 * Return Value: None
1724 static irqreturn_t
mgsl_interrupt(int irq
, void *dev_id
, struct pt_regs
* regs
)
1726 struct mgsl_struct
* info
;
1730 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1731 printk("%s(%d):mgsl_interrupt(%d)entry.\n",
1732 __FILE__
,__LINE__
,irq
);
1734 info
= (struct mgsl_struct
*)dev_id
;
1738 spin_lock(&info
->irq_spinlock
);
1741 /* Read the interrupt vectors from hardware. */
1742 UscVector
= usc_InReg(info
, IVR
) >> 9;
1743 DmaVector
= usc_InDmaReg(info
, DIVR
);
1745 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1746 printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1747 __FILE__
,__LINE__
,info
->device_name
,UscVector
,DmaVector
);
1749 if ( !UscVector
&& !DmaVector
)
1752 /* Dispatch interrupt vector */
1754 (*UscIsrTable
[UscVector
])(info
);
1755 else if ( (DmaVector
&(BIT10
|BIT9
)) == BIT10
)
1756 mgsl_isr_transmit_dma(info
);
1758 mgsl_isr_receive_dma(info
);
1760 if ( info
->isr_overflow
) {
1761 printk(KERN_ERR
"%s(%d):%s isr overflow irq=%d\n",
1762 __FILE__
,__LINE__
,info
->device_name
, irq
);
1763 usc_DisableMasterIrqBit(info
);
1764 usc_DisableDmaInterrupts(info
,DICR_MASTER
);
1769 /* Request bottom half processing if there's something
1770 * for it to do and the bh is not already running
1773 if ( info
->pending_bh
&& !info
->bh_running
&& !info
->bh_requested
) {
1774 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1775 printk("%s(%d):%s queueing bh task.\n",
1776 __FILE__
,__LINE__
,info
->device_name
);
1777 schedule_work(&info
->task
);
1778 info
->bh_requested
= 1;
1781 spin_unlock(&info
->irq_spinlock
);
1783 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1784 printk("%s(%d):mgsl_interrupt(%d)exit.\n",
1785 __FILE__
,__LINE__
,irq
);
1787 } /* end of mgsl_interrupt() */
1791 * Initialize and start device.
1793 * Arguments: info pointer to device instance data
1794 * Return Value: 0 if success, otherwise error code
1796 static int startup(struct mgsl_struct
* info
)
1800 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1801 printk("%s(%d):mgsl_startup(%s)\n",__FILE__
,__LINE__
,info
->device_name
);
1803 if (info
->flags
& ASYNC_INITIALIZED
)
1806 if (!info
->xmit_buf
) {
1807 /* allocate a page of memory for a transmit buffer */
1808 info
->xmit_buf
= (unsigned char *)get_zeroed_page(GFP_KERNEL
);
1809 if (!info
->xmit_buf
) {
1810 printk(KERN_ERR
"%s(%d):%s can't allocate transmit buffer\n",
1811 __FILE__
,__LINE__
,info
->device_name
);
1816 info
->pending_bh
= 0;
1818 memset(&info
->icount
, 0, sizeof(info
->icount
));
1820 init_timer(&info
->tx_timer
);
1821 info
->tx_timer
.data
= (unsigned long)info
;
1822 info
->tx_timer
.function
= mgsl_tx_timeout
;
1824 /* Allocate and claim adapter resources */
1825 retval
= mgsl_claim_resources(info
);
1827 /* perform existence check and diagnostics */
1829 retval
= mgsl_adapter_test(info
);
1832 if (capable(CAP_SYS_ADMIN
) && info
->tty
)
1833 set_bit(TTY_IO_ERROR
, &info
->tty
->flags
);
1834 mgsl_release_resources(info
);
1838 /* program hardware for current parameters */
1839 mgsl_change_params(info
);
1842 clear_bit(TTY_IO_ERROR
, &info
->tty
->flags
);
1844 info
->flags
|= ASYNC_INITIALIZED
;
1848 } /* end of startup() */
1852 * Called by mgsl_close() and mgsl_hangup() to shutdown hardware
1854 * Arguments: info pointer to device instance data
1855 * Return Value: None
1857 static void shutdown(struct mgsl_struct
* info
)
1859 unsigned long flags
;
1861 if (!(info
->flags
& ASYNC_INITIALIZED
))
1864 if (debug_level
>= DEBUG_LEVEL_INFO
)
1865 printk("%s(%d):mgsl_shutdown(%s)\n",
1866 __FILE__
,__LINE__
, info
->device_name
);
1868 /* clear status wait queue because status changes */
1869 /* can't happen after shutting down the hardware */
1870 wake_up_interruptible(&info
->status_event_wait_q
);
1871 wake_up_interruptible(&info
->event_wait_q
);
1873 del_timer(&info
->tx_timer
);
1875 if (info
->xmit_buf
) {
1876 free_page((unsigned long) info
->xmit_buf
);
1877 info
->xmit_buf
= NULL
;
1880 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1881 usc_DisableMasterIrqBit(info
);
1882 usc_stop_receiver(info
);
1883 usc_stop_transmitter(info
);
1884 usc_DisableInterrupts(info
,RECEIVE_DATA
+ RECEIVE_STATUS
+
1885 TRANSMIT_DATA
+ TRANSMIT_STATUS
+ IO_PIN
+ MISC
);
1886 usc_DisableDmaInterrupts(info
,DICR_MASTER
+ DICR_TRANSMIT
+ DICR_RECEIVE
);
1888 /* Disable DMAEN (Port 7, Bit 14) */
1889 /* This disconnects the DMA request signal from the ISA bus */
1890 /* on the ISA adapter. This has no effect for the PCI adapter */
1891 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT15
) | BIT14
));
1893 /* Disable INTEN (Port 6, Bit12) */
1894 /* This disconnects the IRQ request signal to the ISA bus */
1895 /* on the ISA adapter. This has no effect for the PCI adapter */
1896 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT13
) | BIT12
));
1898 if (!info
->tty
|| info
->tty
->termios
->c_cflag
& HUPCL
) {
1899 info
->serial_signals
&= ~(SerialSignal_DTR
+ SerialSignal_RTS
);
1900 usc_set_serial_signals(info
);
1903 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1905 mgsl_release_resources(info
);
1908 set_bit(TTY_IO_ERROR
, &info
->tty
->flags
);
1910 info
->flags
&= ~ASYNC_INITIALIZED
;
1912 } /* end of shutdown() */
1914 static void mgsl_program_hw(struct mgsl_struct
*info
)
1916 unsigned long flags
;
1918 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1920 usc_stop_receiver(info
);
1921 usc_stop_transmitter(info
);
1922 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
1924 if (info
->params
.mode
== MGSL_MODE_HDLC
||
1925 info
->params
.mode
== MGSL_MODE_RAW
||
1927 usc_set_sync_mode(info
);
1929 usc_set_async_mode(info
);
1931 usc_set_serial_signals(info
);
1933 info
->dcd_chkcount
= 0;
1934 info
->cts_chkcount
= 0;
1935 info
->ri_chkcount
= 0;
1936 info
->dsr_chkcount
= 0;
1938 usc_EnableStatusIrqs(info
,SICR_CTS
+SICR_DSR
+SICR_DCD
+SICR_RI
);
1939 usc_EnableInterrupts(info
, IO_PIN
);
1940 usc_get_serial_signals(info
);
1942 if (info
->netcount
|| info
->tty
->termios
->c_cflag
& CREAD
)
1943 usc_start_receiver(info
);
1945 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1948 /* Reconfigure adapter based on new parameters
1950 static void mgsl_change_params(struct mgsl_struct
*info
)
1955 if (!info
->tty
|| !info
->tty
->termios
)
1958 if (debug_level
>= DEBUG_LEVEL_INFO
)
1959 printk("%s(%d):mgsl_change_params(%s)\n",
1960 __FILE__
,__LINE__
, info
->device_name
);
1962 cflag
= info
->tty
->termios
->c_cflag
;
1964 /* if B0 rate (hangup) specified then negate DTR and RTS */
1965 /* otherwise assert DTR and RTS */
1967 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
1969 info
->serial_signals
&= ~(SerialSignal_RTS
+ SerialSignal_DTR
);
1971 /* byte size and parity */
1973 switch (cflag
& CSIZE
) {
1974 case CS5
: info
->params
.data_bits
= 5; break;
1975 case CS6
: info
->params
.data_bits
= 6; break;
1976 case CS7
: info
->params
.data_bits
= 7; break;
1977 case CS8
: info
->params
.data_bits
= 8; break;
1978 /* Never happens, but GCC is too dumb to figure it out */
1979 default: info
->params
.data_bits
= 7; break;
1983 info
->params
.stop_bits
= 2;
1985 info
->params
.stop_bits
= 1;
1987 info
->params
.parity
= ASYNC_PARITY_NONE
;
1988 if (cflag
& PARENB
) {
1990 info
->params
.parity
= ASYNC_PARITY_ODD
;
1992 info
->params
.parity
= ASYNC_PARITY_EVEN
;
1995 info
->params
.parity
= ASYNC_PARITY_SPACE
;
1999 /* calculate number of jiffies to transmit a full
2000 * FIFO (32 bytes) at specified data rate
2002 bits_per_char
= info
->params
.data_bits
+
2003 info
->params
.stop_bits
+ 1;
2005 /* if port data rate is set to 460800 or less then
2006 * allow tty settings to override, otherwise keep the
2007 * current data rate.
2009 if (info
->params
.data_rate
<= 460800)
2010 info
->params
.data_rate
= tty_get_baud_rate(info
->tty
);
2012 if ( info
->params
.data_rate
) {
2013 info
->timeout
= (32*HZ
*bits_per_char
) /
2014 info
->params
.data_rate
;
2016 info
->timeout
+= HZ
/50; /* Add .02 seconds of slop */
2018 if (cflag
& CRTSCTS
)
2019 info
->flags
|= ASYNC_CTS_FLOW
;
2021 info
->flags
&= ~ASYNC_CTS_FLOW
;
2024 info
->flags
&= ~ASYNC_CHECK_CD
;
2026 info
->flags
|= ASYNC_CHECK_CD
;
2028 /* process tty input control flags */
2030 info
->read_status_mask
= RXSTATUS_OVERRUN
;
2031 if (I_INPCK(info
->tty
))
2032 info
->read_status_mask
|= RXSTATUS_PARITY_ERROR
| RXSTATUS_FRAMING_ERROR
;
2033 if (I_BRKINT(info
->tty
) || I_PARMRK(info
->tty
))
2034 info
->read_status_mask
|= RXSTATUS_BREAK_RECEIVED
;
2036 if (I_IGNPAR(info
->tty
))
2037 info
->ignore_status_mask
|= RXSTATUS_PARITY_ERROR
| RXSTATUS_FRAMING_ERROR
;
2038 if (I_IGNBRK(info
->tty
)) {
2039 info
->ignore_status_mask
|= RXSTATUS_BREAK_RECEIVED
;
2040 /* If ignoring parity and break indicators, ignore
2041 * overruns too. (For real raw support).
2043 if (I_IGNPAR(info
->tty
))
2044 info
->ignore_status_mask
|= RXSTATUS_OVERRUN
;
2047 mgsl_program_hw(info
);
2049 } /* end of mgsl_change_params() */
2053 * Add a character to the transmit buffer.
2055 * Arguments: tty pointer to tty information structure
2056 * ch character to add to transmit buffer
2058 * Return Value: None
2060 static void mgsl_put_char(struct tty_struct
*tty
, unsigned char ch
)
2062 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2063 unsigned long flags
;
2065 if ( debug_level
>= DEBUG_LEVEL_INFO
) {
2066 printk( "%s(%d):mgsl_put_char(%d) on %s\n",
2067 __FILE__
,__LINE__
,ch
,info
->device_name
);
2070 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_put_char"))
2073 if (!tty
|| !info
->xmit_buf
)
2076 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2078 if ( (info
->params
.mode
== MGSL_MODE_ASYNC
) || !info
->tx_active
) {
2080 if (info
->xmit_cnt
< SERIAL_XMIT_SIZE
- 1) {
2081 info
->xmit_buf
[info
->xmit_head
++] = ch
;
2082 info
->xmit_head
&= SERIAL_XMIT_SIZE
-1;
2087 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2089 } /* end of mgsl_put_char() */
2091 /* mgsl_flush_chars()
2093 * Enable transmitter so remaining characters in the
2094 * transmit buffer are sent.
2096 * Arguments: tty pointer to tty information structure
2097 * Return Value: None
2099 static void mgsl_flush_chars(struct tty_struct
*tty
)
2101 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2102 unsigned long flags
;
2104 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2105 printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
2106 __FILE__
,__LINE__
,info
->device_name
,info
->xmit_cnt
);
2108 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_flush_chars"))
2111 if (info
->xmit_cnt
<= 0 || tty
->stopped
|| tty
->hw_stopped
||
2115 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2116 printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2117 __FILE__
,__LINE__
,info
->device_name
);
2119 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2121 if (!info
->tx_active
) {
2122 if ( (info
->params
.mode
== MGSL_MODE_HDLC
||
2123 info
->params
.mode
== MGSL_MODE_RAW
) && info
->xmit_cnt
) {
2124 /* operating in synchronous (frame oriented) mode */
2125 /* copy data from circular xmit_buf to */
2126 /* transmit DMA buffer. */
2127 mgsl_load_tx_dma_buffer(info
,
2128 info
->xmit_buf
,info
->xmit_cnt
);
2130 usc_start_transmitter(info
);
2133 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2135 } /* end of mgsl_flush_chars() */
2139 * Send a block of data
2143 * tty pointer to tty information structure
2144 * buf pointer to buffer containing send data
2145 * count size of send data in bytes
2147 * Return Value: number of characters written
2149 static int mgsl_write(struct tty_struct
* tty
,
2150 const unsigned char *buf
, int count
)
2153 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2154 unsigned long flags
;
2156 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2157 printk( "%s(%d):mgsl_write(%s) count=%d\n",
2158 __FILE__
,__LINE__
,info
->device_name
,count
);
2160 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_write"))
2163 if (!tty
|| !info
->xmit_buf
|| !tmp_buf
)
2166 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
2167 info
->params
.mode
== MGSL_MODE_RAW
) {
2168 /* operating in synchronous (frame oriented) mode */
2169 /* operating in synchronous (frame oriented) mode */
2170 if (info
->tx_active
) {
2172 if ( info
->params
.mode
== MGSL_MODE_HDLC
) {
2176 /* transmitter is actively sending data -
2177 * if we have multiple transmit dma and
2178 * holding buffers, attempt to queue this
2179 * frame for transmission at a later time.
2181 if (info
->tx_holding_count
>= info
->num_tx_holding_buffers
) {
2182 /* no tx holding buffers available */
2187 /* queue transmit frame request */
2189 save_tx_buffer_request(info
,buf
,count
);
2191 /* if we have sufficient tx dma buffers,
2192 * load the next buffered tx request
2194 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2195 load_next_tx_holding_buffer(info
);
2196 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2200 /* if operating in HDLC LoopMode and the adapter */
2201 /* has yet to be inserted into the loop, we can't */
2204 if ( (info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
) &&
2205 !usc_loopmode_active(info
) )
2211 if ( info
->xmit_cnt
) {
2212 /* Send accumulated from send_char() calls */
2213 /* as frame and wait before accepting more data. */
2216 /* copy data from circular xmit_buf to */
2217 /* transmit DMA buffer. */
2218 mgsl_load_tx_dma_buffer(info
,
2219 info
->xmit_buf
,info
->xmit_cnt
);
2220 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2221 printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2222 __FILE__
,__LINE__
,info
->device_name
);
2224 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2225 printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2226 __FILE__
,__LINE__
,info
->device_name
);
2228 info
->xmit_cnt
= count
;
2229 mgsl_load_tx_dma_buffer(info
,buf
,count
);
2233 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2234 c
= min_t(int, count
,
2235 min(SERIAL_XMIT_SIZE
- info
->xmit_cnt
- 1,
2236 SERIAL_XMIT_SIZE
- info
->xmit_head
));
2238 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2241 memcpy(info
->xmit_buf
+ info
->xmit_head
, buf
, c
);
2242 info
->xmit_head
= ((info
->xmit_head
+ c
) &
2243 (SERIAL_XMIT_SIZE
-1));
2244 info
->xmit_cnt
+= c
;
2245 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2252 if (info
->xmit_cnt
&& !tty
->stopped
&& !tty
->hw_stopped
) {
2253 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2254 if (!info
->tx_active
)
2255 usc_start_transmitter(info
);
2256 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2259 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2260 printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2261 __FILE__
,__LINE__
,info
->device_name
,ret
);
2265 } /* end of mgsl_write() */
2267 /* mgsl_write_room()
2269 * Return the count of free bytes in transmit buffer
2271 * Arguments: tty pointer to tty info structure
2272 * Return Value: None
2274 static int mgsl_write_room(struct tty_struct
*tty
)
2276 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2279 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_write_room"))
2281 ret
= SERIAL_XMIT_SIZE
- info
->xmit_cnt
- 1;
2285 if (debug_level
>= DEBUG_LEVEL_INFO
)
2286 printk("%s(%d):mgsl_write_room(%s)=%d\n",
2287 __FILE__
,__LINE__
, info
->device_name
,ret
);
2289 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
2290 info
->params
.mode
== MGSL_MODE_RAW
) {
2291 /* operating in synchronous (frame oriented) mode */
2292 if ( info
->tx_active
)
2295 return HDLC_MAX_FRAME_SIZE
;
2300 } /* end of mgsl_write_room() */
2302 /* mgsl_chars_in_buffer()
2304 * Return the count of bytes in transmit buffer
2306 * Arguments: tty pointer to tty info structure
2307 * Return Value: None
2309 static int mgsl_chars_in_buffer(struct tty_struct
*tty
)
2311 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2313 if (debug_level
>= DEBUG_LEVEL_INFO
)
2314 printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2315 __FILE__
,__LINE__
, info
->device_name
);
2317 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_chars_in_buffer"))
2320 if (debug_level
>= DEBUG_LEVEL_INFO
)
2321 printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2322 __FILE__
,__LINE__
, info
->device_name
,info
->xmit_cnt
);
2324 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
2325 info
->params
.mode
== MGSL_MODE_RAW
) {
2326 /* operating in synchronous (frame oriented) mode */
2327 if ( info
->tx_active
)
2328 return info
->max_frame_size
;
2333 return info
->xmit_cnt
;
2334 } /* end of mgsl_chars_in_buffer() */
2336 /* mgsl_flush_buffer()
2338 * Discard all data in the send buffer
2340 * Arguments: tty pointer to tty info structure
2341 * Return Value: None
2343 static void mgsl_flush_buffer(struct tty_struct
*tty
)
2345 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2346 unsigned long flags
;
2348 if (debug_level
>= DEBUG_LEVEL_INFO
)
2349 printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2350 __FILE__
,__LINE__
, info
->device_name
);
2352 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_flush_buffer"))
2355 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2356 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
2357 del_timer(&info
->tx_timer
);
2358 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2360 wake_up_interruptible(&tty
->write_wait
);
2364 /* mgsl_send_xchar()
2366 * Send a high-priority XON/XOFF character
2368 * Arguments: tty pointer to tty info structure
2369 * ch character to send
2370 * Return Value: None
2372 static void mgsl_send_xchar(struct tty_struct
*tty
, char ch
)
2374 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2375 unsigned long flags
;
2377 if (debug_level
>= DEBUG_LEVEL_INFO
)
2378 printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2379 __FILE__
,__LINE__
, info
->device_name
, ch
);
2381 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_send_xchar"))
2386 /* Make sure transmit interrupts are on */
2387 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2388 if (!info
->tx_enabled
)
2389 usc_start_transmitter(info
);
2390 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2392 } /* end of mgsl_send_xchar() */
2396 * Signal remote device to throttle send data (our receive data)
2398 * Arguments: tty pointer to tty info structure
2399 * Return Value: None
2401 static void mgsl_throttle(struct tty_struct
* tty
)
2403 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2404 unsigned long flags
;
2406 if (debug_level
>= DEBUG_LEVEL_INFO
)
2407 printk("%s(%d):mgsl_throttle(%s) entry\n",
2408 __FILE__
,__LINE__
, info
->device_name
);
2410 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_throttle"))
2414 mgsl_send_xchar(tty
, STOP_CHAR(tty
));
2416 if (tty
->termios
->c_cflag
& CRTSCTS
) {
2417 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2418 info
->serial_signals
&= ~SerialSignal_RTS
;
2419 usc_set_serial_signals(info
);
2420 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2422 } /* end of mgsl_throttle() */
2424 /* mgsl_unthrottle()
2426 * Signal remote device to stop throttling send data (our receive data)
2428 * Arguments: tty pointer to tty info structure
2429 * Return Value: None
2431 static void mgsl_unthrottle(struct tty_struct
* tty
)
2433 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2434 unsigned long flags
;
2436 if (debug_level
>= DEBUG_LEVEL_INFO
)
2437 printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2438 __FILE__
,__LINE__
, info
->device_name
);
2440 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_unthrottle"))
2447 mgsl_send_xchar(tty
, START_CHAR(tty
));
2450 if (tty
->termios
->c_cflag
& CRTSCTS
) {
2451 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2452 info
->serial_signals
|= SerialSignal_RTS
;
2453 usc_set_serial_signals(info
);
2454 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2457 } /* end of mgsl_unthrottle() */
2461 * get the current serial parameters information
2463 * Arguments: info pointer to device instance data
2464 * user_icount pointer to buffer to hold returned stats
2466 * Return Value: 0 if success, otherwise error code
2468 static int mgsl_get_stats(struct mgsl_struct
* info
, struct mgsl_icount __user
*user_icount
)
2472 if (debug_level
>= DEBUG_LEVEL_INFO
)
2473 printk("%s(%d):mgsl_get_params(%s)\n",
2474 __FILE__
,__LINE__
, info
->device_name
);
2477 memset(&info
->icount
, 0, sizeof(info
->icount
));
2479 COPY_TO_USER(err
, user_icount
, &info
->icount
, sizeof(struct mgsl_icount
));
2486 } /* end of mgsl_get_stats() */
2488 /* mgsl_get_params()
2490 * get the current serial parameters information
2492 * Arguments: info pointer to device instance data
2493 * user_params pointer to buffer to hold returned params
2495 * Return Value: 0 if success, otherwise error code
2497 static int mgsl_get_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*user_params
)
2500 if (debug_level
>= DEBUG_LEVEL_INFO
)
2501 printk("%s(%d):mgsl_get_params(%s)\n",
2502 __FILE__
,__LINE__
, info
->device_name
);
2504 COPY_TO_USER(err
,user_params
, &info
->params
, sizeof(MGSL_PARAMS
));
2506 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2507 printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2508 __FILE__
,__LINE__
,info
->device_name
);
2514 } /* end of mgsl_get_params() */
2516 /* mgsl_set_params()
2518 * set the serial parameters
2522 * info pointer to device instance data
2523 * new_params user buffer containing new serial params
2525 * Return Value: 0 if success, otherwise error code
2527 static int mgsl_set_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*new_params
)
2529 unsigned long flags
;
2530 MGSL_PARAMS tmp_params
;
2533 if (debug_level
>= DEBUG_LEVEL_INFO
)
2534 printk("%s(%d):mgsl_set_params %s\n", __FILE__
,__LINE__
,
2535 info
->device_name
);
2536 COPY_FROM_USER(err
,&tmp_params
, new_params
, sizeof(MGSL_PARAMS
));
2538 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2539 printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2540 __FILE__
,__LINE__
,info
->device_name
);
2544 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2545 memcpy(&info
->params
,&tmp_params
,sizeof(MGSL_PARAMS
));
2546 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2548 mgsl_change_params(info
);
2552 } /* end of mgsl_set_params() */
2554 /* mgsl_get_txidle()
2556 * get the current transmit idle mode
2558 * Arguments: info pointer to device instance data
2559 * idle_mode pointer to buffer to hold returned idle mode
2561 * Return Value: 0 if success, otherwise error code
2563 static int mgsl_get_txidle(struct mgsl_struct
* info
, int __user
*idle_mode
)
2567 if (debug_level
>= DEBUG_LEVEL_INFO
)
2568 printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2569 __FILE__
,__LINE__
, info
->device_name
, info
->idle_mode
);
2571 COPY_TO_USER(err
,idle_mode
, &info
->idle_mode
, sizeof(int));
2573 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2574 printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2575 __FILE__
,__LINE__
,info
->device_name
);
2581 } /* end of mgsl_get_txidle() */
2583 /* mgsl_set_txidle() service ioctl to set transmit idle mode
2585 * Arguments: info pointer to device instance data
2586 * idle_mode new idle mode
2588 * Return Value: 0 if success, otherwise error code
2590 static int mgsl_set_txidle(struct mgsl_struct
* info
, int idle_mode
)
2592 unsigned long flags
;
2594 if (debug_level
>= DEBUG_LEVEL_INFO
)
2595 printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__
,__LINE__
,
2596 info
->device_name
, idle_mode
);
2598 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2599 info
->idle_mode
= idle_mode
;
2600 usc_set_txidle( info
);
2601 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2604 } /* end of mgsl_set_txidle() */
2608 * enable or disable the transmitter
2612 * info pointer to device instance data
2613 * enable 1 = enable, 0 = disable
2615 * Return Value: 0 if success, otherwise error code
2617 static int mgsl_txenable(struct mgsl_struct
* info
, int enable
)
2619 unsigned long flags
;
2621 if (debug_level
>= DEBUG_LEVEL_INFO
)
2622 printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__
,__LINE__
,
2623 info
->device_name
, enable
);
2625 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2627 if ( !info
->tx_enabled
) {
2629 usc_start_transmitter(info
);
2630 /*--------------------------------------------------
2631 * if HDLC/SDLC Loop mode, attempt to insert the
2632 * station in the 'loop' by setting CMR:13. Upon
2633 * receipt of the next GoAhead (RxAbort) sequence,
2634 * the OnLoop indicator (CCSR:7) should go active
2635 * to indicate that we are on the loop
2636 *--------------------------------------------------*/
2637 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
2638 usc_loopmode_insert_request( info
);
2641 if ( info
->tx_enabled
)
2642 usc_stop_transmitter(info
);
2644 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2647 } /* end of mgsl_txenable() */
2649 /* mgsl_txabort() abort send HDLC frame
2651 * Arguments: info pointer to device instance data
2652 * Return Value: 0 if success, otherwise error code
2654 static int mgsl_txabort(struct mgsl_struct
* info
)
2656 unsigned long flags
;
2658 if (debug_level
>= DEBUG_LEVEL_INFO
)
2659 printk("%s(%d):mgsl_txabort(%s)\n", __FILE__
,__LINE__
,
2662 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2663 if ( info
->tx_active
&& info
->params
.mode
== MGSL_MODE_HDLC
)
2665 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
2666 usc_loopmode_cancel_transmit( info
);
2668 usc_TCmd(info
,TCmd_SendAbort
);
2670 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2673 } /* end of mgsl_txabort() */
2675 /* mgsl_rxenable() enable or disable the receiver
2677 * Arguments: info pointer to device instance data
2678 * enable 1 = enable, 0 = disable
2679 * Return Value: 0 if success, otherwise error code
2681 static int mgsl_rxenable(struct mgsl_struct
* info
, int enable
)
2683 unsigned long flags
;
2685 if (debug_level
>= DEBUG_LEVEL_INFO
)
2686 printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__
,__LINE__
,
2687 info
->device_name
, enable
);
2689 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2691 if ( !info
->rx_enabled
)
2692 usc_start_receiver(info
);
2694 if ( info
->rx_enabled
)
2695 usc_stop_receiver(info
);
2697 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2700 } /* end of mgsl_rxenable() */
2702 /* mgsl_wait_event() wait for specified event to occur
2704 * Arguments: info pointer to device instance data
2705 * mask pointer to bitmask of events to wait for
2706 * Return Value: 0 if successful and bit mask updated with
2707 * of events triggerred,
2708 * otherwise error code
2710 static int mgsl_wait_event(struct mgsl_struct
* info
, int __user
* mask_ptr
)
2712 unsigned long flags
;
2715 struct mgsl_icount cprev
, cnow
;
2718 struct _input_signal_events oldsigs
, newsigs
;
2719 DECLARE_WAITQUEUE(wait
, current
);
2721 COPY_FROM_USER(rc
,&mask
, mask_ptr
, sizeof(int));
2726 if (debug_level
>= DEBUG_LEVEL_INFO
)
2727 printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__
,__LINE__
,
2728 info
->device_name
, mask
);
2730 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2732 /* return immediately if state matches requested events */
2733 usc_get_serial_signals(info
);
2734 s
= info
->serial_signals
;
2736 ( ((s
& SerialSignal_DSR
) ? MgslEvent_DsrActive
:MgslEvent_DsrInactive
) +
2737 ((s
& SerialSignal_DCD
) ? MgslEvent_DcdActive
:MgslEvent_DcdInactive
) +
2738 ((s
& SerialSignal_CTS
) ? MgslEvent_CtsActive
:MgslEvent_CtsInactive
) +
2739 ((s
& SerialSignal_RI
) ? MgslEvent_RiActive
:MgslEvent_RiInactive
) );
2741 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2745 /* save current irq counts */
2746 cprev
= info
->icount
;
2747 oldsigs
= info
->input_signal_events
;
2749 /* enable hunt and idle irqs if needed */
2750 if (mask
& (MgslEvent_ExitHuntMode
+ MgslEvent_IdleReceived
)) {
2751 u16 oldreg
= usc_InReg(info
,RICR
);
2752 u16 newreg
= oldreg
+
2753 (mask
& MgslEvent_ExitHuntMode
? RXSTATUS_EXITED_HUNT
:0) +
2754 (mask
& MgslEvent_IdleReceived
? RXSTATUS_IDLE_RECEIVED
:0);
2755 if (oldreg
!= newreg
)
2756 usc_OutReg(info
, RICR
, newreg
);
2759 set_current_state(TASK_INTERRUPTIBLE
);
2760 add_wait_queue(&info
->event_wait_q
, &wait
);
2762 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2767 if (signal_pending(current
)) {
2772 /* get current irq counts */
2773 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2774 cnow
= info
->icount
;
2775 newsigs
= info
->input_signal_events
;
2776 set_current_state(TASK_INTERRUPTIBLE
);
2777 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2779 /* if no change, wait aborted for some reason */
2780 if (newsigs
.dsr_up
== oldsigs
.dsr_up
&&
2781 newsigs
.dsr_down
== oldsigs
.dsr_down
&&
2782 newsigs
.dcd_up
== oldsigs
.dcd_up
&&
2783 newsigs
.dcd_down
== oldsigs
.dcd_down
&&
2784 newsigs
.cts_up
== oldsigs
.cts_up
&&
2785 newsigs
.cts_down
== oldsigs
.cts_down
&&
2786 newsigs
.ri_up
== oldsigs
.ri_up
&&
2787 newsigs
.ri_down
== oldsigs
.ri_down
&&
2788 cnow
.exithunt
== cprev
.exithunt
&&
2789 cnow
.rxidle
== cprev
.rxidle
) {
2795 ( (newsigs
.dsr_up
!= oldsigs
.dsr_up
? MgslEvent_DsrActive
:0) +
2796 (newsigs
.dsr_down
!= oldsigs
.dsr_down
? MgslEvent_DsrInactive
:0) +
2797 (newsigs
.dcd_up
!= oldsigs
.dcd_up
? MgslEvent_DcdActive
:0) +
2798 (newsigs
.dcd_down
!= oldsigs
.dcd_down
? MgslEvent_DcdInactive
:0) +
2799 (newsigs
.cts_up
!= oldsigs
.cts_up
? MgslEvent_CtsActive
:0) +
2800 (newsigs
.cts_down
!= oldsigs
.cts_down
? MgslEvent_CtsInactive
:0) +
2801 (newsigs
.ri_up
!= oldsigs
.ri_up
? MgslEvent_RiActive
:0) +
2802 (newsigs
.ri_down
!= oldsigs
.ri_down
? MgslEvent_RiInactive
:0) +
2803 (cnow
.exithunt
!= cprev
.exithunt
? MgslEvent_ExitHuntMode
:0) +
2804 (cnow
.rxidle
!= cprev
.rxidle
? MgslEvent_IdleReceived
:0) );
2812 remove_wait_queue(&info
->event_wait_q
, &wait
);
2813 set_current_state(TASK_RUNNING
);
2815 if (mask
& (MgslEvent_ExitHuntMode
+ MgslEvent_IdleReceived
)) {
2816 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2817 if (!waitqueue_active(&info
->event_wait_q
)) {
2818 /* disable enable exit hunt mode/idle rcvd IRQs */
2819 usc_OutReg(info
, RICR
, usc_InReg(info
,RICR
) &
2820 ~(RXSTATUS_EXITED_HUNT
+ RXSTATUS_IDLE_RECEIVED
));
2822 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2826 PUT_USER(rc
, events
, mask_ptr
);
2830 } /* end of mgsl_wait_event() */
2832 static int modem_input_wait(struct mgsl_struct
*info
,int arg
)
2834 unsigned long flags
;
2836 struct mgsl_icount cprev
, cnow
;
2837 DECLARE_WAITQUEUE(wait
, current
);
2839 /* save current irq counts */
2840 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2841 cprev
= info
->icount
;
2842 add_wait_queue(&info
->status_event_wait_q
, &wait
);
2843 set_current_state(TASK_INTERRUPTIBLE
);
2844 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2848 if (signal_pending(current
)) {
2853 /* get new irq counts */
2854 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2855 cnow
= info
->icount
;
2856 set_current_state(TASK_INTERRUPTIBLE
);
2857 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2859 /* if no change, wait aborted for some reason */
2860 if (cnow
.rng
== cprev
.rng
&& cnow
.dsr
== cprev
.dsr
&&
2861 cnow
.dcd
== cprev
.dcd
&& cnow
.cts
== cprev
.cts
) {
2866 /* check for change in caller specified modem input */
2867 if ((arg
& TIOCM_RNG
&& cnow
.rng
!= cprev
.rng
) ||
2868 (arg
& TIOCM_DSR
&& cnow
.dsr
!= cprev
.dsr
) ||
2869 (arg
& TIOCM_CD
&& cnow
.dcd
!= cprev
.dcd
) ||
2870 (arg
& TIOCM_CTS
&& cnow
.cts
!= cprev
.cts
)) {
2877 remove_wait_queue(&info
->status_event_wait_q
, &wait
);
2878 set_current_state(TASK_RUNNING
);
2882 /* return the state of the serial control and status signals
2884 static int tiocmget(struct tty_struct
*tty
, struct file
*file
)
2886 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2887 unsigned int result
;
2888 unsigned long flags
;
2890 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2891 usc_get_serial_signals(info
);
2892 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2894 result
= ((info
->serial_signals
& SerialSignal_RTS
) ? TIOCM_RTS
:0) +
2895 ((info
->serial_signals
& SerialSignal_DTR
) ? TIOCM_DTR
:0) +
2896 ((info
->serial_signals
& SerialSignal_DCD
) ? TIOCM_CAR
:0) +
2897 ((info
->serial_signals
& SerialSignal_RI
) ? TIOCM_RNG
:0) +
2898 ((info
->serial_signals
& SerialSignal_DSR
) ? TIOCM_DSR
:0) +
2899 ((info
->serial_signals
& SerialSignal_CTS
) ? TIOCM_CTS
:0);
2901 if (debug_level
>= DEBUG_LEVEL_INFO
)
2902 printk("%s(%d):%s tiocmget() value=%08X\n",
2903 __FILE__
,__LINE__
, info
->device_name
, result
);
2907 /* set modem control signals (DTR/RTS)
2909 static int tiocmset(struct tty_struct
*tty
, struct file
*file
,
2910 unsigned int set
, unsigned int clear
)
2912 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2913 unsigned long flags
;
2915 if (debug_level
>= DEBUG_LEVEL_INFO
)
2916 printk("%s(%d):%s tiocmset(%x,%x)\n",
2917 __FILE__
,__LINE__
,info
->device_name
, set
, clear
);
2919 if (set
& TIOCM_RTS
)
2920 info
->serial_signals
|= SerialSignal_RTS
;
2921 if (set
& TIOCM_DTR
)
2922 info
->serial_signals
|= SerialSignal_DTR
;
2923 if (clear
& TIOCM_RTS
)
2924 info
->serial_signals
&= ~SerialSignal_RTS
;
2925 if (clear
& TIOCM_DTR
)
2926 info
->serial_signals
&= ~SerialSignal_DTR
;
2928 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2929 usc_set_serial_signals(info
);
2930 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2935 /* mgsl_break() Set or clear transmit break condition
2937 * Arguments: tty pointer to tty instance data
2938 * break_state -1=set break condition, 0=clear
2939 * Return Value: None
2941 static void mgsl_break(struct tty_struct
*tty
, int break_state
)
2943 struct mgsl_struct
* info
= (struct mgsl_struct
*)tty
->driver_data
;
2944 unsigned long flags
;
2946 if (debug_level
>= DEBUG_LEVEL_INFO
)
2947 printk("%s(%d):mgsl_break(%s,%d)\n",
2948 __FILE__
,__LINE__
, info
->device_name
, break_state
);
2950 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_break"))
2953 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2954 if (break_state
== -1)
2955 usc_OutReg(info
,IOCR
,(u16
)(usc_InReg(info
,IOCR
) | BIT7
));
2957 usc_OutReg(info
,IOCR
,(u16
)(usc_InReg(info
,IOCR
) & ~BIT7
));
2958 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2960 } /* end of mgsl_break() */
2962 /* mgsl_ioctl() Service an IOCTL request
2966 * tty pointer to tty instance data
2967 * file pointer to associated file object for device
2968 * cmd IOCTL command code
2969 * arg command argument/context
2971 * Return Value: 0 if success, otherwise error code
2973 static int mgsl_ioctl(struct tty_struct
*tty
, struct file
* file
,
2974 unsigned int cmd
, unsigned long arg
)
2976 struct mgsl_struct
* info
= (struct mgsl_struct
*)tty
->driver_data
;
2978 if (debug_level
>= DEBUG_LEVEL_INFO
)
2979 printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__
,__LINE__
,
2980 info
->device_name
, cmd
);
2982 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_ioctl"))
2985 if ((cmd
!= TIOCGSERIAL
) && (cmd
!= TIOCSSERIAL
) &&
2986 (cmd
!= TIOCMIWAIT
) && (cmd
!= TIOCGICOUNT
)) {
2987 if (tty
->flags
& (1 << TTY_IO_ERROR
))
2991 return mgsl_ioctl_common(info
, cmd
, arg
);
2994 static int mgsl_ioctl_common(struct mgsl_struct
*info
, unsigned int cmd
, unsigned long arg
)
2997 struct mgsl_icount cnow
; /* kernel counter temps */
2998 void __user
*argp
= (void __user
*)arg
;
2999 struct serial_icounter_struct __user
*p_cuser
; /* user space */
3000 unsigned long flags
;
3003 case MGSL_IOCGPARAMS
:
3004 return mgsl_get_params(info
, argp
);
3005 case MGSL_IOCSPARAMS
:
3006 return mgsl_set_params(info
, argp
);
3007 case MGSL_IOCGTXIDLE
:
3008 return mgsl_get_txidle(info
, argp
);
3009 case MGSL_IOCSTXIDLE
:
3010 return mgsl_set_txidle(info
,(int)arg
);
3011 case MGSL_IOCTXENABLE
:
3012 return mgsl_txenable(info
,(int)arg
);
3013 case MGSL_IOCRXENABLE
:
3014 return mgsl_rxenable(info
,(int)arg
);
3015 case MGSL_IOCTXABORT
:
3016 return mgsl_txabort(info
);
3017 case MGSL_IOCGSTATS
:
3018 return mgsl_get_stats(info
, argp
);
3019 case MGSL_IOCWAITEVENT
:
3020 return mgsl_wait_event(info
, argp
);
3021 case MGSL_IOCLOOPTXDONE
:
3022 return mgsl_loopmode_send_done(info
);
3023 /* Wait for modem input (DCD,RI,DSR,CTS) change
3024 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
3027 return modem_input_wait(info
,(int)arg
);
3030 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
3031 * Return: write counters to the user passed counter struct
3032 * NB: both 1->0 and 0->1 transitions are counted except for
3033 * RI where only 0->1 is counted.
3036 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3037 cnow
= info
->icount
;
3038 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3040 PUT_USER(error
,cnow
.cts
, &p_cuser
->cts
);
3041 if (error
) return error
;
3042 PUT_USER(error
,cnow
.dsr
, &p_cuser
->dsr
);
3043 if (error
) return error
;
3044 PUT_USER(error
,cnow
.rng
, &p_cuser
->rng
);
3045 if (error
) return error
;
3046 PUT_USER(error
,cnow
.dcd
, &p_cuser
->dcd
);
3047 if (error
) return error
;
3048 PUT_USER(error
,cnow
.rx
, &p_cuser
->rx
);
3049 if (error
) return error
;
3050 PUT_USER(error
,cnow
.tx
, &p_cuser
->tx
);
3051 if (error
) return error
;
3052 PUT_USER(error
,cnow
.frame
, &p_cuser
->frame
);
3053 if (error
) return error
;
3054 PUT_USER(error
,cnow
.overrun
, &p_cuser
->overrun
);
3055 if (error
) return error
;
3056 PUT_USER(error
,cnow
.parity
, &p_cuser
->parity
);
3057 if (error
) return error
;
3058 PUT_USER(error
,cnow
.brk
, &p_cuser
->brk
);
3059 if (error
) return error
;
3060 PUT_USER(error
,cnow
.buf_overrun
, &p_cuser
->buf_overrun
);
3061 if (error
) return error
;
3064 return -ENOIOCTLCMD
;
3069 /* mgsl_set_termios()
3071 * Set new termios settings
3075 * tty pointer to tty structure
3076 * termios pointer to buffer to hold returned old termios
3078 * Return Value: None
3080 static void mgsl_set_termios(struct tty_struct
*tty
, struct termios
*old_termios
)
3082 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
3083 unsigned long flags
;
3085 if (debug_level
>= DEBUG_LEVEL_INFO
)
3086 printk("%s(%d):mgsl_set_termios %s\n", __FILE__
,__LINE__
,
3087 tty
->driver
->name
);
3089 /* just return if nothing has changed */
3090 if ((tty
->termios
->c_cflag
== old_termios
->c_cflag
)
3091 && (RELEVANT_IFLAG(tty
->termios
->c_iflag
)
3092 == RELEVANT_IFLAG(old_termios
->c_iflag
)))
3095 mgsl_change_params(info
);
3097 /* Handle transition to B0 status */
3098 if (old_termios
->c_cflag
& CBAUD
&&
3099 !(tty
->termios
->c_cflag
& CBAUD
)) {
3100 info
->serial_signals
&= ~(SerialSignal_RTS
+ SerialSignal_DTR
);
3101 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3102 usc_set_serial_signals(info
);
3103 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3106 /* Handle transition away from B0 status */
3107 if (!(old_termios
->c_cflag
& CBAUD
) &&
3108 tty
->termios
->c_cflag
& CBAUD
) {
3109 info
->serial_signals
|= SerialSignal_DTR
;
3110 if (!(tty
->termios
->c_cflag
& CRTSCTS
) ||
3111 !test_bit(TTY_THROTTLED
, &tty
->flags
)) {
3112 info
->serial_signals
|= SerialSignal_RTS
;
3114 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3115 usc_set_serial_signals(info
);
3116 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3119 /* Handle turning off CRTSCTS */
3120 if (old_termios
->c_cflag
& CRTSCTS
&&
3121 !(tty
->termios
->c_cflag
& CRTSCTS
)) {
3122 tty
->hw_stopped
= 0;
3126 } /* end of mgsl_set_termios() */
3130 * Called when port is closed. Wait for remaining data to be
3131 * sent. Disable port and free resources.
3135 * tty pointer to open tty structure
3136 * filp pointer to open file object
3138 * Return Value: None
3140 static void mgsl_close(struct tty_struct
*tty
, struct file
* filp
)
3142 struct mgsl_struct
* info
= (struct mgsl_struct
*)tty
->driver_data
;
3144 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_close"))
3147 if (debug_level
>= DEBUG_LEVEL_INFO
)
3148 printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
3149 __FILE__
,__LINE__
, info
->device_name
, info
->count
);
3154 if (tty_hung_up_p(filp
))
3157 if ((tty
->count
== 1) && (info
->count
!= 1)) {
3159 * tty->count is 1 and the tty structure will be freed.
3160 * info->count should be one in this case.
3161 * if it's not, correct it so that the port is shutdown.
3163 printk("mgsl_close: bad refcount; tty->count is 1, "
3164 "info->count is %d\n", info
->count
);
3170 /* if at least one open remaining, leave hardware active */
3174 info
->flags
|= ASYNC_CLOSING
;
3176 /* set tty->closing to notify line discipline to
3177 * only process XON/XOFF characters. Only the N_TTY
3178 * discipline appears to use this (ppp does not).
3182 /* wait for transmit data to clear all layers */
3184 if (info
->closing_wait
!= ASYNC_CLOSING_WAIT_NONE
) {
3185 if (debug_level
>= DEBUG_LEVEL_INFO
)
3186 printk("%s(%d):mgsl_close(%s) calling tty_wait_until_sent\n",
3187 __FILE__
,__LINE__
, info
->device_name
);
3188 tty_wait_until_sent(tty
, info
->closing_wait
);
3191 if (info
->flags
& ASYNC_INITIALIZED
)
3192 mgsl_wait_until_sent(tty
, info
->timeout
);
3194 if (tty
->driver
->flush_buffer
)
3195 tty
->driver
->flush_buffer(tty
);
3197 tty_ldisc_flush(tty
);
3204 if (info
->blocked_open
) {
3205 if (info
->close_delay
) {
3206 msleep_interruptible(jiffies_to_msecs(info
->close_delay
));
3208 wake_up_interruptible(&info
->open_wait
);
3211 info
->flags
&= ~(ASYNC_NORMAL_ACTIVE
|ASYNC_CLOSING
);
3213 wake_up_interruptible(&info
->close_wait
);
3216 if (debug_level
>= DEBUG_LEVEL_INFO
)
3217 printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__
,__LINE__
,
3218 tty
->driver
->name
, info
->count
);
3220 } /* end of mgsl_close() */
3222 /* mgsl_wait_until_sent()
3224 * Wait until the transmitter is empty.
3228 * tty pointer to tty info structure
3229 * timeout time to wait for send completion
3231 * Return Value: None
3233 static void mgsl_wait_until_sent(struct tty_struct
*tty
, int timeout
)
3235 struct mgsl_struct
* info
= (struct mgsl_struct
*)tty
->driver_data
;
3236 unsigned long orig_jiffies
, char_time
;
3241 if (debug_level
>= DEBUG_LEVEL_INFO
)
3242 printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3243 __FILE__
,__LINE__
, info
->device_name
);
3245 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_wait_until_sent"))
3248 if (!(info
->flags
& ASYNC_INITIALIZED
))
3251 orig_jiffies
= jiffies
;
3253 /* Set check interval to 1/5 of estimated time to
3254 * send a character, and make it at least 1. The check
3255 * interval should also be less than the timeout.
3256 * Note: use tight timings here to satisfy the NIST-PCTS.
3259 if ( info
->params
.data_rate
) {
3260 char_time
= info
->timeout
/(32 * 5);
3267 char_time
= min_t(unsigned long, char_time
, timeout
);
3269 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
3270 info
->params
.mode
== MGSL_MODE_RAW
) {
3271 while (info
->tx_active
) {
3272 msleep_interruptible(jiffies_to_msecs(char_time
));
3273 if (signal_pending(current
))
3275 if (timeout
&& time_after(jiffies
, orig_jiffies
+ timeout
))
3279 while (!(usc_InReg(info
,TCSR
) & TXSTATUS_ALL_SENT
) &&
3281 msleep_interruptible(jiffies_to_msecs(char_time
));
3282 if (signal_pending(current
))
3284 if (timeout
&& time_after(jiffies
, orig_jiffies
+ timeout
))
3290 if (debug_level
>= DEBUG_LEVEL_INFO
)
3291 printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3292 __FILE__
,__LINE__
, info
->device_name
);
3294 } /* end of mgsl_wait_until_sent() */
3298 * Called by tty_hangup() when a hangup is signaled.
3299 * This is the same as to closing all open files for the port.
3301 * Arguments: tty pointer to associated tty object
3302 * Return Value: None
3304 static void mgsl_hangup(struct tty_struct
*tty
)
3306 struct mgsl_struct
* info
= (struct mgsl_struct
*)tty
->driver_data
;
3308 if (debug_level
>= DEBUG_LEVEL_INFO
)
3309 printk("%s(%d):mgsl_hangup(%s)\n",
3310 __FILE__
,__LINE__
, info
->device_name
);
3312 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_hangup"))
3315 mgsl_flush_buffer(tty
);
3319 info
->flags
&= ~ASYNC_NORMAL_ACTIVE
;
3322 wake_up_interruptible(&info
->open_wait
);
3324 } /* end of mgsl_hangup() */
3326 /* block_til_ready()
3328 * Block the current process until the specified port
3329 * is ready to be opened.
3333 * tty pointer to tty info structure
3334 * filp pointer to open file object
3335 * info pointer to device instance data
3337 * Return Value: 0 if success, otherwise error code
3339 static int block_til_ready(struct tty_struct
*tty
, struct file
* filp
,
3340 struct mgsl_struct
*info
)
3342 DECLARE_WAITQUEUE(wait
, current
);
3344 int do_clocal
= 0, extra_count
= 0;
3345 unsigned long flags
;
3347 if (debug_level
>= DEBUG_LEVEL_INFO
)
3348 printk("%s(%d):block_til_ready on %s\n",
3349 __FILE__
,__LINE__
, tty
->driver
->name
);
3351 if (filp
->f_flags
& O_NONBLOCK
|| tty
->flags
& (1 << TTY_IO_ERROR
)){
3352 /* nonblock mode is set or port is not enabled */
3353 info
->flags
|= ASYNC_NORMAL_ACTIVE
;
3357 if (tty
->termios
->c_cflag
& CLOCAL
)
3360 /* Wait for carrier detect and the line to become
3361 * free (i.e., not in use by the callout). While we are in
3362 * this loop, info->count is dropped by one, so that
3363 * mgsl_close() knows when to free things. We restore it upon
3364 * exit, either normal or abnormal.
3368 add_wait_queue(&info
->open_wait
, &wait
);
3370 if (debug_level
>= DEBUG_LEVEL_INFO
)
3371 printk("%s(%d):block_til_ready before block on %s count=%d\n",
3372 __FILE__
,__LINE__
, tty
->driver
->name
, info
->count
);
3374 spin_lock_irqsave(&info
->irq_spinlock
, flags
);
3375 if (!tty_hung_up_p(filp
)) {
3379 spin_unlock_irqrestore(&info
->irq_spinlock
, flags
);
3380 info
->blocked_open
++;
3383 if (tty
->termios
->c_cflag
& CBAUD
) {
3384 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3385 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
3386 usc_set_serial_signals(info
);
3387 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3390 set_current_state(TASK_INTERRUPTIBLE
);
3392 if (tty_hung_up_p(filp
) || !(info
->flags
& ASYNC_INITIALIZED
)){
3393 retval
= (info
->flags
& ASYNC_HUP_NOTIFY
) ?
3394 -EAGAIN
: -ERESTARTSYS
;
3398 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3399 usc_get_serial_signals(info
);
3400 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3402 if (!(info
->flags
& ASYNC_CLOSING
) &&
3403 (do_clocal
|| (info
->serial_signals
& SerialSignal_DCD
)) ) {
3407 if (signal_pending(current
)) {
3408 retval
= -ERESTARTSYS
;
3412 if (debug_level
>= DEBUG_LEVEL_INFO
)
3413 printk("%s(%d):block_til_ready blocking on %s count=%d\n",
3414 __FILE__
,__LINE__
, tty
->driver
->name
, info
->count
);
3419 set_current_state(TASK_RUNNING
);
3420 remove_wait_queue(&info
->open_wait
, &wait
);
3424 info
->blocked_open
--;
3426 if (debug_level
>= DEBUG_LEVEL_INFO
)
3427 printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
3428 __FILE__
,__LINE__
, tty
->driver
->name
, info
->count
);
3431 info
->flags
|= ASYNC_NORMAL_ACTIVE
;
3435 } /* end of block_til_ready() */
3439 * Called when a port is opened. Init and enable port.
3440 * Perform serial-specific initialization for the tty structure.
3442 * Arguments: tty pointer to tty info structure
3443 * filp associated file pointer
3445 * Return Value: 0 if success, otherwise error code
3447 static int mgsl_open(struct tty_struct
*tty
, struct file
* filp
)
3449 struct mgsl_struct
*info
;
3452 unsigned long flags
;
3454 /* verify range of specified line number */
3456 if ((line
< 0) || (line
>= mgsl_device_count
)) {
3457 printk("%s(%d):mgsl_open with invalid line #%d.\n",
3458 __FILE__
,__LINE__
,line
);
3462 /* find the info structure for the specified line */
3463 info
= mgsl_device_list
;
3464 while(info
&& info
->line
!= line
)
3465 info
= info
->next_device
;
3466 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_open"))
3469 tty
->driver_data
= info
;
3472 if (debug_level
>= DEBUG_LEVEL_INFO
)
3473 printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
3474 __FILE__
,__LINE__
,tty
->driver
->name
, info
->count
);
3476 /* If port is closing, signal caller to try again */
3477 if (tty_hung_up_p(filp
) || info
->flags
& ASYNC_CLOSING
){
3478 if (info
->flags
& ASYNC_CLOSING
)
3479 interruptible_sleep_on(&info
->close_wait
);
3480 retval
= ((info
->flags
& ASYNC_HUP_NOTIFY
) ?
3481 -EAGAIN
: -ERESTARTSYS
);
3486 page
= get_zeroed_page(GFP_KERNEL
);
3494 tmp_buf
= (unsigned char *) page
;
3497 info
->tty
->low_latency
= (info
->flags
& ASYNC_LOW_LATENCY
) ? 1 : 0;
3499 spin_lock_irqsave(&info
->netlock
, flags
);
3500 if (info
->netcount
) {
3502 spin_unlock_irqrestore(&info
->netlock
, flags
);
3506 spin_unlock_irqrestore(&info
->netlock
, flags
);
3508 if (info
->count
== 1) {
3509 /* 1st open on this device, init hardware */
3510 retval
= startup(info
);
3515 retval
= block_til_ready(tty
, filp
, info
);
3517 if (debug_level
>= DEBUG_LEVEL_INFO
)
3518 printk("%s(%d):block_til_ready(%s) returned %d\n",
3519 __FILE__
,__LINE__
, info
->device_name
, retval
);
3523 if (debug_level
>= DEBUG_LEVEL_INFO
)
3524 printk("%s(%d):mgsl_open(%s) success\n",
3525 __FILE__
,__LINE__
, info
->device_name
);
3530 if (tty
->count
== 1)
3531 info
->tty
= NULL
; /* tty layer will release tty struct */
3538 } /* end of mgsl_open() */
3541 * /proc fs routines....
3544 static inline int line_info(char *buf
, struct mgsl_struct
*info
)
3548 unsigned long flags
;
3550 if (info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3551 ret
= sprintf(buf
, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3552 info
->device_name
, info
->io_base
, info
->irq_level
,
3553 info
->phys_memory_base
, info
->phys_lcr_base
);
3555 ret
= sprintf(buf
, "%s:(E)ISA io:%04X irq:%d dma:%d",
3556 info
->device_name
, info
->io_base
,
3557 info
->irq_level
, info
->dma_level
);
3560 /* output current serial signal states */
3561 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3562 usc_get_serial_signals(info
);
3563 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3567 if (info
->serial_signals
& SerialSignal_RTS
)
3568 strcat(stat_buf
, "|RTS");
3569 if (info
->serial_signals
& SerialSignal_CTS
)
3570 strcat(stat_buf
, "|CTS");
3571 if (info
->serial_signals
& SerialSignal_DTR
)
3572 strcat(stat_buf
, "|DTR");
3573 if (info
->serial_signals
& SerialSignal_DSR
)
3574 strcat(stat_buf
, "|DSR");
3575 if (info
->serial_signals
& SerialSignal_DCD
)
3576 strcat(stat_buf
, "|CD");
3577 if (info
->serial_signals
& SerialSignal_RI
)
3578 strcat(stat_buf
, "|RI");
3580 if (info
->params
.mode
== MGSL_MODE_HDLC
||
3581 info
->params
.mode
== MGSL_MODE_RAW
) {
3582 ret
+= sprintf(buf
+ret
, " HDLC txok:%d rxok:%d",
3583 info
->icount
.txok
, info
->icount
.rxok
);
3584 if (info
->icount
.txunder
)
3585 ret
+= sprintf(buf
+ret
, " txunder:%d", info
->icount
.txunder
);
3586 if (info
->icount
.txabort
)
3587 ret
+= sprintf(buf
+ret
, " txabort:%d", info
->icount
.txabort
);
3588 if (info
->icount
.rxshort
)
3589 ret
+= sprintf(buf
+ret
, " rxshort:%d", info
->icount
.rxshort
);
3590 if (info
->icount
.rxlong
)
3591 ret
+= sprintf(buf
+ret
, " rxlong:%d", info
->icount
.rxlong
);
3592 if (info
->icount
.rxover
)
3593 ret
+= sprintf(buf
+ret
, " rxover:%d", info
->icount
.rxover
);
3594 if (info
->icount
.rxcrc
)
3595 ret
+= sprintf(buf
+ret
, " rxcrc:%d", info
->icount
.rxcrc
);
3597 ret
+= sprintf(buf
+ret
, " ASYNC tx:%d rx:%d",
3598 info
->icount
.tx
, info
->icount
.rx
);
3599 if (info
->icount
.frame
)
3600 ret
+= sprintf(buf
+ret
, " fe:%d", info
->icount
.frame
);
3601 if (info
->icount
.parity
)
3602 ret
+= sprintf(buf
+ret
, " pe:%d", info
->icount
.parity
);
3603 if (info
->icount
.brk
)
3604 ret
+= sprintf(buf
+ret
, " brk:%d", info
->icount
.brk
);
3605 if (info
->icount
.overrun
)
3606 ret
+= sprintf(buf
+ret
, " oe:%d", info
->icount
.overrun
);
3609 /* Append serial signal status to end */
3610 ret
+= sprintf(buf
+ret
, " %s\n", stat_buf
+1);
3612 ret
+= sprintf(buf
+ret
, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
3613 info
->tx_active
,info
->bh_requested
,info
->bh_running
,
3616 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3618 u16 Tcsr
= usc_InReg( info
, TCSR
);
3619 u16 Tdmr
= usc_InDmaReg( info
, TDMR
);
3620 u16 Ticr
= usc_InReg( info
, TICR
);
3621 u16 Rscr
= usc_InReg( info
, RCSR
);
3622 u16 Rdmr
= usc_InDmaReg( info
, RDMR
);
3623 u16 Ricr
= usc_InReg( info
, RICR
);
3624 u16 Icr
= usc_InReg( info
, ICR
);
3625 u16 Dccr
= usc_InReg( info
, DCCR
);
3626 u16 Tmr
= usc_InReg( info
, TMR
);
3627 u16 Tccr
= usc_InReg( info
, TCCR
);
3628 u16 Ccar
= inw( info
->io_base
+ CCAR
);
3629 ret
+= sprintf(buf
+ret
, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
3630 "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3631 Tcsr
,Tdmr
,Ticr
,Rscr
,Rdmr
,Ricr
,Icr
,Dccr
,Tmr
,Tccr
,Ccar
);
3633 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3637 } /* end of line_info() */
3641 * Called to print information about devices
3644 * page page of memory to hold returned info
3653 static int mgsl_read_proc(char *page
, char **start
, off_t off
, int count
,
3654 int *eof
, void *data
)
3658 struct mgsl_struct
*info
;
3660 len
+= sprintf(page
, "synclink driver:%s\n", driver_version
);
3662 info
= mgsl_device_list
;
3664 l
= line_info(page
+ len
, info
);
3666 if (len
+begin
> off
+count
)
3668 if (len
+begin
< off
) {
3672 info
= info
->next_device
;
3677 if (off
>= len
+begin
)
3679 *start
= page
+ (off
-begin
);
3680 return ((count
< begin
+len
-off
) ? count
: begin
+len
-off
);
3682 } /* end of mgsl_read_proc() */
3684 /* mgsl_allocate_dma_buffers()
3686 * Allocate and format DMA buffers (ISA adapter)
3687 * or format shared memory buffers (PCI adapter).
3689 * Arguments: info pointer to device instance data
3690 * Return Value: 0 if success, otherwise error
3692 static int mgsl_allocate_dma_buffers(struct mgsl_struct
*info
)
3694 unsigned short BuffersPerFrame
;
3696 info
->last_mem_alloc
= 0;
3698 /* Calculate the number of DMA buffers necessary to hold the */
3699 /* largest allowable frame size. Note: If the max frame size is */
3700 /* not an even multiple of the DMA buffer size then we need to */
3701 /* round the buffer count per frame up one. */
3703 BuffersPerFrame
= (unsigned short)(info
->max_frame_size
/DMABUFFERSIZE
);
3704 if ( info
->max_frame_size
% DMABUFFERSIZE
)
3707 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3709 * The PCI adapter has 256KBytes of shared memory to use.
3710 * This is 64 PAGE_SIZE buffers.
3712 * The first page is used for padding at this time so the
3713 * buffer list does not begin at offset 0 of the PCI
3714 * adapter's shared memory.
3716 * The 2nd page is used for the buffer list. A 4K buffer
3717 * list can hold 128 DMA_BUFFER structures at 32 bytes
3720 * This leaves 62 4K pages.
3722 * The next N pages are used for transmit frame(s). We
3723 * reserve enough 4K page blocks to hold the required
3724 * number of transmit dma buffers (num_tx_dma_buffers),
3725 * each of MaxFrameSize size.
3727 * Of the remaining pages (62-N), determine how many can
3728 * be used to receive full MaxFrameSize inbound frames
3730 info
->tx_buffer_count
= info
->num_tx_dma_buffers
* BuffersPerFrame
;
3731 info
->rx_buffer_count
= 62 - info
->tx_buffer_count
;
3733 /* Calculate the number of PAGE_SIZE buffers needed for */
3734 /* receive and transmit DMA buffers. */
3737 /* Calculate the number of DMA buffers necessary to */
3738 /* hold 7 max size receive frames and one max size transmit frame. */
3739 /* The receive buffer count is bumped by one so we avoid an */
3740 /* End of List condition if all receive buffers are used when */
3741 /* using linked list DMA buffers. */
3743 info
->tx_buffer_count
= info
->num_tx_dma_buffers
* BuffersPerFrame
;
3744 info
->rx_buffer_count
= (BuffersPerFrame
* MAXRXFRAMES
) + 6;
3747 * limit total TxBuffers & RxBuffers to 62 4K total
3748 * (ala PCI Allocation)
3751 if ( (info
->tx_buffer_count
+ info
->rx_buffer_count
) > 62 )
3752 info
->rx_buffer_count
= 62 - info
->tx_buffer_count
;
3756 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3757 printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3758 __FILE__
,__LINE__
, info
->tx_buffer_count
,info
->rx_buffer_count
);
3760 if ( mgsl_alloc_buffer_list_memory( info
) < 0 ||
3761 mgsl_alloc_frame_memory(info
, info
->rx_buffer_list
, info
->rx_buffer_count
) < 0 ||
3762 mgsl_alloc_frame_memory(info
, info
->tx_buffer_list
, info
->tx_buffer_count
) < 0 ||
3763 mgsl_alloc_intermediate_rxbuffer_memory(info
) < 0 ||
3764 mgsl_alloc_intermediate_txbuffer_memory(info
) < 0 ) {
3765 printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__
,__LINE__
);
3769 mgsl_reset_rx_dma_buffers( info
);
3770 mgsl_reset_tx_dma_buffers( info
);
3774 } /* end of mgsl_allocate_dma_buffers() */
3777 * mgsl_alloc_buffer_list_memory()
3779 * Allocate a common DMA buffer for use as the
3780 * receive and transmit buffer lists.
3782 * A buffer list is a set of buffer entries where each entry contains
3783 * a pointer to an actual buffer and a pointer to the next buffer entry
3784 * (plus some other info about the buffer).
3786 * The buffer entries for a list are built to form a circular list so
3787 * that when the entire list has been traversed you start back at the
3790 * This function allocates memory for just the buffer entries.
3791 * The links (pointer to next entry) are filled in with the physical
3792 * address of the next entry so the adapter can navigate the list
3793 * using bus master DMA. The pointers to the actual buffers are filled
3794 * out later when the actual buffers are allocated.
3796 * Arguments: info pointer to device instance data
3797 * Return Value: 0 if success, otherwise error
3799 static int mgsl_alloc_buffer_list_memory( struct mgsl_struct
*info
)
3803 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3804 /* PCI adapter uses shared memory. */
3805 info
->buffer_list
= info
->memory_base
+ info
->last_mem_alloc
;
3806 info
->buffer_list_phys
= info
->last_mem_alloc
;
3807 info
->last_mem_alloc
+= BUFFERLISTSIZE
;
3809 /* ISA adapter uses system memory. */
3810 /* The buffer lists are allocated as a common buffer that both */
3811 /* the processor and adapter can access. This allows the driver to */
3812 /* inspect portions of the buffer while other portions are being */
3813 /* updated by the adapter using Bus Master DMA. */
3815 info
->buffer_list
= kmalloc(BUFFERLISTSIZE
, GFP_KERNEL
| GFP_DMA
);
3816 if ( info
->buffer_list
== NULL
)
3819 info
->buffer_list_phys
= isa_virt_to_bus(info
->buffer_list
);
3822 /* We got the memory for the buffer entry lists. */
3823 /* Initialize the memory block to all zeros. */
3824 memset( info
->buffer_list
, 0, BUFFERLISTSIZE
);
3826 /* Save virtual address pointers to the receive and */
3827 /* transmit buffer lists. (Receive 1st). These pointers will */
3828 /* be used by the processor to access the lists. */
3829 info
->rx_buffer_list
= (DMABUFFERENTRY
*)info
->buffer_list
;
3830 info
->tx_buffer_list
= (DMABUFFERENTRY
*)info
->buffer_list
;
3831 info
->tx_buffer_list
+= info
->rx_buffer_count
;
3834 * Build the links for the buffer entry lists such that
3835 * two circular lists are built. (Transmit and Receive).
3837 * Note: the links are physical addresses
3838 * which are read by the adapter to determine the next
3839 * buffer entry to use.
3842 for ( i
= 0; i
< info
->rx_buffer_count
; i
++ ) {
3843 /* calculate and store physical address of this buffer entry */
3844 info
->rx_buffer_list
[i
].phys_entry
=
3845 info
->buffer_list_phys
+ (i
* sizeof(DMABUFFERENTRY
));
3847 /* calculate and store physical address of */
3848 /* next entry in cirular list of entries */
3850 info
->rx_buffer_list
[i
].link
= info
->buffer_list_phys
;
3852 if ( i
< info
->rx_buffer_count
- 1 )
3853 info
->rx_buffer_list
[i
].link
+= (i
+ 1) * sizeof(DMABUFFERENTRY
);
3856 for ( i
= 0; i
< info
->tx_buffer_count
; i
++ ) {
3857 /* calculate and store physical address of this buffer entry */
3858 info
->tx_buffer_list
[i
].phys_entry
= info
->buffer_list_phys
+
3859 ((info
->rx_buffer_count
+ i
) * sizeof(DMABUFFERENTRY
));
3861 /* calculate and store physical address of */
3862 /* next entry in cirular list of entries */
3864 info
->tx_buffer_list
[i
].link
= info
->buffer_list_phys
+
3865 info
->rx_buffer_count
* sizeof(DMABUFFERENTRY
);
3867 if ( i
< info
->tx_buffer_count
- 1 )
3868 info
->tx_buffer_list
[i
].link
+= (i
+ 1) * sizeof(DMABUFFERENTRY
);
3873 } /* end of mgsl_alloc_buffer_list_memory() */
3875 /* Free DMA buffers allocated for use as the
3876 * receive and transmit buffer lists.
3879 * The data transfer buffers associated with the buffer list
3880 * MUST be freed before freeing the buffer list itself because
3881 * the buffer list contains the information necessary to free
3882 * the individual buffers!
3884 static void mgsl_free_buffer_list_memory( struct mgsl_struct
*info
)
3886 if ( info
->buffer_list
&& info
->bus_type
!= MGSL_BUS_TYPE_PCI
)
3887 kfree(info
->buffer_list
);
3889 info
->buffer_list
= NULL
;
3890 info
->rx_buffer_list
= NULL
;
3891 info
->tx_buffer_list
= NULL
;
3893 } /* end of mgsl_free_buffer_list_memory() */
3896 * mgsl_alloc_frame_memory()
3898 * Allocate the frame DMA buffers used by the specified buffer list.
3899 * Each DMA buffer will be one memory page in size. This is necessary
3900 * because memory can fragment enough that it may be impossible
3905 * info pointer to device instance data
3906 * BufferList pointer to list of buffer entries
3907 * Buffercount count of buffer entries in buffer list
3909 * Return Value: 0 if success, otherwise -ENOMEM
3911 static int mgsl_alloc_frame_memory(struct mgsl_struct
*info
,DMABUFFERENTRY
*BufferList
,int Buffercount
)
3914 unsigned long phys_addr
;
3916 /* Allocate page sized buffers for the receive buffer list */
3918 for ( i
= 0; i
< Buffercount
; i
++ ) {
3919 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3920 /* PCI adapter uses shared memory buffers. */
3921 BufferList
[i
].virt_addr
= info
->memory_base
+ info
->last_mem_alloc
;
3922 phys_addr
= info
->last_mem_alloc
;
3923 info
->last_mem_alloc
+= DMABUFFERSIZE
;
3925 /* ISA adapter uses system memory. */
3926 BufferList
[i
].virt_addr
=
3927 kmalloc(DMABUFFERSIZE
, GFP_KERNEL
| GFP_DMA
);
3928 if ( BufferList
[i
].virt_addr
== NULL
)
3930 phys_addr
= isa_virt_to_bus(BufferList
[i
].virt_addr
);
3932 BufferList
[i
].phys_addr
= phys_addr
;
3937 } /* end of mgsl_alloc_frame_memory() */
3940 * mgsl_free_frame_memory()
3942 * Free the buffers associated with
3943 * each buffer entry of a buffer list.
3947 * info pointer to device instance data
3948 * BufferList pointer to list of buffer entries
3949 * Buffercount count of buffer entries in buffer list
3951 * Return Value: None
3953 static void mgsl_free_frame_memory(struct mgsl_struct
*info
, DMABUFFERENTRY
*BufferList
, int Buffercount
)
3958 for ( i
= 0 ; i
< Buffercount
; i
++ ) {
3959 if ( BufferList
[i
].virt_addr
) {
3960 if ( info
->bus_type
!= MGSL_BUS_TYPE_PCI
)
3961 kfree(BufferList
[i
].virt_addr
);
3962 BufferList
[i
].virt_addr
= NULL
;
3967 } /* end of mgsl_free_frame_memory() */
3969 /* mgsl_free_dma_buffers()
3973 * Arguments: info pointer to device instance data
3974 * Return Value: None
3976 static void mgsl_free_dma_buffers( struct mgsl_struct
*info
)
3978 mgsl_free_frame_memory( info
, info
->rx_buffer_list
, info
->rx_buffer_count
);
3979 mgsl_free_frame_memory( info
, info
->tx_buffer_list
, info
->tx_buffer_count
);
3980 mgsl_free_buffer_list_memory( info
);
3982 } /* end of mgsl_free_dma_buffers() */
3986 * mgsl_alloc_intermediate_rxbuffer_memory()
3988 * Allocate a buffer large enough to hold max_frame_size. This buffer
3989 * is used to pass an assembled frame to the line discipline.
3993 * info pointer to device instance data
3995 * Return Value: 0 if success, otherwise -ENOMEM
3997 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct
*info
)
3999 info
->intermediate_rxbuffer
= kmalloc(info
->max_frame_size
, GFP_KERNEL
| GFP_DMA
);
4000 if ( info
->intermediate_rxbuffer
== NULL
)
4005 } /* end of mgsl_alloc_intermediate_rxbuffer_memory() */
4008 * mgsl_free_intermediate_rxbuffer_memory()
4013 * info pointer to device instance data
4015 * Return Value: None
4017 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct
*info
)
4019 if ( info
->intermediate_rxbuffer
)
4020 kfree(info
->intermediate_rxbuffer
);
4022 info
->intermediate_rxbuffer
= NULL
;
4024 } /* end of mgsl_free_intermediate_rxbuffer_memory() */
4027 * mgsl_alloc_intermediate_txbuffer_memory()
4029 * Allocate intermdiate transmit buffer(s) large enough to hold max_frame_size.
4030 * This buffer is used to load transmit frames into the adapter's dma transfer
4031 * buffers when there is sufficient space.
4035 * info pointer to device instance data
4037 * Return Value: 0 if success, otherwise -ENOMEM
4039 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct
*info
)
4043 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4044 printk("%s %s(%d) allocating %d tx holding buffers\n",
4045 info
->device_name
, __FILE__
,__LINE__
,info
->num_tx_holding_buffers
);
4047 memset(info
->tx_holding_buffers
,0,sizeof(info
->tx_holding_buffers
));
4049 for ( i
=0; i
<info
->num_tx_holding_buffers
; ++i
) {
4050 info
->tx_holding_buffers
[i
].buffer
=
4051 kmalloc(info
->max_frame_size
, GFP_KERNEL
);
4052 if ( info
->tx_holding_buffers
[i
].buffer
== NULL
)
4058 } /* end of mgsl_alloc_intermediate_txbuffer_memory() */
4061 * mgsl_free_intermediate_txbuffer_memory()
4066 * info pointer to device instance data
4068 * Return Value: None
4070 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct
*info
)
4074 for ( i
=0; i
<info
->num_tx_holding_buffers
; ++i
) {
4075 if ( info
->tx_holding_buffers
[i
].buffer
) {
4076 kfree(info
->tx_holding_buffers
[i
].buffer
);
4077 info
->tx_holding_buffers
[i
].buffer
=NULL
;
4081 info
->get_tx_holding_index
= 0;
4082 info
->put_tx_holding_index
= 0;
4083 info
->tx_holding_count
= 0;
4085 } /* end of mgsl_free_intermediate_txbuffer_memory() */
4089 * load_next_tx_holding_buffer()
4091 * attempts to load the next buffered tx request into the
4096 * info pointer to device instance data
4098 * Return Value: 1 if next buffered tx request loaded
4099 * into adapter's tx dma buffer,
4102 static int load_next_tx_holding_buffer(struct mgsl_struct
*info
)
4106 if ( info
->tx_holding_count
) {
4107 /* determine if we have enough tx dma buffers
4108 * to accommodate the next tx frame
4110 struct tx_holding_buffer
*ptx
=
4111 &info
->tx_holding_buffers
[info
->get_tx_holding_index
];
4112 int num_free
= num_free_tx_dma_buffers(info
);
4113 int num_needed
= ptx
->buffer_size
/ DMABUFFERSIZE
;
4114 if ( ptx
->buffer_size
% DMABUFFERSIZE
)
4117 if (num_needed
<= num_free
) {
4118 info
->xmit_cnt
= ptx
->buffer_size
;
4119 mgsl_load_tx_dma_buffer(info
,ptx
->buffer
,ptx
->buffer_size
);
4121 --info
->tx_holding_count
;
4122 if ( ++info
->get_tx_holding_index
>= info
->num_tx_holding_buffers
)
4123 info
->get_tx_holding_index
=0;
4125 /* restart transmit timer */
4126 mod_timer(&info
->tx_timer
, jiffies
+ msecs_to_jiffies(5000));
4136 * save_tx_buffer_request()
4138 * attempt to store transmit frame request for later transmission
4142 * info pointer to device instance data
4143 * Buffer pointer to buffer containing frame to load
4144 * BufferSize size in bytes of frame in Buffer
4146 * Return Value: 1 if able to store, 0 otherwise
4148 static int save_tx_buffer_request(struct mgsl_struct
*info
,const char *Buffer
, unsigned int BufferSize
)
4150 struct tx_holding_buffer
*ptx
;
4152 if ( info
->tx_holding_count
>= info
->num_tx_holding_buffers
) {
4153 return 0; /* all buffers in use */
4156 ptx
= &info
->tx_holding_buffers
[info
->put_tx_holding_index
];
4157 ptx
->buffer_size
= BufferSize
;
4158 memcpy( ptx
->buffer
, Buffer
, BufferSize
);
4160 ++info
->tx_holding_count
;
4161 if ( ++info
->put_tx_holding_index
>= info
->num_tx_holding_buffers
)
4162 info
->put_tx_holding_index
=0;
4167 static int mgsl_claim_resources(struct mgsl_struct
*info
)
4169 if (request_region(info
->io_base
,info
->io_addr_size
,"synclink") == NULL
) {
4170 printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4171 __FILE__
,__LINE__
,info
->device_name
, info
->io_base
);
4174 info
->io_addr_requested
= 1;
4176 if ( request_irq(info
->irq_level
,mgsl_interrupt
,info
->irq_flags
,
4177 info
->device_name
, info
) < 0 ) {
4178 printk( "%s(%d):Cant request interrupt on device %s IRQ=%d\n",
4179 __FILE__
,__LINE__
,info
->device_name
, info
->irq_level
);
4182 info
->irq_requested
= 1;
4184 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
4185 if (request_mem_region(info
->phys_memory_base
,0x40000,"synclink") == NULL
) {
4186 printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4187 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
4190 info
->shared_mem_requested
= 1;
4191 if (request_mem_region(info
->phys_lcr_base
+ info
->lcr_offset
,128,"synclink") == NULL
) {
4192 printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4193 __FILE__
,__LINE__
,info
->device_name
, info
->phys_lcr_base
+ info
->lcr_offset
);
4196 info
->lcr_mem_requested
= 1;
4198 info
->memory_base
= ioremap(info
->phys_memory_base
,0x40000);
4199 if (!info
->memory_base
) {
4200 printk( "%s(%d):Cant map shared memory on device %s MemAddr=%08X\n",
4201 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
4205 if ( !mgsl_memory_test(info
) ) {
4206 printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4207 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
4211 info
->lcr_base
= ioremap(info
->phys_lcr_base
,PAGE_SIZE
) + info
->lcr_offset
;
4212 if (!info
->lcr_base
) {
4213 printk( "%s(%d):Cant map LCR memory on device %s MemAddr=%08X\n",
4214 __FILE__
,__LINE__
,info
->device_name
, info
->phys_lcr_base
);
4219 /* claim DMA channel */
4221 if (request_dma(info
->dma_level
,info
->device_name
) < 0){
4222 printk( "%s(%d):Cant request DMA channel on device %s DMA=%d\n",
4223 __FILE__
,__LINE__
,info
->device_name
, info
->dma_level
);
4224 mgsl_release_resources( info
);
4227 info
->dma_requested
= 1;
4229 /* ISA adapter uses bus master DMA */
4230 set_dma_mode(info
->dma_level
,DMA_MODE_CASCADE
);
4231 enable_dma(info
->dma_level
);
4234 if ( mgsl_allocate_dma_buffers(info
) < 0 ) {
4235 printk( "%s(%d):Cant allocate DMA buffers on device %s DMA=%d\n",
4236 __FILE__
,__LINE__
,info
->device_name
, info
->dma_level
);
4242 mgsl_release_resources(info
);
4245 } /* end of mgsl_claim_resources() */
4247 static void mgsl_release_resources(struct mgsl_struct
*info
)
4249 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4250 printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4251 __FILE__
,__LINE__
,info
->device_name
);
4253 if ( info
->irq_requested
) {
4254 free_irq(info
->irq_level
, info
);
4255 info
->irq_requested
= 0;
4257 if ( info
->dma_requested
) {
4258 disable_dma(info
->dma_level
);
4259 free_dma(info
->dma_level
);
4260 info
->dma_requested
= 0;
4262 mgsl_free_dma_buffers(info
);
4263 mgsl_free_intermediate_rxbuffer_memory(info
);
4264 mgsl_free_intermediate_txbuffer_memory(info
);
4266 if ( info
->io_addr_requested
) {
4267 release_region(info
->io_base
,info
->io_addr_size
);
4268 info
->io_addr_requested
= 0;
4270 if ( info
->shared_mem_requested
) {
4271 release_mem_region(info
->phys_memory_base
,0x40000);
4272 info
->shared_mem_requested
= 0;
4274 if ( info
->lcr_mem_requested
) {
4275 release_mem_region(info
->phys_lcr_base
+ info
->lcr_offset
,128);
4276 info
->lcr_mem_requested
= 0;
4278 if (info
->memory_base
){
4279 iounmap(info
->memory_base
);
4280 info
->memory_base
= NULL
;
4282 if (info
->lcr_base
){
4283 iounmap(info
->lcr_base
- info
->lcr_offset
);
4284 info
->lcr_base
= NULL
;
4287 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4288 printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4289 __FILE__
,__LINE__
,info
->device_name
);
4291 } /* end of mgsl_release_resources() */
4293 /* mgsl_add_device()
4295 * Add the specified device instance data structure to the
4296 * global linked list of devices and increment the device count.
4298 * Arguments: info pointer to device instance data
4299 * Return Value: None
4301 static void mgsl_add_device( struct mgsl_struct
*info
)
4303 info
->next_device
= NULL
;
4304 info
->line
= mgsl_device_count
;
4305 sprintf(info
->device_name
,"ttySL%d",info
->line
);
4307 if (info
->line
< MAX_TOTAL_DEVICES
) {
4308 if (maxframe
[info
->line
])
4309 info
->max_frame_size
= maxframe
[info
->line
];
4310 info
->dosyncppp
= dosyncppp
[info
->line
];
4312 if (txdmabufs
[info
->line
]) {
4313 info
->num_tx_dma_buffers
= txdmabufs
[info
->line
];
4314 if (info
->num_tx_dma_buffers
< 1)
4315 info
->num_tx_dma_buffers
= 1;
4318 if (txholdbufs
[info
->line
]) {
4319 info
->num_tx_holding_buffers
= txholdbufs
[info
->line
];
4320 if (info
->num_tx_holding_buffers
< 1)
4321 info
->num_tx_holding_buffers
= 1;
4322 else if (info
->num_tx_holding_buffers
> MAX_TX_HOLDING_BUFFERS
)
4323 info
->num_tx_holding_buffers
= MAX_TX_HOLDING_BUFFERS
;
4327 mgsl_device_count
++;
4329 if ( !mgsl_device_list
)
4330 mgsl_device_list
= info
;
4332 struct mgsl_struct
*current_dev
= mgsl_device_list
;
4333 while( current_dev
->next_device
)
4334 current_dev
= current_dev
->next_device
;
4335 current_dev
->next_device
= info
;
4338 if ( info
->max_frame_size
< 4096 )
4339 info
->max_frame_size
= 4096;
4340 else if ( info
->max_frame_size
> 65535 )
4341 info
->max_frame_size
= 65535;
4343 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
4344 printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4345 info
->hw_version
+ 1, info
->device_name
, info
->io_base
, info
->irq_level
,
4346 info
->phys_memory_base
, info
->phys_lcr_base
,
4347 info
->max_frame_size
);
4349 printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4350 info
->device_name
, info
->io_base
, info
->irq_level
, info
->dma_level
,
4351 info
->max_frame_size
);
4358 } /* end of mgsl_add_device() */
4360 /* mgsl_allocate_device()
4362 * Allocate and initialize a device instance structure
4365 * Return Value: pointer to mgsl_struct if success, otherwise NULL
4367 static struct mgsl_struct
* mgsl_allocate_device(void)
4369 struct mgsl_struct
*info
;
4371 info
= (struct mgsl_struct
*)kmalloc(sizeof(struct mgsl_struct
),
4375 printk("Error can't allocate device instance data\n");
4377 memset(info
, 0, sizeof(struct mgsl_struct
));
4378 info
->magic
= MGSL_MAGIC
;
4379 INIT_WORK(&info
->task
, mgsl_bh_handler
, info
);
4380 info
->max_frame_size
= 4096;
4381 info
->close_delay
= 5*HZ
/10;
4382 info
->closing_wait
= 30*HZ
;
4383 init_waitqueue_head(&info
->open_wait
);
4384 init_waitqueue_head(&info
->close_wait
);
4385 init_waitqueue_head(&info
->status_event_wait_q
);
4386 init_waitqueue_head(&info
->event_wait_q
);
4387 spin_lock_init(&info
->irq_spinlock
);
4388 spin_lock_init(&info
->netlock
);
4389 memcpy(&info
->params
,&default_params
,sizeof(MGSL_PARAMS
));
4390 info
->idle_mode
= HDLC_TXIDLE_FLAGS
;
4391 info
->num_tx_dma_buffers
= 1;
4392 info
->num_tx_holding_buffers
= 0;
4397 } /* end of mgsl_allocate_device()*/
4399 static struct tty_operations mgsl_ops
= {
4401 .close
= mgsl_close
,
4402 .write
= mgsl_write
,
4403 .put_char
= mgsl_put_char
,
4404 .flush_chars
= mgsl_flush_chars
,
4405 .write_room
= mgsl_write_room
,
4406 .chars_in_buffer
= mgsl_chars_in_buffer
,
4407 .flush_buffer
= mgsl_flush_buffer
,
4408 .ioctl
= mgsl_ioctl
,
4409 .throttle
= mgsl_throttle
,
4410 .unthrottle
= mgsl_unthrottle
,
4411 .send_xchar
= mgsl_send_xchar
,
4412 .break_ctl
= mgsl_break
,
4413 .wait_until_sent
= mgsl_wait_until_sent
,
4414 .read_proc
= mgsl_read_proc
,
4415 .set_termios
= mgsl_set_termios
,
4417 .start
= mgsl_start
,
4418 .hangup
= mgsl_hangup
,
4419 .tiocmget
= tiocmget
,
4420 .tiocmset
= tiocmset
,
4424 * perform tty device initialization
4426 static int mgsl_init_tty(void)
4430 serial_driver
= alloc_tty_driver(128);
4434 serial_driver
->owner
= THIS_MODULE
;
4435 serial_driver
->driver_name
= "synclink";
4436 serial_driver
->name
= "ttySL";
4437 serial_driver
->major
= ttymajor
;
4438 serial_driver
->minor_start
= 64;
4439 serial_driver
->type
= TTY_DRIVER_TYPE_SERIAL
;
4440 serial_driver
->subtype
= SERIAL_TYPE_NORMAL
;
4441 serial_driver
->init_termios
= tty_std_termios
;
4442 serial_driver
->init_termios
.c_cflag
=
4443 B9600
| CS8
| CREAD
| HUPCL
| CLOCAL
;
4444 serial_driver
->flags
= TTY_DRIVER_REAL_RAW
;
4445 tty_set_operations(serial_driver
, &mgsl_ops
);
4446 if ((rc
= tty_register_driver(serial_driver
)) < 0) {
4447 printk("%s(%d):Couldn't register serial driver\n",
4449 put_tty_driver(serial_driver
);
4450 serial_driver
= NULL
;
4454 printk("%s %s, tty major#%d\n",
4455 driver_name
, driver_version
,
4456 serial_driver
->major
);
4460 /* enumerate user specified ISA adapters
4462 static void mgsl_enum_isa_devices(void)
4464 struct mgsl_struct
*info
;
4467 /* Check for user specified ISA devices */
4469 for (i
=0 ;(i
< MAX_ISA_DEVICES
) && io
[i
] && irq
[i
]; i
++){
4470 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4471 printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4472 io
[i
], irq
[i
], dma
[i
] );
4474 info
= mgsl_allocate_device();
4476 /* error allocating device instance data */
4477 if ( debug_level
>= DEBUG_LEVEL_ERROR
)
4478 printk( "can't allocate device instance data.\n");
4482 /* Copy user configuration info to device instance data */
4483 info
->io_base
= (unsigned int)io
[i
];
4484 info
->irq_level
= (unsigned int)irq
[i
];
4485 info
->irq_level
= irq_canonicalize(info
->irq_level
);
4486 info
->dma_level
= (unsigned int)dma
[i
];
4487 info
->bus_type
= MGSL_BUS_TYPE_ISA
;
4488 info
->io_addr_size
= 16;
4489 info
->irq_flags
= 0;
4491 mgsl_add_device( info
);
4495 static void synclink_cleanup(void)
4498 struct mgsl_struct
*info
;
4499 struct mgsl_struct
*tmp
;
4501 printk("Unloading %s: %s\n", driver_name
, driver_version
);
4503 if (serial_driver
) {
4504 if ((rc
= tty_unregister_driver(serial_driver
)))
4505 printk("%s(%d) failed to unregister tty driver err=%d\n",
4506 __FILE__
,__LINE__
,rc
);
4507 put_tty_driver(serial_driver
);
4510 info
= mgsl_device_list
;
4515 mgsl_release_resources(info
);
4517 info
= info
->next_device
;
4522 free_page((unsigned long) tmp_buf
);
4527 pci_unregister_driver(&synclink_pci_driver
);
4530 static int __init
synclink_init(void)
4534 if (break_on_load
) {
4535 mgsl_get_text_ptr();
4539 printk("%s %s\n", driver_name
, driver_version
);
4541 mgsl_enum_isa_devices();
4542 if ((rc
= pci_register_driver(&synclink_pci_driver
)) < 0)
4543 printk("%s:failed to register PCI driver, error=%d\n",__FILE__
,rc
);
4547 if ((rc
= mgsl_init_tty()) < 0)
4557 static void __exit
synclink_exit(void)
4562 module_init(synclink_init
);
4563 module_exit(synclink_exit
);
4568 * Issue a USC Receive/Transmit command to the
4569 * Channel Command/Address Register (CCAR).
4573 * The command is encoded in the most significant 5 bits <15..11>
4574 * of the CCAR value. Bits <10..7> of the CCAR must be preserved
4575 * and Bits <6..0> must be written as zeros.
4579 * info pointer to device information structure
4580 * Cmd command mask (use symbolic macros)
4586 static void usc_RTCmd( struct mgsl_struct
*info
, u16 Cmd
)
4588 /* output command to CCAR in bits <15..11> */
4589 /* preserve bits <10..7>, bits <6..0> must be zero */
4591 outw( Cmd
+ info
->loopback_bits
, info
->io_base
+ CCAR
);
4593 /* Read to flush write to CCAR */
4594 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4595 inw( info
->io_base
+ CCAR
);
4597 } /* end of usc_RTCmd() */
4602 * Issue a DMA command to the DMA Command/Address Register (DCAR).
4606 * info pointer to device information structure
4607 * Cmd DMA command mask (usc_DmaCmd_XX Macros)
4613 static void usc_DmaCmd( struct mgsl_struct
*info
, u16 Cmd
)
4615 /* write command mask to DCAR */
4616 outw( Cmd
+ info
->mbre_bit
, info
->io_base
);
4618 /* Read to flush write to DCAR */
4619 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4620 inw( info
->io_base
);
4622 } /* end of usc_DmaCmd() */
4627 * Write a 16-bit value to a USC DMA register
4631 * info pointer to device info structure
4632 * RegAddr register address (number) for write
4633 * RegValue 16-bit value to write to register
4640 static void usc_OutDmaReg( struct mgsl_struct
*info
, u16 RegAddr
, u16 RegValue
)
4642 /* Note: The DCAR is located at the adapter base address */
4643 /* Note: must preserve state of BIT8 in DCAR */
4645 outw( RegAddr
+ info
->mbre_bit
, info
->io_base
);
4646 outw( RegValue
, info
->io_base
);
4648 /* Read to flush write to DCAR */
4649 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4650 inw( info
->io_base
);
4652 } /* end of usc_OutDmaReg() */
4657 * Read a 16-bit value from a DMA register
4661 * info pointer to device info structure
4662 * RegAddr register address (number) to read from
4666 * The 16-bit value read from register
4669 static u16
usc_InDmaReg( struct mgsl_struct
*info
, u16 RegAddr
)
4671 /* Note: The DCAR is located at the adapter base address */
4672 /* Note: must preserve state of BIT8 in DCAR */
4674 outw( RegAddr
+ info
->mbre_bit
, info
->io_base
);
4675 return inw( info
->io_base
);
4677 } /* end of usc_InDmaReg() */
4683 * Write a 16-bit value to a USC serial channel register
4687 * info pointer to device info structure
4688 * RegAddr register address (number) to write to
4689 * RegValue 16-bit value to write to register
4696 static void usc_OutReg( struct mgsl_struct
*info
, u16 RegAddr
, u16 RegValue
)
4698 outw( RegAddr
+ info
->loopback_bits
, info
->io_base
+ CCAR
);
4699 outw( RegValue
, info
->io_base
+ CCAR
);
4701 /* Read to flush write to CCAR */
4702 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4703 inw( info
->io_base
+ CCAR
);
4705 } /* end of usc_OutReg() */
4710 * Reads a 16-bit value from a USC serial channel register
4714 * info pointer to device extension
4715 * RegAddr register address (number) to read from
4719 * 16-bit value read from register
4721 static u16
usc_InReg( struct mgsl_struct
*info
, u16 RegAddr
)
4723 outw( RegAddr
+ info
->loopback_bits
, info
->io_base
+ CCAR
);
4724 return inw( info
->io_base
+ CCAR
);
4726 } /* end of usc_InReg() */
4728 /* usc_set_sdlc_mode()
4730 * Set up the adapter for SDLC DMA communications.
4732 * Arguments: info pointer to device instance data
4733 * Return Value: NONE
4735 static void usc_set_sdlc_mode( struct mgsl_struct
*info
)
4741 * determine if the IUSC on the adapter is pre-SL1660. If
4742 * not, take advantage of the UnderWait feature of more
4743 * modern chips. If an underrun occurs and this bit is set,
4744 * the transmitter will idle the programmed idle pattern
4745 * until the driver has time to service the underrun. Otherwise,
4746 * the dma controller may get the cycles previously requested
4747 * and begin transmitting queued tx data.
4749 usc_OutReg(info
,TMCR
,0x1f);
4750 RegValue
=usc_InReg(info
,TMDR
);
4751 if ( RegValue
== IUSC_PRE_SL1660
)
4757 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
4760 ** Channel Mode Register (CMR)
4762 ** <15..14> 10 Tx Sub Modes, Send Flag on Underrun
4763 ** <13> 0 0 = Transmit Disabled (initially)
4764 ** <12> 0 1 = Consecutive Idles share common 0
4765 ** <11..8> 1110 Transmitter Mode = HDLC/SDLC Loop
4766 ** <7..4> 0000 Rx Sub Modes, addr/ctrl field handling
4767 ** <3..0> 0110 Receiver Mode = HDLC/SDLC
4769 ** 1000 1110 0000 0110 = 0x8e06
4773 /*--------------------------------------------------
4774 * ignore user options for UnderRun Actions and
4776 *--------------------------------------------------*/
4780 /* Channel mode Register (CMR)
4782 * <15..14> 00 Tx Sub modes, Underrun Action
4783 * <13> 0 1 = Send Preamble before opening flag
4784 * <12> 0 1 = Consecutive Idles share common 0
4785 * <11..8> 0110 Transmitter mode = HDLC/SDLC
4786 * <7..4> 0000 Rx Sub modes, addr/ctrl field handling
4787 * <3..0> 0110 Receiver mode = HDLC/SDLC
4789 * 0000 0110 0000 0110 = 0x0606
4791 if (info
->params
.mode
== MGSL_MODE_RAW
) {
4792 RegValue
= 0x0001; /* Set Receive mode = external sync */
4794 usc_OutReg( info
, IOCR
, /* Set IOCR DCD is RxSync Detect Input */
4795 (unsigned short)((usc_InReg(info
, IOCR
) & ~(BIT13
|BIT12
)) | BIT12
));
4799 * CMR <15> 0 Don't send CRC on Tx Underrun
4800 * CMR <14> x undefined
4801 * CMR <13> 0 Send preamble before openning sync
4802 * CMR <12> 0 Send 8-bit syncs, 1=send Syncs per TxLength
4805 * CMR <11-8) 0100 MonoSync
4807 * 0x00 0100 xxxx xxxx 04xx
4815 if ( info
->params
.flags
& HDLC_FLAG_UNDERRUN_ABORT15
)
4817 else if ( info
->params
.flags
& HDLC_FLAG_UNDERRUN_FLAG
)
4819 else if ( info
->params
.flags
& HDLC_FLAG_UNDERRUN_CRC
)
4820 RegValue
|= BIT15
+ BIT14
;
4823 if ( info
->params
.preamble
!= HDLC_PREAMBLE_PATTERN_NONE
)
4827 if ( info
->params
.mode
== MGSL_MODE_HDLC
&&
4828 (info
->params
.flags
& HDLC_FLAG_SHARE_ZERO
) )
4831 if ( info
->params
.addr_filter
!= 0xff )
4833 /* set up receive address filtering */
4834 usc_OutReg( info
, RSR
, info
->params
.addr_filter
);
4838 usc_OutReg( info
, CMR
, RegValue
);
4839 info
->cmr_value
= RegValue
;
4841 /* Receiver mode Register (RMR)
4843 * <15..13> 000 encoding
4844 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4845 * <10> 1 1 = Set CRC to all 1s (use for SDLC/HDLC)
4846 * <9> 0 1 = Include Receive chars in CRC
4847 * <8> 1 1 = Use Abort/PE bit as abort indicator
4848 * <7..6> 00 Even parity
4849 * <5> 0 parity disabled
4850 * <4..2> 000 Receive Char Length = 8 bits
4851 * <1..0> 00 Disable Receiver
4853 * 0000 0101 0000 0000 = 0x0500
4858 switch ( info
->params
.encoding
) {
4859 case HDLC_ENCODING_NRZB
: RegValue
|= BIT13
; break;
4860 case HDLC_ENCODING_NRZI_MARK
: RegValue
|= BIT14
; break;
4861 case HDLC_ENCODING_NRZI_SPACE
: RegValue
|= BIT14
+ BIT13
; break;
4862 case HDLC_ENCODING_BIPHASE_MARK
: RegValue
|= BIT15
; break;
4863 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT15
+ BIT13
; break;
4864 case HDLC_ENCODING_BIPHASE_LEVEL
: RegValue
|= BIT15
+ BIT14
; break;
4865 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: RegValue
|= BIT15
+ BIT14
+ BIT13
; break;
4868 if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_16_CCITT
)
4870 else if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_32_CCITT
)
4871 RegValue
|= ( BIT12
| BIT10
| BIT9
);
4873 usc_OutReg( info
, RMR
, RegValue
);
4875 /* Set the Receive count Limit Register (RCLR) to 0xffff. */
4876 /* When an opening flag of an SDLC frame is recognized the */
4877 /* Receive Character count (RCC) is loaded with the value in */
4878 /* RCLR. The RCC is decremented for each received byte. The */
4879 /* value of RCC is stored after the closing flag of the frame */
4880 /* allowing the frame size to be computed. */
4882 usc_OutReg( info
, RCLR
, RCLRVALUE
);
4884 usc_RCmd( info
, RCmd_SelectRicrdma_level
);
4886 /* Receive Interrupt Control Register (RICR)
4888 * <15..8> ? RxFIFO DMA Request Level
4889 * <7> 0 Exited Hunt IA (Interrupt Arm)
4890 * <6> 0 Idle Received IA
4891 * <5> 0 Break/Abort IA
4893 * <3> 1 Queued status reflects oldest 2 bytes in FIFO
4895 * <1> 1 Rx Overrun IA
4896 * <0> 0 Select TC0 value for readback
4898 * 0000 0000 0000 1000 = 0x000a
4901 /* Carry over the Exit Hunt and Idle Received bits */
4902 /* in case they have been armed by usc_ArmEvents. */
4904 RegValue
= usc_InReg( info
, RICR
) & 0xc0;
4906 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4907 usc_OutReg( info
, RICR
, (u16
)(0x030a | RegValue
) );
4909 usc_OutReg( info
, RICR
, (u16
)(0x140a | RegValue
) );
4911 /* Unlatch all Rx status bits and clear Rx status IRQ Pending */
4913 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
4914 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
);
4916 /* Transmit mode Register (TMR)
4918 * <15..13> 000 encoding
4919 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4920 * <10> 1 1 = Start CRC as all 1s (use for SDLC/HDLC)
4921 * <9> 0 1 = Tx CRC Enabled
4922 * <8> 0 1 = Append CRC to end of transmit frame
4923 * <7..6> 00 Transmit parity Even
4924 * <5> 0 Transmit parity Disabled
4925 * <4..2> 000 Tx Char Length = 8 bits
4926 * <1..0> 00 Disable Transmitter
4928 * 0000 0100 0000 0000 = 0x0400
4933 switch ( info
->params
.encoding
) {
4934 case HDLC_ENCODING_NRZB
: RegValue
|= BIT13
; break;
4935 case HDLC_ENCODING_NRZI_MARK
: RegValue
|= BIT14
; break;
4936 case HDLC_ENCODING_NRZI_SPACE
: RegValue
|= BIT14
+ BIT13
; break;
4937 case HDLC_ENCODING_BIPHASE_MARK
: RegValue
|= BIT15
; break;
4938 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT15
+ BIT13
; break;
4939 case HDLC_ENCODING_BIPHASE_LEVEL
: RegValue
|= BIT15
+ BIT14
; break;
4940 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: RegValue
|= BIT15
+ BIT14
+ BIT13
; break;
4943 if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_16_CCITT
)
4944 RegValue
|= BIT9
+ BIT8
;
4945 else if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_32_CCITT
)
4946 RegValue
|= ( BIT12
| BIT10
| BIT9
| BIT8
);
4948 usc_OutReg( info
, TMR
, RegValue
);
4950 usc_set_txidle( info
);
4953 usc_TCmd( info
, TCmd_SelectTicrdma_level
);
4955 /* Transmit Interrupt Control Register (TICR)
4957 * <15..8> ? Transmit FIFO DMA Level
4958 * <7> 0 Present IA (Interrupt Arm)
4959 * <6> 0 Idle Sent IA
4960 * <5> 1 Abort Sent IA
4961 * <4> 1 EOF/EOM Sent IA
4963 * <2> 1 1 = Wait for SW Trigger to Start Frame
4964 * <1> 1 Tx Underrun IA
4965 * <0> 0 TC0 constant on read back
4967 * 0000 0000 0011 0110 = 0x0036
4970 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4971 usc_OutReg( info
, TICR
, 0x0736 );
4973 usc_OutReg( info
, TICR
, 0x1436 );
4975 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
4976 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
4979 ** Transmit Command/Status Register (TCSR)
4981 ** <15..12> 0000 TCmd
4982 ** <11> 0/1 UnderWait
4983 ** <10..08> 000 TxIdle
4987 ** <4> x EOF/EOM Sent
4993 ** 0000 0000 0000 0000 = 0x0000
4995 info
->tcsr_value
= 0;
4998 info
->tcsr_value
|= TCSR_UNDERWAIT
;
5000 usc_OutReg( info
, TCSR
, info
->tcsr_value
);
5002 /* Clock mode Control Register (CMCR)
5004 * <15..14> 00 counter 1 Source = Disabled
5005 * <13..12> 00 counter 0 Source = Disabled
5006 * <11..10> 11 BRG1 Input is TxC Pin
5007 * <9..8> 11 BRG0 Input is TxC Pin
5008 * <7..6> 01 DPLL Input is BRG1 Output
5009 * <5..3> XXX TxCLK comes from Port 0
5010 * <2..0> XXX RxCLK comes from Port 1
5012 * 0000 1111 0111 0111 = 0x0f77
5017 if ( info
->params
.flags
& HDLC_FLAG_RXC_DPLL
)
5018 RegValue
|= 0x0003; /* RxCLK from DPLL */
5019 else if ( info
->params
.flags
& HDLC_FLAG_RXC_BRG
)
5020 RegValue
|= 0x0004; /* RxCLK from BRG0 */
5021 else if ( info
->params
.flags
& HDLC_FLAG_RXC_TXCPIN
)
5022 RegValue
|= 0x0006; /* RxCLK from TXC Input */
5024 RegValue
|= 0x0007; /* RxCLK from Port1 */
5026 if ( info
->params
.flags
& HDLC_FLAG_TXC_DPLL
)
5027 RegValue
|= 0x0018; /* TxCLK from DPLL */
5028 else if ( info
->params
.flags
& HDLC_FLAG_TXC_BRG
)
5029 RegValue
|= 0x0020; /* TxCLK from BRG0 */
5030 else if ( info
->params
.flags
& HDLC_FLAG_TXC_RXCPIN
)
5031 RegValue
|= 0x0038; /* RxCLK from TXC Input */
5033 RegValue
|= 0x0030; /* TxCLK from Port0 */
5035 usc_OutReg( info
, CMCR
, RegValue
);
5038 /* Hardware Configuration Register (HCR)
5040 * <15..14> 00 CTR0 Divisor:00=32,01=16,10=8,11=4
5041 * <13> 0 CTR1DSel:0=CTR0Div determines CTR0Div
5042 * <12> 0 CVOK:0=report code violation in biphase
5043 * <11..10> 00 DPLL Divisor:00=32,01=16,10=8,11=4
5044 * <9..8> XX DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level
5045 * <7..6> 00 reserved
5046 * <5> 0 BRG1 mode:0=continuous,1=single cycle
5048 * <3..2> 00 reserved
5049 * <1> 0 BRG0 mode:0=continuous,1=single cycle
5055 if ( info
->params
.flags
& (HDLC_FLAG_RXC_DPLL
+ HDLC_FLAG_TXC_DPLL
) ) {
5060 /* DPLL is enabled. Use BRG1 to provide continuous reference clock */
5061 /* for DPLL. DPLL mode in HCR is dependent on the encoding used. */
5063 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
5064 XtalSpeed
= 11059200;
5066 XtalSpeed
= 14745600;
5068 if ( info
->params
.flags
& HDLC_FLAG_DPLL_DIV16
) {
5072 else if ( info
->params
.flags
& HDLC_FLAG_DPLL_DIV8
) {
5079 /* Tc = (Xtal/Speed) - 1 */
5080 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5081 /* then rounding up gives a more precise time constant. Instead */
5082 /* of rounding up and then subtracting 1 we just don't subtract */
5083 /* the one in this case. */
5085 /*--------------------------------------------------
5086 * ejz: for DPLL mode, application should use the
5087 * same clock speed as the partner system, even
5088 * though clocking is derived from the input RxData.
5089 * In case the user uses a 0 for the clock speed,
5090 * default to 0xffffffff and don't try to divide by
5092 *--------------------------------------------------*/
5093 if ( info
->params
.clock_speed
)
5095 Tc
= (u16
)((XtalSpeed
/DpllDivisor
)/info
->params
.clock_speed
);
5096 if ( !((((XtalSpeed
/DpllDivisor
) % info
->params
.clock_speed
) * 2)
5097 / info
->params
.clock_speed
) )
5104 /* Write 16-bit Time Constant for BRG1 */
5105 usc_OutReg( info
, TC1R
, Tc
);
5107 RegValue
|= BIT4
; /* enable BRG1 */
5109 switch ( info
->params
.encoding
) {
5110 case HDLC_ENCODING_NRZ
:
5111 case HDLC_ENCODING_NRZB
:
5112 case HDLC_ENCODING_NRZI_MARK
:
5113 case HDLC_ENCODING_NRZI_SPACE
: RegValue
|= BIT8
; break;
5114 case HDLC_ENCODING_BIPHASE_MARK
:
5115 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT9
; break;
5116 case HDLC_ENCODING_BIPHASE_LEVEL
:
5117 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: RegValue
|= BIT9
+ BIT8
; break;
5121 usc_OutReg( info
, HCR
, RegValue
);
5124 /* Channel Control/status Register (CCSR)
5126 * <15> X RCC FIFO Overflow status (RO)
5127 * <14> X RCC FIFO Not Empty status (RO)
5128 * <13> 0 1 = Clear RCC FIFO (WO)
5129 * <12> X DPLL Sync (RW)
5130 * <11> X DPLL 2 Missed Clocks status (RO)
5131 * <10> X DPLL 1 Missed Clock status (RO)
5132 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
5133 * <7> X SDLC Loop On status (RO)
5134 * <6> X SDLC Loop Send status (RO)
5135 * <5> 1 Bypass counters for TxClk and RxClk (RW)
5136 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
5137 * <1..0> 00 reserved
5139 * 0000 0000 0010 0000 = 0x0020
5142 usc_OutReg( info
, CCSR
, 0x1020 );
5145 if ( info
->params
.flags
& HDLC_FLAG_AUTO_CTS
) {
5146 usc_OutReg( info
, SICR
,
5147 (u16
)(usc_InReg(info
,SICR
) | SICR_CTS_INACTIVE
) );
5151 /* enable Master Interrupt Enable bit (MIE) */
5152 usc_EnableMasterIrqBit( info
);
5154 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
+ RECEIVE_DATA
+
5155 TRANSMIT_STATUS
+ TRANSMIT_DATA
+ MISC
);
5157 /* arm RCC underflow interrupt */
5158 usc_OutReg(info
, SICR
, (u16
)(usc_InReg(info
,SICR
) | BIT3
));
5159 usc_EnableInterrupts(info
, MISC
);
5162 outw( 0, info
->io_base
); /* clear Master Bus Enable (DCAR) */
5163 usc_DmaCmd( info
, DmaCmd_ResetAllChannels
); /* disable both DMA channels */
5164 info
->mbre_bit
= BIT8
;
5165 outw( BIT8
, info
->io_base
); /* set Master Bus Enable (DCAR) */
5167 if (info
->bus_type
== MGSL_BUS_TYPE_ISA
) {
5168 /* Enable DMAEN (Port 7, Bit 14) */
5169 /* This connects the DMA request signal to the ISA bus */
5170 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT15
) & ~BIT14
));
5173 /* DMA Control Register (DCR)
5175 * <15..14> 10 Priority mode = Alternating Tx/Rx
5176 * 01 Rx has priority
5177 * 00 Tx has priority
5179 * <13> 1 Enable Priority Preempt per DCR<15..14>
5180 * (WARNING DCR<11..10> must be 00 when this is 1)
5181 * 0 Choose activate channel per DCR<11..10>
5183 * <12> 0 Little Endian for Array/List
5184 * <11..10> 00 Both Channels can use each bus grant
5185 * <9..6> 0000 reserved
5186 * <5> 0 7 CLK - Minimum Bus Re-request Interval
5187 * <4> 0 1 = drive D/C and S/D pins
5188 * <3> 1 1 = Add one wait state to all DMA cycles.
5189 * <2> 0 1 = Strobe /UAS on every transfer.
5190 * <1..0> 11 Addr incrementing only affects LS24 bits
5192 * 0110 0000 0000 1011 = 0x600b
5195 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
5196 /* PCI adapter does not need DMA wait state */
5197 usc_OutDmaReg( info
, DCR
, 0xa00b );
5200 usc_OutDmaReg( info
, DCR
, 0x800b );
5203 /* Receive DMA mode Register (RDMR)
5205 * <15..14> 11 DMA mode = Linked List Buffer mode
5206 * <13> 1 RSBinA/L = store Rx status Block in Arrary/List entry
5207 * <12> 1 Clear count of List Entry after fetching
5208 * <11..10> 00 Address mode = Increment
5209 * <9> 1 Terminate Buffer on RxBound
5210 * <8> 0 Bus Width = 16bits
5211 * <7..0> ? status Bits (write as 0s)
5213 * 1111 0010 0000 0000 = 0xf200
5216 usc_OutDmaReg( info
, RDMR
, 0xf200 );
5219 /* Transmit DMA mode Register (TDMR)
5221 * <15..14> 11 DMA mode = Linked List Buffer mode
5222 * <13> 1 TCBinA/L = fetch Tx Control Block from List entry
5223 * <12> 1 Clear count of List Entry after fetching
5224 * <11..10> 00 Address mode = Increment
5225 * <9> 1 Terminate Buffer on end of frame
5226 * <8> 0 Bus Width = 16bits
5227 * <7..0> ? status Bits (Read Only so write as 0)
5229 * 1111 0010 0000 0000 = 0xf200
5232 usc_OutDmaReg( info
, TDMR
, 0xf200 );
5235 /* DMA Interrupt Control Register (DICR)
5237 * <15> 1 DMA Interrupt Enable
5238 * <14> 0 1 = Disable IEO from USC
5239 * <13> 0 1 = Don't provide vector during IntAck
5240 * <12> 1 1 = Include status in Vector
5241 * <10..2> 0 reserved, Must be 0s
5242 * <1> 0 1 = Rx DMA Interrupt Enabled
5243 * <0> 0 1 = Tx DMA Interrupt Enabled
5245 * 1001 0000 0000 0000 = 0x9000
5248 usc_OutDmaReg( info
, DICR
, 0x9000 );
5250 usc_InDmaReg( info
, RDMR
); /* clear pending receive DMA IRQ bits */
5251 usc_InDmaReg( info
, TDMR
); /* clear pending transmit DMA IRQ bits */
5252 usc_OutDmaReg( info
, CDIR
, 0x0303 ); /* clear IUS and Pending for Tx and Rx */
5254 /* Channel Control Register (CCR)
5256 * <15..14> 10 Use 32-bit Tx Control Blocks (TCBs)
5257 * <13> 0 Trigger Tx on SW Command Disabled
5258 * <12> 0 Flag Preamble Disabled
5259 * <11..10> 00 Preamble Length
5260 * <9..8> 00 Preamble Pattern
5261 * <7..6> 10 Use 32-bit Rx status Blocks (RSBs)
5262 * <5> 0 Trigger Rx on SW Command Disabled
5265 * 1000 0000 1000 0000 = 0x8080
5270 switch ( info
->params
.preamble_length
) {
5271 case HDLC_PREAMBLE_LENGTH_16BITS
: RegValue
|= BIT10
; break;
5272 case HDLC_PREAMBLE_LENGTH_32BITS
: RegValue
|= BIT11
; break;
5273 case HDLC_PREAMBLE_LENGTH_64BITS
: RegValue
|= BIT11
+ BIT10
; break;
5276 switch ( info
->params
.preamble
) {
5277 case HDLC_PREAMBLE_PATTERN_FLAGS
: RegValue
|= BIT8
+ BIT12
; break;
5278 case HDLC_PREAMBLE_PATTERN_ONES
: RegValue
|= BIT8
; break;
5279 case HDLC_PREAMBLE_PATTERN_10
: RegValue
|= BIT9
; break;
5280 case HDLC_PREAMBLE_PATTERN_01
: RegValue
|= BIT9
+ BIT8
; break;
5283 usc_OutReg( info
, CCR
, RegValue
);
5287 * Burst/Dwell Control Register
5289 * <15..8> 0x20 Maximum number of transfers per bus grant
5290 * <7..0> 0x00 Maximum number of clock cycles per bus grant
5293 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
5294 /* don't limit bus occupancy on PCI adapter */
5295 usc_OutDmaReg( info
, BDCR
, 0x0000 );
5298 usc_OutDmaReg( info
, BDCR
, 0x2000 );
5300 usc_stop_transmitter(info
);
5301 usc_stop_receiver(info
);
5303 } /* end of usc_set_sdlc_mode() */
5305 /* usc_enable_loopback()
5307 * Set the 16C32 for internal loopback mode.
5308 * The TxCLK and RxCLK signals are generated from the BRG0 and
5309 * the TxD is looped back to the RxD internally.
5311 * Arguments: info pointer to device instance data
5312 * enable 1 = enable loopback, 0 = disable
5313 * Return Value: None
5315 static void usc_enable_loopback(struct mgsl_struct
*info
, int enable
)
5318 /* blank external TXD output */
5319 usc_OutReg(info
,IOCR
,usc_InReg(info
,IOCR
) | (BIT7
+BIT6
));
5321 /* Clock mode Control Register (CMCR)
5323 * <15..14> 00 counter 1 Disabled
5324 * <13..12> 00 counter 0 Disabled
5325 * <11..10> 11 BRG1 Input is TxC Pin
5326 * <9..8> 11 BRG0 Input is TxC Pin
5327 * <7..6> 01 DPLL Input is BRG1 Output
5328 * <5..3> 100 TxCLK comes from BRG0
5329 * <2..0> 100 RxCLK comes from BRG0
5331 * 0000 1111 0110 0100 = 0x0f64
5334 usc_OutReg( info
, CMCR
, 0x0f64 );
5336 /* Write 16-bit Time Constant for BRG0 */
5337 /* use clock speed if available, otherwise use 8 for diagnostics */
5338 if (info
->params
.clock_speed
) {
5339 if (info
->bus_type
== MGSL_BUS_TYPE_PCI
)
5340 usc_OutReg(info
, TC0R
, (u16
)((11059200/info
->params
.clock_speed
)-1));
5342 usc_OutReg(info
, TC0R
, (u16
)((14745600/info
->params
.clock_speed
)-1));
5344 usc_OutReg(info
, TC0R
, (u16
)8);
5346 /* Hardware Configuration Register (HCR) Clear Bit 1, BRG0
5347 mode = Continuous Set Bit 0 to enable BRG0. */
5348 usc_OutReg( info
, HCR
, (u16
)((usc_InReg( info
, HCR
) & ~BIT1
) | BIT0
) );
5350 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5351 usc_OutReg(info
, IOCR
, (u16
)((usc_InReg(info
, IOCR
) & 0xfff8) | 0x0004));
5353 /* set Internal Data loopback mode */
5354 info
->loopback_bits
= 0x300;
5355 outw( 0x0300, info
->io_base
+ CCAR
);
5357 /* enable external TXD output */
5358 usc_OutReg(info
,IOCR
,usc_InReg(info
,IOCR
) & ~(BIT7
+BIT6
));
5360 /* clear Internal Data loopback mode */
5361 info
->loopback_bits
= 0;
5362 outw( 0,info
->io_base
+ CCAR
);
5365 } /* end of usc_enable_loopback() */
5367 /* usc_enable_aux_clock()
5369 * Enabled the AUX clock output at the specified frequency.
5373 * info pointer to device extension
5374 * data_rate data rate of clock in bits per second
5375 * A data rate of 0 disables the AUX clock.
5377 * Return Value: None
5379 static void usc_enable_aux_clock( struct mgsl_struct
*info
, u32 data_rate
)
5385 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
5386 XtalSpeed
= 11059200;
5388 XtalSpeed
= 14745600;
5391 /* Tc = (Xtal/Speed) - 1 */
5392 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5393 /* then rounding up gives a more precise time constant. Instead */
5394 /* of rounding up and then subtracting 1 we just don't subtract */
5395 /* the one in this case. */
5398 Tc
= (u16
)(XtalSpeed
/data_rate
);
5399 if ( !(((XtalSpeed
% data_rate
) * 2) / data_rate
) )
5402 /* Write 16-bit Time Constant for BRG0 */
5403 usc_OutReg( info
, TC0R
, Tc
);
5406 * Hardware Configuration Register (HCR)
5407 * Clear Bit 1, BRG0 mode = Continuous
5408 * Set Bit 0 to enable BRG0.
5411 usc_OutReg( info
, HCR
, (u16
)((usc_InReg( info
, HCR
) & ~BIT1
) | BIT0
) );
5413 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5414 usc_OutReg( info
, IOCR
, (u16
)((usc_InReg(info
, IOCR
) & 0xfff8) | 0x0004) );
5416 /* data rate == 0 so turn off BRG0 */
5417 usc_OutReg( info
, HCR
, (u16
)(usc_InReg( info
, HCR
) & ~BIT0
) );
5420 } /* end of usc_enable_aux_clock() */
5424 * usc_process_rxoverrun_sync()
5426 * This function processes a receive overrun by resetting the
5427 * receive DMA buffers and issuing a Purge Rx FIFO command
5428 * to allow the receiver to continue receiving.
5432 * info pointer to device extension
5434 * Return Value: None
5436 static void usc_process_rxoverrun_sync( struct mgsl_struct
*info
)
5440 int frame_start_index
;
5441 int start_of_frame_found
= FALSE
;
5442 int end_of_frame_found
= FALSE
;
5443 int reprogram_dma
= FALSE
;
5445 DMABUFFERENTRY
*buffer_list
= info
->rx_buffer_list
;
5448 usc_DmaCmd( info
, DmaCmd_PauseRxChannel
);
5449 usc_RCmd( info
, RCmd_EnterHuntmode
);
5450 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5452 /* CurrentRxBuffer points to the 1st buffer of the next */
5453 /* possibly available receive frame. */
5455 frame_start_index
= start_index
= end_index
= info
->current_rx_buffer
;
5457 /* Search for an unfinished string of buffers. This means */
5458 /* that a receive frame started (at least one buffer with */
5459 /* count set to zero) but there is no terminiting buffer */
5460 /* (status set to non-zero). */
5462 while( !buffer_list
[end_index
].count
)
5464 /* Count field has been reset to zero by 16C32. */
5465 /* This buffer is currently in use. */
5467 if ( !start_of_frame_found
)
5469 start_of_frame_found
= TRUE
;
5470 frame_start_index
= end_index
;
5471 end_of_frame_found
= FALSE
;
5474 if ( buffer_list
[end_index
].status
)
5476 /* Status field has been set by 16C32. */
5477 /* This is the last buffer of a received frame. */
5479 /* We want to leave the buffers for this frame intact. */
5480 /* Move on to next possible frame. */
5482 start_of_frame_found
= FALSE
;
5483 end_of_frame_found
= TRUE
;
5486 /* advance to next buffer entry in linked list */
5488 if ( end_index
== info
->rx_buffer_count
)
5491 if ( start_index
== end_index
)
5493 /* The entire list has been searched with all Counts == 0 and */
5494 /* all Status == 0. The receive buffers are */
5495 /* completely screwed, reset all receive buffers! */
5496 mgsl_reset_rx_dma_buffers( info
);
5497 frame_start_index
= 0;
5498 start_of_frame_found
= FALSE
;
5499 reprogram_dma
= TRUE
;
5504 if ( start_of_frame_found
&& !end_of_frame_found
)
5506 /* There is an unfinished string of receive DMA buffers */
5507 /* as a result of the receiver overrun. */
5509 /* Reset the buffers for the unfinished frame */
5510 /* and reprogram the receive DMA controller to start */
5511 /* at the 1st buffer of unfinished frame. */
5513 start_index
= frame_start_index
;
5517 *((unsigned long *)&(info
->rx_buffer_list
[start_index
++].count
)) = DMABUFFERSIZE
;
5519 /* Adjust index for wrap around. */
5520 if ( start_index
== info
->rx_buffer_count
)
5523 } while( start_index
!= end_index
);
5525 reprogram_dma
= TRUE
;
5528 if ( reprogram_dma
)
5530 usc_UnlatchRxstatusBits(info
,RXSTATUS_ALL
);
5531 usc_ClearIrqPendingBits(info
, RECEIVE_DATA
|RECEIVE_STATUS
);
5532 usc_UnlatchRxstatusBits(info
, RECEIVE_DATA
|RECEIVE_STATUS
);
5534 usc_EnableReceiver(info
,DISABLE_UNCONDITIONAL
);
5536 /* This empties the receive FIFO and loads the RCC with RCLR */
5537 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5539 /* program 16C32 with physical address of 1st DMA buffer entry */
5540 phys_addr
= info
->rx_buffer_list
[frame_start_index
].phys_entry
;
5541 usc_OutDmaReg( info
, NRARL
, (u16
)phys_addr
);
5542 usc_OutDmaReg( info
, NRARU
, (u16
)(phys_addr
>> 16) );
5544 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5545 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5546 usc_EnableInterrupts( info
, RECEIVE_STATUS
);
5548 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5549 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5551 usc_OutDmaReg( info
, RDIAR
, BIT3
+ BIT2
);
5552 usc_OutDmaReg( info
, DICR
, (u16
)(usc_InDmaReg(info
,DICR
) | BIT1
) );
5553 usc_DmaCmd( info
, DmaCmd_InitRxChannel
);
5554 if ( info
->params
.flags
& HDLC_FLAG_AUTO_DCD
)
5555 usc_EnableReceiver(info
,ENABLE_AUTO_DCD
);
5557 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
5561 /* This empties the receive FIFO and loads the RCC with RCLR */
5562 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5563 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5566 } /* end of usc_process_rxoverrun_sync() */
5568 /* usc_stop_receiver()
5570 * Disable USC receiver
5572 * Arguments: info pointer to device instance data
5573 * Return Value: None
5575 static void usc_stop_receiver( struct mgsl_struct
*info
)
5577 if (debug_level
>= DEBUG_LEVEL_ISR
)
5578 printk("%s(%d):usc_stop_receiver(%s)\n",
5579 __FILE__
,__LINE__
, info
->device_name
);
5581 /* Disable receive DMA channel. */
5582 /* This also disables receive DMA channel interrupts */
5583 usc_DmaCmd( info
, DmaCmd_ResetRxChannel
);
5585 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5586 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5587 usc_DisableInterrupts( info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5589 usc_EnableReceiver(info
,DISABLE_UNCONDITIONAL
);
5591 /* This empties the receive FIFO and loads the RCC with RCLR */
5592 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5593 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5595 info
->rx_enabled
= 0;
5596 info
->rx_overflow
= 0;
5597 info
->rx_rcc_underrun
= 0;
5599 } /* end of stop_receiver() */
5601 /* usc_start_receiver()
5603 * Enable the USC receiver
5605 * Arguments: info pointer to device instance data
5606 * Return Value: None
5608 static void usc_start_receiver( struct mgsl_struct
*info
)
5612 if (debug_level
>= DEBUG_LEVEL_ISR
)
5613 printk("%s(%d):usc_start_receiver(%s)\n",
5614 __FILE__
,__LINE__
, info
->device_name
);
5616 mgsl_reset_rx_dma_buffers( info
);
5617 usc_stop_receiver( info
);
5619 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5620 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5622 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
5623 info
->params
.mode
== MGSL_MODE_RAW
) {
5624 /* DMA mode Transfers */
5625 /* Program the DMA controller. */
5626 /* Enable the DMA controller end of buffer interrupt. */
5628 /* program 16C32 with physical address of 1st DMA buffer entry */
5629 phys_addr
= info
->rx_buffer_list
[0].phys_entry
;
5630 usc_OutDmaReg( info
, NRARL
, (u16
)phys_addr
);
5631 usc_OutDmaReg( info
, NRARU
, (u16
)(phys_addr
>> 16) );
5633 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5634 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5635 usc_EnableInterrupts( info
, RECEIVE_STATUS
);
5637 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5638 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5640 usc_OutDmaReg( info
, RDIAR
, BIT3
+ BIT2
);
5641 usc_OutDmaReg( info
, DICR
, (u16
)(usc_InDmaReg(info
,DICR
) | BIT1
) );
5642 usc_DmaCmd( info
, DmaCmd_InitRxChannel
);
5643 if ( info
->params
.flags
& HDLC_FLAG_AUTO_DCD
)
5644 usc_EnableReceiver(info
,ENABLE_AUTO_DCD
);
5646 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
5648 usc_UnlatchRxstatusBits(info
, RXSTATUS_ALL
);
5649 usc_ClearIrqPendingBits(info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5650 usc_EnableInterrupts(info
, RECEIVE_DATA
);
5652 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5653 usc_RCmd( info
, RCmd_EnterHuntmode
);
5655 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
5658 usc_OutReg( info
, CCSR
, 0x1020 );
5660 info
->rx_enabled
= 1;
5662 } /* end of usc_start_receiver() */
5664 /* usc_start_transmitter()
5666 * Enable the USC transmitter and send a transmit frame if
5667 * one is loaded in the DMA buffers.
5669 * Arguments: info pointer to device instance data
5670 * Return Value: None
5672 static void usc_start_transmitter( struct mgsl_struct
*info
)
5675 unsigned int FrameSize
;
5677 if (debug_level
>= DEBUG_LEVEL_ISR
)
5678 printk("%s(%d):usc_start_transmitter(%s)\n",
5679 __FILE__
,__LINE__
, info
->device_name
);
5681 if ( info
->xmit_cnt
) {
5683 /* If auto RTS enabled and RTS is inactive, then assert */
5684 /* RTS and set a flag indicating that the driver should */
5685 /* negate RTS when the transmission completes. */
5687 info
->drop_rts_on_tx_done
= 0;
5689 if ( info
->params
.flags
& HDLC_FLAG_AUTO_RTS
) {
5690 usc_get_serial_signals( info
);
5691 if ( !(info
->serial_signals
& SerialSignal_RTS
) ) {
5692 info
->serial_signals
|= SerialSignal_RTS
;
5693 usc_set_serial_signals( info
);
5694 info
->drop_rts_on_tx_done
= 1;
5699 if ( info
->params
.mode
== MGSL_MODE_ASYNC
) {
5700 if ( !info
->tx_active
) {
5701 usc_UnlatchTxstatusBits(info
, TXSTATUS_ALL
);
5702 usc_ClearIrqPendingBits(info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
);
5703 usc_EnableInterrupts(info
, TRANSMIT_DATA
);
5704 usc_load_txfifo(info
);
5707 /* Disable transmit DMA controller while programming. */
5708 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
5710 /* Transmit DMA buffer is loaded, so program USC */
5711 /* to send the frame contained in the buffers. */
5713 FrameSize
= info
->tx_buffer_list
[info
->start_tx_dma_buffer
].rcc
;
5715 /* if operating in Raw sync mode, reset the rcc component
5716 * of the tx dma buffer entry, otherwise, the serial controller
5717 * will send a closing sync char after this count.
5719 if ( info
->params
.mode
== MGSL_MODE_RAW
)
5720 info
->tx_buffer_list
[info
->start_tx_dma_buffer
].rcc
= 0;
5722 /* Program the Transmit Character Length Register (TCLR) */
5723 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
5724 usc_OutReg( info
, TCLR
, (u16
)FrameSize
);
5726 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
5728 /* Program the address of the 1st DMA Buffer Entry in linked list */
5729 phys_addr
= info
->tx_buffer_list
[info
->start_tx_dma_buffer
].phys_entry
;
5730 usc_OutDmaReg( info
, NTARL
, (u16
)phys_addr
);
5731 usc_OutDmaReg( info
, NTARU
, (u16
)(phys_addr
>> 16) );
5733 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
5734 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
5735 usc_EnableInterrupts( info
, TRANSMIT_STATUS
);
5737 if ( info
->params
.mode
== MGSL_MODE_RAW
&&
5738 info
->num_tx_dma_buffers
> 1 ) {
5739 /* When running external sync mode, attempt to 'stream' transmit */
5740 /* by filling tx dma buffers as they become available. To do this */
5741 /* we need to enable Tx DMA EOB Status interrupts : */
5743 /* 1. Arm End of Buffer (EOB) Transmit DMA Interrupt (BIT2 of TDIAR) */
5744 /* 2. Enable Transmit DMA Interrupts (BIT0 of DICR) */
5746 usc_OutDmaReg( info
, TDIAR
, BIT2
|BIT3
);
5747 usc_OutDmaReg( info
, DICR
, (u16
)(usc_InDmaReg(info
,DICR
) | BIT0
) );
5750 /* Initialize Transmit DMA Channel */
5751 usc_DmaCmd( info
, DmaCmd_InitTxChannel
);
5753 usc_TCmd( info
, TCmd_SendFrame
);
5755 info
->tx_timer
.expires
= jiffies
+ msecs_to_jiffies(5000);
5756 add_timer(&info
->tx_timer
);
5758 info
->tx_active
= 1;
5761 if ( !info
->tx_enabled
) {
5762 info
->tx_enabled
= 1;
5763 if ( info
->params
.flags
& HDLC_FLAG_AUTO_CTS
)
5764 usc_EnableTransmitter(info
,ENABLE_AUTO_CTS
);
5766 usc_EnableTransmitter(info
,ENABLE_UNCONDITIONAL
);
5769 } /* end of usc_start_transmitter() */
5771 /* usc_stop_transmitter()
5773 * Stops the transmitter and DMA
5775 * Arguments: info pointer to device isntance data
5776 * Return Value: None
5778 static void usc_stop_transmitter( struct mgsl_struct
*info
)
5780 if (debug_level
>= DEBUG_LEVEL_ISR
)
5781 printk("%s(%d):usc_stop_transmitter(%s)\n",
5782 __FILE__
,__LINE__
, info
->device_name
);
5784 del_timer(&info
->tx_timer
);
5786 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
5787 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
);
5788 usc_DisableInterrupts( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
);
5790 usc_EnableTransmitter(info
,DISABLE_UNCONDITIONAL
);
5791 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
5792 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
5794 info
->tx_enabled
= 0;
5795 info
->tx_active
= 0;
5797 } /* end of usc_stop_transmitter() */
5799 /* usc_load_txfifo()
5801 * Fill the transmit FIFO until the FIFO is full or
5802 * there is no more data to load.
5804 * Arguments: info pointer to device extension (instance data)
5805 * Return Value: None
5807 static void usc_load_txfifo( struct mgsl_struct
*info
)
5812 if ( !info
->xmit_cnt
&& !info
->x_char
)
5815 /* Select transmit FIFO status readback in TICR */
5816 usc_TCmd( info
, TCmd_SelectTicrTxFifostatus
);
5818 /* load the Transmit FIFO until FIFOs full or all data sent */
5820 while( (Fifocount
= usc_InReg(info
, TICR
) >> 8) && info
->xmit_cnt
) {
5821 /* there is more space in the transmit FIFO and */
5822 /* there is more data in transmit buffer */
5824 if ( (info
->xmit_cnt
> 1) && (Fifocount
> 1) && !info
->x_char
) {
5825 /* write a 16-bit word from transmit buffer to 16C32 */
5827 TwoBytes
[0] = info
->xmit_buf
[info
->xmit_tail
++];
5828 info
->xmit_tail
= info
->xmit_tail
& (SERIAL_XMIT_SIZE
-1);
5829 TwoBytes
[1] = info
->xmit_buf
[info
->xmit_tail
++];
5830 info
->xmit_tail
= info
->xmit_tail
& (SERIAL_XMIT_SIZE
-1);
5832 outw( *((u16
*)TwoBytes
), info
->io_base
+ DATAREG
);
5834 info
->xmit_cnt
-= 2;
5835 info
->icount
.tx
+= 2;
5837 /* only 1 byte left to transmit or 1 FIFO slot left */
5839 outw( (inw( info
->io_base
+ CCAR
) & 0x0780) | (TDR
+LSBONLY
),
5840 info
->io_base
+ CCAR
);
5843 /* transmit pending high priority char */
5844 outw( info
->x_char
,info
->io_base
+ CCAR
);
5847 outw( info
->xmit_buf
[info
->xmit_tail
++],info
->io_base
+ CCAR
);
5848 info
->xmit_tail
= info
->xmit_tail
& (SERIAL_XMIT_SIZE
-1);
5855 } /* end of usc_load_txfifo() */
5859 * Reset the adapter to a known state and prepare it for further use.
5861 * Arguments: info pointer to device instance data
5862 * Return Value: None
5864 static void usc_reset( struct mgsl_struct
*info
)
5866 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
5870 /* Set BIT30 of Misc Control Register */
5871 /* (Local Control Register 0x50) to force reset of USC. */
5873 volatile u32
*MiscCtrl
= (u32
*)(info
->lcr_base
+ 0x50);
5874 u32
*LCR0BRDR
= (u32
*)(info
->lcr_base
+ 0x28);
5876 info
->misc_ctrl_value
|= BIT30
;
5877 *MiscCtrl
= info
->misc_ctrl_value
;
5880 * Force at least 170ns delay before clearing
5881 * reset bit. Each read from LCR takes at least
5882 * 30ns so 10 times for 300ns to be safe.
5885 readval
= *MiscCtrl
;
5887 info
->misc_ctrl_value
&= ~BIT30
;
5888 *MiscCtrl
= info
->misc_ctrl_value
;
5890 *LCR0BRDR
= BUS_DESCRIPTOR(
5891 1, // Write Strobe Hold (0-3)
5892 2, // Write Strobe Delay (0-3)
5893 2, // Read Strobe Delay (0-3)
5894 0, // NWDD (Write data-data) (0-3)
5895 4, // NWAD (Write Addr-data) (0-31)
5896 0, // NXDA (Read/Write Data-Addr) (0-3)
5897 0, // NRDD (Read Data-Data) (0-3)
5898 5 // NRAD (Read Addr-Data) (0-31)
5902 outb( 0,info
->io_base
+ 8 );
5906 info
->loopback_bits
= 0;
5907 info
->usc_idle_mode
= 0;
5910 * Program the Bus Configuration Register (BCR)
5912 * <15> 0 Don't use separate address
5913 * <14..6> 0 reserved
5914 * <5..4> 00 IAckmode = Default, don't care
5915 * <3> 1 Bus Request Totem Pole output
5916 * <2> 1 Use 16 Bit data bus
5917 * <1> 0 IRQ Totem Pole output
5918 * <0> 0 Don't Shift Right Addr
5920 * 0000 0000 0000 1100 = 0x000c
5922 * By writing to io_base + SDPIN the Wait/Ack pin is
5923 * programmed to work as a Wait pin.
5926 outw( 0x000c,info
->io_base
+ SDPIN
);
5929 outw( 0,info
->io_base
);
5930 outw( 0,info
->io_base
+ CCAR
);
5932 /* select little endian byte ordering */
5933 usc_RTCmd( info
, RTCmd_SelectLittleEndian
);
5936 /* Port Control Register (PCR)
5938 * <15..14> 11 Port 7 is Output (~DMAEN, Bit 14 : 0 = Enabled)
5939 * <13..12> 11 Port 6 is Output (~INTEN, Bit 12 : 0 = Enabled)
5940 * <11..10> 00 Port 5 is Input (No Connect, Don't Care)
5941 * <9..8> 00 Port 4 is Input (No Connect, Don't Care)
5942 * <7..6> 11 Port 3 is Output (~RTS, Bit 6 : 0 = Enabled )
5943 * <5..4> 11 Port 2 is Output (~DTR, Bit 4 : 0 = Enabled )
5944 * <3..2> 01 Port 1 is Input (Dedicated RxC)
5945 * <1..0> 01 Port 0 is Input (Dedicated TxC)
5947 * 1111 0000 1111 0101 = 0xf0f5
5950 usc_OutReg( info
, PCR
, 0xf0f5 );
5954 * Input/Output Control Register
5956 * <15..14> 00 CTS is active low input
5957 * <13..12> 00 DCD is active low input
5958 * <11..10> 00 TxREQ pin is input (DSR)
5959 * <9..8> 00 RxREQ pin is input (RI)
5960 * <7..6> 00 TxD is output (Transmit Data)
5961 * <5..3> 000 TxC Pin in Input (14.7456MHz Clock)
5962 * <2..0> 100 RxC is Output (drive with BRG0)
5964 * 0000 0000 0000 0100 = 0x0004
5967 usc_OutReg( info
, IOCR
, 0x0004 );
5969 } /* end of usc_reset() */
5971 /* usc_set_async_mode()
5973 * Program adapter for asynchronous communications.
5975 * Arguments: info pointer to device instance data
5976 * Return Value: None
5978 static void usc_set_async_mode( struct mgsl_struct
*info
)
5982 /* disable interrupts while programming USC */
5983 usc_DisableMasterIrqBit( info
);
5985 outw( 0, info
->io_base
); /* clear Master Bus Enable (DCAR) */
5986 usc_DmaCmd( info
, DmaCmd_ResetAllChannels
); /* disable both DMA channels */
5988 usc_loopback_frame( info
);
5990 /* Channel mode Register (CMR)
5992 * <15..14> 00 Tx Sub modes, 00 = 1 Stop Bit
5993 * <13..12> 00 00 = 16X Clock
5994 * <11..8> 0000 Transmitter mode = Asynchronous
5995 * <7..6> 00 reserved?
5996 * <5..4> 00 Rx Sub modes, 00 = 16X Clock
5997 * <3..0> 0000 Receiver mode = Asynchronous
5999 * 0000 0000 0000 0000 = 0x0
6003 if ( info
->params
.stop_bits
!= 1 )
6005 usc_OutReg( info
, CMR
, RegValue
);
6008 /* Receiver mode Register (RMR)
6010 * <15..13> 000 encoding = None
6011 * <12..08> 00000 reserved (Sync Only)
6012 * <7..6> 00 Even parity
6013 * <5> 0 parity disabled
6014 * <4..2> 000 Receive Char Length = 8 bits
6015 * <1..0> 00 Disable Receiver
6017 * 0000 0000 0000 0000 = 0x0
6022 if ( info
->params
.data_bits
!= 8 )
6023 RegValue
|= BIT4
+BIT3
+BIT2
;
6025 if ( info
->params
.parity
!= ASYNC_PARITY_NONE
) {
6027 if ( info
->params
.parity
!= ASYNC_PARITY_ODD
)
6031 usc_OutReg( info
, RMR
, RegValue
);
6034 /* Set IRQ trigger level */
6036 usc_RCmd( info
, RCmd_SelectRicrIntLevel
);
6039 /* Receive Interrupt Control Register (RICR)
6041 * <15..8> ? RxFIFO IRQ Request Level
6043 * Note: For async mode the receive FIFO level must be set
6044 * to 0 to aviod the situation where the FIFO contains fewer bytes
6045 * than the trigger level and no more data is expected.
6047 * <7> 0 Exited Hunt IA (Interrupt Arm)
6048 * <6> 0 Idle Received IA
6049 * <5> 0 Break/Abort IA
6051 * <3> 0 Queued status reflects oldest byte in FIFO
6053 * <1> 0 Rx Overrun IA
6054 * <0> 0 Select TC0 value for readback
6056 * 0000 0000 0100 0000 = 0x0000 + (FIFOLEVEL in MSB)
6059 usc_OutReg( info
, RICR
, 0x0000 );
6061 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
6062 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
);
6065 /* Transmit mode Register (TMR)
6067 * <15..13> 000 encoding = None
6068 * <12..08> 00000 reserved (Sync Only)
6069 * <7..6> 00 Transmit parity Even
6070 * <5> 0 Transmit parity Disabled
6071 * <4..2> 000 Tx Char Length = 8 bits
6072 * <1..0> 00 Disable Transmitter
6074 * 0000 0000 0000 0000 = 0x0
6079 if ( info
->params
.data_bits
!= 8 )
6080 RegValue
|= BIT4
+BIT3
+BIT2
;
6082 if ( info
->params
.parity
!= ASYNC_PARITY_NONE
) {
6084 if ( info
->params
.parity
!= ASYNC_PARITY_ODD
)
6088 usc_OutReg( info
, TMR
, RegValue
);
6090 usc_set_txidle( info
);
6093 /* Set IRQ trigger level */
6095 usc_TCmd( info
, TCmd_SelectTicrIntLevel
);
6098 /* Transmit Interrupt Control Register (TICR)
6100 * <15..8> ? Transmit FIFO IRQ Level
6101 * <7> 0 Present IA (Interrupt Arm)
6102 * <6> 1 Idle Sent IA
6103 * <5> 0 Abort Sent IA
6104 * <4> 0 EOF/EOM Sent IA
6106 * <2> 0 1 = Wait for SW Trigger to Start Frame
6107 * <1> 0 Tx Underrun IA
6108 * <0> 0 TC0 constant on read back
6110 * 0000 0000 0100 0000 = 0x0040
6113 usc_OutReg( info
, TICR
, 0x1f40 );
6115 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
6116 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
6118 usc_enable_async_clock( info
, info
->params
.data_rate
);
6121 /* Channel Control/status Register (CCSR)
6123 * <15> X RCC FIFO Overflow status (RO)
6124 * <14> X RCC FIFO Not Empty status (RO)
6125 * <13> 0 1 = Clear RCC FIFO (WO)
6126 * <12> X DPLL in Sync status (RO)
6127 * <11> X DPLL 2 Missed Clocks status (RO)
6128 * <10> X DPLL 1 Missed Clock status (RO)
6129 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
6130 * <7> X SDLC Loop On status (RO)
6131 * <6> X SDLC Loop Send status (RO)
6132 * <5> 1 Bypass counters for TxClk and RxClk (RW)
6133 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
6134 * <1..0> 00 reserved
6136 * 0000 0000 0010 0000 = 0x0020
6139 usc_OutReg( info
, CCSR
, 0x0020 );
6141 usc_DisableInterrupts( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
+
6142 RECEIVE_DATA
+ RECEIVE_STATUS
);
6144 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
+
6145 RECEIVE_DATA
+ RECEIVE_STATUS
);
6147 usc_EnableMasterIrqBit( info
);
6149 if (info
->bus_type
== MGSL_BUS_TYPE_ISA
) {
6150 /* Enable INTEN (Port 6, Bit12) */
6151 /* This connects the IRQ request signal to the ISA bus */
6152 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT13
) & ~BIT12
));
6155 if (info
->params
.loopback
) {
6156 info
->loopback_bits
= 0x300;
6157 outw(0x0300, info
->io_base
+ CCAR
);
6160 } /* end of usc_set_async_mode() */
6162 /* usc_loopback_frame()
6164 * Loop back a small (2 byte) dummy SDLC frame.
6165 * Interrupts and DMA are NOT used. The purpose of this is to
6166 * clear any 'stale' status info left over from running in async mode.
6168 * The 16C32 shows the strange behaviour of marking the 1st
6169 * received SDLC frame with a CRC error even when there is no
6170 * CRC error. To get around this a small dummy from of 2 bytes
6171 * is looped back when switching from async to sync mode.
6173 * Arguments: info pointer to device instance data
6174 * Return Value: None
6176 static void usc_loopback_frame( struct mgsl_struct
*info
)
6179 unsigned long oldmode
= info
->params
.mode
;
6181 info
->params
.mode
= MGSL_MODE_HDLC
;
6183 usc_DisableMasterIrqBit( info
);
6185 usc_set_sdlc_mode( info
);
6186 usc_enable_loopback( info
, 1 );
6188 /* Write 16-bit Time Constant for BRG0 */
6189 usc_OutReg( info
, TC0R
, 0 );
6191 /* Channel Control Register (CCR)
6193 * <15..14> 00 Don't use 32-bit Tx Control Blocks (TCBs)
6194 * <13> 0 Trigger Tx on SW Command Disabled
6195 * <12> 0 Flag Preamble Disabled
6196 * <11..10> 00 Preamble Length = 8-Bits
6197 * <9..8> 01 Preamble Pattern = flags
6198 * <7..6> 10 Don't use 32-bit Rx status Blocks (RSBs)
6199 * <5> 0 Trigger Rx on SW Command Disabled
6202 * 0000 0001 0000 0000 = 0x0100
6205 usc_OutReg( info
, CCR
, 0x0100 );
6207 /* SETUP RECEIVER */
6208 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
6209 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
6211 /* SETUP TRANSMITTER */
6212 /* Program the Transmit Character Length Register (TCLR) */
6213 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
6214 usc_OutReg( info
, TCLR
, 2 );
6215 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
6217 /* unlatch Tx status bits, and start transmit channel. */
6218 usc_UnlatchTxstatusBits(info
,TXSTATUS_ALL
);
6219 outw(0,info
->io_base
+ DATAREG
);
6221 /* ENABLE TRANSMITTER */
6222 usc_TCmd( info
, TCmd_SendFrame
);
6223 usc_EnableTransmitter(info
,ENABLE_UNCONDITIONAL
);
6225 /* WAIT FOR RECEIVE COMPLETE */
6226 for (i
=0 ; i
<1000 ; i
++)
6227 if (usc_InReg( info
, RCSR
) & (BIT8
+ BIT4
+ BIT3
+ BIT1
))
6230 /* clear Internal Data loopback mode */
6231 usc_enable_loopback(info
, 0);
6233 usc_EnableMasterIrqBit(info
);
6235 info
->params
.mode
= oldmode
;
6237 } /* end of usc_loopback_frame() */
6239 /* usc_set_sync_mode() Programs the USC for SDLC communications.
6241 * Arguments: info pointer to adapter info structure
6242 * Return Value: None
6244 static void usc_set_sync_mode( struct mgsl_struct
*info
)
6246 usc_loopback_frame( info
);
6247 usc_set_sdlc_mode( info
);
6249 if (info
->bus_type
== MGSL_BUS_TYPE_ISA
) {
6250 /* Enable INTEN (Port 6, Bit12) */
6251 /* This connects the IRQ request signal to the ISA bus */
6252 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT13
) & ~BIT12
));
6255 usc_enable_aux_clock(info
, info
->params
.clock_speed
);
6257 if (info
->params
.loopback
)
6258 usc_enable_loopback(info
,1);
6260 } /* end of mgsl_set_sync_mode() */
6262 /* usc_set_txidle() Set the HDLC idle mode for the transmitter.
6264 * Arguments: info pointer to device instance data
6265 * Return Value: None
6267 static void usc_set_txidle( struct mgsl_struct
*info
)
6269 u16 usc_idle_mode
= IDLEMODE_FLAGS
;
6271 /* Map API idle mode to USC register bits */
6273 switch( info
->idle_mode
){
6274 case HDLC_TXIDLE_FLAGS
: usc_idle_mode
= IDLEMODE_FLAGS
; break;
6275 case HDLC_TXIDLE_ALT_ZEROS_ONES
: usc_idle_mode
= IDLEMODE_ALT_ONE_ZERO
; break;
6276 case HDLC_TXIDLE_ZEROS
: usc_idle_mode
= IDLEMODE_ZERO
; break;
6277 case HDLC_TXIDLE_ONES
: usc_idle_mode
= IDLEMODE_ONE
; break;
6278 case HDLC_TXIDLE_ALT_MARK_SPACE
: usc_idle_mode
= IDLEMODE_ALT_MARK_SPACE
; break;
6279 case HDLC_TXIDLE_SPACE
: usc_idle_mode
= IDLEMODE_SPACE
; break;
6280 case HDLC_TXIDLE_MARK
: usc_idle_mode
= IDLEMODE_MARK
; break;
6283 info
->usc_idle_mode
= usc_idle_mode
;
6284 //usc_OutReg(info, TCSR, usc_idle_mode);
6285 info
->tcsr_value
&= ~IDLEMODE_MASK
; /* clear idle mode bits */
6286 info
->tcsr_value
+= usc_idle_mode
;
6287 usc_OutReg(info
, TCSR
, info
->tcsr_value
);
6290 * if SyncLink WAN adapter is running in external sync mode, the
6291 * transmitter has been set to Monosync in order to try to mimic
6292 * a true raw outbound bit stream. Monosync still sends an open/close
6293 * sync char at the start/end of a frame. Try to match those sync
6294 * patterns to the idle mode set here
6296 if ( info
->params
.mode
== MGSL_MODE_RAW
) {
6297 unsigned char syncpat
= 0;
6298 switch( info
->idle_mode
) {
6299 case HDLC_TXIDLE_FLAGS
:
6302 case HDLC_TXIDLE_ALT_ZEROS_ONES
:
6305 case HDLC_TXIDLE_ZEROS
:
6306 case HDLC_TXIDLE_SPACE
:
6309 case HDLC_TXIDLE_ONES
:
6310 case HDLC_TXIDLE_MARK
:
6313 case HDLC_TXIDLE_ALT_MARK_SPACE
:
6318 usc_SetTransmitSyncChars(info
,syncpat
,syncpat
);
6321 } /* end of usc_set_txidle() */
6323 /* usc_get_serial_signals()
6325 * Query the adapter for the state of the V24 status (input) signals.
6327 * Arguments: info pointer to device instance data
6328 * Return Value: None
6330 static void usc_get_serial_signals( struct mgsl_struct
*info
)
6334 /* clear all serial signals except DTR and RTS */
6335 info
->serial_signals
&= SerialSignal_DTR
+ SerialSignal_RTS
;
6337 /* Read the Misc Interrupt status Register (MISR) to get */
6338 /* the V24 status signals. */
6340 status
= usc_InReg( info
, MISR
);
6342 /* set serial signal bits to reflect MISR */
6344 if ( status
& MISCSTATUS_CTS
)
6345 info
->serial_signals
|= SerialSignal_CTS
;
6347 if ( status
& MISCSTATUS_DCD
)
6348 info
->serial_signals
|= SerialSignal_DCD
;
6350 if ( status
& MISCSTATUS_RI
)
6351 info
->serial_signals
|= SerialSignal_RI
;
6353 if ( status
& MISCSTATUS_DSR
)
6354 info
->serial_signals
|= SerialSignal_DSR
;
6356 } /* end of usc_get_serial_signals() */
6358 /* usc_set_serial_signals()
6360 * Set the state of DTR and RTS based on contents of
6361 * serial_signals member of device extension.
6363 * Arguments: info pointer to device instance data
6364 * Return Value: None
6366 static void usc_set_serial_signals( struct mgsl_struct
*info
)
6369 unsigned char V24Out
= info
->serial_signals
;
6371 /* get the current value of the Port Control Register (PCR) */
6373 Control
= usc_InReg( info
, PCR
);
6375 if ( V24Out
& SerialSignal_RTS
)
6380 if ( V24Out
& SerialSignal_DTR
)
6385 usc_OutReg( info
, PCR
, Control
);
6387 } /* end of usc_set_serial_signals() */
6389 /* usc_enable_async_clock()
6391 * Enable the async clock at the specified frequency.
6393 * Arguments: info pointer to device instance data
6394 * data_rate data rate of clock in bps
6395 * 0 disables the AUX clock.
6396 * Return Value: None
6398 static void usc_enable_async_clock( struct mgsl_struct
*info
, u32 data_rate
)
6402 * Clock mode Control Register (CMCR)
6404 * <15..14> 00 counter 1 Disabled
6405 * <13..12> 00 counter 0 Disabled
6406 * <11..10> 11 BRG1 Input is TxC Pin
6407 * <9..8> 11 BRG0 Input is TxC Pin
6408 * <7..6> 01 DPLL Input is BRG1 Output
6409 * <5..3> 100 TxCLK comes from BRG0
6410 * <2..0> 100 RxCLK comes from BRG0
6412 * 0000 1111 0110 0100 = 0x0f64
6415 usc_OutReg( info
, CMCR
, 0x0f64 );
6419 * Write 16-bit Time Constant for BRG0
6420 * Time Constant = (ClkSpeed / data_rate) - 1
6421 * ClkSpeed = 921600 (ISA), 691200 (PCI)
6424 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
6425 usc_OutReg( info
, TC0R
, (u16
)((691200/data_rate
) - 1) );
6427 usc_OutReg( info
, TC0R
, (u16
)((921600/data_rate
) - 1) );
6431 * Hardware Configuration Register (HCR)
6432 * Clear Bit 1, BRG0 mode = Continuous
6433 * Set Bit 0 to enable BRG0.
6436 usc_OutReg( info
, HCR
,
6437 (u16
)((usc_InReg( info
, HCR
) & ~BIT1
) | BIT0
) );
6440 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
6442 usc_OutReg( info
, IOCR
,
6443 (u16
)((usc_InReg(info
, IOCR
) & 0xfff8) | 0x0004) );
6445 /* data rate == 0 so turn off BRG0 */
6446 usc_OutReg( info
, HCR
, (u16
)(usc_InReg( info
, HCR
) & ~BIT0
) );
6449 } /* end of usc_enable_async_clock() */
6452 * Buffer Structures:
6454 * Normal memory access uses virtual addresses that can make discontiguous
6455 * physical memory pages appear to be contiguous in the virtual address
6456 * space (the processors memory mapping handles the conversions).
6458 * DMA transfers require physically contiguous memory. This is because
6459 * the DMA system controller and DMA bus masters deal with memory using
6460 * only physical addresses.
6462 * This causes a problem under Windows NT when large DMA buffers are
6463 * needed. Fragmentation of the nonpaged pool prevents allocations of
6464 * physically contiguous buffers larger than the PAGE_SIZE.
6466 * However the 16C32 supports Bus Master Scatter/Gather DMA which
6467 * allows DMA transfers to physically discontiguous buffers. Information
6468 * about each data transfer buffer is contained in a memory structure
6469 * called a 'buffer entry'. A list of buffer entries is maintained
6470 * to track and control the use of the data transfer buffers.
6472 * To support this strategy we will allocate sufficient PAGE_SIZE
6473 * contiguous memory buffers to allow for the total required buffer
6476 * The 16C32 accesses the list of buffer entries using Bus Master
6477 * DMA. Control information is read from the buffer entries by the
6478 * 16C32 to control data transfers. status information is written to
6479 * the buffer entries by the 16C32 to indicate the status of completed
6482 * The CPU writes control information to the buffer entries to control
6483 * the 16C32 and reads status information from the buffer entries to
6484 * determine information about received and transmitted frames.
6486 * Because the CPU and 16C32 (adapter) both need simultaneous access
6487 * to the buffer entries, the buffer entry memory is allocated with
6488 * HalAllocateCommonBuffer(). This restricts the size of the buffer
6489 * entry list to PAGE_SIZE.
6491 * The actual data buffers on the other hand will only be accessed
6492 * by the CPU or the adapter but not by both simultaneously. This allows
6493 * Scatter/Gather packet based DMA procedures for using physically
6494 * discontiguous pages.
6498 * mgsl_reset_tx_dma_buffers()
6500 * Set the count for all transmit buffers to 0 to indicate the
6501 * buffer is available for use and set the current buffer to the
6502 * first buffer. This effectively makes all buffers free and
6503 * discards any data in buffers.
6505 * Arguments: info pointer to device instance data
6506 * Return Value: None
6508 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct
*info
)
6512 for ( i
= 0; i
< info
->tx_buffer_count
; i
++ ) {
6513 *((unsigned long *)&(info
->tx_buffer_list
[i
].count
)) = 0;
6516 info
->current_tx_buffer
= 0;
6517 info
->start_tx_dma_buffer
= 0;
6518 info
->tx_dma_buffers_used
= 0;
6520 info
->get_tx_holding_index
= 0;
6521 info
->put_tx_holding_index
= 0;
6522 info
->tx_holding_count
= 0;
6524 } /* end of mgsl_reset_tx_dma_buffers() */
6527 * num_free_tx_dma_buffers()
6529 * returns the number of free tx dma buffers available
6531 * Arguments: info pointer to device instance data
6532 * Return Value: number of free tx dma buffers
6534 static int num_free_tx_dma_buffers(struct mgsl_struct
*info
)
6536 return info
->tx_buffer_count
- info
->tx_dma_buffers_used
;
6540 * mgsl_reset_rx_dma_buffers()
6542 * Set the count for all receive buffers to DMABUFFERSIZE
6543 * and set the current buffer to the first buffer. This effectively
6544 * makes all buffers free and discards any data in buffers.
6546 * Arguments: info pointer to device instance data
6547 * Return Value: None
6549 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct
*info
)
6553 for ( i
= 0; i
< info
->rx_buffer_count
; i
++ ) {
6554 *((unsigned long *)&(info
->rx_buffer_list
[i
].count
)) = DMABUFFERSIZE
;
6555 // info->rx_buffer_list[i].count = DMABUFFERSIZE;
6556 // info->rx_buffer_list[i].status = 0;
6559 info
->current_rx_buffer
= 0;
6561 } /* end of mgsl_reset_rx_dma_buffers() */
6564 * mgsl_free_rx_frame_buffers()
6566 * Free the receive buffers used by a received SDLC
6567 * frame such that the buffers can be reused.
6571 * info pointer to device instance data
6572 * StartIndex index of 1st receive buffer of frame
6573 * EndIndex index of last receive buffer of frame
6575 * Return Value: None
6577 static void mgsl_free_rx_frame_buffers( struct mgsl_struct
*info
, unsigned int StartIndex
, unsigned int EndIndex
)
6580 DMABUFFERENTRY
*pBufEntry
;
6583 /* Starting with 1st buffer entry of the frame clear the status */
6584 /* field and set the count field to DMA Buffer Size. */
6589 pBufEntry
= &(info
->rx_buffer_list
[Index
]);
6591 if ( Index
== EndIndex
) {
6592 /* This is the last buffer of the frame! */
6596 /* reset current buffer for reuse */
6597 // pBufEntry->status = 0;
6598 // pBufEntry->count = DMABUFFERSIZE;
6599 *((unsigned long *)&(pBufEntry
->count
)) = DMABUFFERSIZE
;
6601 /* advance to next buffer entry in linked list */
6603 if ( Index
== info
->rx_buffer_count
)
6607 /* set current buffer to next buffer after last buffer of frame */
6608 info
->current_rx_buffer
= Index
;
6610 } /* end of free_rx_frame_buffers() */
6612 /* mgsl_get_rx_frame()
6614 * This function attempts to return a received SDLC frame from the
6615 * receive DMA buffers. Only frames received without errors are returned.
6617 * Arguments: info pointer to device extension
6618 * Return Value: 1 if frame returned, otherwise 0
6620 static int mgsl_get_rx_frame(struct mgsl_struct
*info
)
6622 unsigned int StartIndex
, EndIndex
; /* index of 1st and last buffers of Rx frame */
6623 unsigned short status
;
6624 DMABUFFERENTRY
*pBufEntry
;
6625 unsigned int framesize
= 0;
6627 unsigned long flags
;
6628 struct tty_struct
*tty
= info
->tty
;
6629 int return_frame
= 0;
6632 * current_rx_buffer points to the 1st buffer of the next available
6633 * receive frame. To find the last buffer of the frame look for
6634 * a non-zero status field in the buffer entries. (The status
6635 * field is set by the 16C32 after completing a receive frame.
6638 StartIndex
= EndIndex
= info
->current_rx_buffer
;
6640 while( !info
->rx_buffer_list
[EndIndex
].status
) {
6642 * If the count field of the buffer entry is non-zero then
6643 * this buffer has not been used. (The 16C32 clears the count
6644 * field when it starts using the buffer.) If an unused buffer
6645 * is encountered then there are no frames available.
6648 if ( info
->rx_buffer_list
[EndIndex
].count
)
6651 /* advance to next buffer entry in linked list */
6653 if ( EndIndex
== info
->rx_buffer_count
)
6656 /* if entire list searched then no frame available */
6657 if ( EndIndex
== StartIndex
) {
6658 /* If this occurs then something bad happened,
6659 * all buffers have been 'used' but none mark
6660 * the end of a frame. Reset buffers and receiver.
6663 if ( info
->rx_enabled
){
6664 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6665 usc_start_receiver(info
);
6666 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6673 /* check status of receive frame */
6675 status
= info
->rx_buffer_list
[EndIndex
].status
;
6677 if ( status
& (RXSTATUS_SHORT_FRAME
+ RXSTATUS_OVERRUN
+
6678 RXSTATUS_CRC_ERROR
+ RXSTATUS_ABORT
) ) {
6679 if ( status
& RXSTATUS_SHORT_FRAME
)
6680 info
->icount
.rxshort
++;
6681 else if ( status
& RXSTATUS_ABORT
)
6682 info
->icount
.rxabort
++;
6683 else if ( status
& RXSTATUS_OVERRUN
)
6684 info
->icount
.rxover
++;
6686 info
->icount
.rxcrc
++;
6687 if ( info
->params
.crc_type
& HDLC_CRC_RETURN_EX
)
6693 struct net_device_stats
*stats
= hdlc_stats(info
->netdev
);
6695 stats
->rx_frame_errors
++;
6701 if ( return_frame
) {
6702 /* receive frame has no errors, get frame size.
6703 * The frame size is the starting value of the RCC (which was
6704 * set to 0xffff) minus the ending value of the RCC (decremented
6705 * once for each receive character) minus 2 for the 16-bit CRC.
6708 framesize
= RCLRVALUE
- info
->rx_buffer_list
[EndIndex
].rcc
;
6710 /* adjust frame size for CRC if any */
6711 if ( info
->params
.crc_type
== HDLC_CRC_16_CCITT
)
6713 else if ( info
->params
.crc_type
== HDLC_CRC_32_CCITT
)
6717 if ( debug_level
>= DEBUG_LEVEL_BH
)
6718 printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
6719 __FILE__
,__LINE__
,info
->device_name
,status
,framesize
);
6721 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6722 mgsl_trace_block(info
,info
->rx_buffer_list
[StartIndex
].virt_addr
,
6723 min_t(int, framesize
, DMABUFFERSIZE
),0);
6726 if ( ( (info
->params
.crc_type
& HDLC_CRC_RETURN_EX
) &&
6727 ((framesize
+1) > info
->max_frame_size
) ) ||
6728 (framesize
> info
->max_frame_size
) )
6729 info
->icount
.rxlong
++;
6731 /* copy dma buffer(s) to contiguous intermediate buffer */
6732 int copy_count
= framesize
;
6733 int index
= StartIndex
;
6734 unsigned char *ptmp
= info
->intermediate_rxbuffer
;
6736 if ( !(status
& RXSTATUS_CRC_ERROR
))
6737 info
->icount
.rxok
++;
6741 if ( copy_count
> DMABUFFERSIZE
)
6742 partial_count
= DMABUFFERSIZE
;
6744 partial_count
= copy_count
;
6746 pBufEntry
= &(info
->rx_buffer_list
[index
]);
6747 memcpy( ptmp
, pBufEntry
->virt_addr
, partial_count
);
6748 ptmp
+= partial_count
;
6749 copy_count
-= partial_count
;
6751 if ( ++index
== info
->rx_buffer_count
)
6755 if ( info
->params
.crc_type
& HDLC_CRC_RETURN_EX
) {
6757 *ptmp
= (status
& RXSTATUS_CRC_ERROR
?
6761 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6762 printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n",
6763 __FILE__
,__LINE__
,info
->device_name
,
6769 hdlcdev_rx(info
,info
->intermediate_rxbuffer
,framesize
);
6772 ldisc_receive_buf(tty
, info
->intermediate_rxbuffer
, info
->flag_buf
, framesize
);
6775 /* Free the buffers used by this frame. */
6776 mgsl_free_rx_frame_buffers( info
, StartIndex
, EndIndex
);
6782 if ( info
->rx_enabled
&& info
->rx_overflow
) {
6783 /* The receiver needs to restarted because of
6784 * a receive overflow (buffer or FIFO). If the
6785 * receive buffers are now empty, then restart receiver.
6788 if ( !info
->rx_buffer_list
[EndIndex
].status
&&
6789 info
->rx_buffer_list
[EndIndex
].count
) {
6790 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6791 usc_start_receiver(info
);
6792 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6798 } /* end of mgsl_get_rx_frame() */
6800 /* mgsl_get_raw_rx_frame()
6802 * This function attempts to return a received frame from the
6803 * receive DMA buffers when running in external loop mode. In this mode,
6804 * we will return at most one DMABUFFERSIZE frame to the application.
6805 * The USC receiver is triggering off of DCD going active to start a new
6806 * frame, and DCD going inactive to terminate the frame (similar to
6807 * processing a closing flag character).
6809 * In this routine, we will return DMABUFFERSIZE "chunks" at a time.
6810 * If DCD goes inactive, the last Rx DMA Buffer will have a non-zero
6811 * status field and the RCC field will indicate the length of the
6812 * entire received frame. We take this RCC field and get the modulus
6813 * of RCC and DMABUFFERSIZE to determine if number of bytes in the
6814 * last Rx DMA buffer and return that last portion of the frame.
6816 * Arguments: info pointer to device extension
6817 * Return Value: 1 if frame returned, otherwise 0
6819 static int mgsl_get_raw_rx_frame(struct mgsl_struct
*info
)
6821 unsigned int CurrentIndex
, NextIndex
;
6822 unsigned short status
;
6823 DMABUFFERENTRY
*pBufEntry
;
6824 unsigned int framesize
= 0;
6826 unsigned long flags
;
6827 struct tty_struct
*tty
= info
->tty
;
6830 * current_rx_buffer points to the 1st buffer of the next available
6831 * receive frame. The status field is set by the 16C32 after
6832 * completing a receive frame. If the status field of this buffer
6833 * is zero, either the USC is still filling this buffer or this
6834 * is one of a series of buffers making up a received frame.
6836 * If the count field of this buffer is zero, the USC is either
6837 * using this buffer or has used this buffer. Look at the count
6838 * field of the next buffer. If that next buffer's count is
6839 * non-zero, the USC is still actively using the current buffer.
6840 * Otherwise, if the next buffer's count field is zero, the
6841 * current buffer is complete and the USC is using the next
6844 CurrentIndex
= NextIndex
= info
->current_rx_buffer
;
6846 if ( NextIndex
== info
->rx_buffer_count
)
6849 if ( info
->rx_buffer_list
[CurrentIndex
].status
!= 0 ||
6850 (info
->rx_buffer_list
[CurrentIndex
].count
== 0 &&
6851 info
->rx_buffer_list
[NextIndex
].count
== 0)) {
6853 * Either the status field of this dma buffer is non-zero
6854 * (indicating the last buffer of a receive frame) or the next
6855 * buffer is marked as in use -- implying this buffer is complete
6856 * and an intermediate buffer for this received frame.
6859 status
= info
->rx_buffer_list
[CurrentIndex
].status
;
6861 if ( status
& (RXSTATUS_SHORT_FRAME
+ RXSTATUS_OVERRUN
+
6862 RXSTATUS_CRC_ERROR
+ RXSTATUS_ABORT
) ) {
6863 if ( status
& RXSTATUS_SHORT_FRAME
)
6864 info
->icount
.rxshort
++;
6865 else if ( status
& RXSTATUS_ABORT
)
6866 info
->icount
.rxabort
++;
6867 else if ( status
& RXSTATUS_OVERRUN
)
6868 info
->icount
.rxover
++;
6870 info
->icount
.rxcrc
++;
6874 * A receive frame is available, get frame size and status.
6876 * The frame size is the starting value of the RCC (which was
6877 * set to 0xffff) minus the ending value of the RCC (decremented
6878 * once for each receive character) minus 2 or 4 for the 16-bit
6881 * If the status field is zero, this is an intermediate buffer.
6884 * If the DMA Buffer Entry's Status field is non-zero, the
6885 * receive operation completed normally (ie: DCD dropped). The
6886 * RCC field is valid and holds the received frame size.
6887 * It is possible that the RCC field will be zero on a DMA buffer
6888 * entry with a non-zero status. This can occur if the total
6889 * frame size (number of bytes between the time DCD goes active
6890 * to the time DCD goes inactive) exceeds 65535 bytes. In this
6891 * case the 16C32 has underrun on the RCC count and appears to
6892 * stop updating this counter to let us know the actual received
6893 * frame size. If this happens (non-zero status and zero RCC),
6894 * simply return the entire RxDMA Buffer
6898 * In the event that the final RxDMA Buffer is
6899 * terminated with a non-zero status and the RCC
6900 * field is zero, we interpret this as the RCC
6901 * having underflowed (received frame > 65535 bytes).
6903 * Signal the event to the user by passing back
6904 * a status of RxStatus_CrcError returning the full
6905 * buffer and let the app figure out what data is
6908 if ( info
->rx_buffer_list
[CurrentIndex
].rcc
)
6909 framesize
= RCLRVALUE
- info
->rx_buffer_list
[CurrentIndex
].rcc
;
6911 framesize
= DMABUFFERSIZE
;
6914 framesize
= DMABUFFERSIZE
;
6917 if ( framesize
> DMABUFFERSIZE
) {
6919 * if running in raw sync mode, ISR handler for
6920 * End Of Buffer events terminates all buffers at 4K.
6921 * If this frame size is said to be >4K, get the
6922 * actual number of bytes of the frame in this buffer.
6924 framesize
= framesize
% DMABUFFERSIZE
;
6928 if ( debug_level
>= DEBUG_LEVEL_BH
)
6929 printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n",
6930 __FILE__
,__LINE__
,info
->device_name
,status
,framesize
);
6932 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6933 mgsl_trace_block(info
,info
->rx_buffer_list
[CurrentIndex
].virt_addr
,
6934 min_t(int, framesize
, DMABUFFERSIZE
),0);
6937 /* copy dma buffer(s) to contiguous intermediate buffer */
6938 /* NOTE: we never copy more than DMABUFFERSIZE bytes */
6940 pBufEntry
= &(info
->rx_buffer_list
[CurrentIndex
]);
6941 memcpy( info
->intermediate_rxbuffer
, pBufEntry
->virt_addr
, framesize
);
6942 info
->icount
.rxok
++;
6944 ldisc_receive_buf(tty
, info
->intermediate_rxbuffer
, info
->flag_buf
, framesize
);
6947 /* Free the buffers used by this frame. */
6948 mgsl_free_rx_frame_buffers( info
, CurrentIndex
, CurrentIndex
);
6954 if ( info
->rx_enabled
&& info
->rx_overflow
) {
6955 /* The receiver needs to restarted because of
6956 * a receive overflow (buffer or FIFO). If the
6957 * receive buffers are now empty, then restart receiver.
6960 if ( !info
->rx_buffer_list
[CurrentIndex
].status
&&
6961 info
->rx_buffer_list
[CurrentIndex
].count
) {
6962 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6963 usc_start_receiver(info
);
6964 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6970 } /* end of mgsl_get_raw_rx_frame() */
6972 /* mgsl_load_tx_dma_buffer()
6974 * Load the transmit DMA buffer with the specified data.
6978 * info pointer to device extension
6979 * Buffer pointer to buffer containing frame to load
6980 * BufferSize size in bytes of frame in Buffer
6982 * Return Value: None
6984 static void mgsl_load_tx_dma_buffer(struct mgsl_struct
*info
,
6985 const char *Buffer
, unsigned int BufferSize
)
6987 unsigned short Copycount
;
6989 DMABUFFERENTRY
*pBufEntry
;
6991 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6992 mgsl_trace_block(info
,Buffer
, min_t(int, BufferSize
, DMABUFFERSIZE
), 1);
6994 if (info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
) {
6995 /* set CMR:13 to start transmit when
6996 * next GoAhead (abort) is received
6998 info
->cmr_value
|= BIT13
;
7001 /* begin loading the frame in the next available tx dma
7002 * buffer, remember it's starting location for setting
7003 * up tx dma operation
7005 i
= info
->current_tx_buffer
;
7006 info
->start_tx_dma_buffer
= i
;
7008 /* Setup the status and RCC (Frame Size) fields of the 1st */
7009 /* buffer entry in the transmit DMA buffer list. */
7011 info
->tx_buffer_list
[i
].status
= info
->cmr_value
& 0xf000;
7012 info
->tx_buffer_list
[i
].rcc
= BufferSize
;
7013 info
->tx_buffer_list
[i
].count
= BufferSize
;
7015 /* Copy frame data from 1st source buffer to the DMA buffers. */
7016 /* The frame data may span multiple DMA buffers. */
7018 while( BufferSize
){
7019 /* Get a pointer to next DMA buffer entry. */
7020 pBufEntry
= &info
->tx_buffer_list
[i
++];
7022 if ( i
== info
->tx_buffer_count
)
7025 /* Calculate the number of bytes that can be copied from */
7026 /* the source buffer to this DMA buffer. */
7027 if ( BufferSize
> DMABUFFERSIZE
)
7028 Copycount
= DMABUFFERSIZE
;
7030 Copycount
= BufferSize
;
7032 /* Actually copy data from source buffer to DMA buffer. */
7033 /* Also set the data count for this individual DMA buffer. */
7034 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
7035 mgsl_load_pci_memory(pBufEntry
->virt_addr
, Buffer
,Copycount
);
7037 memcpy(pBufEntry
->virt_addr
, Buffer
, Copycount
);
7039 pBufEntry
->count
= Copycount
;
7041 /* Advance source pointer and reduce remaining data count. */
7042 Buffer
+= Copycount
;
7043 BufferSize
-= Copycount
;
7045 ++info
->tx_dma_buffers_used
;
7048 /* remember next available tx dma buffer */
7049 info
->current_tx_buffer
= i
;
7051 } /* end of mgsl_load_tx_dma_buffer() */
7054 * mgsl_register_test()
7056 * Performs a register test of the 16C32.
7058 * Arguments: info pointer to device instance data
7059 * Return Value: TRUE if test passed, otherwise FALSE
7061 static BOOLEAN
mgsl_register_test( struct mgsl_struct
*info
)
7063 static unsigned short BitPatterns
[] =
7064 { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
7065 static unsigned int Patterncount
= sizeof(BitPatterns
)/sizeof(unsigned short);
7068 unsigned long flags
;
7070 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7073 /* Verify the reset state of some registers. */
7075 if ( (usc_InReg( info
, SICR
) != 0) ||
7076 (usc_InReg( info
, IVR
) != 0) ||
7077 (usc_InDmaReg( info
, DIVR
) != 0) ){
7082 /* Write bit patterns to various registers but do it out of */
7083 /* sync, then read back and verify values. */
7085 for ( i
= 0 ; i
< Patterncount
; i
++ ) {
7086 usc_OutReg( info
, TC0R
, BitPatterns
[i
] );
7087 usc_OutReg( info
, TC1R
, BitPatterns
[(i
+1)%Patterncount
] );
7088 usc_OutReg( info
, TCLR
, BitPatterns
[(i
+2)%Patterncount
] );
7089 usc_OutReg( info
, RCLR
, BitPatterns
[(i
+3)%Patterncount
] );
7090 usc_OutReg( info
, RSR
, BitPatterns
[(i
+4)%Patterncount
] );
7091 usc_OutDmaReg( info
, TBCR
, BitPatterns
[(i
+5)%Patterncount
] );
7093 if ( (usc_InReg( info
, TC0R
) != BitPatterns
[i
]) ||
7094 (usc_InReg( info
, TC1R
) != BitPatterns
[(i
+1)%Patterncount
]) ||
7095 (usc_InReg( info
, TCLR
) != BitPatterns
[(i
+2)%Patterncount
]) ||
7096 (usc_InReg( info
, RCLR
) != BitPatterns
[(i
+3)%Patterncount
]) ||
7097 (usc_InReg( info
, RSR
) != BitPatterns
[(i
+4)%Patterncount
]) ||
7098 (usc_InDmaReg( info
, TBCR
) != BitPatterns
[(i
+5)%Patterncount
]) ){
7106 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7110 } /* end of mgsl_register_test() */
7112 /* mgsl_irq_test() Perform interrupt test of the 16C32.
7114 * Arguments: info pointer to device instance data
7115 * Return Value: TRUE if test passed, otherwise FALSE
7117 static BOOLEAN
mgsl_irq_test( struct mgsl_struct
*info
)
7119 unsigned long EndTime
;
7120 unsigned long flags
;
7122 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7126 * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition.
7127 * The ISR sets irq_occurred to 1.
7130 info
->irq_occurred
= FALSE
;
7132 /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */
7133 /* Enable INTEN (Port 6, Bit12) */
7134 /* This connects the IRQ request signal to the ISA bus */
7135 /* on the ISA adapter. This has no effect for the PCI adapter */
7136 usc_OutReg( info
, PCR
, (unsigned short)((usc_InReg(info
, PCR
) | BIT13
) & ~BIT12
) );
7138 usc_EnableMasterIrqBit(info
);
7139 usc_EnableInterrupts(info
, IO_PIN
);
7140 usc_ClearIrqPendingBits(info
, IO_PIN
);
7142 usc_UnlatchIostatusBits(info
, MISCSTATUS_TXC_LATCHED
);
7143 usc_EnableStatusIrqs(info
, SICR_TXC_ACTIVE
+ SICR_TXC_INACTIVE
);
7145 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7148 while( EndTime
-- && !info
->irq_occurred
) {
7149 msleep_interruptible(10);
7152 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7154 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7156 if ( !info
->irq_occurred
)
7161 } /* end of mgsl_irq_test() */
7165 * Perform a DMA test of the 16C32. A small frame is
7166 * transmitted via DMA from a transmit buffer to a receive buffer
7167 * using single buffer DMA mode.
7169 * Arguments: info pointer to device instance data
7170 * Return Value: TRUE if test passed, otherwise FALSE
7172 static BOOLEAN
mgsl_dma_test( struct mgsl_struct
*info
)
7174 unsigned short FifoLevel
;
7175 unsigned long phys_addr
;
7176 unsigned int FrameSize
;
7180 unsigned short status
=0;
7181 unsigned long EndTime
;
7182 unsigned long flags
;
7183 MGSL_PARAMS tmp_params
;
7185 /* save current port options */
7186 memcpy(&tmp_params
,&info
->params
,sizeof(MGSL_PARAMS
));
7187 /* load default port options */
7188 memcpy(&info
->params
,&default_params
,sizeof(MGSL_PARAMS
));
7190 #define TESTFRAMESIZE 40
7192 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7194 /* setup 16C32 for SDLC DMA transfer mode */
7197 usc_set_sdlc_mode(info
);
7198 usc_enable_loopback(info
,1);
7200 /* Reprogram the RDMR so that the 16C32 does NOT clear the count
7201 * field of the buffer entry after fetching buffer address. This
7202 * way we can detect a DMA failure for a DMA read (which should be
7203 * non-destructive to system memory) before we try and write to
7204 * memory (where a failure could corrupt system memory).
7207 /* Receive DMA mode Register (RDMR)
7209 * <15..14> 11 DMA mode = Linked List Buffer mode
7210 * <13> 1 RSBinA/L = store Rx status Block in List entry
7211 * <12> 0 1 = Clear count of List Entry after fetching
7212 * <11..10> 00 Address mode = Increment
7213 * <9> 1 Terminate Buffer on RxBound
7214 * <8> 0 Bus Width = 16bits
7215 * <7..0> ? status Bits (write as 0s)
7217 * 1110 0010 0000 0000 = 0xe200
7220 usc_OutDmaReg( info
, RDMR
, 0xe200 );
7222 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7225 /* SETUP TRANSMIT AND RECEIVE DMA BUFFERS */
7227 FrameSize
= TESTFRAMESIZE
;
7229 /* setup 1st transmit buffer entry: */
7230 /* with frame size and transmit control word */
7232 info
->tx_buffer_list
[0].count
= FrameSize
;
7233 info
->tx_buffer_list
[0].rcc
= FrameSize
;
7234 info
->tx_buffer_list
[0].status
= 0x4000;
7236 /* build a transmit frame in 1st transmit DMA buffer */
7238 TmpPtr
= info
->tx_buffer_list
[0].virt_addr
;
7239 for (i
= 0; i
< FrameSize
; i
++ )
7242 /* setup 1st receive buffer entry: */
7243 /* clear status, set max receive buffer size */
7245 info
->rx_buffer_list
[0].status
= 0;
7246 info
->rx_buffer_list
[0].count
= FrameSize
+ 4;
7248 /* zero out the 1st receive buffer */
7250 memset( info
->rx_buffer_list
[0].virt_addr
, 0, FrameSize
+ 4 );
7252 /* Set count field of next buffer entries to prevent */
7253 /* 16C32 from using buffers after the 1st one. */
7255 info
->tx_buffer_list
[1].count
= 0;
7256 info
->rx_buffer_list
[1].count
= 0;
7259 /***************************/
7260 /* Program 16C32 receiver. */
7261 /***************************/
7263 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7265 /* setup DMA transfers */
7266 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
7268 /* program 16C32 receiver with physical address of 1st DMA buffer entry */
7269 phys_addr
= info
->rx_buffer_list
[0].phys_entry
;
7270 usc_OutDmaReg( info
, NRARL
, (unsigned short)phys_addr
);
7271 usc_OutDmaReg( info
, NRARU
, (unsigned short)(phys_addr
>> 16) );
7273 /* Clear the Rx DMA status bits (read RDMR) and start channel */
7274 usc_InDmaReg( info
, RDMR
);
7275 usc_DmaCmd( info
, DmaCmd_InitRxChannel
);
7277 /* Enable Receiver (RMR <1..0> = 10) */
7278 usc_OutReg( info
, RMR
, (unsigned short)((usc_InReg(info
, RMR
) & 0xfffc) | 0x0002) );
7280 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7283 /*************************************************************/
7284 /* WAIT FOR RECEIVER TO DMA ALL PARAMETERS FROM BUFFER ENTRY */
7285 /*************************************************************/
7287 /* Wait 100ms for interrupt. */
7288 EndTime
= jiffies
+ msecs_to_jiffies(100);
7291 if (time_after(jiffies
, EndTime
)) {
7296 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7297 status
= usc_InDmaReg( info
, RDMR
);
7298 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7300 if ( !(status
& BIT4
) && (status
& BIT5
) ) {
7301 /* INITG (BIT 4) is inactive (no entry read in progress) AND */
7302 /* BUSY (BIT 5) is active (channel still active). */
7303 /* This means the buffer entry read has completed. */
7309 /******************************/
7310 /* Program 16C32 transmitter. */
7311 /******************************/
7313 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7315 /* Program the Transmit Character Length Register (TCLR) */
7316 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
7318 usc_OutReg( info
, TCLR
, (unsigned short)info
->tx_buffer_list
[0].count
);
7319 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
7321 /* Program the address of the 1st DMA Buffer Entry in linked list */
7323 phys_addr
= info
->tx_buffer_list
[0].phys_entry
;
7324 usc_OutDmaReg( info
, NTARL
, (unsigned short)phys_addr
);
7325 usc_OutDmaReg( info
, NTARU
, (unsigned short)(phys_addr
>> 16) );
7327 /* unlatch Tx status bits, and start transmit channel. */
7329 usc_OutReg( info
, TCSR
, (unsigned short)(( usc_InReg(info
, TCSR
) & 0x0f00) | 0xfa) );
7330 usc_DmaCmd( info
, DmaCmd_InitTxChannel
);
7332 /* wait for DMA controller to fill transmit FIFO */
7334 usc_TCmd( info
, TCmd_SelectTicrTxFifostatus
);
7336 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7339 /**********************************/
7340 /* WAIT FOR TRANSMIT FIFO TO FILL */
7341 /**********************************/
7344 EndTime
= jiffies
+ msecs_to_jiffies(100);
7347 if (time_after(jiffies
, EndTime
)) {
7352 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7353 FifoLevel
= usc_InReg(info
, TICR
) >> 8;
7354 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7356 if ( FifoLevel
< 16 )
7359 if ( FrameSize
< 32 ) {
7360 /* This frame is smaller than the entire transmit FIFO */
7361 /* so wait for the entire frame to be loaded. */
7362 if ( FifoLevel
<= (32 - FrameSize
) )
7370 /* Enable 16C32 transmitter. */
7372 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7374 /* Transmit mode Register (TMR), <1..0> = 10, Enable Transmitter */
7375 usc_TCmd( info
, TCmd_SendFrame
);
7376 usc_OutReg( info
, TMR
, (unsigned short)((usc_InReg(info
, TMR
) & 0xfffc) | 0x0002) );
7378 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7381 /******************************/
7382 /* WAIT FOR TRANSMIT COMPLETE */
7383 /******************************/
7386 EndTime
= jiffies
+ msecs_to_jiffies(100);
7388 /* While timer not expired wait for transmit complete */
7390 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7391 status
= usc_InReg( info
, TCSR
);
7392 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7394 while ( !(status
& (BIT6
+BIT5
+BIT4
+BIT2
+BIT1
)) ) {
7395 if (time_after(jiffies
, EndTime
)) {
7400 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7401 status
= usc_InReg( info
, TCSR
);
7402 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7408 /* CHECK FOR TRANSMIT ERRORS */
7409 if ( status
& (BIT5
+ BIT1
) )
7414 /* WAIT FOR RECEIVE COMPLETE */
7417 EndTime
= jiffies
+ msecs_to_jiffies(100);
7419 /* Wait for 16C32 to write receive status to buffer entry. */
7420 status
=info
->rx_buffer_list
[0].status
;
7421 while ( status
== 0 ) {
7422 if (time_after(jiffies
, EndTime
)) {
7426 status
=info
->rx_buffer_list
[0].status
;
7432 /* CHECK FOR RECEIVE ERRORS */
7433 status
= info
->rx_buffer_list
[0].status
;
7435 if ( status
& (BIT8
+ BIT3
+ BIT1
) ) {
7436 /* receive error has occurred */
7439 if ( memcmp( info
->tx_buffer_list
[0].virt_addr
,
7440 info
->rx_buffer_list
[0].virt_addr
, FrameSize
) ){
7446 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7448 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7450 /* restore current port options */
7451 memcpy(&info
->params
,&tmp_params
,sizeof(MGSL_PARAMS
));
7455 } /* end of mgsl_dma_test() */
7457 /* mgsl_adapter_test()
7459 * Perform the register, IRQ, and DMA tests for the 16C32.
7461 * Arguments: info pointer to device instance data
7462 * Return Value: 0 if success, otherwise -ENODEV
7464 static int mgsl_adapter_test( struct mgsl_struct
*info
)
7466 if ( debug_level
>= DEBUG_LEVEL_INFO
)
7467 printk( "%s(%d):Testing device %s\n",
7468 __FILE__
,__LINE__
,info
->device_name
);
7470 if ( !mgsl_register_test( info
) ) {
7471 info
->init_error
= DiagStatus_AddressFailure
;
7472 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
7473 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->io_base
) );
7477 if ( !mgsl_irq_test( info
) ) {
7478 info
->init_error
= DiagStatus_IrqFailure
;
7479 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
7480 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->irq_level
) );
7484 if ( !mgsl_dma_test( info
) ) {
7485 info
->init_error
= DiagStatus_DmaFailure
;
7486 printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
7487 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->dma_level
) );
7491 if ( debug_level
>= DEBUG_LEVEL_INFO
)
7492 printk( "%s(%d):device %s passed diagnostics\n",
7493 __FILE__
,__LINE__
,info
->device_name
);
7497 } /* end of mgsl_adapter_test() */
7499 /* mgsl_memory_test()
7501 * Test the shared memory on a PCI adapter.
7503 * Arguments: info pointer to device instance data
7504 * Return Value: TRUE if test passed, otherwise FALSE
7506 static BOOLEAN
mgsl_memory_test( struct mgsl_struct
*info
)
7508 static unsigned long BitPatterns
[] = { 0x0, 0x55555555, 0xaaaaaaaa,
7509 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
7510 unsigned long Patterncount
= sizeof(BitPatterns
)/sizeof(unsigned long);
7512 unsigned long TestLimit
= SHARED_MEM_ADDRESS_SIZE
/sizeof(unsigned long);
7513 unsigned long * TestAddr
;
7515 if ( info
->bus_type
!= MGSL_BUS_TYPE_PCI
)
7518 TestAddr
= (unsigned long *)info
->memory_base
;
7520 /* Test data lines with test pattern at one location. */
7522 for ( i
= 0 ; i
< Patterncount
; i
++ ) {
7523 *TestAddr
= BitPatterns
[i
];
7524 if ( *TestAddr
!= BitPatterns
[i
] )
7528 /* Test address lines with incrementing pattern over */
7529 /* entire address range. */
7531 for ( i
= 0 ; i
< TestLimit
; i
++ ) {
7536 TestAddr
= (unsigned long *)info
->memory_base
;
7538 for ( i
= 0 ; i
< TestLimit
; i
++ ) {
7539 if ( *TestAddr
!= i
* 4 )
7544 memset( info
->memory_base
, 0, SHARED_MEM_ADDRESS_SIZE
);
7548 } /* End Of mgsl_memory_test() */
7551 /* mgsl_load_pci_memory()
7553 * Load a large block of data into the PCI shared memory.
7554 * Use this instead of memcpy() or memmove() to move data
7555 * into the PCI shared memory.
7559 * This function prevents the PCI9050 interface chip from hogging
7560 * the adapter local bus, which can starve the 16C32 by preventing
7561 * 16C32 bus master cycles.
7563 * The PCI9050 documentation says that the 9050 will always release
7564 * control of the local bus after completing the current read
7565 * or write operation.
7567 * It appears that as long as the PCI9050 write FIFO is full, the
7568 * PCI9050 treats all of the writes as a single burst transaction
7569 * and will not release the bus. This causes DMA latency problems
7570 * at high speeds when copying large data blocks to the shared
7573 * This function in effect, breaks the a large shared memory write
7574 * into multiple transations by interleaving a shared memory read
7575 * which will flush the write FIFO and 'complete' the write
7576 * transation. This allows any pending DMA request to gain control
7577 * of the local bus in a timely fasion.
7581 * TargetPtr pointer to target address in PCI shared memory
7582 * SourcePtr pointer to source buffer for data
7583 * count count in bytes of data to copy
7585 * Return Value: None
7587 static void mgsl_load_pci_memory( char* TargetPtr
, const char* SourcePtr
,
7588 unsigned short count
)
7590 /* 16 32-bit writes @ 60ns each = 960ns max latency on local bus */
7591 #define PCI_LOAD_INTERVAL 64
7593 unsigned short Intervalcount
= count
/ PCI_LOAD_INTERVAL
;
7594 unsigned short Index
;
7595 unsigned long Dummy
;
7597 for ( Index
= 0 ; Index
< Intervalcount
; Index
++ )
7599 memcpy(TargetPtr
, SourcePtr
, PCI_LOAD_INTERVAL
);
7600 Dummy
= *((volatile unsigned long *)TargetPtr
);
7601 TargetPtr
+= PCI_LOAD_INTERVAL
;
7602 SourcePtr
+= PCI_LOAD_INTERVAL
;
7605 memcpy( TargetPtr
, SourcePtr
, count
% PCI_LOAD_INTERVAL
);
7607 } /* End Of mgsl_load_pci_memory() */
7609 static void mgsl_trace_block(struct mgsl_struct
*info
,const char* data
, int count
, int xmit
)
7614 printk("%s tx data:\n",info
->device_name
);
7616 printk("%s rx data:\n",info
->device_name
);
7624 for(i
=0;i
<linecount
;i
++)
7625 printk("%02X ",(unsigned char)data
[i
]);
7628 for(i
=0;i
<linecount
;i
++) {
7629 if (data
[i
]>=040 && data
[i
]<=0176)
7630 printk("%c",data
[i
]);
7639 } /* end of mgsl_trace_block() */
7641 /* mgsl_tx_timeout()
7643 * called when HDLC frame times out
7644 * update stats and do tx completion processing
7646 * Arguments: context pointer to device instance data
7647 * Return Value: None
7649 static void mgsl_tx_timeout(unsigned long context
)
7651 struct mgsl_struct
*info
= (struct mgsl_struct
*)context
;
7652 unsigned long flags
;
7654 if ( debug_level
>= DEBUG_LEVEL_INFO
)
7655 printk( "%s(%d):mgsl_tx_timeout(%s)\n",
7656 __FILE__
,__LINE__
,info
->device_name
);
7657 if(info
->tx_active
&&
7658 (info
->params
.mode
== MGSL_MODE_HDLC
||
7659 info
->params
.mode
== MGSL_MODE_RAW
) ) {
7660 info
->icount
.txtimeout
++;
7662 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7663 info
->tx_active
= 0;
7664 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
7666 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
7667 usc_loopmode_cancel_transmit( info
);
7669 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7673 hdlcdev_tx_done(info
);
7676 mgsl_bh_transmit(info
);
7678 } /* end of mgsl_tx_timeout() */
7680 /* signal that there are no more frames to send, so that
7681 * line is 'released' by echoing RxD to TxD when current
7682 * transmission is complete (or immediately if no tx in progress).
7684 static int mgsl_loopmode_send_done( struct mgsl_struct
* info
)
7686 unsigned long flags
;
7688 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7689 if (info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
) {
7690 if (info
->tx_active
)
7691 info
->loopmode_send_done_requested
= TRUE
;
7693 usc_loopmode_send_done(info
);
7695 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7700 /* release the line by echoing RxD to TxD
7701 * upon completion of a transmit frame
7703 static void usc_loopmode_send_done( struct mgsl_struct
* info
)
7705 info
->loopmode_send_done_requested
= FALSE
;
7706 /* clear CMR:13 to 0 to start echoing RxData to TxData */
7707 info
->cmr_value
&= ~BIT13
;
7708 usc_OutReg(info
, CMR
, info
->cmr_value
);
7711 /* abort a transmit in progress while in HDLC LoopMode
7713 static void usc_loopmode_cancel_transmit( struct mgsl_struct
* info
)
7715 /* reset tx dma channel and purge TxFifo */
7716 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
7717 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
7718 usc_loopmode_send_done( info
);
7721 /* for HDLC/SDLC LoopMode, setting CMR:13 after the transmitter is enabled
7722 * is an Insert Into Loop action. Upon receipt of a GoAhead sequence (RxAbort)
7723 * we must clear CMR:13 to begin repeating TxData to RxData
7725 static void usc_loopmode_insert_request( struct mgsl_struct
* info
)
7727 info
->loopmode_insert_requested
= TRUE
;
7729 /* enable RxAbort irq. On next RxAbort, clear CMR:13 to
7730 * begin repeating TxData on RxData (complete insertion)
7732 usc_OutReg( info
, RICR
,
7733 (usc_InReg( info
, RICR
) | RXSTATUS_ABORT_RECEIVED
) );
7735 /* set CMR:13 to insert into loop on next GoAhead (RxAbort) */
7736 info
->cmr_value
|= BIT13
;
7737 usc_OutReg(info
, CMR
, info
->cmr_value
);
7740 /* return 1 if station is inserted into the loop, otherwise 0
7742 static int usc_loopmode_active( struct mgsl_struct
* info
)
7744 return usc_InReg( info
, CCSR
) & BIT7
? 1 : 0 ;
7750 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
7751 * set encoding and frame check sequence (FCS) options
7753 * dev pointer to network device structure
7754 * encoding serial encoding setting
7755 * parity FCS setting
7757 * returns 0 if success, otherwise error code
7759 static int hdlcdev_attach(struct net_device
*dev
, unsigned short encoding
,
7760 unsigned short parity
)
7762 struct mgsl_struct
*info
= dev_to_port(dev
);
7763 unsigned char new_encoding
;
7764 unsigned short new_crctype
;
7766 /* return error if TTY interface open */
7772 case ENCODING_NRZ
: new_encoding
= HDLC_ENCODING_NRZ
; break;
7773 case ENCODING_NRZI
: new_encoding
= HDLC_ENCODING_NRZI_SPACE
; break;
7774 case ENCODING_FM_MARK
: new_encoding
= HDLC_ENCODING_BIPHASE_MARK
; break;
7775 case ENCODING_FM_SPACE
: new_encoding
= HDLC_ENCODING_BIPHASE_SPACE
; break;
7776 case ENCODING_MANCHESTER
: new_encoding
= HDLC_ENCODING_BIPHASE_LEVEL
; break;
7777 default: return -EINVAL
;
7782 case PARITY_NONE
: new_crctype
= HDLC_CRC_NONE
; break;
7783 case PARITY_CRC16_PR1_CCITT
: new_crctype
= HDLC_CRC_16_CCITT
; break;
7784 case PARITY_CRC32_PR1_CCITT
: new_crctype
= HDLC_CRC_32_CCITT
; break;
7785 default: return -EINVAL
;
7788 info
->params
.encoding
= new_encoding
;
7789 info
->params
.crc_type
= new_crctype
;;
7791 /* if network interface up, reprogram hardware */
7793 mgsl_program_hw(info
);
7799 * called by generic HDLC layer to send frame
7801 * skb socket buffer containing HDLC frame
7802 * dev pointer to network device structure
7804 * returns 0 if success, otherwise error code
7806 static int hdlcdev_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
7808 struct mgsl_struct
*info
= dev_to_port(dev
);
7809 struct net_device_stats
*stats
= hdlc_stats(dev
);
7810 unsigned long flags
;
7812 if (debug_level
>= DEBUG_LEVEL_INFO
)
7813 printk(KERN_INFO
"%s:hdlc_xmit(%s)\n",__FILE__
,dev
->name
);
7815 /* stop sending until this frame completes */
7816 netif_stop_queue(dev
);
7818 /* copy data to device buffers */
7819 info
->xmit_cnt
= skb
->len
;
7820 mgsl_load_tx_dma_buffer(info
, skb
->data
, skb
->len
);
7822 /* update network statistics */
7823 stats
->tx_packets
++;
7824 stats
->tx_bytes
+= skb
->len
;
7826 /* done with socket buffer, so free it */
7829 /* save start time for transmit timeout detection */
7830 dev
->trans_start
= jiffies
;
7832 /* start hardware transmitter if necessary */
7833 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7834 if (!info
->tx_active
)
7835 usc_start_transmitter(info
);
7836 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7842 * called by network layer when interface enabled
7843 * claim resources and initialize hardware
7845 * dev pointer to network device structure
7847 * returns 0 if success, otherwise error code
7849 static int hdlcdev_open(struct net_device
*dev
)
7851 struct mgsl_struct
*info
= dev_to_port(dev
);
7853 unsigned long flags
;
7855 if (debug_level
>= DEBUG_LEVEL_INFO
)
7856 printk("%s:hdlcdev_open(%s)\n",__FILE__
,dev
->name
);
7858 /* generic HDLC layer open processing */
7859 if ((rc
= hdlc_open(dev
)))
7862 /* arbitrate between network and tty opens */
7863 spin_lock_irqsave(&info
->netlock
, flags
);
7864 if (info
->count
!= 0 || info
->netcount
!= 0) {
7865 printk(KERN_WARNING
"%s: hdlc_open returning busy\n", dev
->name
);
7866 spin_unlock_irqrestore(&info
->netlock
, flags
);
7870 spin_unlock_irqrestore(&info
->netlock
, flags
);
7872 /* claim resources and init adapter */
7873 if ((rc
= startup(info
)) != 0) {
7874 spin_lock_irqsave(&info
->netlock
, flags
);
7876 spin_unlock_irqrestore(&info
->netlock
, flags
);
7880 /* assert DTR and RTS, apply hardware settings */
7881 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
7882 mgsl_program_hw(info
);
7884 /* enable network layer transmit */
7885 dev
->trans_start
= jiffies
;
7886 netif_start_queue(dev
);
7888 /* inform generic HDLC layer of current DCD status */
7889 spin_lock_irqsave(&info
->irq_spinlock
, flags
);
7890 usc_get_serial_signals(info
);
7891 spin_unlock_irqrestore(&info
->irq_spinlock
, flags
);
7892 hdlc_set_carrier(info
->serial_signals
& SerialSignal_DCD
, dev
);
7898 * called by network layer when interface is disabled
7899 * shutdown hardware and release resources
7901 * dev pointer to network device structure
7903 * returns 0 if success, otherwise error code
7905 static int hdlcdev_close(struct net_device
*dev
)
7907 struct mgsl_struct
*info
= dev_to_port(dev
);
7908 unsigned long flags
;
7910 if (debug_level
>= DEBUG_LEVEL_INFO
)
7911 printk("%s:hdlcdev_close(%s)\n",__FILE__
,dev
->name
);
7913 netif_stop_queue(dev
);
7915 /* shutdown adapter and release resources */
7920 spin_lock_irqsave(&info
->netlock
, flags
);
7922 spin_unlock_irqrestore(&info
->netlock
, flags
);
7928 * called by network layer to process IOCTL call to network device
7930 * dev pointer to network device structure
7931 * ifr pointer to network interface request structure
7932 * cmd IOCTL command code
7934 * returns 0 if success, otherwise error code
7936 static int hdlcdev_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
7938 const size_t size
= sizeof(sync_serial_settings
);
7939 sync_serial_settings new_line
;
7940 sync_serial_settings __user
*line
= ifr
->ifr_settings
.ifs_ifsu
.sync
;
7941 struct mgsl_struct
*info
= dev_to_port(dev
);
7944 if (debug_level
>= DEBUG_LEVEL_INFO
)
7945 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__
,dev
->name
);
7947 /* return error if TTY interface open */
7951 if (cmd
!= SIOCWANDEV
)
7952 return hdlc_ioctl(dev
, ifr
, cmd
);
7954 switch(ifr
->ifr_settings
.type
) {
7955 case IF_GET_IFACE
: /* return current sync_serial_settings */
7957 ifr
->ifr_settings
.type
= IF_IFACE_SYNC_SERIAL
;
7958 if (ifr
->ifr_settings
.size
< size
) {
7959 ifr
->ifr_settings
.size
= size
; /* data size wanted */
7963 flags
= info
->params
.flags
& (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
7964 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
7965 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
7966 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
);
7969 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_TXCPIN
): new_line
.clock_type
= CLOCK_EXT
; break;
7970 case (HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
): new_line
.clock_type
= CLOCK_INT
; break;
7971 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_BRG
): new_line
.clock_type
= CLOCK_TXINT
; break;
7972 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_RXCPIN
): new_line
.clock_type
= CLOCK_TXFROMRX
; break;
7973 default: new_line
.clock_type
= CLOCK_DEFAULT
;
7976 new_line
.clock_rate
= info
->params
.clock_speed
;
7977 new_line
.loopback
= info
->params
.loopback
? 1:0;
7979 if (copy_to_user(line
, &new_line
, size
))
7983 case IF_IFACE_SYNC_SERIAL
: /* set sync_serial_settings */
7985 if(!capable(CAP_NET_ADMIN
))
7987 if (copy_from_user(&new_line
, line
, size
))
7990 switch (new_line
.clock_type
)
7992 case CLOCK_EXT
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_TXCPIN
; break;
7993 case CLOCK_TXFROMRX
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_RXCPIN
; break;
7994 case CLOCK_INT
: flags
= HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
; break;
7995 case CLOCK_TXINT
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_BRG
; break;
7996 case CLOCK_DEFAULT
: flags
= info
->params
.flags
&
7997 (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
7998 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
7999 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
8000 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
); break;
8001 default: return -EINVAL
;
8004 if (new_line
.loopback
!= 0 && new_line
.loopback
!= 1)
8007 info
->params
.flags
&= ~(HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
8008 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
8009 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
8010 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
);
8011 info
->params
.flags
|= flags
;
8013 info
->params
.loopback
= new_line
.loopback
;
8015 if (flags
& (HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
))
8016 info
->params
.clock_speed
= new_line
.clock_rate
;
8018 info
->params
.clock_speed
= 0;
8020 /* if network interface up, reprogram hardware */
8022 mgsl_program_hw(info
);
8026 return hdlc_ioctl(dev
, ifr
, cmd
);
8031 * called by network layer when transmit timeout is detected
8033 * dev pointer to network device structure
8035 static void hdlcdev_tx_timeout(struct net_device
*dev
)
8037 struct mgsl_struct
*info
= dev_to_port(dev
);
8038 struct net_device_stats
*stats
= hdlc_stats(dev
);
8039 unsigned long flags
;
8041 if (debug_level
>= DEBUG_LEVEL_INFO
)
8042 printk("hdlcdev_tx_timeout(%s)\n",dev
->name
);
8045 stats
->tx_aborted_errors
++;
8047 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
8048 usc_stop_transmitter(info
);
8049 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
8051 netif_wake_queue(dev
);
8055 * called by device driver when transmit completes
8056 * reenable network layer transmit if stopped
8058 * info pointer to device instance information
8060 static void hdlcdev_tx_done(struct mgsl_struct
*info
)
8062 if (netif_queue_stopped(info
->netdev
))
8063 netif_wake_queue(info
->netdev
);
8067 * called by device driver when frame received
8068 * pass frame to network layer
8070 * info pointer to device instance information
8071 * buf pointer to buffer contianing frame data
8072 * size count of data bytes in buf
8074 static void hdlcdev_rx(struct mgsl_struct
*info
, char *buf
, int size
)
8076 struct sk_buff
*skb
= dev_alloc_skb(size
);
8077 struct net_device
*dev
= info
->netdev
;
8078 struct net_device_stats
*stats
= hdlc_stats(dev
);
8080 if (debug_level
>= DEBUG_LEVEL_INFO
)
8081 printk("hdlcdev_rx(%s)\n",dev
->name
);
8084 printk(KERN_NOTICE
"%s: can't alloc skb, dropping packet\n", dev
->name
);
8085 stats
->rx_dropped
++;
8089 memcpy(skb_put(skb
, size
),buf
,size
);
8091 skb
->protocol
= hdlc_type_trans(skb
, info
->netdev
);
8093 stats
->rx_packets
++;
8094 stats
->rx_bytes
+= size
;
8098 info
->netdev
->last_rx
= jiffies
;
8102 * called by device driver when adding device instance
8103 * do generic HDLC initialization
8105 * info pointer to device instance information
8107 * returns 0 if success, otherwise error code
8109 static int hdlcdev_init(struct mgsl_struct
*info
)
8112 struct net_device
*dev
;
8115 /* allocate and initialize network and HDLC layer objects */
8117 if (!(dev
= alloc_hdlcdev(info
))) {
8118 printk(KERN_ERR
"%s:hdlc device allocation failure\n",__FILE__
);
8122 /* for network layer reporting purposes only */
8123 dev
->base_addr
= info
->io_base
;
8124 dev
->irq
= info
->irq_level
;
8125 dev
->dma
= info
->dma_level
;
8127 /* network layer callbacks and settings */
8128 dev
->do_ioctl
= hdlcdev_ioctl
;
8129 dev
->open
= hdlcdev_open
;
8130 dev
->stop
= hdlcdev_close
;
8131 dev
->tx_timeout
= hdlcdev_tx_timeout
;
8132 dev
->watchdog_timeo
= 10*HZ
;
8133 dev
->tx_queue_len
= 50;
8135 /* generic HDLC layer callbacks and settings */
8136 hdlc
= dev_to_hdlc(dev
);
8137 hdlc
->attach
= hdlcdev_attach
;
8138 hdlc
->xmit
= hdlcdev_xmit
;
8140 /* register objects with HDLC layer */
8141 if ((rc
= register_hdlc_device(dev
))) {
8142 printk(KERN_WARNING
"%s:unable to register hdlc device\n",__FILE__
);
8152 * called by device driver when removing device instance
8153 * do generic HDLC cleanup
8155 * info pointer to device instance information
8157 static void hdlcdev_exit(struct mgsl_struct
*info
)
8159 unregister_hdlc_device(info
->netdev
);
8160 free_netdev(info
->netdev
);
8161 info
->netdev
= NULL
;
8164 #endif /* CONFIG_HDLC */
8167 static int __devinit
synclink_init_one (struct pci_dev
*dev
,
8168 const struct pci_device_id
*ent
)
8170 struct mgsl_struct
*info
;
8172 if (pci_enable_device(dev
)) {
8173 printk("error enabling pci device %p\n", dev
);
8177 if (!(info
= mgsl_allocate_device())) {
8178 printk("can't allocate device instance data.\n");
8182 /* Copy user configuration info to device instance data */
8184 info
->io_base
= pci_resource_start(dev
, 2);
8185 info
->irq_level
= dev
->irq
;
8186 info
->phys_memory_base
= pci_resource_start(dev
, 3);
8188 /* Because veremap only works on page boundaries we must map
8189 * a larger area than is actually implemented for the LCR
8190 * memory range. We map a full page starting at the page boundary.
8192 info
->phys_lcr_base
= pci_resource_start(dev
, 0);
8193 info
->lcr_offset
= info
->phys_lcr_base
& (PAGE_SIZE
-1);
8194 info
->phys_lcr_base
&= ~(PAGE_SIZE
-1);
8196 info
->bus_type
= MGSL_BUS_TYPE_PCI
;
8197 info
->io_addr_size
= 8;
8198 info
->irq_flags
= SA_SHIRQ
;
8200 if (dev
->device
== 0x0210) {
8201 /* Version 1 PCI9030 based universal PCI adapter */
8202 info
->misc_ctrl_value
= 0x007c4080;
8203 info
->hw_version
= 1;
8205 /* Version 0 PCI9050 based 5V PCI adapter
8206 * A PCI9050 bug prevents reading LCR registers if
8207 * LCR base address bit 7 is set. Maintain shadow
8208 * value so we can write to LCR misc control reg.
8210 info
->misc_ctrl_value
= 0x087e4546;
8211 info
->hw_version
= 0;
8214 mgsl_add_device(info
);
8219 static void __devexit
synclink_remove_one (struct pci_dev
*dev
)