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[linux-2.6/verdex.git] / drivers / serial / s3c2410.c
blob7365d4b50b954d2729ce1051acb461cc4ac35cc9
1 /*
2 * linux/drivers/serial/s3c2410.c
3 *
4 * Driver for onboard UARTs on the Samsung S3C24XX
5 *
6 * Based on drivers/char/serial.c and drivers/char/21285.c
7 *
8 * Ben Dooks, (c) 2003-2005 Simtec Electronics
9 * http://www.simtec.co.uk/products/SWLINUX/
10 *
11 * Changelog:
12 *
13 * 22-Jul-2004 BJD Finished off device rewrite
14 *
15 * 21-Jul-2004 BJD Thanks to <herbet@13thfloor.at> for pointing out
16 * problems with baud rate and loss of IR settings. Update
17 * to add configuration via platform_device structure
18 *
19 * 28-Sep-2004 BJD Re-write for the following items
20 * - S3C2410 and S3C2440 serial support
21 * - Power Management support
22 * - Fix console via IrDA devices
23 * - SysReq (Herbert Pötzl)
24 * - Break character handling (Herbert Pötzl)
25 * - spin-lock initialisation (Dimitry Andric)
26 * - added clock control
27 * - updated init code to use platform_device info
28 *
29 * 06-Mar-2005 BJD Add s3c2440 fclk clock source
30 *
31 * 09-Mar-2005 BJD Add s3c2400 support
32 *
33 * 10-Mar-2005 LCVR Changed S3C2410_VA_UART to S3C24XX_VA_UART
34 */
35
36 /* Note on 2440 fclk clock source handling
37 *
38 * Whilst it is possible to use the fclk as clock source, the method
39 * of properly switching too/from this is currently un-implemented, so
40 * whichever way is configured at startup is the one that will be used.
41 */
42
43 /* Hote on 2410 error handling
44 *
45 * The s3c2410 manual has a love/hate affair with the contents of the
46 * UERSTAT register in the UART blocks, and keeps marking some of the
47 * error bits as reserved. Having checked with the s3c2410x01,
48 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
49 * feature from the latter versions of the manual.
50 *
51 * If it becomes aparrent that latter versions of the 2410 remove these
52 * bits, then action will have to be taken to differentiate the versions
53 * and change the policy on BREAK
54 *
55 * BJD, 04-Nov-2004
56 */
57
58 #include <linux/config.h>
59
60 #if defined(CONFIG_SERIAL_S3C2410_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
61 #define SUPPORT_SYSRQ
62 #endif
63
64 #include <linux/module.h>
65 #include <linux/ioport.h>
66 #include <linux/device.h>
67 #include <linux/init.h>
68 #include <linux/sysrq.h>
69 #include <linux/console.h>
70 #include <linux/tty.h>
71 #include <linux/tty_flip.h>
72 #include <linux/serial_core.h>
73 #include <linux/serial.h>
74 #include <linux/delay.h>
75
76 #include <asm/io.h>
77 #include <asm/irq.h>
78
79 #include <asm/hardware.h>
80 #include <asm/hardware/clock.h>
81
82 #include <asm/arch/regs-serial.h>
83 #include <asm/arch/regs-gpio.h>
84
85 #include <asm/mach-types.h>
86
87 /* structures */
88
89 struct s3c24xx_uart_info {
90 char *name;
91 unsigned int type;
92 unsigned int fifosize;
93 unsigned long rx_fifomask;
94 unsigned long rx_fifoshift;
95 unsigned long rx_fifofull;
96 unsigned long tx_fifomask;
97 unsigned long tx_fifoshift;
98 unsigned long tx_fifofull;
99
100 /* clock source control */
101
102 int (*get_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
103 int (*set_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
104
105 /* uart controls */
106 int (*reset_port)(struct uart_port *, struct s3c2410_uartcfg *);
107 };
108
109 struct s3c24xx_uart_port {
110 unsigned char rx_claimed;
111 unsigned char tx_claimed;
112
113 struct s3c24xx_uart_info *info;
114 struct s3c24xx_uart_clksrc *clksrc;
115 struct clk *clk;
116 struct clk *baudclk;
117 struct uart_port port;
118 };
119
120
121 /* configuration defines */
122
123 #if 0
124 #if 1
125 /* send debug to the low-level output routines */
126
127 extern void printascii(const char *);
128
129 static void
130 s3c24xx_serial_dbg(const char *fmt, ...)
131 {
132 va_list va;
133 char buff[256];
134
135 va_start(va, fmt);
136 vsprintf(buff, fmt, va);
137 va_end(va);
138
139 printascii(buff);
140 }
141
142 #define dbg(x...) s3c24xx_serial_dbg(x)
143
144 #else
145 #define dbg(x...) printk(KERN_DEBUG "s3c24xx: ");
146 #endif
147 #else /* no debug */
148 #define dbg(x...) do {} while(0)
149 #endif
150
151 /* UART name and device definitions */
152
153 #define S3C24XX_SERIAL_NAME "ttySAC"
154 #define S3C24XX_SERIAL_DEVFS "tts/"
155 #define S3C24XX_SERIAL_MAJOR 204
156 #define S3C24XX_SERIAL_MINOR 64
157
158
159 /* conversion functions */
160
161 #define s3c24xx_dev_to_port(__dev) (struct uart_port *)dev_get_drvdata(__dev)
162 #define s3c24xx_dev_to_cfg(__dev) (struct s3c2410_uartcfg *)((__dev)->platform_data)
163
164 /* we can support 3 uarts, but not always use them */
165
166 #define NR_PORTS (3)
167
168 /* port irq numbers */
169
170 #define TX_IRQ(port) ((port)->irq + 1)
171 #define RX_IRQ(port) ((port)->irq)
172
173 /* register access controls */
174
175 #define portaddr(port, reg) ((port)->membase + (reg))
176
177 #define rd_regb(port, reg) (__raw_readb(portaddr(port, reg)))
178 #define rd_regl(port, reg) (__raw_readl(portaddr(port, reg)))
179
180 #define wr_regb(port, reg, val) \
181 do { __raw_writeb(val, portaddr(port, reg)); } while(0)
182
183 #define wr_regl(port, reg, val) \
184 do { __raw_writel(val, portaddr(port, reg)); } while(0)
185
186 /* macros to change one thing to another */
187
188 #define tx_enabled(port) ((port)->unused[0])
189 #define rx_enabled(port) ((port)->unused[1])
190
191 /* flag to ignore all characters comming in */
192 #define RXSTAT_DUMMY_READ (0x10000000)
193
194 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
195 {
196 return container_of(port, struct s3c24xx_uart_port, port);
197 }
198
199 /* translate a port to the device name */
200
201 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
202 {
203 return to_platform_device(port->dev)->name;
204 }
205
206 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
207 {
208 return (rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE);
209 }
210
211 static void s3c24xx_serial_rx_enable(struct uart_port *port)
212 {
213 unsigned long flags;
214 unsigned int ucon, ufcon;
215 int count = 10000;
216
217 spin_lock_irqsave(&port->lock, flags);
218
219 while (--count && !s3c24xx_serial_txempty_nofifo(port))
220 udelay(100);
221
222 ufcon = rd_regl(port, S3C2410_UFCON);
223 ufcon |= S3C2410_UFCON_RESETRX;
224 wr_regl(port, S3C2410_UFCON, ufcon);
225
226 ucon = rd_regl(port, S3C2410_UCON);
227 ucon |= S3C2410_UCON_RXIRQMODE;
228 wr_regl(port, S3C2410_UCON, ucon);
229
230 rx_enabled(port) = 1;
231 spin_unlock_irqrestore(&port->lock, flags);
232 }
233
234 static void s3c24xx_serial_rx_disable(struct uart_port *port)
235 {
236 unsigned long flags;
237 unsigned int ucon;
238
239 spin_lock_irqsave(&port->lock, flags);
240
241 ucon = rd_regl(port, S3C2410_UCON);
242 ucon &= ~S3C2410_UCON_RXIRQMODE;
243 wr_regl(port, S3C2410_UCON, ucon);
244
245 rx_enabled(port) = 0;
246 spin_unlock_irqrestore(&port->lock, flags);
247 }
248
249 static void
250 s3c24xx_serial_stop_tx(struct uart_port *port, unsigned int tty_stop)
251 {
252 if (tx_enabled(port)) {
253 disable_irq(TX_IRQ(port));
254 tx_enabled(port) = 0;
255 if (port->flags & UPF_CONS_FLOW)
256 s3c24xx_serial_rx_enable(port);
257 }
258 }
259
260 static void
261 s3c24xx_serial_start_tx(struct uart_port *port, unsigned int tty_start)
262 {
263 if (!tx_enabled(port)) {
264 if (port->flags & UPF_CONS_FLOW)
265 s3c24xx_serial_rx_disable(port);
266
267 enable_irq(TX_IRQ(port));
268 tx_enabled(port) = 1;
269 }
270 }
271
272
273 static void s3c24xx_serial_stop_rx(struct uart_port *port)
274 {
275 if (rx_enabled(port)) {
276 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
277 disable_irq(RX_IRQ(port));
278 rx_enabled(port) = 0;
279 }
280 }
281
282 static void s3c24xx_serial_enable_ms(struct uart_port *port)
283 {
284 }
285
286 static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
287 {
288 return to_ourport(port)->info;
289 }
290
291 static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
292 {
293 if (port->dev == NULL)
294 return NULL;
295
296 return (struct s3c2410_uartcfg *)port->dev->platform_data;
297 }
298
299 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
300 unsigned long ufstat)
301 {
302 struct s3c24xx_uart_info *info = ourport->info;
303
304 if (ufstat & info->rx_fifofull)
305 return info->fifosize;
306
307 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
308 }
309
310
311 /* ? - where has parity gone?? */
312 #define S3C2410_UERSTAT_PARITY (0x1000)
313
314 static irqreturn_t
315 s3c24xx_serial_rx_chars(int irq, void *dev_id, struct pt_regs *regs)
316 {
317 struct s3c24xx_uart_port *ourport = dev_id;
318 struct uart_port *port = &ourport->port;
319 struct tty_struct *tty = port->info->tty;
320 unsigned int ufcon, ch, flag, ufstat, uerstat;
321 int max_count = 64;
322
323 while (max_count-- > 0) {
324 ufcon = rd_regl(port, S3C2410_UFCON);
325 ufstat = rd_regl(port, S3C2410_UFSTAT);
326
327 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
328 break;
329
330 if (tty->flip.count >= TTY_FLIPBUF_SIZE) {
331 if (tty->low_latency)
332 tty_flip_buffer_push(tty);
333
334 /*
335 * If this failed then we will throw away the
336 * bytes but must do so to clear interrupts
337 */
338 }
339
340 uerstat = rd_regl(port, S3C2410_UERSTAT);
341 ch = rd_regb(port, S3C2410_URXH);
342
343 if (port->flags & UPF_CONS_FLOW) {
344 int txe = s3c24xx_serial_txempty_nofifo(port);
345
346 if (rx_enabled(port)) {
347 if (!txe) {
348 rx_enabled(port) = 0;
349 continue;
350 }
351 } else {
352 if (txe) {
353 ufcon |= S3C2410_UFCON_RESETRX;
354 wr_regl(port, S3C2410_UFCON, ufcon);
355 rx_enabled(port) = 1;
356 goto out;
357 }
358 continue;
359 }
360 }
361
362 /* insert the character into the buffer */
363
364 flag = TTY_NORMAL;
365 port->icount.rx++;
366
367 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
368 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
369 ch, uerstat);
370
371 /* check for break */
372 if (uerstat & S3C2410_UERSTAT_BREAK) {
373 dbg("break!\n");
374 port->icount.brk++;
375 if (uart_handle_break(port))
376 goto ignore_char;
377 }
378
379 if (uerstat & S3C2410_UERSTAT_FRAME)
380 port->icount.frame++;
381 if (uerstat & S3C2410_UERSTAT_OVERRUN)
382 port->icount.overrun++;
383
384 uerstat &= port->read_status_mask;
385
386 if (uerstat & S3C2410_UERSTAT_BREAK)
387 flag = TTY_BREAK;
388 else if (uerstat & S3C2410_UERSTAT_PARITY)
389 flag = TTY_PARITY;
390 else if (uerstat & ( S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_OVERRUN))
391 flag = TTY_FRAME;
392 }
393
394 if (uart_handle_sysrq_char(port, ch, regs))
395 goto ignore_char;
396
397 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN, ch, flag);
398
399 ignore_char:
400 continue;
401 }
402 tty_flip_buffer_push(tty);
403
404 out:
405 return IRQ_HANDLED;
406 }
407
408 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id, struct pt_regs *regs)
409 {
410 struct s3c24xx_uart_port *ourport = id;
411 struct uart_port *port = &ourport->port;
412 struct circ_buf *xmit = &port->info->xmit;
413 int count = 256;
414
415 if (port->x_char) {
416 wr_regb(port, S3C2410_UTXH, port->x_char);
417 port->icount.tx++;
418 port->x_char = 0;
419 goto out;
420 }
421
422 /* if there isnt anything more to transmit, or the uart is now
423 * stopped, disable the uart and exit
424 */
425
426 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
427 s3c24xx_serial_stop_tx(port, 0);
428 goto out;
429 }
430
431 /* try and drain the buffer... */
432
433 while (!uart_circ_empty(xmit) && count-- > 0) {
434 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
435 break;
436
437 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
438 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
439 port->icount.tx++;
440 }
441
442 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
443 uart_write_wakeup(port);
444
445 if (uart_circ_empty(xmit))
446 s3c24xx_serial_stop_tx(port, 0);
447
448 out:
449 return IRQ_HANDLED;
450 }
451
452 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
453 {
454 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
455 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
456 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
457
458 if (ufcon & S3C2410_UFCON_FIFOMODE) {
459 if ((ufstat & info->tx_fifomask) != 0 ||
460 (ufstat & info->tx_fifofull))
461 return 0;
462
463 return 1;
464 }
465
466 return s3c24xx_serial_txempty_nofifo(port);
467 }
468
469 /* no modem control lines */
470 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
471 {
472 unsigned int umstat = rd_regb(port,S3C2410_UMSTAT);
473
474 if (umstat & S3C2410_UMSTAT_CTS)
475 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
476 else
477 return TIOCM_CAR | TIOCM_DSR;
478 }
479
480 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
481 {
482 /* todo - possibly remove AFC and do manual CTS */
483 }
484
485 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
486 {
487 unsigned long flags;
488 unsigned int ucon;
489
490 spin_lock_irqsave(&port->lock, flags);
491
492 ucon = rd_regl(port, S3C2410_UCON);
493
494 if (break_state)
495 ucon |= S3C2410_UCON_SBREAK;
496 else
497 ucon &= ~S3C2410_UCON_SBREAK;
498
499 wr_regl(port, S3C2410_UCON, ucon);
500
501 spin_unlock_irqrestore(&port->lock, flags);
502 }
503
504 static void s3c24xx_serial_shutdown(struct uart_port *port)
505 {
506 struct s3c24xx_uart_port *ourport = to_ourport(port);
507
508 if (ourport->tx_claimed) {
509 free_irq(TX_IRQ(port), ourport);
510 tx_enabled(port) = 0;
511 ourport->tx_claimed = 0;
512 }
513
514 if (ourport->rx_claimed) {
515 free_irq(RX_IRQ(port), ourport);
516 ourport->rx_claimed = 0;
517 rx_enabled(port) = 0;
518 }
519 }
520
521
522 static int s3c24xx_serial_startup(struct uart_port *port)
523 {
524 struct s3c24xx_uart_port *ourport = to_ourport(port);
525 int ret;
526
527 dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
528 port->mapbase, port->membase);
529
530 rx_enabled(port) = 1;
531
532 ret = request_irq(RX_IRQ(port),
533 s3c24xx_serial_rx_chars, 0,
534 s3c24xx_serial_portname(port), ourport);
535
536 if (ret != 0) {
537 printk(KERN_ERR "cannot get irq %d\n", RX_IRQ(port));
538 return ret;
539 }
540
541 ourport->rx_claimed = 1;
542
543 dbg("requesting tx irq...\n");
544
545 tx_enabled(port) = 1;
546
547 ret = request_irq(TX_IRQ(port),
548 s3c24xx_serial_tx_chars, 0,
549 s3c24xx_serial_portname(port), ourport);
550
551 if (ret) {
552 printk(KERN_ERR "cannot get irq %d\n", TX_IRQ(port));
553 goto err;
554 }
555
556 ourport->tx_claimed = 1;
557
558 dbg("s3c24xx_serial_startup ok\n");
559
560 /* the port reset code should have done the correct
561 * register setup for the port controls */
562
563 return ret;
564
565 err:
566 s3c24xx_serial_shutdown(port);
567 return ret;
568 }
569
570 /* power power management control */
571
572 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
573 unsigned int old)
574 {
575 struct s3c24xx_uart_port *ourport = to_ourport(port);
576
577 switch (level) {
578 case 3:
579 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
580 clk_disable(ourport->baudclk);
581
582 clk_disable(ourport->clk);
583 break;
584
585 case 0:
586 clk_enable(ourport->clk);
587
588 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
589 clk_enable(ourport->baudclk);
590
591 break;
592 default:
593 printk(KERN_ERR "s3c24xx_serial: unknown pm %d\n", level);
594 }
595 }
596
597 /* baud rate calculation
598 *
599 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
600 * of different sources, including the peripheral clock ("pclk") and an
601 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
602 * with a programmable extra divisor.
603 *
604 * The following code goes through the clock sources, and calculates the
605 * baud clocks (and the resultant actual baud rates) and then tries to
606 * pick the closest one and select that.
607 *
608 */
609
610
611 #define MAX_CLKS (8)
612
613 static struct s3c24xx_uart_clksrc tmp_clksrc = {
614 .name = "pclk",
615 .min_baud = 0,
616 .max_baud = 0,
617 .divisor = 1,
618 };
619
620 static inline int
621 s3c24xx_serial_getsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
622 {
623 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
624
625 return (info->get_clksrc)(port, c);
626 }
627
628 static inline int
629 s3c24xx_serial_setsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
630 {
631 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
632
633 return (info->set_clksrc)(port, c);
634 }
635
636 struct baud_calc {
637 struct s3c24xx_uart_clksrc *clksrc;
638 unsigned int calc;
639 unsigned int quot;
640 struct clk *src;
641 };
642
643 static int s3c24xx_serial_calcbaud(struct baud_calc *calc,
644 struct uart_port *port,
645 struct s3c24xx_uart_clksrc *clksrc,
646 unsigned int baud)
647 {
648 unsigned long rate;
649
650 calc->src = clk_get(port->dev, clksrc->name);
651 if (calc->src == NULL || IS_ERR(calc->src))
652 return 0;
653
654 rate = clk_get_rate(calc->src);
655 rate /= clksrc->divisor;
656
657 calc->clksrc = clksrc;
658 calc->quot = (rate + (8 * baud)) / (16 * baud);
659 calc->calc = (rate / (calc->quot * 16));
660
661 calc->quot--;
662 return 1;
663 }
664
665 static unsigned int s3c24xx_serial_getclk(struct uart_port *port,
666 struct s3c24xx_uart_clksrc **clksrc,
667 struct clk **clk,
668 unsigned int baud)
669 {
670 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
671 struct s3c24xx_uart_clksrc *clkp;
672 struct baud_calc res[MAX_CLKS];
673 struct baud_calc *resptr, *best, *sptr;
674 int i;
675
676 clkp = cfg->clocks;
677 best = NULL;
678
679 if (cfg->clocks_size < 2) {
680 if (cfg->clocks_size == 0)
681 clkp = &tmp_clksrc;
682
683 /* check to see if we're sourcing fclk, and if so we're
684 * going to have to update the clock source
685 */
686
687 if (strcmp(clkp->name, "fclk") == 0) {
688 struct s3c24xx_uart_clksrc src;
689
690 s3c24xx_serial_getsource(port, &src);
691
692 /* check that the port already using fclk, and if
693 * not, then re-select fclk
694 */
695
696 if (strcmp(src.name, clkp->name) == 0) {
697 s3c24xx_serial_setsource(port, clkp);
698 s3c24xx_serial_getsource(port, &src);
699 }
700
701 clkp->divisor = src.divisor;
702 }
703
704 s3c24xx_serial_calcbaud(res, port, clkp, baud);
705 best = res;
706 resptr = best + 1;
707 } else {
708 resptr = res;
709
710 for (i = 0; i < cfg->clocks_size; i++, clkp++) {
711 if (s3c24xx_serial_calcbaud(resptr, port, clkp, baud))
712 resptr++;
713 }
714 }
715
716 /* ok, we now need to select the best clock we found */
717
718 if (!best) {
719 unsigned int deviation = (1<<30)|((1<<30)-1);
720 int calc_deviation;
721
722 for (sptr = res; sptr < resptr; sptr++) {
723 printk(KERN_DEBUG
724 "found clk %p (%s) quot %d, calc %d\n",
725 sptr->clksrc, sptr->clksrc->name,
726 sptr->quot, sptr->calc);
727
728 calc_deviation = baud - sptr->calc;
729 if (calc_deviation < 0)
730 calc_deviation = -calc_deviation;
731
732 if (calc_deviation < deviation) {
733 best = sptr;
734 deviation = calc_deviation;
735 }
736 }
737
738 printk(KERN_DEBUG "best %p (deviation %d)\n", best, deviation);
739 }
740
741 printk(KERN_DEBUG "selected clock %p (%s) quot %d, calc %d\n",
742 best->clksrc, best->clksrc->name, best->quot, best->calc);
743
744 /* store results to pass back */
745
746 *clksrc = best->clksrc;
747 *clk = best->src;
748
749 return best->quot;
750 }
751
752 static void s3c24xx_serial_set_termios(struct uart_port *port,
753 struct termios *termios,
754 struct termios *old)
755 {
756 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
757 struct s3c24xx_uart_port *ourport = to_ourport(port);
758 struct s3c24xx_uart_clksrc *clksrc;
759 struct clk *clk;
760 unsigned long flags;
761 unsigned int baud, quot;
762 unsigned int ulcon;
763 unsigned int umcon;
764
765 /*
766 * We don't support modem control lines.
767 */
768 termios->c_cflag &= ~(HUPCL | CMSPAR);
769 termios->c_cflag |= CLOCAL;
770
771 /*
772 * Ask the core to calculate the divisor for us.
773 */
774
775 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
776
777 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
778 quot = port->custom_divisor;
779 else
780 quot = s3c24xx_serial_getclk(port, &clksrc, &clk, baud);
781
782 /* check to see if we need to change clock source */
783
784 if (ourport->clksrc != clksrc || ourport->baudclk != clk) {
785 s3c24xx_serial_setsource(port, clksrc);
786
787 if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) {
788 clk_disable(ourport->baudclk);
789 clk_unuse(ourport->baudclk);
790 ourport->baudclk = NULL;
791 }
792
793 clk_use(clk);
794 clk_enable(clk);
795
796 ourport->clksrc = clksrc;
797 ourport->baudclk = clk;
798 }
799
800 switch (termios->c_cflag & CSIZE) {
801 case CS5:
802 dbg("config: 5bits/char\n");
803 ulcon = S3C2410_LCON_CS5;
804 break;
805 case CS6:
806 dbg("config: 6bits/char\n");
807 ulcon = S3C2410_LCON_CS6;
808 break;
809 case CS7:
810 dbg("config: 7bits/char\n");
811 ulcon = S3C2410_LCON_CS7;
812 break;
813 case CS8:
814 default:
815 dbg("config: 8bits/char\n");
816 ulcon = S3C2410_LCON_CS8;
817 break;
818 }
819
820 /* preserve original lcon IR settings */
821 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
822
823 if (termios->c_cflag & CSTOPB)
824 ulcon |= S3C2410_LCON_STOPB;
825
826 umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0;
827
828 if (termios->c_cflag & PARENB) {
829 if (termios->c_cflag & PARODD)
830 ulcon |= S3C2410_LCON_PODD;
831 else
832 ulcon |= S3C2410_LCON_PEVEN;
833 } else {
834 ulcon |= S3C2410_LCON_PNONE;
835 }
836
837 spin_lock_irqsave(&port->lock, flags);
838
839 dbg("setting ulcon to %08x, brddiv to %d\n", ulcon, quot);
840
841 wr_regl(port, S3C2410_ULCON, ulcon);
842 wr_regl(port, S3C2410_UBRDIV, quot);
843 wr_regl(port, S3C2410_UMCON, umcon);
844
845 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
846 rd_regl(port, S3C2410_ULCON),
847 rd_regl(port, S3C2410_UCON),
848 rd_regl(port, S3C2410_UFCON));
849
850 /*
851 * Update the per-port timeout.
852 */
853 uart_update_timeout(port, termios->c_cflag, baud);
854
855 /*
856 * Which character status flags are we interested in?
857 */
858 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
859 if (termios->c_iflag & INPCK)
860 port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
861
862 /*
863 * Which character status flags should we ignore?
864 */
865 port->ignore_status_mask = 0;
866 if (termios->c_iflag & IGNPAR)
867 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
868 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
869 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
870
871 /*
872 * Ignore all characters if CREAD is not set.
873 */
874 if ((termios->c_cflag & CREAD) == 0)
875 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
876
877 spin_unlock_irqrestore(&port->lock, flags);
878 }
879
880 static const char *s3c24xx_serial_type(struct uart_port *port)
881 {
882 switch (port->type) {
883 case PORT_S3C2410:
884 return "S3C2410";
885 case PORT_S3C2440:
886 return "S3C2440";
887 default:
888 return NULL;
889 }
890 }
891
892 #define MAP_SIZE (0x100)
893
894 static void s3c24xx_serial_release_port(struct uart_port *port)
895 {
896 release_mem_region(port->mapbase, MAP_SIZE);
897 }
898
899 static int s3c24xx_serial_request_port(struct uart_port *port)
900 {
901 const char *name = s3c24xx_serial_portname(port);
902 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
903 }
904
905 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
906 {
907 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
908
909 if (flags & UART_CONFIG_TYPE &&
910 s3c24xx_serial_request_port(port) == 0)
911 port->type = info->type;
912 }
913
914 /*
915 * verify the new serial_struct (for TIOCSSERIAL).
916 */
917 static int
918 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
919 {
920 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
921
922 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
923 return -EINVAL;
924
925 return 0;
926 }
927
928
929 #ifdef CONFIG_SERIAL_S3C2410_CONSOLE
930
931 static struct console s3c24xx_serial_console;
932
933 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
934 #else
935 #define S3C24XX_SERIAL_CONSOLE NULL
936 #endif
937
938 static struct uart_ops s3c24xx_serial_ops = {
939 .pm = s3c24xx_serial_pm,
940 .tx_empty = s3c24xx_serial_tx_empty,
941 .get_mctrl = s3c24xx_serial_get_mctrl,
942 .set_mctrl = s3c24xx_serial_set_mctrl,
943 .stop_tx = s3c24xx_serial_stop_tx,
944 .start_tx = s3c24xx_serial_start_tx,
945 .stop_rx = s3c24xx_serial_stop_rx,
946 .enable_ms = s3c24xx_serial_enable_ms,
947 .break_ctl = s3c24xx_serial_break_ctl,
948 .startup = s3c24xx_serial_startup,
949 .shutdown = s3c24xx_serial_shutdown,
950 .set_termios = s3c24xx_serial_set_termios,
951 .type = s3c24xx_serial_type,
952 .release_port = s3c24xx_serial_release_port,
953 .request_port = s3c24xx_serial_request_port,
954 .config_port = s3c24xx_serial_config_port,
955 .verify_port = s3c24xx_serial_verify_port,
956 };
957
958
959 static struct uart_driver s3c24xx_uart_drv = {
960 .owner = THIS_MODULE,
961 .dev_name = "s3c2410_serial",
962 .nr = 3,
963 .cons = S3C24XX_SERIAL_CONSOLE,
964 .driver_name = S3C24XX_SERIAL_NAME,
965 .devfs_name = S3C24XX_SERIAL_DEVFS,
966 .major = S3C24XX_SERIAL_MAJOR,
967 .minor = S3C24XX_SERIAL_MINOR,
968 };
969
970 static struct s3c24xx_uart_port s3c24xx_serial_ports[NR_PORTS] = {
971 [0] = {
972 .port = {
973 .lock = SPIN_LOCK_UNLOCKED,
974 .iotype = UPIO_MEM,
975 .irq = IRQ_S3CUART_RX0,
976 .uartclk = 0,
977 .fifosize = 16,
978 .ops = &s3c24xx_serial_ops,
979 .flags = UPF_BOOT_AUTOCONF,
980 .line = 0,
981 }
982 },
983 [1] = {
984 .port = {
985 .lock = SPIN_LOCK_UNLOCKED,
986 .iotype = UPIO_MEM,
987 .irq = IRQ_S3CUART_RX1,
988 .uartclk = 0,
989 .fifosize = 16,
990 .ops = &s3c24xx_serial_ops,
991 .flags = UPF_BOOT_AUTOCONF,
992 .line = 1,
993 }
994 },
995 #if NR_PORTS > 2
996
997 [2] = {
998 .port = {
999 .lock = SPIN_LOCK_UNLOCKED,
1000 .iotype = UPIO_MEM,
1001 .irq = IRQ_S3CUART_RX2,
1002 .uartclk = 0,
1003 .fifosize = 16,
1004 .ops = &s3c24xx_serial_ops,
1005 .flags = UPF_BOOT_AUTOCONF,
1006 .line = 2,
1007 }
1008 }
1009 #endif
1010 };
1011
1012 /* s3c24xx_serial_resetport
1013 *
1014 * wrapper to call the specific reset for this port (reset the fifos
1015 * and the settings)
1016 */
1017
1018 static inline int s3c24xx_serial_resetport(struct uart_port * port,
1019 struct s3c2410_uartcfg *cfg)
1020 {
1021 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1022
1023 return (info->reset_port)(port, cfg);
1024 }
1025
1026 /* s3c24xx_serial_init_port
1027 *
1028 * initialise a single serial port from the platform device given
1029 */
1030
1031 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1032 struct s3c24xx_uart_info *info,
1033 struct platform_device *platdev)
1034 {
1035 struct uart_port *port = &ourport->port;
1036 struct s3c2410_uartcfg *cfg;
1037 struct resource *res;
1038
1039 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1040
1041 if (platdev == NULL)
1042 return -ENODEV;
1043
1044 cfg = s3c24xx_dev_to_cfg(&platdev->dev);
1045
1046 if (port->mapbase != 0)
1047 return 0;
1048
1049 if (cfg->hwport > 3)
1050 return -EINVAL;
1051
1052 /* setup info for port */
1053 port->dev = &platdev->dev;
1054 ourport->info = info;
1055
1056 /* copy the info in from provided structure */
1057 ourport->port.fifosize = info->fifosize;
1058
1059 dbg("s3c24xx_serial_init_port: %p (hw %d)...\n", port, cfg->hwport);
1060
1061 port->uartclk = 1;
1062
1063 if (cfg->uart_flags & UPF_CONS_FLOW) {
1064 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1065 port->flags |= UPF_CONS_FLOW;
1066 }
1067
1068 /* sort our the physical and virtual addresses for each UART */
1069
1070 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1071 if (res == NULL) {
1072 printk(KERN_ERR "failed to find memory resource for uart\n");
1073 return -EINVAL;
1074 }
1075
1076 dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
1077
1078 port->mapbase = res->start;
1079 port->membase = S3C24XX_VA_UART + (res->start - S3C2410_PA_UART);
1080 port->irq = platform_get_irq(platdev, 0);
1081
1082 ourport->clk = clk_get(&platdev->dev, "uart");
1083
1084 if (ourport->clk != NULL && !IS_ERR(ourport->clk))
1085 clk_use(ourport->clk);
1086
1087 dbg("port: map=%08x, mem=%08x, irq=%d, clock=%ld\n",
1088 port->mapbase, port->membase, port->irq, port->uartclk);
1089
1090 /* reset the fifos (and setup the uart) */
1091 s3c24xx_serial_resetport(port, cfg);
1092 return 0;
1093 }
1094
1095 /* Device driver serial port probe */
1096
1097 static int probe_index = 0;
1098
1099 int s3c24xx_serial_probe(struct device *_dev,
1100 struct s3c24xx_uart_info *info)
1101 {
1102 struct s3c24xx_uart_port *ourport;
1103 struct platform_device *dev = to_platform_device(_dev);
1104 int ret;
1105
1106 dbg("s3c24xx_serial_probe(%p, %p) %d\n", _dev, info, probe_index);
1107
1108 ourport = &s3c24xx_serial_ports[probe_index];
1109 probe_index++;
1110
1111 dbg("%s: initialising port %p...\n", __FUNCTION__, ourport);
1112
1113 ret = s3c24xx_serial_init_port(ourport, info, dev);
1114 if (ret < 0)
1115 goto probe_err;
1116
1117 dbg("%s: adding port\n", __FUNCTION__);
1118 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1119 dev_set_drvdata(_dev, &ourport->port);
1120
1121 return 0;
1122
1123 probe_err:
1124 return ret;
1125 }
1126
1127 int s3c24xx_serial_remove(struct device *_dev)
1128 {
1129 struct uart_port *port = s3c24xx_dev_to_port(_dev);
1130
1131 if (port)
1132 uart_remove_one_port(&s3c24xx_uart_drv, port);
1133
1134 return 0;
1135 }
1136
1137 /* UART power management code */
1138
1139 #ifdef CONFIG_PM
1140
1141 int s3c24xx_serial_suspend(struct device *dev, pm_message_t state, u32 level)
1142 {
1143 struct uart_port *port = s3c24xx_dev_to_port(dev);
1144
1145 if (port && level == SUSPEND_DISABLE)
1146 uart_suspend_port(&s3c24xx_uart_drv, port);
1147
1148 return 0;
1149 }
1150
1151 int s3c24xx_serial_resume(struct device *dev, u32 level)
1152 {
1153 struct uart_port *port = s3c24xx_dev_to_port(dev);
1154 struct s3c24xx_uart_port *ourport = to_ourport(port);
1155
1156 if (port && level == RESUME_ENABLE) {
1157 clk_enable(ourport->clk);
1158 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1159 clk_disable(ourport->clk);
1160
1161 uart_resume_port(&s3c24xx_uart_drv, port);
1162 }
1163
1164 return 0;
1165 }
1166
1167 #else
1168 #define s3c24xx_serial_suspend NULL
1169 #define s3c24xx_serial_resume NULL
1170 #endif
1171
1172 int s3c24xx_serial_init(struct device_driver *drv,
1173 struct s3c24xx_uart_info *info)
1174 {
1175 dbg("s3c24xx_serial_init(%p,%p)\n", drv, info);
1176 return driver_register(drv);
1177 }
1178
1179
1180 /* now comes the code to initialise either the s3c2410 or s3c2440 serial
1181 * port information
1182 */
1183
1184 /* cpu specific variations on the serial port support */
1185
1186 #ifdef CONFIG_CPU_S3C2400
1187
1188 static int s3c2400_serial_getsource(struct uart_port *port,
1189 struct s3c24xx_uart_clksrc *clk)
1190 {
1191 clk->divisor = 1;
1192 clk->name = "pclk";
1193
1194 return 0;
1195 }
1196
1197 static int s3c2400_serial_setsource(struct uart_port *port,
1198 struct s3c24xx_uart_clksrc *clk)
1199 {
1200 return 0;
1201 }
1202
1203 static int s3c2400_serial_resetport(struct uart_port *port,
1204 struct s3c2410_uartcfg *cfg)
1205 {
1206 dbg("s3c2400_serial_resetport: port=%p (%08lx), cfg=%p\n",
1207 port, port->mapbase, cfg);
1208
1209 wr_regl(port, S3C2410_UCON, cfg->ucon);
1210 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1211
1212 /* reset both fifos */
1213
1214 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1215 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1216
1217 return 0;
1218 }
1219
1220 static struct s3c24xx_uart_info s3c2400_uart_inf = {
1221 .name = "Samsung S3C2400 UART",
1222 .type = PORT_S3C2400,
1223 .fifosize = 16,
1224 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1225 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1226 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1227 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1228 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1229 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1230 .get_clksrc = s3c2400_serial_getsource,
1231 .set_clksrc = s3c2400_serial_setsource,
1232 .reset_port = s3c2400_serial_resetport,
1233 };
1234
1235 static int s3c2400_serial_probe(struct device *dev)
1236 {
1237 return s3c24xx_serial_probe(dev, &s3c2400_uart_inf);
1238 }
1239
1240 static struct device_driver s3c2400_serial_drv = {
1241 .name = "s3c2400-uart",
1242 .bus = &platform_bus_type,
1243 .probe = s3c2400_serial_probe,
1244 .remove = s3c24xx_serial_remove,
1245 .suspend = s3c24xx_serial_suspend,
1246 .resume = s3c24xx_serial_resume,
1247 };
1248
1249 static inline int s3c2400_serial_init(void)
1250 {
1251 return s3c24xx_serial_init(&s3c2400_serial_drv, &s3c2400_uart_inf);
1252 }
1253
1254 static inline void s3c2400_serial_exit(void)
1255 {
1256 driver_unregister(&s3c2400_serial_drv);
1257 }
1258
1259 #define s3c2400_uart_inf_at &s3c2400_uart_inf
1260 #else
1261
1262 static inline int s3c2400_serial_init(void)
1263 {
1264 return 0;
1265 }
1266
1267 static inline void s3c2400_serial_exit(void)
1268 {
1269 }
1270
1271 #define s3c2400_uart_inf_at NULL
1272
1273 #endif /* CONFIG_CPU_S3C2400 */
1274
1275 /* S3C2410 support */
1276
1277 #ifdef CONFIG_CPU_S3C2410
1278
1279 static int s3c2410_serial_setsource(struct uart_port *port,
1280 struct s3c24xx_uart_clksrc *clk)
1281 {
1282 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1283
1284 if (strcmp(clk->name, "uclk") == 0)
1285 ucon |= S3C2410_UCON_UCLK;
1286 else
1287 ucon &= ~S3C2410_UCON_UCLK;
1288
1289 wr_regl(port, S3C2410_UCON, ucon);
1290 return 0;
1291 }
1292
1293 static int s3c2410_serial_getsource(struct uart_port *port,
1294 struct s3c24xx_uart_clksrc *clk)
1295 {
1296 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1297
1298 clk->divisor = 1;
1299 clk->name = (ucon & S3C2410_UCON_UCLK) ? "uclk" : "pclk";
1300
1301 return 0;
1302 }
1303
1304 static int s3c2410_serial_resetport(struct uart_port *port,
1305 struct s3c2410_uartcfg *cfg)
1306 {
1307 dbg("s3c2410_serial_resetport: port=%p (%08lx), cfg=%p\n",
1308 port, port->mapbase, cfg);
1309
1310 wr_regl(port, S3C2410_UCON, cfg->ucon);
1311 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1312
1313 /* reset both fifos */
1314
1315 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1316 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1317
1318 return 0;
1319 }
1320
1321 static struct s3c24xx_uart_info s3c2410_uart_inf = {
1322 .name = "Samsung S3C2410 UART",
1323 .type = PORT_S3C2410,
1324 .fifosize = 16,
1325 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1326 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1327 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1328 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1329 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1330 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1331 .get_clksrc = s3c2410_serial_getsource,
1332 .set_clksrc = s3c2410_serial_setsource,
1333 .reset_port = s3c2410_serial_resetport,
1334 };
1335
1336 /* device management */
1337
1338 static int s3c2410_serial_probe(struct device *dev)
1339 {
1340 return s3c24xx_serial_probe(dev, &s3c2410_uart_inf);
1341 }
1342
1343 static struct device_driver s3c2410_serial_drv = {
1344 .name = "s3c2410-uart",
1345 .bus = &platform_bus_type,
1346 .probe = s3c2410_serial_probe,
1347 .remove = s3c24xx_serial_remove,
1348 .suspend = s3c24xx_serial_suspend,
1349 .resume = s3c24xx_serial_resume,
1350 };
1351
1352 static inline int s3c2410_serial_init(void)
1353 {
1354 return s3c24xx_serial_init(&s3c2410_serial_drv, &s3c2410_uart_inf);
1355 }
1356
1357 static inline void s3c2410_serial_exit(void)
1358 {
1359 driver_unregister(&s3c2410_serial_drv);
1360 }
1361
1362 #define s3c2410_uart_inf_at &s3c2410_uart_inf
1363 #else
1364
1365 static inline int s3c2410_serial_init(void)
1366 {
1367 return 0;
1368 }
1369
1370 static inline void s3c2410_serial_exit(void)
1371 {
1372 }
1373
1374 #define s3c2410_uart_inf_at NULL
1375
1376 #endif /* CONFIG_CPU_S3C2410 */
1377
1378 #ifdef CONFIG_CPU_S3C2440
1379
1380 static int s3c2440_serial_setsource(struct uart_port *port,
1381 struct s3c24xx_uart_clksrc *clk)
1382 {
1383 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1384
1385 // todo - proper fclk<>nonfclk switch //
1386
1387 ucon &= ~S3C2440_UCON_CLKMASK;
1388
1389 if (strcmp(clk->name, "uclk") == 0)
1390 ucon |= S3C2440_UCON_UCLK;
1391 else if (strcmp(clk->name, "pclk") == 0)
1392 ucon |= S3C2440_UCON_PCLK;
1393 else if (strcmp(clk->name, "fclk") == 0)
1394 ucon |= S3C2440_UCON_FCLK;
1395 else {
1396 printk(KERN_ERR "unknown clock source %s\n", clk->name);
1397 return -EINVAL;
1398 }
1399
1400 wr_regl(port, S3C2410_UCON, ucon);
1401 return 0;
1402 }
1403
1404
1405 static int s3c2440_serial_getsource(struct uart_port *port,
1406 struct s3c24xx_uart_clksrc *clk)
1407 {
1408 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1409 unsigned long ucon0, ucon1, ucon2;
1410
1411 switch (ucon & S3C2440_UCON_CLKMASK) {
1412 case S3C2440_UCON_UCLK:
1413 clk->divisor = 1;
1414 clk->name = "uclk";
1415 break;
1416
1417 case S3C2440_UCON_PCLK:
1418 case S3C2440_UCON_PCLK2:
1419 clk->divisor = 1;
1420 clk->name = "pclk";
1421 break;
1422
1423 case S3C2440_UCON_FCLK:
1424 /* the fun of calculating the uart divisors on
1425 * the s3c2440 */
1426
1427 ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON);
1428 ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON);
1429 ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON);
1430
1431 printk("ucons: %08lx, %08lx, %08lx\n", ucon0, ucon1, ucon2);
1432
1433 ucon0 &= S3C2440_UCON0_DIVMASK;
1434 ucon1 &= S3C2440_UCON1_DIVMASK;
1435 ucon2 &= S3C2440_UCON2_DIVMASK;
1436
1437 if (ucon0 != 0) {
1438 clk->divisor = ucon0 >> S3C2440_UCON_DIVSHIFT;
1439 clk->divisor += 6;
1440 } else if (ucon1 != 0) {
1441 clk->divisor = ucon1 >> S3C2440_UCON_DIVSHIFT;
1442 clk->divisor += 21;
1443 } else if (ucon2 != 0) {
1444 clk->divisor = ucon2 >> S3C2440_UCON_DIVSHIFT;
1445 clk->divisor += 36;
1446 } else {
1447 /* manual calims 44, seems to be 9 */
1448 clk->divisor = 9;
1449 }
1450
1451 clk->name = "fclk";
1452 break;
1453 }
1454
1455 return 0;
1456 }
1457
1458 static int s3c2440_serial_resetport(struct uart_port *port,
1459 struct s3c2410_uartcfg *cfg)
1460 {
1461 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1462
1463 dbg("s3c2440_serial_resetport: port=%p (%08lx), cfg=%p\n",
1464 port, port->mapbase, cfg);
1465
1466 /* ensure we don't change the clock settings... */
1467
1468 ucon &= (S3C2440_UCON0_DIVMASK | (3<<10));
1469
1470 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1471 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1472
1473 /* reset both fifos */
1474
1475 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1476 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1477
1478 return 0;
1479 }
1480
1481 static struct s3c24xx_uart_info s3c2440_uart_inf = {
1482 .name = "Samsung S3C2440 UART",
1483 .type = PORT_S3C2440,
1484 .fifosize = 64,
1485 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1486 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1487 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1488 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1489 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1490 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1491 .get_clksrc = s3c2440_serial_getsource,
1492 .set_clksrc = s3c2440_serial_setsource,
1493 .reset_port = s3c2440_serial_resetport,
1494 };
1495
1496 /* device management */
1497
1498 static int s3c2440_serial_probe(struct device *dev)
1499 {
1500 dbg("s3c2440_serial_probe: dev=%p\n", dev);
1501 return s3c24xx_serial_probe(dev, &s3c2440_uart_inf);
1502 }
1503
1504 static struct device_driver s3c2440_serial_drv = {
1505 .name = "s3c2440-uart",
1506 .bus = &platform_bus_type,
1507 .probe = s3c2440_serial_probe,
1508 .remove = s3c24xx_serial_remove,
1509 .suspend = s3c24xx_serial_suspend,
1510 .resume = s3c24xx_serial_resume,
1511 };
1512
1513
1514 static inline int s3c2440_serial_init(void)
1515 {
1516 return s3c24xx_serial_init(&s3c2440_serial_drv, &s3c2440_uart_inf);
1517 }
1518
1519 static inline void s3c2440_serial_exit(void)
1520 {
1521 driver_unregister(&s3c2440_serial_drv);
1522 }
1523
1524 #define s3c2440_uart_inf_at &s3c2440_uart_inf
1525 #else
1526
1527 static inline int s3c2440_serial_init(void)
1528 {
1529 return 0;
1530 }
1531
1532 static inline void s3c2440_serial_exit(void)
1533 {
1534 }
1535
1536 #define s3c2440_uart_inf_at NULL
1537 #endif /* CONFIG_CPU_S3C2440 */
1538
1539 /* module initialisation code */
1540
1541 static int __init s3c24xx_serial_modinit(void)
1542 {
1543 int ret;
1544
1545 ret = uart_register_driver(&s3c24xx_uart_drv);
1546 if (ret < 0) {
1547 printk(KERN_ERR "failed to register UART driver\n");
1548 return -1;
1549 }
1550
1551 s3c2400_serial_init();
1552 s3c2410_serial_init();
1553 s3c2440_serial_init();
1554
1555 return 0;
1556 }
1557
1558 static void __exit s3c24xx_serial_modexit(void)
1559 {
1560 s3c2400_serial_exit();
1561 s3c2410_serial_exit();
1562 s3c2440_serial_exit();
1563
1564 uart_unregister_driver(&s3c24xx_uart_drv);
1565 }
1566
1567
1568 module_init(s3c24xx_serial_modinit);
1569 module_exit(s3c24xx_serial_modexit);
1570
1571 /* Console code */
1572
1573 #ifdef CONFIG_SERIAL_S3C2410_CONSOLE
1574
1575 static struct uart_port *cons_uart;
1576
1577 static int
1578 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1579 {
1580 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1581 unsigned long ufstat, utrstat;
1582
1583 if (ufcon & S3C2410_UFCON_FIFOMODE) {
1584 /* fifo mode - check ammount of data in fifo registers... */
1585
1586 ufstat = rd_regl(port, S3C2410_UFSTAT);
1587 return (ufstat & info->tx_fifofull) ? 0 : 1;
1588 }
1589
1590 /* in non-fifo mode, we go and use the tx buffer empty */
1591
1592 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1593 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1594 }
1595
1596 static void
1597 s3c24xx_serial_console_write(struct console *co, const char *s,
1598 unsigned int count)
1599 {
1600 int i;
1601 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1602
1603 for (i = 0; i < count; i++) {
1604 while (!s3c24xx_serial_console_txrdy(cons_uart, ufcon))
1605 barrier();
1606
1607 wr_regb(cons_uart, S3C2410_UTXH, s[i]);
1608
1609 if (s[i] == '\n') {
1610 while (!s3c24xx_serial_console_txrdy(cons_uart, ufcon))
1611 barrier();
1612
1613 wr_regb(cons_uart, S3C2410_UTXH, '\r');
1614 }
1615 }
1616 }
1617
1618 static void __init
1619 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1620 int *parity, int *bits)
1621 {
1622 struct s3c24xx_uart_clksrc clksrc;
1623 struct clk *clk;
1624 unsigned int ulcon;
1625 unsigned int ucon;
1626 unsigned int ubrdiv;
1627 unsigned long rate;
1628
1629 ulcon = rd_regl(port, S3C2410_ULCON);
1630 ucon = rd_regl(port, S3C2410_UCON);
1631 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1632
1633 dbg("s3c24xx_serial_get_options: port=%p\n"
1634 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1635 port, ulcon, ucon, ubrdiv);
1636
1637 if ((ucon & 0xf) != 0) {
1638 /* consider the serial port configured if the tx/rx mode set */
1639
1640 switch (ulcon & S3C2410_LCON_CSMASK) {
1641 case S3C2410_LCON_CS5:
1642 *bits = 5;
1643 break;
1644 case S3C2410_LCON_CS6:
1645 *bits = 6;
1646 break;
1647 case S3C2410_LCON_CS7:
1648 *bits = 7;
1649 break;
1650 default:
1651 case S3C2410_LCON_CS8:
1652 *bits = 8;
1653 break;
1654 }
1655
1656 switch (ulcon & S3C2410_LCON_PMASK) {
1657 case S3C2410_LCON_PEVEN:
1658 *parity = 'e';
1659 break;
1660
1661 case S3C2410_LCON_PODD:
1662 *parity = 'o';
1663 break;
1664
1665 case S3C2410_LCON_PNONE:
1666 default:
1667 *parity = 'n';
1668 }
1669
1670 /* now calculate the baud rate */
1671
1672 s3c24xx_serial_getsource(port, &clksrc);
1673
1674 clk = clk_get(port->dev, clksrc.name);
1675 if (!IS_ERR(clk) && clk != NULL)
1676 rate = clk_get_rate(clk) / clksrc.divisor;
1677 else
1678 rate = 1;
1679
1680
1681 *baud = rate / ( 16 * (ubrdiv + 1));
1682 dbg("calculated baud %d\n", *baud);
1683 }
1684
1685 }
1686
1687 /* s3c24xx_serial_init_ports
1688 *
1689 * initialise the serial ports from the machine provided initialisation
1690 * data.
1691 */
1692
1693 static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info *info)
1694 {
1695 struct s3c24xx_uart_port *ptr = s3c24xx_serial_ports;
1696 struct platform_device **platdev_ptr;
1697 int i;
1698
1699 dbg("s3c24xx_serial_init_ports: initialising ports...\n");
1700
1701 platdev_ptr = s3c24xx_uart_devs;
1702
1703 for (i = 0; i < NR_PORTS; i++, ptr++, platdev_ptr++) {
1704 s3c24xx_serial_init_port(ptr, info, *platdev_ptr);
1705 }
1706
1707 return 0;
1708 }
1709
1710 static int __init
1711 s3c24xx_serial_console_setup(struct console *co, char *options)
1712 {
1713 struct uart_port *port;
1714 int baud = 9600;
1715 int bits = 8;
1716 int parity = 'n';
1717 int flow = 'n';
1718
1719 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1720 co, co->index, options);
1721
1722 /* is this a valid port */
1723
1724 if (co->index == -1 || co->index >= NR_PORTS)
1725 co->index = 0;
1726
1727 port = &s3c24xx_serial_ports[co->index].port;
1728
1729 /* is the port configured? */
1730
1731 if (port->mapbase == 0x0) {
1732 co->index = 0;
1733 port = &s3c24xx_serial_ports[co->index].port;
1734 }
1735
1736 cons_uart = port;
1737
1738 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1739
1740 /*
1741 * Check whether an invalid uart number has been specified, and
1742 * if so, search for the first available port that does have
1743 * console support.
1744 */
1745 if (options)
1746 uart_parse_options(options, &baud, &parity, &bits, &flow);
1747 else
1748 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1749
1750 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1751
1752 return uart_set_options(port, co, baud, parity, bits, flow);
1753 }
1754
1755 /* s3c24xx_serial_initconsole
1756 *
1757 * initialise the console from one of the uart drivers
1758 */
1759
1760 static struct console s3c24xx_serial_console =
1761 {
1762 .name = S3C24XX_SERIAL_NAME,
1763 .device = uart_console_device,
1764 .flags = CON_PRINTBUFFER,
1765 .index = -1,
1766 .write = s3c24xx_serial_console_write,
1767 .setup = s3c24xx_serial_console_setup
1768 };
1769
1770 static int s3c24xx_serial_initconsole(void)
1771 {
1772 struct s3c24xx_uart_info *info;
1773 struct platform_device *dev = s3c24xx_uart_devs[0];
1774
1775 dbg("s3c24xx_serial_initconsole\n");
1776
1777 /* select driver based on the cpu */
1778
1779 if (dev == NULL) {
1780 printk(KERN_ERR "s3c24xx: no devices for console init\n");
1781 return 0;
1782 }
1783
1784 if (strcmp(dev->name, "s3c2400-uart") == 0) {
1785 info = s3c2400_uart_inf_at;
1786 } else if (strcmp(dev->name, "s3c2410-uart") == 0) {
1787 info = s3c2410_uart_inf_at;
1788 } else if (strcmp(dev->name, "s3c2440-uart") == 0) {
1789 info = s3c2440_uart_inf_at;
1790 } else {
1791 printk(KERN_ERR "s3c24xx: no driver for %s\n", dev->name);
1792 return 0;
1793 }
1794
1795 if (info == NULL) {
1796 printk(KERN_ERR "s3c24xx: no driver for console\n");
1797 return 0;
1798 }
1799
1800 s3c24xx_serial_console.data = &s3c24xx_uart_drv;
1801 s3c24xx_serial_init_ports(info);
1802
1803 register_console(&s3c24xx_serial_console);
1804 return 0;
1805 }
1806
1807 console_initcall(s3c24xx_serial_initconsole);
1808
1809 #endif /* CONFIG_SERIAL_S3C2410_CONSOLE */
1810
1811 MODULE_LICENSE("GPL");
1812 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1813 MODULE_DESCRIPTION("Samsung S3C2410/S3C2440 Serial port driver");
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